Dynamic on-resistance test circuit based on gallium nitride transistor and test method thereof

Abstract

The invention discloses a dynamic on-resistance test circuit based on a gallium nitride transistor and a test method thereof. Belongs to the technical field of power electronics. The circuit comprises a DPT test circuit, a switch state switching circuit and a clamping circuit, the test method comprises the following steps: monitoring the voltage between test points on the clamping circuit and the current on the coaxial resistor to obtain the on resistance of the to-be-tested tube; the switching between the hard switching test and the soft switching test is realized by changing the switch interface. According to the invention, a gallium nitride transistor and a clamping circuit are introduced into a traditional double-pulse test circuit, and a dynamic on-resistance test function in a soft switching mode and a hard switching mode is integrated. Compared with a traditional testing circuit, the clamping circuit can capture the dynamic on-resistance within nanosecond time delay, meanwhile, the peak of the clamping voltage is greatly reduced, the testing precision is improved, and rapid and accurate measurement of the dynamic on-resistance is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, and in particular relates to a dynamic on-resistance test circuit based on a gallium nitride transistor and a test method thereof. Background Art

[0002] Gallium nitride devices are widely used in the industry for high-efficiency and high-power density converter designs due to their low on-resistance, high breakdown voltage, and fast switching speed. However, the reliability of high-voltage GaN devices in practical applications remains an issue. Under dynamic conditions, gallium nitride high electron mobility transistors will experience on-resistance degradation, which is a huge challenge facing gallium nitride researchers and developers.

[0003] Dynamic on-resistance degradation is a serious problem that limits the large-scale application of GaN power devices. It is caused by the capture effect, which is specifically manifested as the on-resistance between the source and drain of the GaN device increases after being stressed for a period of time, and returns to the original static value after a sufficiently long time. Considering that GaN devices usually operate at high switching frequencies in actual power electronics applications, the extremely short on-time is not enough to restore the resistance, so more conduction losses are generated, causing the device to operate at a higher junction temperature and lower efficiency. The degradation of dynamic on-resistance increases the uncertainty of the conduction power loss evaluation of GaN devices and also increases the difficulty of base converter design. Therefore, the characterization of the dynamic on-resistance of GaN devices is of great significance.

[0004] In order to accurately measure the dynamic on-resistance, the oscilloscope needs to have enough measurement range to simultaneously display the high voltage of the device under test in the off state and the low voltage of the on state. Otherwise, the part beyond the measurement range will cause the oscilloscope to be overdriven, resulting in the inability to accurately measure the drain-source voltage of the device under test. Increasing the measurement range of the oscilloscope will result in insufficient measurement resolution of the oscilloscope, greatly reducing the measurement accuracy. To this end, many studies have introduced clamping circuits to solve the above problems, but the high voltage spikes caused by the clamping circuit make the clamping effect unsatisfactory. At the same time, the introduction of internal capacitor charging and discharging and passive devices of the device also brings other problems such as test response delay and leakage current. Therefore, a fast and accurate clamping circuit is needed to clamp the higher drain-source voltage of the device under test when it is turned on to a lower value, and minimize the negative effects such as oscillation and delay caused by the introduction of the clamping circuit. Summary of the invention

[0005] Purpose of the invention: In view of the technical problems existing in measuring the dynamic on-resistance of GaN transistors mentioned above, the purpose of the present invention is to provide a dynamic on-resistance test circuit based on GaN transistors and a test method thereof, which can effectively clamp high voltage, reduce the output capacitance in the clamping circuit, reduce the oscillation caused by the rapid change of the voltage of the device under test, and have a lower response delay.

[0006] Technical solution: A dynamic on-resistance test circuit based on a gallium nitride transistor of the present invention includes a DPT test circuit, a switch state switching circuit and a clamping circuit; the DPT test circuit is used to generate a double pulse or multi-pulse test signal to control the on and off of the device under test and the accompanying device under test; the switch state switching circuit can switch between hard switch and soft switch states through a switch unit after changing the input gate signal; the clamping circuit is used to clamp the high voltage at the drain-source end of the device under test in the off state to a lower level, and can timely unclamp and accurately measure the on-voltage when the device under test is turned on. The DPT test circuit includes a DC power supply, a first capacitor, a coaxial resistor, a control signal, a gate drive, a first gallium nitride device, and a second gallium nitride device;

[0007] The DC power supply is respectively connected to one end of the first capacitor, one end of the switch state switching circuit and the drain end of the first gallium nitride device; the other end of the switch state switching circuit is respectively connected to one end of the coaxial resistor, the other end of the DC power supply and the other end of the first capacitor; the source end of the first gallium nitride device is respectively connected to the drain end of the second gallium nitride device, the output end of the switch state switching circuit and one end of the clamping circuit; the source end of the second gallium nitride device is respectively connected to the other end of the clamping circuit and the other end of the coaxial resistor and is grounded; the gate driver is respectively connected to the gate of the first gallium nitride device and the gate of the second gallium nitride device; the clamping circuit is connected in parallel to both ends of the second gallium nitride device for measuring its drain-source voltage.

[0008] Further, the switch state switching circuit includes a second capacitor, a third capacitor, a first resistor, a second resistor, a switch unit, and a load inductor;

[0009] One end of the second capacitor is respectively connected to one end of the first resistor and end 2 of the switch unit; the other end of the second capacitor is respectively connected to the other end of the first resistor, one end of the third capacitor, one end of the second resistor and end 3 of the switch unit; the other end of the third capacitor is connected to the other end of the second resistor; end 1 of the switch unit is connected to one end of the load inductor; switching the switch unit to ends 2 and 3 can respectively put the test circuit under soft switching and hard switching test conditions.

[0010] Furthermore, the second capacitor and the third capacitor of the switch state switching circuit have the same size; the first resistor and the second resistor have the same size; and connecting resistors of the same size in parallel to the capacitor providing pre-voltage stress can control the waveform duty cycle during multi-pulse testing to 50%.

[0011] Further, the clamping circuit includes a third gallium nitride device, a second voltage source, a Schottky diode, a Zener diode, and a fourth resistor;

[0012] The drain terminal of the third gallium nitride device is connected to the drain terminal of the second gallium nitride device; the source terminal of the third gallium nitride device is connected to the cathode of the Zener diode; the anode of the Zener diode is connected to one end of the fourth resistor and the cathode of the Zener diode; the anode of the second voltage source is connected to the gate of the third gallium nitride device; the cathode of the second voltage source is respectively connected to the anode of the Schottky diode and the other end of the fourth resistor to the source terminal of the second gallium nitride device.

[0013] Furthermore, the withstand voltage value of the third gallium nitride device in the clamping circuit should be greater than or equal to the withstand voltage value of the second gallium nitride device to prevent the third gallium nitride device from being broken down when testing high-voltage working conditions.

[0014] Furthermore, the third gallium nitride device is an enhancement-mode gallium nitride device and its on-resistance is much smaller than that of the second gallium nitride device, so as to reduce the influence of the third gallium nitride device on the on-voltage drop during the test.

[0015] The dynamic on-resistance test method based on GaN transistors includes:

[0016] S1, a DC power supply supplies power to the first capacitor and the load inductor;

[0017] S2, control signals PWM1 and PWM2 of the first gallium nitride device and the second gallium nitride device respectively generate different pulse waveforms when switching the switch unit to different ports to control the second gallium nitride device to be in a soft switching or hard switching test state;

[0018] When the terminal 1 of the switch unit is connected to the terminal 2, the control signal causes the test system to be in a hard switch test mode, wherein from the third moment to the fourth moment, PWM2 controls the second gallium nitride device to be in a conducting state; from the fourth moment to the seventh moment, PWM2 controls the second gallium nitride device to be in a cut-off state; from the seventh moment to the eighth moment, PWM2 controls the second gallium nitride device to be in a conducting state;

[0019] When the terminal 1 of the switch unit is connected to the terminal 3, the control signal makes the test system in the soft switching test mode, wherein from the first moment to the second moment, PWM1 controls the first gallium nitride device to be in the on state; from the second moment to the fifth moment, PWM1 controls the first gallium nitride device to be in the off state; from the fifth moment to the sixth moment, PWM1 controls the first gallium nitride device to be in the on state; from the third moment to the fourth moment, PWM2 controls the second gallium nitride device to be in the on state; from the fourth moment to the seventh moment, PWM2 controls the second gallium nitride device to be in the off state; from the seventh moment to the eighth moment, PWM2 controls the second gallium nitride device to be in the on state; by applying a narrow pulse to the accompanying device before the device under test is turned on, the device under test can discharge the load inductance before turning on, thereby realizing zero voltage turn-on to meet the test requirements of soft switching.

[0020] S3, when the third GaN device is turned off, the voltage between the test points AB can be calculated by V CC -V TH Calculate and select a suitable second voltage source so that the V measured on the oscilloscope is AB The size can meet the measurement accuracy requirements. When the third gallium nitride device is turned on, since the on-resistance of the third gallium nitride device is much smaller than that of the second gallium nitride device, the cathode of the Zener diode and the anode of the Schottky diode are selected as two test points, and the voltage difference between the test points is equal to the on-voltage of the second gallium nitride device; the voltage measured between the seventh moment and the eighth moment is selected as the required on-voltage V of the device under test. AB ;

[0021] S4. Calculate the current flowing through the coaxial resistor based on the voltage drop across the coaxial resistor, i.e., the drain-source current of the device under test, V AB The ratio of it is the dynamic on-resistance.

[0022] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0023] 1. The present invention can clamp the voltage value of the test point to within 5V, while controlling the voltage spike introduced by the clamping circuit to a lower level, allowing the oscilloscope to display the on-voltage more accurately without distortion of the internal amplifier, thereby improving the measurement accuracy of the dynamic on-resistance.

[0024] 2. The present invention can respectively realize soft switching test and hard switching test of dynamic on-resistance, and overcomes the resonance phenomenon that may be caused by the loop inductance and the output capacitance of the accompanying test tube through zero voltage and zero current technology, so that the oscillation in the switching process of the device under test is greatly reduced, and the test accuracy is improved.

[0025] 3. The clamping circuit used in the present invention greatly reduces the parasitic capacitance of the Zener diode in the clamping circuit by connecting the Schottky diode and the Zener diode in series, thereby reducing the charging and discharging time and effectively reducing the test response delay. At the same time, the series resistor after the Zener diode can avoid the heating of the Zener diode due to the large current in the frequent switching process during multi-pulse testing, and the test system is more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A structural diagram of a dynamic on-resistance test circuit based on a gallium nitride transistor provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of a clamping circuit of a dynamic on-resistance test circuit based on a gallium nitride transistor provided in an embodiment of the present application;

[0028] Figure 3 The schematic diagram of the on-state voltage of the device under test measured after the clamping circuit is introduced;

[0029] Figure 4 The control signal timing diagram required to realize hard switching test and soft switching test respectively;

[0030] Figure 5 is an equivalent circuit diagram of hard switch and soft switch test in the present invention;

[0031] Figure 6 It is a schematic diagram of the zero voltage turn-on waveform in the present invention;

[0032] Figure 7 This is the dynamic on-resistance simulation test effect diagram.

[0033] The numbers in the accompanying drawings are: DC, direct current power supply; Vcc, second voltage source; C1, first capacitor; C2, second capacitor; C3, third capacitor; R1, first resistor; R2, second resistor; R3, coaxial resistor; R4, fourth resistor; Q1, first gallium nitride device; Q2, second gallium nitride device; Q3, third gallium nitride device; D1, Schottky diode; Dz, Zener diode; L, load inductance. DETAILED DESCRIPTION

[0034] The present invention will be further explained below in conjunction with the detailed description of the accompanying drawings so that those skilled in the art can have a deeper understanding of the present invention and be able to implement it. However, the reference examples below are only used to explain the present invention and are not intended to limit the present invention.

[0035] like Figure 1As shown, a dynamic on-resistance test circuit based on a gallium nitride transistor includes a DPT test circuit, a switch state switching circuit, and a clamping circuit. The DPT test circuit includes a direct current power supply DC, a first capacitor C1, a coaxial resistor R3, a control signal, a gate drive, a first gallium nitride device Q1, and a second gallium nitride device Q2. The direct current power supply DC is used to charge the first capacitor C1, i.e., the bus capacitor, to maintain the stability of the test voltage. The first gallium nitride device Q1 is a companion test tube, which provides a freewheeling path for the load inductor L when the device under test is turned off. The second gallium nitride device Q2 is a device under test, and a clamping circuit for testing the on-voltage is connected in parallel at both ends. The coaxial resistor R3 is used to measure the current flowing through the device under test.

[0036] The direct current power source DC is respectively connected to one end of the first capacitor C1, one end of the switch state switching circuit and the drain end of the first gallium nitride device Q1; the other end of the switch state switching circuit is respectively connected to one end of the coaxial resistor R3, the other end of the direct current power source DC and the other end of the first capacitor C1; the source end of the first gallium nitride device Q1 is respectively connected to the drain end of the second gallium nitride device Q2, the output end of the switch state switching circuit and one end of the clamping circuit; the source end of the second gallium nitride device Q2 is respectively connected to the other end of the clamping circuit and the other end of the coaxial resistor R3 and is grounded; the gate drive is respectively connected to the gate of the first gallium nitride device Q1 and the gate of the second gallium nitride device Q2; the input end of the clamping circuit is connected to the drain end of the second gallium nitride device Q2; and the output end of the clamping circuit is connected to the source end of the second gallium nitride device Q2.

[0037] The switch state switching circuit includes a second capacitor C2, a third capacitor C3, a first resistor R1, a second resistor R2, a switch unit S, and a load inductor L; one end of the second capacitor C2 is respectively connected to one end of the first resistor R1 and two ends of the switch unit S; the other end of the second capacitor C2 is respectively connected to the other end of the first resistor R1, one end of the third capacitor C3, one end of the second resistor R2, and three ends of the switch unit S; the other end of the third capacitor C3 is connected to the other end of the second resistor R2; one end of the switch unit S is connected to one end of the load inductor L. Since the second capacitor C2 and the third capacitor C3 are connected in series, the output capacitor has been charged to the initial value before the gate signal arrives. Therefore, it can be forced to work in a pulse mode but stable state without the need for an initial pre-charging process of the output capacitor.

[0038] The second capacitor C2 and the third capacitor C3 of the switch state switching circuit are of the same size; the first resistor R1 and the second resistor R2 are of the same size. Here, the voltage drop across the second capacitor and the third capacitor can be determined by the first resistor R1 and the second resistor R2, which enables the switch state switching circuit to directly enter a stable state with different duty cycles in a multi-pulse test mode. Here, the first resistor R1 and the second resistor R2 are selected to be the same in order to match a 50% duty cycle.

[0039] The clamping circuit includes a third gallium nitride device Q3, a second voltage source Vcc, a Schottky diode D1, a Zener diode Dz, and a fourth resistor R4; the drain end of the third gallium nitride device Q3 is connected to the drain end of the second gallium nitride device Q2; the source end of the third gallium nitride device Q3 is connected to the cathode of the Zener diode Dz; the anode of the Zener diode Dz is connected to one end of the fourth resistor R4 and the cathode of the Schottky diode D1; the anode of the second voltage source Vcc is connected to the gate of the third gallium nitride device Q3; the cathode of the second voltage source Vcc is connected to the anode of the Schottky diode D1 and the other end of the fourth resistor R4, respectively, and is connected to the source end of the second gallium nitride device Q2.

[0040] The withstand voltage of the third gallium nitride device Q3 in the clamping circuit should be greater than or equal to the withstand voltage of the second gallium nitride device Q2.

[0041] The third gallium nitride device Q3 is an enhancement-mode gallium nitride device and its on-resistance is much smaller than the on-resistance of the second gallium nitride device Q2.

[0042] The working state of the clamp circuit can be divided into two processes: the off state and the on state of the device under test. When the device under test is in the off state, the voltage added by the second voltage source Vcc to the gate of the third GaN device makes the third GaN device conduct, and the source voltage of the third GaN device starts to rise. When the source voltage rises and the gate-source voltage is less than the threshold voltage, the third GaN device starts to turn off again, thereby establishing a voltage balance. The clamp voltage V AB is the difference between the second voltage source Vcc and the threshold voltage of the third GaN device, such as Figure 2 As shown. When the device under test is turned on, the voltage across the device under test drops, the gate-source voltage of the third GaN device is greater than the threshold voltage, and the transistor is fully turned on. Since the on-resistance of the selected third GaN device is much smaller than that of the second GaN device, the voltage drop on the third GaN device can be ignored. At this time, the voltage between the measurement points A and B is the on-voltage of the device under test. The Zener diode can reduce the clamping voltage spike caused by the drain-source parasitic capacitance of the third GaN device. In the traditional clamping circuit, this spike may even be several times the clamping voltage, such as Figure 3 At the same time, the fourth resistor connected in series after the Zener diode can avoid the heating of the Zener diode due to the large current in the frequent switching process during multi-pulse testing, and the test system is more stable. In addition, the Schottky diode connected in series with the Zener diode further reduces the charging and discharging time of the internal capacitance of the Zener diode, thereby greatly reducing the response delay of the test.

[0043] A method for testing dynamic on-resistance of a gallium nitride transistor comprises the following steps:

[0044] S1, a DC power supply supplies power to the first capacitor C1 and the load inductor L.

[0045] When the control signals PWM1 and PWM2 of the first gallium nitride device Q1 and the second gallium nitride device Q2 are respectively switched to different ports by the switch unit S, Figure 4 The pulse waveform shown is used to control the second gallium nitride device Q2 to be in a soft switching or hard switching test state.

[0046] When the terminal 1 of the switch unit S is connected to the terminal 2, the control signal makes the test system in the hard switch test mode, wherein from the third moment to the fourth moment, PWM2 controls the second gallium nitride device Q2 to be in the on state; from the fourth moment to the seventh moment, PWM2 controls the second gallium nitride device Q2 to be in the off state; from the seventh moment to the eighth moment, PWM2 controls the second gallium nitride device Q2 to be in the on state. The hard switch equivalent schematic diagram is shown in FIG. Figure 5 As shown in (a), at this time, the companion device acts as a freewheeling tube to provide a path for reverse conduction when the device under test is turned off.

[0047] When the terminal 1 of the switch unit S is connected to the terminal 3, the control signal makes the test system in the soft switching test mode, wherein from the first moment to the second moment, PWM1 controls the first gallium nitride device Q1 to be in the on state; from the second moment to the fifth moment, PWM1 controls the first gallium nitride device Q1 to be in the off state; from the fifth moment to the sixth moment, PWM1 controls the first gallium nitride device Q1 to be in the on state; from the third moment to the fourth moment, PWM2 controls the second gallium nitride device Q2 to be in the on state; from the fourth moment to the seventh moment, PWM2 controls the second gallium nitride device Q2 to be in the off state; from the seventh moment to the eighth moment, PWM2 controls the second gallium nitride device Q2 to be in the on state.

[0048] The equivalent schematic diagram of soft switching is as follows Figure 5 (b) During t1-t2, a narrow pulse gate signal is provided to the first GaN device Q1. Q1 is turned on for a short period of time, the load inductor is charged, and the load current I L Increase to a smaller value. During the dead time t2-t3, the parasitic capacitance of Q2 discharges to the load inductance, so the drain-source voltage of Q2 begins to drop. When the drain-source voltage drops to zero, the channel of Q2 begins to reverse conduct, and a small reverse current flows through the device under test. The waveform diagram is shown in the figure. Figure 6 Subsequently, Q2 can be turned on with zero voltage at time t3, thereby achieving soft switching of the device under test.

[0049] S3, when the third GaN device Q3 is turned off, the voltage between the test points A and B can be calculated by V CC -V THCalculate and select a suitable DC voltage source V CC , so that the V measured on the oscilloscope AB The size of can meet the measurement accuracy requirements. When the third gallium nitride device Q3 is turned on, since the on-resistance of the third gallium nitride device Q3 is much smaller than that of the second gallium nitride device Q2, the Zener diode D Z The negative electrode of the device under test and the positive electrode of the Schottky diode D1 are two test points. The voltage difference between the test points is equal to the turn-on voltage of the second GaN device Q2. The V AB As the on-state voltage of the device under test.

[0050] S4. The current flowing through is calculated based on the voltage drop on the coaxial resistor R3, i.e., the drain-source current of the device under test. The dynamic on-resistance of the device can be obtained by Ohm's law. The simulation test delay effect diagram is shown in Figure 7 shown.

[0051] Compared with the traditional test circuit, the present invention can use the improved clamping circuit to clamp the on-voltage of the device under test to a lower value, while greatly reducing the additional voltage spikes caused by the introduction of active devices, allowing the oscilloscope to display the on-voltage more accurately without distortion of the internal amplifier, thereby improving the measurement accuracy of the dynamic on-resistance. In addition, most traditional test circuits still use hard switching conditions for testing. The present invention can respectively implement soft switching tests and hard switching tests for dynamic on-resistance, and greatly reduce the oscillation during the switching conversion process of the device under test through zero voltage technology, thereby improving the test accuracy. The innovation of the present invention lies in connecting the Schottky diode and the Zener diode in the clamping circuit in series, which greatly reduces the parasitic capacitance of the Zener diode in the clamping circuit, thereby reducing the charging and discharging time and effectively reducing the test response delay. At the same time, the series resistance after the Zener diode can avoid the heating of the Zener diode due to the large current in the frequent switching conversion process during multi-pulse testing, and the test system is more stable.

[0052] The specific implementation scheme described above further describes in detail the purpose, technical scheme and beneficial effects of the present invention. It should be understood that the above is only a specific implementation scheme of the present invention and is not intended to limit the scope of the present invention. Any equivalent changes and modifications made by any technician in the field without departing from the concept and principle of the present invention should fall within the scope of protection of the present invention.

Claims

1. A dynamic on-resistance test circuit based on gallium nitride transistor, characterized in that: It includes a DPT test circuit, a switch state switching circuit and a clamping circuit; wherein the DPT test circuit includes a direct current power supply (DC), a first capacitor (C1), a coaxial resistor (R3), a control signal, a gate drive, a first gallium nitride device (Q1), and a second gallium nitride device (Q2); The direct current power supply (DC) is respectively connected to one end of the first capacitor (C1), one end of the switch state switching circuit and the drain end of the first gallium nitride device (Q1); the other end of the switch state switching circuit is respectively connected to one end of the coaxial resistor (R3), the other end of the direct current power supply (DC) and the other end of the first capacitor (C1); the source end of the first gallium nitride device (Q1) is respectively connected to the drain end of the second gallium nitride device (Q2), the output end of the switch state switching circuit and one end of the clamping circuit; the source end of the second gallium nitride device (Q2) is respectively connected to the other end of the clamping circuit and the other end of the coaxial resistor (R3) and is grounded; the gate drive is respectively connected to the gate of the first gallium nitride device (Q1) and the gate of the second gallium nitride device (Q2); wherein the first gallium nitride device is a companion device and the second gallium nitride device is a device to be tested; the input end of the clamping circuit is connected to the drain end of the second gallium nitride device (Q2); and the output end of the clamping circuit is connected to the source end of the second gallium nitride device (Q2).

2. A dynamic on-resistance test circuit based on gallium nitride transistor according to claim 1, characterized in that: The switch state switching circuit includes a second capacitor (C2), a third capacitor (C3), a first resistor (R1), a second resistor (R2), a switch unit (S), and a load inductor (L); One end of the second capacitor (C2) is respectively connected to one end of the first resistor (R1) and two ends of the switch unit (S); the other end of the second capacitor (C2) is respectively connected to the other end of the first resistor (R1), one end of the third capacitor (C3), one end of the second resistor (R2) and three ends of the switch unit (S); the other end of the third capacitor (C3) is connected to the other end of the second resistor (R2); one end of the switch unit (S) is connected to one end of the load inductance (L).

3. A dynamic on-resistance test circuit based on gallium nitride transistor according to claim 2, characterized in that: The second capacitor (C2) and the third capacitor (C3) of the switch state switching circuit have the same size; the first resistor (R1) and the second resistor (R2) have the same size to match the 50% duty cycle during multi-pulse testing.

4. The dynamic on-resistance test circuit based on gallium nitride transistor according to claim 1, characterized in that: The clamping circuit includes a third gallium nitride device (Q3), a second voltage source (Vcc), a Schottky diode (D1), a Zener diode (Dz), and a fourth resistor (R4); The drain end of the third gallium nitride device (Q3) is connected to the drain end of the second gallium nitride device (Q2); the source end of the third gallium nitride device (Q3) is connected to the cathode of the Zener diode (Dz); the anode of the Zener diode (Dz) is connected to one end of the fourth resistor (R4) and the cathode of the Schottky diode (Dz); the anode of the second voltage source (Vcc) is connected to the gate of the third gallium nitride device (Q3); the cathode of the second voltage source (Vcc) is respectively connected to the anode of the Schottky diode (D1) and the other end of the fourth resistor (R4) to the source end of the second gallium nitride device (Q2).

5. A dynamic on-resistance test circuit based on gallium nitride transistor according to claim 4, characterized in that: The withstand voltage value of the third gallium nitride device (Q3) in the clamping circuit is greater than or equal to the withstand voltage value of the second gallium nitride device (Q2).

6. A dynamic on-resistance test circuit based on gallium nitride transistor according to claim 4, characterized in that: The third gallium nitride device (Q3) is an enhanced gallium nitride device and its on-resistance is much smaller than the on-resistance of the second gallium nitride device (Q2).

7. A method for testing dynamic on-resistance of a gallium nitride transistor according to any one of claims 1 to 6, characterized in that: The steps include: S1, a DC power supply supplies power to the first capacitor (C1), the load inductor (L) and; S2, control signals PWM1 and PWM2 of the first gallium nitride device (Q1) and the second gallium nitride device (Q2) respectively generate different pulse waveforms when switching the switch unit (S) to different ports to control the second gallium nitride device (Q2) to be in a soft switching or hard switching test state; S3, when the third GaN device (Q3) is turned off, the voltage between test points A and B is V CC -V TH Calculate and select the preset DC voltage source (V CC ), so that the V AB The size of meets the measurement accuracy requirement; when the third gallium nitride device (Q3) is turned on, since the on-resistance of the third gallium nitride device (Q3) is much smaller than that of the second gallium nitride device (Q2), a Zener diode (D Z ) and the anode of the Schottky diode (D1) are two test points, and the voltage difference between the test points is equal to the on-voltage of the second gallium nitride device (Q2); the voltage measured between the seventh moment and the eighth moment is selected as the required on-voltage V of the device under test AB ; S4. Calculate the current flowing through the coaxial resistor (R3) according to the voltage drop across the coaxial resistor (R3), i.e., the drain-source current of the device under test. The V measured in step S3 is AB The ratio of it is the dynamic on-resistance.

8. The testing method according to claim 7, characterized in that: Step S2 specifically includes: when the terminal 1 of the switch unit (S) is connected to the terminal 2, the control signal makes the test system be in a hard switch test mode, wherein from the third moment to the fourth moment, PWM2 controls the second gallium nitride device (Q2) to be in a conducting state; from the fourth moment to the seventh moment, PWM2 controls the second gallium nitride device (Q2) to be in a cut-off state; from the seventh moment to the eighth moment, PWM2 controls the second gallium nitride device (Q2) to be in a conducting state; When the terminal 1 of the switch unit (S) is connected to the terminal 3, the control signal causes the test system to be in a soft switching test mode, wherein from the first moment to the second moment, PWM1 controls the first gallium nitride device (Q1) to be in a conducting state; from the second moment to the fifth moment, PWM1 controls the first gallium nitride device (Q1) to be in a cut-off state; from the fifth moment to the sixth moment, PWM1 controls the first gallium nitride device (Q1) to be in a conducting state; from the third moment to the fourth moment, PWM2 controls the second gallium nitride device (Q2) to be in a conducting state; from the fourth moment to the seventh moment, PWM2 controls the second gallium nitride device (Q2) to be in a cut-off state; from the seventh moment to the eighth moment, PWM2 controls the second gallium nitride device (Q2) to be in a conducting state.

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