Multi-cycle average tap delay line type TDC (time-to-digital converter) implementation method and system based on FPGA (field programmable gate array)
By using long delay tap delay line and multi-period averaging methods in FPGA, the synchronization difficulties and multi-fan-out problems of tap delay TDC under multi-channel carry chain resources are solved, and higher time measurement accuracy and stability are achieved. Simplifies the coding process and reduces resource usage.
Patent Information
- Application Number
- CN202411403450.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-01-03
AI Technical Summary
The existing FPGA-based tap delay TDC has difficulty in synchronizing and multi-fan-out problems in HIT signals when performing fine-time measurement of multi-channel carry chain resources, resulting in reduced FPGA wiring stability, which is not conducive to timing convergence.
A long delay tap delay line is adopted to vertically utilize the delay unit resources through the multi-period averaging method to achieve the resolution and accuracy of the tap delay line TDC, avoiding the problem of multiple fanouts, and using lookup tables and addition trees in the encoding module Reduce resource occupation and 'bubbly' interference.
It effectively improves the resolution and accuracy of time measurement, eliminates the negative impact of multiple fanouts on FPGA wiring stability, simplifies decoder design and reduces the difficulty of correcting the 'bubble' problem.
Smart Images
Figure CN119247724A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of digital measurement technology, and relates to digital measurement technology, and specifically to a method and system for realizing a multi-cycle average tapped delay line type TDC based on FPGA. Background Art
[0002] The tapped delay line time digital converter (TDC) based on field programmable gate array (FPGA) is a commonly used high-resolution and high-precision time measurement method. It constructs a tapped delay line (TDL) composed of delay units, and each node is read out by a register. The input single-edge HIT signal is transmitted on the TDL, and when the clock rising edge arrives, the thermometer code read out by these registers can reflect the size of the fine time.
[0003] The resolution and accuracy of the above-mentioned fine time are limited by the physical length of the FPGA delay unit; in order to break through the hardware limitation of the delay unit, an averaging method is usually used. There are currently three main solutions for averaging the tap-delay TDC: the first is the Wave-Union A type solution, in which each HIT signal triggers a multi-edge signal to be transmitted on the TDL, and multiple edges are measured simultaneously, and the measured data is decoded to obtain the average result; and the simultaneous measurement of multiple edges greatly increases the complexity of subsequent decoding and the difficulty of correcting the "bubble" problem. The second is the Wave-Union B type solution, in which the input HIT signal triggers a periodic oscillation on the TDL, and the edges of the signal are repeatedly measured in the next multiple cycles, and the measurement results are decoded to obtain the average result; and the stability of the periodic oscillation will affect the measurement accuracy, and this solution will increase the dead time of the test. The third is a multi-chain averaging scheme, in which the input HIT signal will fan out to multiple TDLs for propagation, and multiple TDLs will be measured simultaneously within one clock cycle. The measured data will be decoded to obtain the average result. In order to obtain higher-precision time measurement indicators, this scheme needs to consume more carry chain resources. At the same time, this scheme has synchronization difficulties and multiple fan-out problems of HIT signals. The multiple fan-out problem will seriously affect the stability of FPGA wiring and is not conducive to timing convergence.
[0004] The prior art (invention patent application with publication number CN114637182A) discloses a TDC fine time measurement system and method based on FPGA carry chain. The system includes: a fixed delay chain module, used to generate multiple delay signals corresponding to the pulse signal to be measured; a carry chain module, used to generate the carry chain logic required to measure the fine time based on the multiple delay signals; a carry chain running position value calculation module, used to extract and calculate the carry chain running position value based on the carry chain logic; an equivalent carry chain average delay calculation module, used to calculate the equivalent average delay of the carry chain module based on the carry chain running position value; a fine time output module, used to calculate the fine time value based on the equivalent average delay and the carry chain running position value. While improving the sensitivity and accuracy of fine time measurement, this solution also improves the stability of the measurement system and reduces the impact of temperature and voltage changes. It has the advantages of simple structure, low calculation complexity, easy implementation and fast response time.
[0005] The above-mentioned fine time measurement system uses multiple channel carry chain resources for fine time measurement; in order to obtain higher-precision time measurement indicators, more carry chain resources need to be consumed; at the same time, this solution has synchronization difficulties and HIT signal multi-fan-out problems, among which the multi-fan-out problem will seriously affect the stability of FPGA wiring and is not conducive to timing convergence.
[0006] Therefore, a method and system for realizing a multi-cycle average tapped delay line TDC based on FPGA is needed to solve the problems existing in the current averaging scheme of tapped delay TDC. Summary of the invention
[0007] The present application aims to solve at least one of the technical problems existing in the prior art; to this end, the present application proposes a multi-cycle average tapped delay line TDC implementation method and system based on FPGA, which is used to solve the technical problems that when the existing multiple channel carry chain resources are used for fine time measurement; there are synchronization difficulties and HIT signal multi-fan-out problems, which lead to reduced stability of FPGA wiring and are not conducive to timing convergence. The present application solves the above problems by adopting a long delay tapped delay line to realize the vertical utilization of delay unit resources.
[0008] To achieve the above objectives, the first aspect of the present application provides a multi-cycle average tapped delay line TDC implementation system based on FPGA.
[0009] It includes: a tap delay chain module, an encoding module, an edge detection module, a nonlinear correction module and a coarse counting module;
[0010] The tap delay chain module is a long-delay tap delay line; it includes a number of delay units and registers, and the delay units correspond to the registers one by one; it is used to generate a set of thermometer codes corresponding to the single-edge HIT signal;
[0011] The encoding module is used to generate a binary code corresponding to the thermometer code;
[0012] The edge detection module: obtains a set of binary codes from the encoding module in each clock cycle; obtains the number of clock cycles N, and obtains the binary code and the corresponding flag signal corresponding to N delay cycles after the arrival of the single edge HIT signal through the beat delay;
[0013] The nonlinear correction module: obtains binary codes of N delay periods, superimposes the binary codes of the N delay periods to obtain a set of superimposed binary codes; searches in a lookup table based on the superimposed binary codes to obtain corresponding fine time;
[0014] The present application establishes N measurement results and a lookup table with fine time in the nonlinear correction module according to the code density measurement results; during the formal measurement, the single-edge HIT signal is input to the tap delay chain module for propagation, and the tap delay module only includes a long tap delay line TDL; the tap delay chain module outputs a set of thermometer codes on the rising edge of each clock, and sends the thermometer codes to the encoding module for encoding to obtain the corresponding binary codes; the edge monitoring module obtains the binary codes, and performs beat delay according to the binary codes to obtain the binary codes and corresponding flag signals of N cycles after the input single-edge HIT signal arrives; the nonlinear correction module obtains N cycles The binary codes of the N periods are obtained by superimposing the binary codes to obtain superimposed binary codes, the corresponding fine time is found according to the N superimposed binary codes and the lookup table, and the fine time is output; the present application further improves the resolution and accuracy of the tapped delay line TDC by a multi-cycle averaging method, breaking through the hardware limitation of the delay unit; the single-edge HIT signal has the advantages of less fan-out, which can effectively improve the time measurement resolution and accuracy; the present application is implemented on a long tapped delay line TDL by setting a tapped delay line, vertically utilizing the delay unit resources, without the problem of multiple fan-out, and will not affect the stability and timing convergence of FPGA wiring.
[0015] Preferably, the coarse counting module is composed of several counters: used to output the coarse time of the system; the module counts the counter at the rising edge of each clock cycle; when the first flag signal of the arrival of the single-edge HIT signal is obtained from the edge detection module, the value of the current counter is output, and the product of the value and the clock cycle is the coarse time of the system.
[0016] Preferably, each delay unit in the tapped delay chain module corresponds to a delay duration; and the total delay duration of each delay unit in the tapped delay chain module is greater than or equal to the total duration of N clock cycles.
[0017] The present application is implemented on a long TDL by setting a tapped delay line, and there is no problem of multiple fan-out, which will not affect the stability and timing convergence of FPGA wiring.
[0018] Preferably, the generating of the binary code corresponding to the thermometer code comprises the following steps:
[0019] A1: Get 795 bits of thermometer code per cycle;
[0020] A2: The 795-bit thermometer code is passed through a lookup table group consisting of several 2-LUT4 lookup tables to obtain the 2-bit binary sum of several 3-bit thermometer codes;
[0021] A3: Use an addition tree to add the binary sum to obtain an 11-bit binary code.
[0022] In the first stage of this application, a 2-bit binary sum of a 3-bit thermometer code is generated through a group of 2 LUT4 lookup tables; subsequently, the addition operation of several 2-bit binary sums is implemented by means of an addition tree, and finally the binary code corresponding to the thermometer code is obtained; the core of the encoding module is to implement the recursive call of the module implemented in the FPGA, which greatly reduces the resource usage and effectively reduces the interference of the "bubble" problem on the thermometer code.
[0023] Preferably, the binary code and the corresponding flag signal corresponding to N delay periods after the arrival of the single-edge HIT signal obtained by beat delay include:
[0024] B1: Get a set of 11-bit binary code out from the decoding module in each clock cycle;
[0025] B2: The binary code out is beat once through the primary register to obtain the binary code FF1_out of one delay cycle; the binary code out is beat N times through the N secondary registers to obtain the binary code FFN_out of N delay cycles;
[0026] B3: When the binary code FF1_out is "0" and the binary code out is not "0", the binary code out is set to the first clock rising edge fine count Data_1; and its corresponding flag signal Flag_1 is set to 1 in the clock cycle; when the j-th binary code FFj_out is "0" and the binary code FFj-x_out and the binary code out are both not "0", the binary code out is set to the j-th clock rising edge fine count Data_j; and its corresponding flag signal Flag_j is set to 1 in the clock cycle; wherein, x=1, 2, ..., j-1, and the binary codes and corresponding flag signals corresponding to N delay cycles are obtained in turn.
[0027] Preferably, the binary codes of the N delay periods are superimposed to obtain a set of superimposed binary codes, including:
[0028] C1: Get the binary code of N delay cycles;
[0029] C2: Summing the 1st to jth binary codes by binary addition to obtain the superimposed binary code corresponding to the jth delay period;
[0030] C3: Count and obtain the superimposed binary codes of each delay period, and integrate several superimposed binary codes into a group of superimposed binary codes.
[0031] Preferably, the lookup table is obtained by the following steps:
[0032] D1: Obtain a single-edge HIT signal that is unrelated to the sampling clock, and obtain a corresponding set of thermometer codes by passing the HIT signal through a tap delay module;
[0033] D2: Input a set of thermometer codes into the encoding module to obtain the corresponding binary code;
[0034] D3: Input the binary code into the edge detection module to obtain the binary code corresponding to N delay cycles;
[0035] D4: superimpose N binary codes to obtain a set of superimposed binary codes;
[0036] D5: The code density Wi of the superimposed binary code numbered i is calculated by the formula Wi = T × Ni / N; where T is the clock period of the TDC system; Ni is the number of times the single-edge HIT signal hits the i-th binary superimposed code; and N is the total number of single-edge HIT signals;
[0037] The fine time Ti corresponding to the superimposed binary code numbered i is calculated by the formula Ti=∑(Wk)+Wi / 2; wherein k=0, 1, ..., i-1;
[0038] D6: Establish a lookup table between the superimposed binary code and its corresponding fine time.
[0039] The second aspect of the present application provides a method for implementing a multi-cycle average tapped delay line TDC based on FPGA, comprising the following steps:
[0040] Step 1: Get single edge HIT signal;
[0041] Step 2: Sampling once in each clock cycle to obtain a set of thermometer codes corresponding to the single-edge HIT signal;
[0042] Step 3: Convert a set of thermometer codes corresponding to each clock cycle into binary code;
[0043] Step 4: delay the binary code corresponding to each clock cycle to obtain the binary code of N delayed cycles corresponding to each clock cycle and the corresponding flag signal;
[0044] Step 5: Superimpose the binary codes of N delay periods to obtain superimposed binary codes;
[0045] Step 6: Look up the corresponding fine time in the lookup table according to the superimposed binary code;
[0046] Step 7: When the flag signal of the first clock cycle after the single-edge HIT signal arrives is high, the current coarse time is output.
[0047] Compared with the prior art, the beneficial effects of this application are:
[0048] 1. The present application establishes N measurement results and a lookup table with fine time in the nonlinear correction module according to the code density measurement results; during the formal measurement, the single-edge HIT signal is input into the tapped delay chain module for propagation, and the tapped delay module only includes a long tapped delay line TDL; the tapped delay chain module outputs a set of thermometer codes at the rising edge of each clock, and sends the thermometer codes to the encoding module for encoding to obtain the corresponding binary code; the edge monitoring module obtains the binary code, and performs a beat delay according to the binary code to obtain the binary code and the corresponding flag signal of N cycles after the arrival of the input single-edge HIT signal; the nonlinear correction module obtains the binary code of N cycles, and superimposes the binary code to obtain the superimposed binary code, searches for the corresponding fine time according to the N superimposed binary codes and the lookup table, and outputs the fine time; the present application is implemented on a long tapped delay line TDL by setting a tapped delay line, vertically utilizing the delay unit resources, without the problem of multiple fan-outs, and will not affect the stability and timing convergence of the FPGA wiring.
[0049] 2. In the first stage of the present application, a 2-bit binary sum of a 3-bit thermometer code is generated through a group of 2 LUT4 lookup tables; subsequently, the addition operation of several 2-bit binary sums is realized by means of an addition tree, and finally the binary code corresponding to the thermometer code is obtained; the core of the encoding module is to realize the recursive call of the module implemented in the FPGA, which greatly reduces the resource occupation; at the same time, the encoding method of the present application is consistent with the traditional single-chain TDC, which is simpler than the Wave-Union type decoding; and a mature anti-"bubble" algorithm can be used to effectively reduce the interference of the "bubble" problem on the thermometer code; making the "bubble" problem less difficult to correct. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0051] Figure 1 This is a schematic diagram of the principle of this application;
[0052] Figure 2 This is the working sequence diagram of this application;
[0053] Figure 3 This is a working principle diagram of the encoding module in this application;
[0054] Figure 4 This is the working timing diagram of the edge detection module in this application;
[0055] Figure 5 This is a diagram of the method steps of this application. DETAILED DESCRIPTION
[0056] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0057] See also Figure 1-Figure 2 The first aspect of the present application provides a multi-cycle average tapped delay line TDC implementation system based on FPGA,
[0058] It includes: a tap delay chain module, an encoding module, an edge detection module, a nonlinear correction module and a coarse counting module;
[0059] The tap delay chain module is a long-delay tap delay line; it includes several delay units and registers, and the delay units correspond to the registers one by one; a fixed number of continuous delay units and their corresponding registers are set as a delay chain of one cycle; several delay units and registers in the tap delay chain model are divided into a delay chain of N cycles; it is used to generate a set of thermometer codes corresponding to a single-edge HIT signal; the single-edge HIT signal is input into the tap delay module, the number of clock cycles N is set, and a set of thermometer codes is obtained at the rising edge of each clock cycle in the N clock cycles; by constructing a long delay chain and adopting a multi-cycle averaging method, the division of ultra-wide delay units across clock domains is realized at a high sampling clock frequency, and there is no ultra-wide delay unit in the averaged TDL code density; this allows the delay unit resources to be utilized vertically. The clock cycle is the clock adoption cycle built into the TDC fine time measurement system;
[0060] Encoding module: used to generate binary code corresponding to the thermometer code;
[0061] Edge detection module: obtains a set of binary codes from the encoding module in each clock cycle; obtains the number of clock cycles N, and obtains the binary code and corresponding flag signal corresponding to N delay cycles after the arrival of the single edge HIT signal through beat delay;
[0062] Nonlinear correction module: obtaining binary codes of N delay periods, superimposing the binary codes of the N delay periods to obtain a set of superimposed binary codes; searching in a lookup table based on the superimposed binary codes to obtain corresponding fine time;
[0063] Figure 2 Where tdc_cik is the clock signal; start_hit is the single-edge HIT signal at the start; stop_hit is the single-edge HIT signal at the end; tcoarse is the coarse time; tst_fine1, tsp_fine, etc. are the corresponding fine times;
[0064] In this embodiment, N measurement results and a lookup table with fine time are established in the nonlinear correction module according to the code density measurement result; in the formal measurement, the single-edge HIT signal is input to the tap delay chain module for propagation, and the tap delay module only includes a long tap delay line TDL; the tap delay chain module outputs a set of thermometer codes at the rising edge of each clock, and sends the thermometer codes to the encoding module for encoding to obtain the corresponding binary code; the edge monitoring module obtains the binary code, and performs a beat delay according to the binary code to obtain the binary code and the corresponding flag signal of N cycles after the input single-edge HIT signal arrives; the nonlinear correction module obtains the binary code of N cycles The binary code is encoded, and the superimposed binary code is obtained by superimposed binary code. The corresponding fine time is found according to the N times of superimposed binary code and the lookup table, and the fine time is output; at the same time, the coarse counting module outputs the corresponding coarse time at the first clock rising edge of the single-edge HIT signal; the present application further improves the resolution and accuracy of the tapped delay line TDC by a multi-cycle averaging method, breaking through the hardware limitation of the delay unit; at the same time, the present application has the advantages of eliminating the influence of the ultra-wide delay unit, simple decoder design, low difficulty in correcting the "bubble" problem, simple synchronization, and less fan-out of the single-edge HIT signal, which can effectively improve the time measurement resolution and accuracy.
[0065] The coarse counting module is composed of several counters: used to output the coarse time of the system; the module counts the counter at the rising edge of each clock cycle; when the first flag signal of the single-edge HIT signal arrives from the edge detection module, the current counter value is output, and the product of the value and the clock cycle is the coarse time of the system; the flag signal is Figure 1 The middle is the edge mark signal.
[0066] The coarse counting module in this example is composed of a 32-bit counter, which obtains the system coarse time through direct counting method. The coarse counting module counts the counter at each rising edge of the sampling clock, obtains the first flag signal of the arrival of the single-edge HIT signal from the edge detection module, and outputs the current counter value. In the case where the counter reaches the maximum value and resets, the relevant circuit in the FPGA eliminates it through screening.
[0067] Each delay unit in the tapped delay chain module corresponds to a delay duration; the total delay duration of each delay unit in the tapped delay chain module is greater than or equal to the total duration of N clock cycles.
[0068] This embodiment is implemented on a long tapped delay line TDL by setting a tapped delay line, and does not have the problem of multiple fan-outs, and does not affect the stability and timing convergence of FPGA wiring.
[0069] See also Figure 3 , generating a binary code corresponding to the thermometer code, including the following steps:
[0070] A1: Get 795 bits of thermometer code per cycle;
[0071] A2: The 795-bit thermometer code is passed through a lookup table group consisting of several 2-LUT4 lookup tables to obtain the 2-bit binary sum of several 3-bit thermometer codes;
[0072] A3: Use an addition tree to add the binary sum to obtain an 11-bit binary code.
[0073] This embodiment is implemented in the XC7K325TFBG676-1 model FPGA chip; the delay unit in this embodiment uses the Carry4 carry chain resources in the FPGA chip, and each Carry4 can tap out 4 delay units. The final number of delay units used is 795; the system sampling clock frequency is 500MHz, and the corresponding clock period is 2ns. The total delay of TDL must be greater than the size of 4 sampling clock cycles to meet the requirements of the 4-cycle average tapped delay line TDC for TDL delay and sampling clock period. The tapped delay line is implemented on a long TDL, and there is no problem of multiple fan-out, which will not affect the stability and timing convergence of FPGA wiring. The input hit signal is propagated to the tapped delay chain module, and the module outputs a set of thermometer codes per cycle.
[0074] In the first stage of this embodiment, a 2-bit binary sum of a 3-bit thermometer code is generated through a group of 2 LUT4 lookup tables; subsequently, the addition operation of several 2-bit binary sums is implemented by means of an addition tree, and finally the binary code corresponding to the thermometer code is obtained; the core of the encoding module is to implement the recursive call of the module implemented in the FPGA, which greatly reduces the resource occupation; at the same time, the encoding method of the present application is consistent with the traditional single-chain TDC, which is simpler than the Wave-Union type decoding; and a mature anti-"bubble" algorithm can be used to effectively reduce the interference of the "bubble" problem on the thermometer code; making the "bubble" problem less difficult to correct.
[0075] See also Figure 4 , through the beat delay, the binary code and the corresponding flag signal corresponding to N delay cycles after the arrival of the single edge HIT signal are obtained, including:
[0076] B1: Get a set of 11-bit binary code out from the decoding module in each clock cycle;
[0077] B2: The binary code out is beat once through the primary register to obtain the binary code FF1_out of one delay cycle; the binary code out is beat N times through the N secondary registers to obtain the binary code FFN_out of N delay cycles;
[0078] B3: When the binary code FF1_out is "0" and the binary code out is not "0", the binary code out is set to the first clock rising edge fine count Data_1; and its corresponding flag signal Flag_1 is set to 1 in the clock cycle; when the j-th binary code FFj_out is "0" and the binary code FFj-x_out and the binary code out are both not "0", the binary code out is set to the j-th clock rising edge fine count Data_j; and its corresponding flag signal Flag_j is set to 1 in the clock cycle; wherein, x=1, 2, ..., j-1, and the binary codes and corresponding flag signals corresponding to N delay cycles are obtained in turn.
[0079] In this embodiment, the edge detection module in this embodiment obtains a set of 11-bit binary codes out from the decoding module in each cycle; the binary code out is beat once through a register to obtain a binary code FF1_out delayed by one cycle; in this embodiment, a 4-cycle average tap delay linear TDC is set, so the delay signal binary codes FF2_out, FF3_out, and FF4_out are obtained by continuing to beat;
[0080] By judging that FF1_out is 0 and out is non-0, the fine count Data_1 corresponding to the first clock rising edge after the arrival of the single-edge HIT signal is set to the binary code out, and the corresponding flag signal Flag_1 is set to 1 in the clock cycle; by judging that FF2_out is 0, FF1_out is non-0, and out is non-0, the fine count Data_2 corresponding to the second clock rising edge after the arrival of the single-edge HIT signal is set to the binary code out, and the corresponding flag signal Flag_2 is set to 1 in the clock cycle; by judging that FF3_out is 0, FF2_out is non-0, FF1_out is non-0, and out is non-0, the fine count Data_3 corresponding to the third clock rising edge after the arrival of the single-edge HIT signal is set to Binary code out, and its corresponding flag signal Flag_3 is set to 1 in the clock cycle; by judging that FF4_out is 0, FF3_out is non-0, FF2_out is non-0, FF1_out is non-0 and out is non-0, the fine count Data_4 corresponding to the fourth clock rising edge after the arrival of the single-edge HIT signal is set to binary code out, and its corresponding flag signal Flag_4 is set to 1 in the clock cycle; in the average tapped delay line TDC of N cycles, the N-th clock rising edge fine count and flag signal after the arrival of the HIT signal in the average tapped delay line TDC of N cycles can be deduced by analogy; the binary code and the corresponding flag signal of N cycles after the arrival of the single-edge HIT signal are detected, making data and clock synchronization simpler and more convenient.
[0081] The binary codes of N delay periods are superimposed to obtain a set of superimposed binary codes, including:
[0082] C1: Get the binary code of N delay cycles;
[0083] C2: Summing the 1st to jth binary codes by binary addition to obtain the superimposed binary code corresponding to the jth delay period;
[0084] C3: Count and obtain the superimposed binary codes of each delay period, and integrate several superimposed binary codes into a group of superimposed binary codes.
[0085] The lookup table is obtained by the following steps:
[0086] D1: Obtain a single-edge HIT signal that is unrelated to the sampling clock, and obtain a corresponding set of thermometer codes by passing the HIT signal through a tap delay module;
[0087] D2: Input a set of thermometer codes into the encoding module to obtain the corresponding binary code;
[0088] D3: Input the binary code into the edge detection module to obtain the binary code corresponding to N delay cycles;
[0089] D4: superimpose N binary codes to obtain a set of superimposed binary codes;
[0090] D5: The code density Wi of the superimposed binary code numbered i is calculated by the formula Wi = T × Ni / N; where T is the clock period of the TDC system; Ni is the number of times the single-edge HIT signal hits the i-th binary superimposed code; and N is the total number of single-edge HIT signals;
[0091] The fine time Ti corresponding to the superimposed binary code numbered i is calculated by the formula Ti=∑(Wk)+Wi / 2; wherein k=0, 1, ..., i-1;
[0092] D6: Establish a lookup table between the superimposed binary code and its corresponding fine time.
[0093] See also Figure 5 The second aspect of the present application provides a method for implementing a multi-cycle average tapped delay line TDC based on FPGA, comprising the following steps:
[0094] Step 1: Get single edge HIT signal;
[0095] Step 2: Sampling once in each clock cycle to obtain a set of thermometer codes corresponding to the single-edge HIT signal;
[0096] Step 3: Convert a set of thermometer codes corresponding to each clock cycle into binary code;
[0097] Step 4: delay the binary code corresponding to each clock cycle to obtain the binary code of N delayed cycles corresponding to each clock cycle and the corresponding flag signal;
[0098] Step 5: Superimpose the binary codes of N delay periods to obtain superimposed binary codes;
[0099] Step 6: Look up the corresponding fine time in the lookup table according to the superimposed binary code;
[0100] Step 7: When the flag signal of the first clock cycle after the single-edge HIT signal arrives is high, the current coarse time is output.
[0101] Part of the data in the above formula is calculated by removing the dimension and taking its numerical value. The formula is a formula closest to the actual situation obtained by software simulation of a large amount of collected data; the preset parameters and preset thresholds in the formula are set by technical personnel in this field according to actual conditions or obtained through simulation of a large amount of data.
[0102] How this application works:
[0103] The present application establishes N measurement results and a lookup table with fine time in the nonlinear correction module according to the code density measurement results; during the formal measurement, the single-edge HIT signal is input to the tap delay chain module for propagation, and the tap delay module only includes a long tap delay line TDL; the tap delay chain module outputs a set of thermometer codes at the rising edge of each clock, and sends the thermometer codes to the encoding module for encoding to obtain the corresponding binary codes; the edge monitoring module obtains the binary codes, and performs beat delay according to the binary codes to obtain the binary codes and corresponding flag signals of N cycles after the input single-edge HIT signal arrives; the nonlinear correction module obtains the binary codes of N cycles The invention adopts a binary encoding method, and superimposes the binary encoding to obtain the superimposed binary encoding, searches for the corresponding fine time according to the N times of superimposed binary encoding and the lookup table, and outputs the fine time; at the same time, the coarse counting module outputs the corresponding coarse time at the first clock rising edge of the single-edge HIT signal; the present application further improves the resolution and accuracy of the tapped delay line TDC by a multi-cycle averaging method, breaking through the hardware limitation of the delay unit; at the same time, the present application has the advantages of eliminating the influence of the ultra-wide delay unit, simple decoder design, low difficulty in correcting the "bubble" problem, simple synchronization, and less fan-out of the HIT signal, which can effectively improve the time measurement resolution and accuracy.
[0104] The above embodiments are only used to illustrate the technical method of the present application and are not intended to limit it. Although the present application has been described in detail with reference to the preferred embodiments, a person of ordinary skill in the art should understand that the technical method of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present application.
Claims
1. A multi-cycle average tapped delay line TDC implementation system based on FPGA, comprising: The tap delay chain module, the encoding module, the edge detection module, the nonlinear correction module and the coarse counting module are characterized in that: The tap delay chain module is a long-delay tap delay line; it includes a number of delay units and registers, and the delay units correspond to the registers one by one; it is used to generate a set of thermometer codes corresponding to the single-edge HIT signal; The encoding module is used to generate a binary code corresponding to the thermometer code; The edge detection module: obtains a set of binary codes from the encoding module in each clock cycle; obtains the number of clock cycles N, and obtains the binary code and the corresponding flag signal corresponding to N delay cycles after the arrival of the single edge HIT signal through the beat delay; The nonlinear correction module: obtains binary codes of N delay periods, superimposes the binary codes of the N delay periods to obtain a set of superimposed binary codes; searches in a lookup table based on the superimposed binary codes to obtain corresponding fine time.
2. The FPGA-based multi-cycle average tapped delay line TDC implementation system according to claim 1, characterized in that: The coarse counting module is composed of several counters: used to output the coarse time of the system; the module counts the counter at the rising edge of each clock cycle; when the first flag signal of the single-edge HIT signal is obtained from the edge detection module, the value of the current counter is output, and the product of the value and the clock cycle is the coarse time of the system.
3. The FPGA-based multi-cycle average tapped delay line TDC implementation system according to claim 1, characterized in that: Each delay unit in the tapped delay chain module corresponds to a delay duration; the total delay duration of the delay units in the tapped delay chain module is greater than or equal to the total duration of N clock cycles.
4. The FPGA-based multi-cycle average tapped delay line TDC implementation system according to claim 1, characterized in that: The step of generating a binary code corresponding to the thermometer code comprises the following steps: A1: Get 795 bits of thermometer code per cycle; A2: The 795-bit thermometer code is passed through a lookup table group consisting of several 2-LUT4 lookup tables to obtain the 2-bit binary sum of several 3-bit thermometer codes; A3: Use an addition tree to add the binary sum to obtain an 11-bit binary code.
5. The FPGA-based multi-cycle average tapped delay line TDC implementation system according to claim 1, characterized in that: The binary code and the corresponding flag signal corresponding to N delay periods after the arrival of the single-edge HIT signal obtained by beat delay include: B1: Get a set of 11-bit binary code out from the decoding module in each clock cycle; B2: The binary code out is beat once through the primary register to obtain the binary code FF1_out of one delay cycle; the binary code out is beat N times through the N secondary registers to obtain the binary code FFN_out of N delay cycles; B3: When the binary code FF1_out is "0" and the binary code out is not "0", the binary code out is set to the first clock rising edge fine count Data_1; at the same time, its corresponding flag signal Flag_1 is set to 1 in the corresponding clock cycle; when the j-th binary code FFj_out is "0", and the binary code FFj-x_out and the binary code out are both not "0"; the binary code out is set to the j-th clock rising edge fine count Data_j; at the same time, its corresponding flag signal Flag_j is set to 1 in the clock cycle; wherein, x=1, 2, ..., j-1, and the binary codes and corresponding flag signals corresponding to N delay cycles are obtained in turn; the clock cycle is.
6. The FPGA-based multi-cycle average tapped delay line TDC implementation system according to claim 1, characterized in that: The binary codes of the N delay periods are superimposed to obtain a set of superimposed binary codes, including: C1: Get the binary code of N delay cycles; C2: Summing the 1st to jth binary codes by binary addition to obtain the superimposed binary code corresponding to the jth delay period; C3: Count and obtain the superimposed binary codes of each delay period, and integrate several superimposed binary codes into a group of superimposed binary codes.
7. The FPGA-based multi-cycle average tapped delay line TDC implementation system according to claim 1, characterized in that: The lookup table is obtained by the following steps: D1: Obtain a single-edge HIT signal that is unrelated to the sampling clock, and obtain a corresponding set of thermometer codes by passing the HIT signal through a tap delay module; D2: Input a set of thermometer codes into the encoding module to obtain the corresponding binary code; D3: Input the binary code into the edge detection module to obtain the binary code corresponding to N delay cycles; D4: superimpose N binary codes to obtain a set of superimposed binary codes; D5: The code density Wi of the superimposed binary code numbered i is calculated by the formula Wi = T × Ni / N; where T is the clock period of the TDC system; Ni is the number of times the single-edge HIT signal hits the i-th binary superimposed code; and N is the total number of single-edge HIT signals; The fine time Ti corresponding to the superimposed binary code numbered i is calculated by the formula Ti=∑(Wk)+Wi / 2; wherein k=0, 1, ..., i-1; D6: Establish a lookup table between the superimposed binary code and its corresponding fine time.
8. A method for implementing a multi-cycle average tapped delay line TDC based on FPGA, based on the operation of a multi-cycle average tapped delay line TDC implementation system based on FPGA according to any one of claims 1 to 7, characterized in that: The following steps are involved: Step 1: Get single edge HIT signal; Step 2: Sampling once in each clock cycle to obtain a set of thermometer codes corresponding to the single-edge HIT signal; Step 3: Convert a set of thermometer codes corresponding to each clock cycle into binary code; Step 4: delay the binary code corresponding to each clock cycle to obtain the binary code of N delayed cycles corresponding to each clock cycle and the corresponding flag signal; Step 5: Superimpose the binary codes of N delay periods to obtain superimposed binary codes; Step 6: Look up the corresponding fine time in the lookup table according to the superimposed binary code; Step 7: When the flag signal of the first clock cycle after the single-edge HIT signal arrives is high, the current coarse time is output.
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TDC fine time measuring system and method based on FPGA carry chain
CN114637182A