System Exception Handling Method, Control System, and Storage Medium

Abstract

The present application relates to a method for system exception handling. First, it is determined whether there is a communication exception between the main processor and the unit modules in the system. If a communication exception occurs in a unit module, the main processor sends a preset level signal to the monitoring chip. The monitoring chip reads and analyzes this preset level signal, and based on the received exception module identification information, controls the unit module with the communication exception to perform a reset or power-on / off operation. Among them, the main processor and the monitoring chip are connected through a first signal line and a second signal line, and the first signal line and the second signal line have two states of high and low levels. In this way, it is realized to determine the unit module with an exception through the high and low levels between the main processor and the monitoring chip, the corresponding level signal period, and the exception module identification information known by the main processor. Furthermore, the monitoring chip performs a reset or power-on / off on the exception unit module to make it return to normal.

Description

Technical Field

[0001] This application relates to the field of embedded system security, and in particular, to a system exception handling method, a control system, and a storage medium. Background Art

[0002] For the operation of an embedded system, ensuring the long-term normal and secure operation of the system is the primary task. In the prior art, the commonly used system protection method is to directly trigger a system-wide reset when an exception occurs in the system.

[0003] This method has certain drawbacks. For example, it is impossible to separately reset the functional unit module with an exception in the system, which affects the working efficiency of the system. In addition, there is also a situation where the system soft reset fails to successfully reset the system, resulting in the system being unable to work properly. Summary of the Invention

[0004] This application provides a system exception handling method, a control system, and a storage medium to solve the problem in the prior art that if an exception occurs in the system, directly triggering a system-wide reset affects the working efficiency of the system or causes the system to be unable to work properly.

[0005] In a first aspect, this application provides a system exception handling method. The system includes a main processor, a monitoring chip, and multiple unit modules. The method includes:

[0006] Determine whether there is a communication exception between the main processor and the unit modules in the system;

[0007] If there is a communication exception in the unit module, the main processor sends a preset level signal to the monitoring chip. Among them, the main processor and the monitoring chip are connected through a first signal line and a second signal line, and the first signal line and the second signal line have two states of high and low levels;

[0008] The monitoring chip reads and analyzes the preset level signal, and based on the received exception module identification information, controls the unit module with a communication exception to perform a reset or power-on / off operation.

[0009] Further, the step of if there is a communication exception in the unit module, the main processor sends a preset level signal to the monitoring chip includes:

[0010] If there is only one unit module with a communication exception, the main processor controls the first signal line and the second signal line to output a level signal,

[0011] Among them, the level signal includes a first signal and a second signal;

[0012] The first signal is the first signal line and the second signal line, one outputs a high level and the other outputs a low level, and the opposite levels are maintained for a first preset time;

[0013] The second signal is that after the output of the first signal ends, both the first signal line and the second signal line maintain a low-level output and continue for a second preset time.

[0014] Further, if there is a communication anomaly in the unit module, the main processor sends a preset level signal to the monitoring chip, and further includes:

[0015] If there is more than 1 unit module with a communication anomaly, count the number N of abnormal unit modules detected by the main processor;

[0016] The main processor controls the first signal line and the second signal line to output the level signal N times in sequence,

[0017] wherein, the level signal includes the first signal and the second signal;

[0018] The first signal is the first signal line and the second signal line, one outputs a high level and the other outputs a low level, and the opposite levels are maintained for a first preset time;

[0019] The second signal is that after the output of the first signal is completed, both the first signal line and the second signal line maintain a low-level output and continue for a second preset time.

[0020] Further, the monitoring chip reads and analyzes the preset level signal, and based on the received abnormal module identification information, controls the unit module with a communication anomaly to perform a reset or power-on / off operation, including:

[0021] The monitoring chip determines the target module based on the signal analysis information and the abnormal module identification information;

[0022] Judge whether the target module has a reset port;

[0023] If there is a reset port, the monitoring chip controls the reset port of the target module to reset the target module;

[0024] If there is no reset port, the monitoring chip controls the power supply port of the target module to power off the target module, and after the third preset time of power-off, then controls the target module to power on.

[0025] Further, after the monitoring chip reads and analyzes the preset level signal, and based on the received abnormal module identification information, controls the unit module with a communication anomaly to perform a reset or power-on / off operation, the method further includes:

[0026] Monitor whether the target module resumes normal communication within the fourth preset time, where the fourth preset time is counted starting from the time when the monitoring chip receives the preset level signal;

[0027] If not, return to execute the step of the main processor sending a preset level signal to the monitoring chip, and the step of the monitoring chip reading and parsing the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to perform a reset or power-on / off operation.

[0028] Further, the step of returning to execute the step of the monitoring chip reading and parsing the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to perform a reset or power-on / off operation includes:

[0029] If the target module has a reset port, and the monitoring chip can control both the reset port and the power supply port of the target module, then execute the step of the monitoring chip controlling the power supply port of the target module to power off the target module, and after the third preset time of power-off, then control the target module to power on.

[0030] Further, after the step of returning to execute the step of the main processor sending a preset level signal to the monitoring chip, and the step of the monitoring chip reading and parsing the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to perform a reset or power-on / off operation, the method further includes:

[0031] If the target module has not resumed normal communication yet, then after the monitoring chip reads and parses the preset level signal, continuously control the power supply port of the target module to power on and off, so that the target module resumes normal communication.

[0032] Further, the judgment of whether there is a communication abnormality between the main processor and the unit module in the system includes:

[0033] If the first signal line or the second signal line outputs a high level or a low level, and the duration is greater than the fourth preset time, then it is determined that the main processor has a communication abnormality;

[0034] After the judgment of whether there is a communication abnormality between the main processor and the unit module in the system, the method further includes:

[0035] If the main processor has a communication abnormality, then the monitoring chip controls the reset port of the main processor to reset it;

[0036] Judge whether both the first signal line and the second signal line output a high level or a low level, and the duration is greater than the fourth preset time;

[0037] If so, the monitoring chip controls the power supply port of the main processor to power off. After the fourth preset time of power-off, the monitoring chip then controls the power supply port of the main processor to power on.

[0038] Again, determine whether both the first signal line and the second signal line output a high level or a low level, and the duration is greater than the fourth preset time.

[0039] If so, the monitoring chip controls the power supply port of the main processor and the power supply ports of all unit modules to power off all of them. After the fourth preset time of power-off, the monitoring chip then controls the power supply port of the main processor and the power supply ports of all unit modules to power on all of them.

[0040] In a second aspect, the present application provides a control system. The control system includes a main processor module, a monitoring module, and a plurality of unit modules. The main processor module and the monitoring module are connected through a first signal line and a second signal line. The first signal line and the second signal line have two states of high level and low level.

[0041] The monitoring module is configured to determine whether there is a communication abnormality in the main processor module and the unit modules in the system based on a monitoring signal.

[0042] The main processor module is configured to, if a communication abnormality occurs in the unit module, send a preset level signal to the monitoring module.

[0043] The monitoring module is further configured to read and analyze the preset level signal, and based on the received abnormal module identification information, control the unit module with a communication abnormality to perform a reset or power-on / power-off operation.

[0044] In a third aspect, the present application further provides a computer storage medium storing computer-executable instructions for executing the system abnormality handling method of the present application.

[0045] The above technical solutions provided by the embodiments of the present application have the following advantages compared with the prior art:

[0046] 1. When one or more functional unit modules in the system have operation problems, there is no need to reset the entire system, realizing fixed-point reset of specific unit modules, shortening the time from abnormality to normal of the system, and improving the stability and reliability of the system.

[0047] 2. When a problem occurs in a certain unit module of the system, it is possible to first control the reset input port to reset the unit module in a safe manner. If it is ineffective, then in a tough way, power the unit module on and off again through the power supply port. In this way, instead of directly cutting off the power in a rough manner when encountering an abnormality, it is possible to protect the unit module as much as possible to quickly and safely resume operation, reduce the physical damage caused by power-off to the system, and extend the service life of the system. In addition, when the system cannot be restored to normal through the reset port or the power supply port, it can be tried several more times. In this way, the probability of the system being restored to normal can be increased, and thus the operation of the system is more secure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings herein are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present invention and, together with the specification, are used to explain the principles of the present invention.

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0050] One or more embodiments are exemplarily illustrated by the pictures in the corresponding accompanying drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the drawings in the figures do not constitute a scale limitation.

[0051] Figure 1 It is a flowchart of a system exception handling method provided by an embodiment of the present application;

[0052] Figure 2 It is a schematic diagram of system communication provided by an embodiment of the present application;

[0053] Figure 3 It is a schematic diagram of the output of a level signal indicating normal communication between the main processor and each unit module provided by an embodiment of the present application;

[0054] Figure 4 It is a schematic diagram of the output of a level signal indicating abnormal communication of 1 unit module provided by an embodiment of the present application;

[0055] Figure 5 It is a schematic diagram of the output of a level signal indicating abnormal communication of 2 unit modules provided by an embodiment of the present application;

[0056] Figure 6 It is another flowchart of a system exception handling method provided by an embodiment of the present application;

[0057] Figure 7 Another flowchart of a system exception handling method provided by an embodiment of the present application (for main processor exceptions);

[0058] Figure 8 A module interaction diagram of a control system provided by an embodiment of the present application. Detailed implementation manners

[0059] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0060] The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or letters in different examples. Such repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0061] To solve the problems in the prior art, the present application provides a method for automatically restoring normal operation when each unit module and the main processor of a system are abnormal through a specific waveform.

[0062] Figure 1 A system exception handling method provided by an embodiment of the present application, the method includes:

[0063] S101, determining whether there is a communication exception between the main processor and the unit module in the system;

[0064] In an embodiment, the system in the present application consists of a main processor, a watchdog IC (monitoring chip), and multiple unit modules. According to the functions and architectures of the system, the unit module can be different functional modules with different quantities, and there can be multiple. Refer to Figure 2 , taking 3 unit modules as an example, the communication of each module in the system is as follows:

[0065] The main processor is connected to the watchdog IC via signal line A and signal line B. Here, signal line A and signal line B are the first signal line and the second signal line, and signal line A and signal line B have two states of high and low levels. The watchdog IC is connected to the power supply ports (VCC) of the main processor and unit modules in the system. The main processor and each unit module perform output transmission interaction through their respective signal lines (sync). If the main processor and unit modules have their own reset signal (RESET) input ports, each input port is connected to the watchdog IC. Whether there is a reset signal input port is judged according to the self-conditions of the main processor and unit modules to see if there is a RESET pin itself.

[0066] After the external power supply (VBAT) supplies power to the system, the watchdog IC works normally. The watchdog IC turns on the power supply (VCC) switch of each unit to power on the main processor and unit modules in the system.

[0067] The main processor checks whether the communication of each unit module is normal. If the communication between each unit module and the main processor is normal, the main processor loops every second to control signal line A and signal line B to output a high level simultaneously for 300 ms, and then output a low level simultaneously for 700 ms. For the signal output schematic diagram, see Figure 3 . It should be noted that according to the communication protocol and communication mechanism between the main processor and each unit module, if the unit module has an abnormality, the main processor can learn about it. This is common knowledge, and the specific principle will not be elaborated here.

[0068] This application involves two situations: the main processor is abnormal or the unit module is abnormal. For different abnormal situations, the level outputs of signal line A and signal line B are different, and based on this, it is judged which abnormal situation it belongs to. Further, if the unit module is abnormal, for 1 unit module being abnormal and more than 1 unit module being abnormal, the level outputs of signal line A and signal line B are also different.

[0069] S102: If the unit module has a communication abnormality, the main processor sends a preset level signal to the monitoring chip, where the main processor and the monitoring chip are connected via the first signal line and the second signal line, and the first signal line and the second signal line have two states of high and low levels;

[0070] In the embodiment of this application, if the main processor finds that the unit module has a communication abnormality, after outputting the level signal indicating normal communication between the main processor and the unit module, it controls signal line A and signal line B to send a preset level signal to the watchdog IC so that the watchdog IC can learn about this abnormal situation, and then the watchdog IC controls the corresponding unit module to return to normal.

[0071] Specifically, the preset level signal is divided into the following two situations:

[0072] The first case: If there is only 1 unit module with communication anomaly, the main processor controls the first signal line and the second signal line to output level signals, where the level signals include a first signal and a second signal;

[0073] The output of the first signal is: controlling the first signal line and the second signal line, one outputs a high level and the other outputs a low level, and the two maintain opposite levels for a first preset time;

[0074] The output of the second signal is: after the output of the first signal is completed, controlling the first signal line and the second signal line to both output a low level and continue for a second preset time.

[0075] The second case: If the number of unit modules with communication anomaly is greater than 1, count the number N of anomaly unit modules detected by the main processor, and then the main processor controls the first signal line and the second signal line to output level signals N times in sequence. It can be understood that the signal output of the first case is looped N times.

[0076] It should be noted that N≥2 and is an integer. The first preset time is preferably 50ms, and the second preset time is preferably 100ms. These two preferred time values are the best values for testing. During specific implementation, it is also possible to take time values that fluctuate within a small range around these two preferred time values, and no specific limitation is made in this regard. Further, refer to Figure 4 and Figure 5 , Figure 4 is a schematic diagram of the preset level signal for 1 unit module with anomaly, Figure 5 is a schematic diagram of the preset level signal for 2 unit modules with anomaly.

[0077] It should be noted that the first signal indicates signal flipping, the second signal indicates the end of flipping, and the number of signal flips indicates the number of unit modules with anomaly.

[0078] S103. The monitoring chip reads and analyzes the preset level signal, and based on the received anomaly module identification information, controls the unit module with communication anomaly to perform a reset or power-on / off operation.

[0079] In the embodiment of the present application, step S103 specifically includes the following sub-steps:

[0080] S1031. The monitoring chip determines the target module based on the signal analysis information and the anomaly module identification information;

[0081] S1032. Determine whether the target module has a reset port;

[0082] S1033. If there is a reset port, the monitoring chip controls the reset port of the target module to reset the target module;

[0083] S1034: If there is no reset port, the monitoring chip controls the power supply port of the target module to power off the target module, and then controls the target module to power on after a third preset time has passed since the power-off.

[0084] In the embodiment of the present application, the watchdog IC reads and analyzes the received preset level signal, and determines the abnormalities of several unit modules according to the specific high and low levels and the corresponding level signal cycle. In addition, since the main processor knows which unit modules are abnormal, the main processor sends the abnormal module identification information (which can be understood as: the identity ID of the unit module with abnormality) to the watchdog IC. At this time, the watchdog IC can determine the unit module with abnormality, that is, the target module. Further, it is determined whether there is a reset port (reset signal input port) according to whether the target module has a RESET pin. If the target module has a reset port, the watchdog IC controls its reset port to reset it; if there is no reset port, the watchdog IC controls its power supply port, first powers off the target module, then waits for the third preset time, and then controls the power supply port of the target module to power it on. Exemplarily, the third preset time is preferably 2s, that is, the target module is first powered off, then waits for 2s, and then controls the target module to power it on. It should be noted that the setting of the third preset time is the same as the above explanation of the first preset time and the second preset time. In addition, the target module can be 1, 2 or more.

[0085] In the embodiment of the present application, it is first determined whether the main processor and the unit module in the system have communication anomalies. If the unit module has communication anomalies, the main processor sends a preset level signal to the monitoring chip, and the monitoring chip reads and parses the preset level signal, and based on the received abnormal module identification information, controls the unit module with communication anomalies to reset or power on and off, wherein the main processor and the monitoring chip are connected through a first signal line and a second signal line, and the first signal line and the second signal line have two states of high and low levels. In this way, the unit module with abnormalities is determined through the high and low levels between the main processor and the monitoring chip and the corresponding level signal cycle, as well as the abnormal module identification information known by the main processor, and then the monitoring chip resets or powers on and off the abnormal unit module to restore it to normal.

[0086] After determining the target module and resetting or powering it on, it is also necessary to consider whether the target module has resumed normal operation. For this purpose, the present application includes another embodiment. For details, see Figure 6 After controlling the unit module with communication abnormality to reset or power on / off, the method of the present application further includes:

[0087] S104, monitoring whether the target module restores normal communication within a fourth preset time, wherein the fourth preset time is counted from the time when the monitoring chip receives the preset level signal;

[0088] If not, the process returns to the step of the main processor sending a preset level signal to the monitoring chip, and the monitoring chip reading and parsing the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to reset or power on / off. That is, the process returns to the step of executing S102 and S103.

[0089] In the embodiment of the present application, the target module is the unit module 1 as an example, and it is checked whether the unit module 1 returns to normal after being reset or powered on and off. Specifically, after sending the preset level signal to the watchdog IC, the main processor will check the communication with the unit module 1, starting from the time when the watchdog IC receives the preset level signal, or starting from the time after the main processor sends the preset level signal to the watchdog IC. If the communication between the main processor and the unit module 1 returns to normal within 10s, then the main processor cycles every second, controls the signal line A and the signal line B to output a high level for 300ms at the same time, and then outputs a low level for 700ms at the same time, and repeats the operation of the unit module. On the contrary, if the communication between the main processor and the unit module 1 still does not return to normal within 10s, then the main processor will send the preset level signal to the watchdog IC again, and then the watchdog IC will read and parse it again, and then the control unit module 1 will be reset or powered on and off.

[0090] It can be seen from the above embodiments that the fourth preset time of the present application is preferably 10s. The setting of the fourth preset time is the same as the above explanation of the first preset time and the second preset time, which will not be repeated here.

[0091] In addition, regarding the watchdog IC controlling the reset or power on / off of the unit module 1 again, it should be noted that if the watchdog IC can only control the reset input port or power supply port of the unit module 1, then when controlling again, if there is a reset port, control the reset port, if there is no reset port, control the power supply port, and try to restore the unit module 1 to normal again. If the watchdog IC can control both the reset input port and the power supply port of the unit module 1, then when controlling again, for the case where there is a reset port, since the watchdog IC has tried to restore the unit module 1 to normal through the reset input port last time, but it still did not recover after 10 seconds, then this time the watchdog IC will control its power supply port, power off the unit module 1, and then wait for 2 seconds before controlling the unit module 1 to power it on. For the case where there is no reset port, follow the process of controlling the power supply port.

[0092] Further, after attempting to restore the unit module 1 to normal again, it is also necessary to consider whether the unit module 1 has resumed normal operation. There are the following two cases:

[0093] If the unit module 1 resumes normal, then the next time the unit module 1 has an abnormality, the watchdog IC will first attempt to control the reset input port for reset, and then attempt to control the power supply port to restore the unit module 1. That is to say, directly perform two controls on the unit module 1 (of course, if the unit module 1 resumes normal after the first reset port control, there is no need for the second time). In this way, it is equivalent to adopting the experience of the foregoing control process and directly performing two controls, which helps the unit module to quickly resume normal.

[0094] In another case, after attempting to restore the unit module 1 to normal again, if the unit module 1 is still abnormal, then the next time the watchdog IC will continuously attempt to control the power supply port to try to restore the unit module 1. That is to say, regardless of whether the unit module 1 has a reset port, the reset port will not be controlled. Among them, the method of controlling the power supply port is: power down the unit module 1, then wait for 2 s, and then control the unit module 1 to power on.

[0095] It should be noted that the principle and process of the watchdog IC's re-control of other unit modules are the same as those of the unit module 1.

[0096] In the embodiment of the present application, after the watchdog IC performs a reset or power-on / off operation on the abnormal unit module, the main processor detects whether it has resumed normal. If not, the main processor sends a preset level signal again, and the watchdog IC continuously controls the corresponding power supply port. In this way, through multiple repeated actions, the system is ensured to quickly resume normal operation.

[0097] In the present application, the abnormal communication of the system is caused not only by the abnormality of the unit module but also by the abnormality of the main processor. Therefore, the present application also includes another embodiment. Specifically, see Figure 7 , after determining whether there is a communication abnormality in the main processor and the unit module in the system, the method of the present application further includes:

[0098] S106. If the main processor has a communication abnormality, the monitoring chip controls the reset port of the main processor to reset it;

[0099] S107. Determine whether both the first signal line and the second signal line output a high level or a low level and the duration is greater than the fourth preset time;

[0100] S108. If so, the monitoring chip controls the power supply port of the main processor to power it down. After powering down for the fourth preset time, then control the power supply port of the main processor to power it on;

[0101] S107. Determine again whether both the first signal line and the second signal line output a high level or a low level, and the duration is greater than a fourth preset time;

[0102] S109. If so, the monitoring chip controls the power supply ports of the main processor and all unit modules to power off all of them. After powering off for the fourth preset time, it then controls the power supply ports of the main processor and all unit modules to power on all of them.

[0103] In an embodiment, if the first signal line or the second signal line outputs a high level or a low level, and the duration is greater than the fourth preset time, it is determined that the main processor has a communication anomaly. Exemplarily, if the watchdog IC detects that signal line A or signal line B continuously maintains a high level or a low level for more than 10 s, it indicates that the main processor has an anomaly.

[0104] For the handling of the anomaly of the main processor, the watchdog IC first controls the reset input port of the main processor and attempts to reset the main processor. After that, if signal line A / B still maintains a high level or a low level for more than 10 s, then the watchdog IC will attempt to cut off the power supply port of the main processor to power it off, and then power on the main processor after 10 s. Then determine again whether signal line A / B maintains a high level or a low level for more than 10 s. If so, it indicates that the main processor is still abnormal. At this time, the watchdog IC will control the main processor and all other unit modules to power off all of them, and then power on the main processor and each unit module after 10 s.

[0105] In the embodiment of the present application, the situation where the main processor has an anomaly is considered, and a corresponding handling method is also given for this anomaly. In this way, the operation safety of the system is comprehensively guaranteed. In addition, when the main processor cannot be restored to normal by only the reset port or the power supply port alone, the entire system is powered on and off, avoiding directly triggering the overall reset of the system when the system has an anomaly, and improving the working efficiency of the system.

[0106] It should be noted that the anomaly handling method of the present application is for the software faults of the system and does not apply to the system anomalies caused by hardware device faults.

[0107] As Figure 8 shown, the embodiment of the present application also provides a control system, including: a main processor module 801, a monitoring module 802, and a plurality of unit modules 803. Among them, the main processor module and the monitoring module are connected through a first signal line and a second signal line, and the first signal line and the second signal line have two states of high and low levels;

[0108] The monitoring module 802 is configured to determine whether there is a communication anomaly in the main processor module and the unit modules in the system based on the monitoring signal;

[0109] The main processor module 801 is configured to send a preset level signal to the monitoring module if a communication anomaly occurs in a unit module;

[0110] The monitoring module 802 is further configured to read and parse the preset level signal, and based on the received anomaly module identification information, control the unit module with a communication anomaly to perform a reset or power-on / off operation.

[0111] Specifically, the first signal line and the second signal line are signal line A and signal line B in any of the foregoing method embodiments, and the monitoring module includes a watchdog IC. In one embodiment, the control system can be a smart home control system or a control system for security devices, which plays a role in protecting devices that need to run for a long time and prevent downtime.

[0112] The embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the system anomaly handling method provided in any of the foregoing method embodiments are implemented.

[0113] The device / system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0114] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution or the part that contributes to the related technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disc, etc., including several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0115] It should be understood that the terms used herein are for the purpose of describing particular example embodiments only and are not intended to be limiting. Unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" as used herein may also include the plural forms. The terms "comprising", "including", "containing", and "having" are inclusive and thus specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the particular order described or illustrated, unless the order of performance is expressly stated. It should also be understood that additional or alternative steps may be used.

[0116] The foregoing are only specific embodiments of the present invention, which enable those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather will be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A system exception handling method, the system comprising a main processor, a monitoring chip, and a plurality of unit modules, characterized in that, The method includes: Determining whether there is a communication anomaly between the main processor and the unit modules in the system; If there is a communication anomaly in the unit module, the main processor sends a preset level signal to the monitoring chip, where the main processor and the monitoring chip are connected by a first signal line and a second signal line, and the first signal line and the second signal line have two states of high level and low level; The monitoring chip reads and analyzes the preset level signal, and based on the received abnormal module identification information, controls the unit module with communication anomaly to perform a reset or power-on / off operation; Among them, the step that if there is a communication anomaly in the unit module, the main processor sends a preset level signal to the monitoring chip includes: If there is only 1 unit module with communication anomaly, the main processor controls the first signal line and the second signal line to output a level signal, where the level signal includes a first signal and a second signal; The first signal is that one of the first signal line and the second signal line outputs a high level and the other outputs a low level, and maintains the opposite level for a first preset time; The second signal is that after the output of the first signal ends, both the first signal line and the second signal line maintain a low level output and last for a second preset time; And, if there are more than 1 unit modules with communication anomaly, count the number N of abnormal unit modules detected by the main processor; The main processor controls the first signal line and the second signal line to output the level signal N times in sequence, where the level signal includes a first signal and a second signal; The first signal is that one of the first signal line and the second signal line outputs a high level and the other outputs a low level, and maintains the opposite level for a first preset time; The second signal is that after the output of the first signal is completed, both the first signal line and the second signal line maintain a low level output and last for a second preset time; Among them, the step of determining whether there is a communication anomaly between the main processor and the unit modules in the system includes: If the first signal line or the second signal line outputs a high level or a low level and the duration is greater than a fourth preset time, it is determined that the main processor has a communication anomaly; After determining whether there is a communication anomaly between the main processor and the unit modules in the system, the method further includes: If the main processor has a communication anomaly, the monitoring chip controls the reset port of the main processor to reset it; Determining whether both the first signal line and the second signal line output a high level or a low level and the duration is greater than a fourth preset time; If so, the monitoring chip controls the power supply port of the main processor to power it down, and after powering it down for a fourth preset time, then controls the power supply port of the main processor to power it up; Determining again whether both the first signal line and the second signal line output a high level or a low level and the duration is greater than a fourth preset time; If so, the monitoring chip controls the power supply ports of the main processor and all unit modules to power them all down, and after powering them down for a fourth preset time, then controls the power supply ports of the main processor and all unit modules to power them all up.

2. The method according to claim 1, characterized in that, The monitoring chip reads and analyzes the preset level signal, and based on the received abnormal module identification information, controls the unit module with communication abnormality to perform reset or power-on / off operations, including: The monitoring chip determines a target module based on the signal analysis information and the abnormal module identification information; Judge whether the target module has a reset port; If there is a reset port, the monitoring chip controls the reset port of the target module to reset the target module; If there is no reset port, the monitoring chip controls the power supply port of the target module to power off the target module. After the third preset time of power-off, then control the target module to power on.

3. The method according to claim 2, wherein After the monitoring chip reads and analyzes the preset level signal, and based on the received abnormal module identification information, controls the unit module with communication abnormality to perform reset or power-on / off operations, the method further includes: Monitor whether the target module resumes normal communication within the fourth preset time, where the fourth preset time is counted starting from the time when the monitoring chip receives the preset level signal; If not, return to execute the step of the main processor sending the preset level signal to the monitoring chip, and the step of the monitoring chip reading and analyzing the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to perform reset or power-on / off operations.

4. The method according to claim 3, wherein The step of returning to execute the step of the monitoring chip reading and analyzing the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to perform reset or power-on / off operations includes: If the target module has a reset port, and the monitoring chip can control both the reset port and the power supply port of the target module, then execute the step of the monitoring chip controlling the power supply port of the target module to power off the target module. After the third preset time of power-off, then control the target module to power on.

5. The method according to claim 3, wherein After the step of returning to execute the step of the main processor sending the preset level signal to the monitoring chip, and the step of the monitoring chip reading and analyzing the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to perform reset or power-on / off operations, the method further includes: If the target module has not resumed normal communication, then after the monitoring chip reads and analyzes the preset level signal, continuously control the power supply port of the target module to power on and off, so that the target module resumes normal communication.

6. A control system, characterized in that, The control system includes a main processor module, a monitoring module, and multiple unit modules. The main processor module and the monitoring module are connected through a first signal line and a second signal line. The first signal line and the second signal line have two states of high level and low level; The monitoring module is used to judge whether there is communication abnormality between the main processor module and the unit module in the system based on the monitoring signal; The main processor module is used to send a preset level signal to the monitoring module if there is communication abnormality in the unit module; The monitoring module is further configured to read and parse the preset level signal, and based on the received abnormal module identification information, control the unit module with communication abnormality to perform reset or power-on / off operations; Wherein, when the unit module has a communication abnormality, the main processor module sends a preset level signal to the monitoring module, including: If there is only one unit module with communication abnormality, the main processor module controls the first signal line and the second signal line to output level signals, Wherein, the level signal includes a first signal and a second signal; The first signal is that one of the first signal line and the second signal line outputs a high level, and the other outputs a low level, and the opposite levels are maintained for a first preset time; The second signal is that after the output of the first signal ends, both the first signal line and the second signal line maintain a low level output and last for a second preset time; And, if there are more than one unit modules with communication abnormality, count the number N of abnormal unit modules detected by the main processor module; The main processor module controls the first signal line and the second signal line to output the level signal N times in sequence, Wherein, the level signal includes a first signal and a second signal; The first signal is that one of the first signal line and the second signal line outputs a high level, and the other outputs a low level, and the opposite levels are maintained for a first preset time; The second signal is that after the output of the first signal is completed, both the first signal line and the second signal line maintain a low level output and last for a second preset time; Wherein, judging whether there is a communication abnormality in the main processor module and the unit module in the system includes: If the first signal line or the second signal line outputs a high level or a low level and the duration is greater than a fourth preset time, it is determined that the main processor module has a communication abnormality; After judging whether there is a communication abnormality in the main processor module and the unit module in the system, it further includes: If the main processor module has a communication abnormality, the monitoring module controls the reset port of the main processor module to reset it; Judge whether both the first signal line and the second signal line output a high level or a low level and the duration is greater than a fourth preset time; If so, the monitoring module controls the power supply port of the main processor module to power it off. After powering off for a fourth preset time, then control the power supply port of the main processor module to power it on; Judge again whether both the first signal line and the second signal line output a high level or a low level and the duration is greater than a fourth preset time; If so, the monitoring module controls the power supply ports of the main processor module and all unit modules to power them all off. After powering off for a fourth preset time, then control the power supply ports of the main processor module and all unit modules to power them all on.

7. A storage medium, characterized in that, Stores computer-executable instructions, and the computer-executable instructions are used to execute the method according to any one of claims 1-5.

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