Explicit integrity check value initialization for spatial and temporal security

Abstract

The present disclosure describes explicit integrity check value initialization for spatial and temporal security. Techniques for explicit integrity check value initialization are described. In an embodiment, an apparatus includes an instruction decoder to decode a single instruction to set an integrity check value (ICV) corresponding to a destination location in memory; and execution circuitry coupled to the instruction decoder, the execution circuitry to execute one or more operations corresponding to the single instruction, the one or more operations including storing data indicated by the single instruction into the destination location and storing the ICV in the memory.

Description

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT

[0001] This invention was made with Government support under Agreement No. N66001-23-9-4004 awarded by the Naval Information Warfare Center, Pacific Division, and funded by the Defense Advanced Research Projects Agency. The Government has certain rights in this invention. Background Art

[0002] Computers and other information processing systems may store confidential, private, and secret information in their memory. Therefore, memory security and confidentiality are important considerations in computer system architecture and design. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Various examples according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0004] Figure 1 Illustrated is a computing system for explicit integrity check value initialization according to an embodiment.

[0005] Figure 2 A method for explicit integrity check value initialization according to an embodiment is illustrated.

[0006] Figure 3 Illustrated is a memory object including a tripwire, according to an embodiment.

[0007] Figure 4 An example computing system is illustrated.

[0008] Figure 5 A block diagram illustrating an example processor and / or System on a Chip (SoC) that may have one or more cores and an integrated memory controller.

[0009] 6(A) is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to an example.

[0010] 6(B) is a block diagram illustrating both an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example.

[0011] Figure 7 The figure shows an example of execution unit(s) circuitry.

[0012] Figure 8 is a block diagram illustrating converting binary instructions in a source instruction set architecture to binary instructions in a target instruction set architecture using a software instruction converter according to an example. DETAILED DESCRIPTION

[0013] The present disclosure relates to methods, devices, systems, and non-transitory computer-readable storage media for explicit integrity check value initialization. According to some examples, the device includes: an instruction decoder for decoding a single instruction to set an integrity check value ICV corresponding to a destination location in a memory; and an execution circuit system coupled to the instruction decoder, the execution circuit system for performing one or more operations corresponding to the single instruction, including storing data indicated by the single instruction in the destination location and storing the ICV in the memory.

[0014] As mentioned in the Background section, memory security and security protection are important concerns in computer system architecture and design.

[0015] Some methods of protecting memory from attacks may include using integrity check values ​​(ICVs), message authentication codes (MACs), checksums, or other values ​​(each of which may be referred to as an ICV for convenience) in integrity checking techniques to verify whether a code segment, data object, code or data structure, pointer, etc. is valid and / or can be effectively entered, used, etc.

[0016] Existing techniques may be limited in their ability to mitigate overflows between different fields within the same structure (e.g., overflows within an object), overflows between multiple entries in an array, etc. Methods according to embodiments described in this specification may overcome these limitations, for example, by providing support for establishing tripwires around fields where overflows may occur.

[0017] Prior art may also be limited in its ability to mitigate uninitialized use vulnerabilities in software because many memory security mechanisms consider an allocation to be fully valid once it is returned by the allocator, even if it has not yet been initialized. Methods according to embodiments described in this specification may also overcome these limitations, for example, by setting invalid ICVs for the entire object when it is allocated, and then incrementally replacing these invalid ICVs with valid ICVs as valid data is initialized into each portion of the object.

[0018] The methods according to the embodiments described in this specification can also be used to mitigate use-after-free (UAF) vulnerabilities, pass subroutine pointers that reference nested objects within a complex hierarchy of objects with different field types, immediately detect uninitialized uses, etc.

[0019] In an embodiment, a cryptographic integrity check linked to the security context contained in the pointer may be performed such that an attempt to access a memory location using an incorrect cryptographic address (CA) will (with high probability) result in an integrity check failure, which in turn may result in a detected exception. In various embodiments, the integrity checking architecture may support integrity checks at various granularities (e.g., 8B, 16B, 64B). In addition to CA, other security contexts (e.g., data types) may also be incorporated to be subject to integrity checks.

[0020] The description of the embodiments based on ICV, cryptographic capability computing (C3), etc. is provided as an example. The embodiments may include and / or involve other memory security, integrity checking, etc. technologies.

[0021] Figure 1 1 shows an apparatus (eg, a computing system) 100 for initializing an explicit integrity check value according to an embodiment. The apparatus 100 may correspond to a system such as Figure 4 A computer system such as the multi-processor system 400 in FIG.

[0022] Figure 1 1. The device 100 is shown as including a processor 110 and a memory 140, each of which may represent any number of corresponding components (eg, multiple processors and / or processor cores, multiple dynamic random-access memories (DRAMs), etc.).

[0023] For example, processor 100 may represent all or part of one or more hardware components including one or more processors, processor cores, or execution cores integrated on a single substrate or packaged in a single package, each of which may include multiple execution threads and / or multiple execution cores in any combination. Each processor represented as processor 110 or in processor 100 may be any type of processor, including a general-purpose microprocessor (such as a processor such as a processor 110 or processor 110). Processor family or from The processor 110 may be a processor in a family of processors from Intel Corporation or another company), a special purpose processor, or a microcontroller, or any other device or component in an information processing system in which an embodiment may be implemented. The processor 110 may be architected and designed to operate according to any instruction set architecture (ISA) with or without microcode control.

[0024] Processor 110 may be implemented using circuit systems, gates, logic, structures, hardware, etc., all or part of which may be included in discrete components and / or integrated into the circuit systems of a processing device or any other device in a computer or other information processing system. For example, Figure 1 The processor 110 in the embodiment may correspond to and / or be implemented / included in any of the following: Figure 4 The processor 470, 480 or 415, Figure 5 Processor 500 or one of cores 502A to 502N in FIG. 6(B), and / or core 690 in FIG. 6(B), each as described below.

[0025] Memory 140 may represent one or more DRAMs and / or other memory components that provide system memory or other memory or storage in or for device 100. Memory 140 may include one or more memory objects 142. Any such memory object may represent an object, region, structure, segment, etc. in memory, and operations of explicit ICV initialization according to embodiments may be associated with such memory objects.

[0026] As shown, processor 110 includes instruction unit 120 and execution unit 130. Processor 110 may include any number of each of these elements (eg, multiple execution units) and / or Figure 1 Any other elements not shown.

[0027] As described below, instruction unit 120 may correspond to and / or be implemented / included in front end unit 630 in FIG. 6(B), and / or may include any circuitry, gates, logic, structures, hardware, etc. (such as an instruction decoder) to fetch, receive, decode, interpret, schedule and / or handle instructions to be executed by processor 110, such as InvICV 121, InitICV 122, StoreIgnoreIntegrity 123, LoadIgnoreIntegrity 124, PreInitICV 125, and MemCopyWithTripwires 126, each of which is described below. Figure 1 , instructions that may be decoded or otherwise handled by instruction unit 120 are represented as blocks with dashed boundaries because the instructions themselves are not hardware, but instruction unit 120 may include hardware or logic capable of decoding or otherwise handling these instructions.

[0028] Any instruction format may be used in embodiments; for example, an instruction may include an opcode and one or more operands, where the opcode may be decoded into one or more microinstructions or micro-operations for execution by execution unit 130. The operands or other parameters may be associated with the instruction implicitly, directly, indirectly, or in any other manner.

[0029] The execution unit 130 may be associated with the execution engine 650 in FIG. 6(B) and / or the execution engine 650 in FIG. 6(B) and Figure 7 Any of the execution unit circuit systems 662 in FIG. 6(B) corresponds to and / or is implemented / included in the execution engine 650 in FIG. 6(B) and / or FIG. 6(B) and Figure 7 Any of the execution unit circuit systems 662 in (each as described below), and / or including any circuit systems, gates, logic, structures, hardware, etc. (such as arithmetic units, logic units, floating point units, shifters, load / store units, etc.) to process data and execute instructions (including Figure 1 ), microinstructions, and / or micro-operations. Execution unit 130 may represent any one or more physically or logically distinct execution units.

[0030] Example instructions

[0031] Embodiments may include using instructions indicated by an example mnemonic followed by one or more example operand sources (eg, memory or registers) and sizes.

[0032] InvICV m8

[0033] Action: Invalidate (e.g., zero) the ICV that overwrites the memory granule containing the specified memory address. Subsequent accesses to this location will (most likely) generate an integrity check violation. Optionally, before invalidating the ICV, check that the integrity check of the initial ICV succeeded using the specified CA. This option can help avoid potential denial of service scenarios due to an attacker invalidating a memory location that they are not authorized to access.

[0034] InitICV m64, r64 (similar size for other data operation objects)

[0035] Action: Sets the specified data memory location to the specified data value, performing CA-based encryption of the data if applicable. Sets the associated ICV. If the specified data operand size is smaller than the integrity check granule, any existing data within that granule is read and used to compute the associated ICV. If the access is large or misaligned so that it spans multiple integrity check granules, each of the associated ICVs is initialized.

[0036] StoreIgnoreIntegrity m64, r64 (similar for other data operation object sizes)

[0037] Action: If a series of stores are to be performed to fully initialize a single granule of data, this may enable more accurate uninitialized use checking to wait for the initialization ICV until all initialization stores have completed. However, by default, normal data stores will perform integrity checks. Therefore, if a normal store is used to initialize an early value within a granule, a spurious integrity check violation will occur. Instead, the compiler can instrument the software to use a series of StoreIgnoreIntegrity instructions to update the data without performing integrity checks. The final initialization store to the granule will be performed using an InitICV instruction.

[0038] LoadIgnoreIntegrity m64,r64 (similar size for other data operation objects)

[0039] Action: If a series of loads are to be performed to fully initialize a single data granule, this may enable more accurate uninitialized use checking to wait for the initialization ICV until all initialization loads have completed. However, by default, normal data loads will perform integrity checks. Therefore, if normal loads are used to initialize early values ​​within a granule, a spurious integrity check violation will occur. Instead, the compiler can instrument the software to update the data without performing integrity checks using a series of LoadIgnoreIntegrity instructions. The final initialization load to the granule will be performed using an InitICV instruction.

[0040] MemCopyWithTripwires dest:m64,src:m64,size:r64

[0041] Operation: Copies a memory region of a specified size from a source location to a destination location. For each memory granule, if the integrity check of the source granule succeeds, initialize the ICV at the destination location with the data loaded from the source. Otherwise, check if the decrypted value of the granule is a "magic number" indicating that the granule is a tripwire within the object. If so, invalidate the ICV of the destination granule. Otherwise, generate an integrity check violation exception. Some embodiments may have an upper limit on the size of memory copies that can be feasibly performed using this instruction. For larger copies, it may be necessary to use repeated sequences of different instructions to copy memory in smaller units, updating the architectural state as the copy proceeds so that the copy can be resumed in the event that the copy is interrupted or an exception is generated. For example, the REP MOVS instruction allows data to be copied from a location indicated by the value of a specific register to a location indicated by the value of another specific register. A repeat count is indicated in a third register. All three of these registers may be updated as the copy proceeds, which allows the copy to be resumed in the event that the copy is interrupted or an exception is generated. New instruction encodings may be specified to indicate that the memory copy should also copy the tripwire. For example, a prefix may be added before, for example, causing an encoding of DS REP MOVS. Alternative embodiments may indicate in a control register or flags register whether a REP MOVS operation should copy the tripwire.

[0042] PreInitICV m64,r64,imm8 (similar sizes for other data operation objects)

[0043] Operation: Same as InitICV, but also sets the "PreInit" flag bit associated with the granule to indicate that the granule has not yet been fully initialized. Any attempt to perform a normal load from the granule while the PreInit flag bit is set will be treated as an integrity violation. The PreInit flag bit can be made part of the granule value that is subject to integrity checking to mitigate the risk of an attacker (e.g., via a memory interposer) directly modifying this bit. The immediate operand indicates whether the granule is expected to have been initialized with a valid ICV, i.e., whether PreInitICV should perform an integrity check on the granule's initial value before updating its value and the ICV. Similar changes to InitICV can allow it to operate on uninitialized or partially initialized memory locations.

[0044] PreInitICV can be used as an alternative to StoreIgnoreIntegrity or LoadIgnoreIntegrity, because bypassing integrity checks using StoreIgnoreIntegrity or LoadIgnoreIntegrity can allow an attacker to potentially corrupt data without detection, for example, after data is placed with StoreIgnoreIntegrity or LoadIgnoreIntegrity and before InitICV is executed for the containing granule.

[0045] Figure 2 The operation of PreInitICV is illustrated in FIG.

[0046] Figure 2 The figure shows a method 200 for explicit ICV initialization according to an embodiment. The method 200 may be performed by, for example, Figure 1 to perform and / or in conjunction with the operation of an apparatus such as apparatus 100 in Figure 1 Therefore, all or any part of the foregoing description of device 100 may be applicable to method 200.

[0047] At 210 , the PreInitICV instruction is decoded and execution of the decoded instruction begins.

[0048] In 220, it is determined whether the immediate operand value indicates that the expected ICV has been initialized. If so, the method 200 continues in 230. If not, the method 200 continues in 240.

[0049] At 230, it is determined whether the integrity check of the previous data value using the previous ICV passes. If not, then at 232, an integrity check violation indicator is generated. If yes, then method 200 continues at 240.

[0050] In 240, the PreInit flag bit is set. In 242, the new data is written. In 244, for data locations that are not overwritten by the new data, the ICV is updated with the new data combined with the previous data in the granule.

[0051] At 250, execution of the PreInitICV instruction ends.

[0052] Example Use

[0053] In an embodiment, software may use these instructions to mitigate uninitialized uses, overflows within objects, UAFs, other memory security vulnerabilities, and the like.

[0054] For example, to mitigate UAF vulnerabilities, a memory allocator may use InvICV to invalidate all or part of the ICV of a freed allocation or a freed portion of an allocation (e.g., an allocation that has been shrunk using realloc). However, UAF issues are typically security-related when they occur after the underlying memory has been reallocated. Therefore, an allocator may choose not to incur the overhead of explicitly invalidating the ICV as long as the underlying memory is referenced using a new CA after it has been reallocated. If an attacker corrupts freed and reallocated memory using an out-of-date CA, this will likely be detected when data is loaded using a pointer to the new allocation. Conversely, if an attacker attempts to read new data written via a new CA via an out-of-date CA, this will also likely be detected.

[0055] As another example, to mitigate uninitialized use vulnerabilities, the compiler may instrument the code so that the first instruction to initialize an allocation (e.g., the first storage to an object just returned by malloc or the first storage to a new stack allocation) may be emitted as a PreInitICV or InitICV instruction.

[0056] As another example, to mitigate overflow within an object, the compiler may adjust the structure layout to leave one or more padding particles (tripwires) around structure fields that may be prone to overflow, such as Figure 3 The compiler can omit initialization of these padding areas so that linear overflows into these areas can be detected.

[0057] Figure 3 FIG. 3 shows an example of a memory object 300 including a tripwire according to an embodiment. The memory object 300 may correspond to Figure 1 An instance of a memory object 142 in .

[0058] For compatibility with mass storage operations on objects containing embedded tripwires, the MemCopyWithTripwires instruction (or other instruction for copying data including tripwires) may be used to propagate the tripwires to new locations.

[0059] Example Apparatus, Methods, etc.

[0060] According to some examples, an apparatus (e.g., a processing device) includes: an instruction decoder for decoding a single instruction to set an integrity check value ICV corresponding to a destination location in a memory; and an execution circuit system coupled to the instruction decoder, the execution circuit system being used to perform one or more operations corresponding to the single instruction, the one or more operations including: storing data indicated by the single instruction in the destination location, and storing the ICV in the memory.

[0061] According to some examples, a method includes: decoding a single instruction with an instruction decoder of a processing device to set an integrity check value (ICV) corresponding to a destination location in a memory; and performing, by the processing device, one or more operations corresponding to the single instruction, the one or more operations including: storing data indicated by the single instruction in the destination location, and storing the ICV in the memory.

[0062] Any such examples may include any of the following aspects or any combination thereof. One or more operations may also include: performing an integrity check before storing the ICV. The ICV may be invalid. One or more operations may also include: generating the ICV based at least in part on the indicated data. Generating the ICV based at least in part on the indicated data may include: generating the ICV based at least in part on existing data stored in a memory area including the destination location. One or more operations may also include: determining whether the memory area including the destination location has been initialized. One or more operations also include: setting a flag bit to indicate that the memory area including the destination location has not been initialized. One or more operations may also include: copying the indicated data from a source location in the memory, and performing an integrity check on the indicated data.

[0063] According to some examples, a device may include means for performing any function disclosed herein; a device may include a data storage device storing code, which, when executed by a hardware processor or controller, causes the hardware processor or controller to perform any method or any part of a method disclosed herein; the device, method, system, etc. may be as described in the detailed description; a non-transitory machine-readable medium may store instructions, which, when executed by a machine, causes the machine to perform any method or any part of a method disclosed herein. Embodiments may include any details, features, etc. described in this specification or a combination of details, features, etc.

[0064] Example Computer Architecture

[0065] The description of the example computer architecture is described in detail below. Other system designs and configurations for laptops, desktop computers, handheld personal computers (PCs), personal digital assistants, engineering workstations, servers, separate servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices known in the art are also suitable. In general, various systems or electronic devices that can contain processors and / or other execution logic as disclosed herein are generally suitable.

[0066] Figure 4 An example computing system is shown. Multiprocessor system 400 is a system provided with an interface and includes multiple processors or cores, including a first processor 470 and a second processor 480 coupled via an interface 450 such as a point-to-point (PP) interconnect, a fabric, and / or a bus. In some examples, the first processor 470 and the second processor 480 are isomorphic. In some examples, the first processor 470 and the second processor 480 are heterogeneous. Although example system 400 is shown as having two processors, the system can have three or more processors, or can be a single processor system. In some examples, the computing system is a system on chip (SoC).

[0067] Processors 470 and 480 are shown as including integrated memory controller (IMC) circuitry 472 and 482, respectively. Processor 470 also includes interface circuits 476 and 478; similarly, second processor 480 includes interface circuits 486 and 488. Processors 470, 480 may exchange information via interface 450 using interface circuits 478, 488. IMCs 472 and 482 couple processors 470, 480 to respective memories, namely memory 432 and memory 434, which may be portions of main memory locally attached to the respective processors.

[0068] Processors 470, 480 may each use interface circuits 476, 494, 486, 498 to exchange information with a network interface (NW I / F) 490 via separate interfaces 452, 454. Network interface 490 (e.g., one or more of an interconnect, bus, and / or fabric, and in some examples, a chipset) may optionally exchange information with a coprocessor 438 via interface circuit 492. In some examples, coprocessor 438 is a special-purpose processor such as, for example, a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general-purpose graphics processing unit (GPGPU), a neural-network processing unit (NPU), an embedded processor, and the like.

[0069] A shared cache (not shown) may be included in any processor 470, 480, or external to both processors but connected to these processors via an interface (such as, the PP interconnect) so that if the processor is placed in a low power mode, the local cache information of either or both processors can be stored in the shared cache.

[0070] The network interface 490 can be coupled to the first interface 416 via the interface circuit 496. In some examples, the first interface 416 can be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect, or another I / O interconnect. In some examples, the first interface 416 is coupled to a power control unit (PCU) 417, which may include circuitry, software, and / or firmware for performing power management operations related to the processors 470, 480, and / or the coprocessor 438. The PCU 417 provides control information to a voltage regulator (not shown) so that the voltage regulator generates an appropriate regulated voltage. The PCU 417 also provides control information to control the generated operating voltage. In various examples, the PCU 417 may include various power management logic units (circuitry) for performing hardware-based power management. Such power management may be entirely controlled by the processor (e.g., by various processor hardware, and which may be triggered by workload and / or power, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (such as a platform or power management source or system software).

[0071] PCU 417 is illustrated as existing as logic separate from processor 470 and / or processor 480. In other cases, PCU 417 may execute on a given one or more cores (not shown) of the cores of processor 470 or 480. In some cases, PCU 417 may be implemented as a (dedicated or general purpose) microcontroller or other control logic configured to execute its own dedicated power management code (sometimes referred to as P-code). In still other examples, the power management operations to be performed by PCU 417 may be implemented outside the processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In still other examples, the power management operations to be performed by PCU 417 may be implemented within BIOS or other system software.

[0072] Various I / O devices 414 may be coupled to the first interface 416 along with a bus bridge 418, which couples the first interface 416 to the second interface 420. In some examples, one or more additional processors 415 (such as a coprocessor, a high-throughput many integrated core (MIC) processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor) are coupled to the first interface 416. In some examples, the second interface 420 may be a low pin count (LPC) interface. Various devices may be coupled to the second interface 420, including, for example, a keyboard and / or mouse 422, a communication device 427, and a storage circuit system 428. The storage circuit system 428 may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device that may include instructions / code and data 430. Further, an audio I / O 424 may be coupled to the second interface 420. Note that other architectures are possible besides the point-to-point architecture described above. For example, a system such as multiprocessor system 400 may implement a multi-drop interface or other such architecture instead of a point-to-point architecture.

[0073] Example core architectures, processors, and computer architectures.

[0074] Processor cores may be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a special-purpose core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU including one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special-purpose cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors give rise to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic or as a dedicated core, such as integrated graphics and / or scientific (throughput) logic); and 4) a system on a chip (SoC), which may include the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessor described above, and additional functionality on the same die. An example core architecture is described next, followed by a description of an example processor and computer architecture.

[0075] Figure 5 A block diagram of an example processor and / or SoC 500 that may have one or more cores, and an integrated memory controller is illustrated. The solid line block diagram shows a processor 500 having a single core 502(A), a system agent unit circuitry 510, and a collection of one or more interface controller unit circuitry 516, while the optional addition of dashed line blocks shows an alternative processor 500 having multiple cores 502(A)-(N), a collection of one or more integrated memory controller units 514 in the system agent unit circuitry 510, and dedicated logic 508 and a collection of one or more interface controller unit circuitry 516. Note that the processor 500 may be Figure 4 one of the processors 470 or 480, or the coprocessors 438 or 415.

[0076] Thus, different implementations of processor 500 may include: 1) a CPU, where the dedicated logic 508 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 502(A)-(N) are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor, where cores 502(A)-(N) are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor, where cores 502(A)-(N) are a large number of general purpose in-order cores. Thus, processor 500 may be a general purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, and the like. The processor may be implemented on one or more chips. Processor 500 may be part of and / or implemented on one or more substrates using any of a variety of process technologies, such as, for example, complementary metal-oxide-semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0077] The memory hierarchy includes one or more levels of cache unit circuitry 504(A)-(N) within the cores 502(A)-(N), a set of one or more shared cache unit circuitry 506, and external memory (not shown) coupled to a set of (one or more) integrated memory controller unit circuitry 514. The set of one or more shared cache unit circuitry 506 may include one or more intermediate levels of cache (such as level 2 (L2), level 3 (L3), level 4 (L4)) or other levels of cache (such as last level cache (LLC)) and / or combinations thereof. Although in some examples, an interface network circuitry 512 (e.g., a ring interconnect) provides an interface to the dedicated logic 508 (e.g., integrated graphics logic), the set of (one or more) shared cache unit circuitry 506, and the system agent unit circuitry 510, alternative examples use any number of well-known techniques for providing interfaces to such units. In some examples, coherency is maintained between the shared cache unit circuitry 506 and one or more of the cores 502(A)-(N). In some examples, the interface controller unit circuitry 516 couples the core 502 to one or more other devices 518, such as one or more I / O devices, storage, one or more communication devices (e.g., a wireless network, a wired network, etc.), etc.

[0078] In some examples, one or more of the cores 502(A)-(N) may be capable of multithreading. System agent unit circuitry 510 includes those components that coordinate and operate the cores 502(A)-(N). System agent unit circuitry 510 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be, or may include, the logic and components required to regulate the power state of the cores 502(A)-(N) and / or the dedicated logic 508 (e.g., integrated graphics logic). The display unit circuitry is used to drive one or more externally connected displays.

[0079] The cores 502(A)-(N) may be homogeneous in terms of instruction set architecture (ISA). Alternatively, the cores 502(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores 502(A)-(N) may be capable of executing an ISA, while other cores may only be capable of executing a subset of the ISA or another ISA.

[0080] Example core architectures—in-order and out-of-order core block diagrams.

[0081] Figure 6(A) is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to an example. Figure 6(B) is a block diagram illustrating both an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example. Figure 6(A)-Figure 6(B) The solid line boxes in show the in-order pipeline and in-order core, while the optional addition of dashed line boxes shows the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0082] In FIG. 6(A), the processor pipeline 600 includes a fetch stage 602, an optional length decode stage 604, a decode stage 606, an optional allocation (Alloc) stage 608, an optional rename stage 610, a dispatch (also called dispatch or issue) stage 612, an optional register read / memory read stage 614, an execute stage 616, a write back / memory write stage 618, an optional exception handling stage 622, and an optional commit stage 624. One or more operations may be performed in each of these processor pipeline stages. For example, during the fetch stage 602, one or more instructions are fetched from the instruction memory, and during the decode stage 606, the fetched one or more instructions may be decoded, an address using a forwarded register port (e.g., a load store unit (LSU) address) may be generated, and branch forwarding (e.g., an immediate offset or a link register (LR)) may be performed. In one example, the decode stage 606 and the register read / memory read stage 614 may be combined into one pipeline stage. In one example, during the execute stage 616, decoded instructions may be executed, LSU address / data pipelining to an Advanced Microcontroller Bus (AMB) interface may be performed, multiplication and addition operations may be performed, arithmetic operations with branch results may be performed, and so on.

[0083] As an example, the example register renaming, out-of-order issue / execution architecture core of FIG. 6(B) may implement pipeline 600 as follows: 1) instruction fetch circuit system 638 executes fetch stage 602 and length decoding stage 604; 2) decoding circuit system 640 executes decoding stage 606; 3) rename / allocator unit circuit system 652 executes allocation stage 608 and rename stage 610; 4) (one or more) scheduler circuit systems 656 execute scheduling stage 612; 5) (one or more) physical register file circuit systems 658 and memory unit circuit systems 670 execute register read / memory read stage 614; (one or more) execution clusters 660 execute execution stage 616; 6) memory unit circuit system 670 and (one or more) physical register file circuit systems 658 execute write back / memory write stage 618; 7) various circuit systems may be involved in exception handling stage 622; and 8) retirement unit circuit system 654 and (one or more) physical register file circuit systems 658 execute commit stage 624.

[0084] 6(B) shows a processor core 690, which includes a front end unit circuit system 630 coupled to an execution engine unit circuit system 650, and both are coupled to a memory unit circuit system 670. The core 690 can be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 690 can be a special-purpose core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, and the like.

[0085] The front end unit circuit system 630 may include a branch prediction circuit system 632 coupled to an instruction cache circuit system 634, which is coupled to an instruction translation lookaside buffer (TLB) 636, which is coupled to an instruction fetch circuit system 638, which is coupled to a decoding circuit system 640. In one example, the instruction cache circuit system 634 is included in the memory unit circuit system 670 instead of in the front end circuit system 630. The decoding circuit system 640 (or decoder) can decode the instruction and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals decoded from the original instruction, or otherwise reflecting the original instruction, or derived from the original instruction as output. The decoding circuit system 640 may further include an address generation unit (AGU, not shown) circuit system. In one example, the AGU generates an LSU address using the forwarded register port, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decoding circuit system 640 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read only memories (ROM), etc. In one example, the core 690 includes a microcode ROM (not shown) or other medium (e.g., in the decoding circuit system 640, or otherwise within the front-end circuit system 630) that stores microcode for certain macroinstructions. In one example, the decoding circuit system 640 includes a micro-op or operation cache (not shown) to hold / cache decoded operations, micro-tags, or micro-operations generated during the decoding stage or other stages of the processor pipeline 600. The decoding circuit system 640 may be coupled to the rename / allocator unit circuit system 652 in the execution engine circuit system 650.

[0086] Execution engine circuitry 650 includes rename / allocator unit circuitry 652 coupled to retirement unit circuitry 654 and a set of one or more scheduler circuitry 656. Scheduler circuitry(s) 656 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. In some examples, scheduler circuitry(s) 656 may include arithmetic logic unit (ALU) scheduler / scheduling circuitry, ALU queues, address generation unit (AGU) scheduler / scheduling circuitry, AGU queues, and the like. Scheduler circuitry(s) 656 are coupled to physical register file(s) circuitry 658. Each of the physical register file(s) circuitry in physical register file(s) circuitry 658 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one example, the physical register file(s) circuit system 658 includes a vector register unit circuit system, a write mask register unit circuit system, and a scalar register unit circuit system. These register units may provide architectural vector registers, vector mask registers, general registers, etc. The physical register file(s) circuit system 658 is coupled to a retirement unit circuit system 654 (also referred to as a retirement queue (“retire queue” or “retirement queue”)) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using (one or more) reorder buffers (ROBs) and (one or more) retirement register files; using (one or more) future files, (one or more) history buffers and (one or more) retirement register files; using register maps and register pools, etc.). The retirement unit circuit system 654 and the physical register file(s) circuit system 658 are coupled to (one or more) execution clusters 660. The execution cluster(s) 660 includes a set of one or more execution unit circuit systems 662 and a set of one or more memory access circuit systems 664. Execution unit circuitry 662 may perform various arithmetic, logical, floating point, or other types of operations (e.g., shifts, additions, subtractions, multiplications) and may operate on various data types (e.g., scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some examples may include multiple execution units or execution unit circuitry dedicated to a particular function or set of functions, other examples may include only one execution unit circuitry or multiple execution units / execution unit circuitry that all perform all functions.Scheduler circuitry(s) 656, physical register file circuitry(s) 658, and execution cluster(s) 660 are shown as potentially multiple, as some examples create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines each with its own scheduler circuitry, physical register file circuitry(s), and / or execution cluster—and in the case of separate memory access pipelines, certain examples are implemented where only the execution cluster of that pipeline has memory access unit circuitry(s) 664). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the remaining pipelines may be in-order issue / execution.

[0087] In some examples, the execution engine unit circuit system 650 can perform a load store unit (LSU) address / data pipeline to an Advanced Microcontroller Bus (AMB) interface (not shown), as well as address staging and writeback, data staging load, store, and branch.

[0088] The set of memory access circuitry 664 is coupled to memory cell circuitry 670, which includes data TLB circuitry 672, which is coupled to data cache circuitry 674, which is coupled to second level (L2) cache circuitry 676. In one example, memory access circuitry 664 may include load unit circuitry, store address unit circuitry, and store data unit circuitry, each of which is coupled to data TLB circuitry 672 in memory cell circuitry 670. Instruction cache circuitry 634 is further coupled to second level (L2) cache circuitry 676 in memory cell circuitry 670. In one example, instruction cache 634 and data cache 674 are combined into L2 cache circuitry 676, third level (L3) cache circuitry (not shown), and / or a single instruction and data cache in main memory (not shown). L2 cache circuitry 676 is coupled to one or more other levels of cache and ultimately to main memory.

[0089] Core 690 may support one or more instruction sets (e.g., x86 instruction set architecture (optionally with some extensions that have been added with newer versions); MIPS instruction set architecture; ARM instruction set architecture (optionally with optional additional extensions such as NEON)), including the instruction(s) described herein. In one example, core 690 includes logic to support packed data instruction set architecture extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0090] Example execution unit(s) circuitry.

[0091] Figure 7 An example of (one or more) execution unit circuits is shown, such as (one or more) execution unit circuits 662 of FIG. 6 (B). As shown, (one or more) execution unit circuit systems 662 may include one or more ALU circuits 701, optional vector / single instruction multiple data (single instruction multiple data, SIMD) circuits 703, load / store circuits 705, branch / jump circuits 707 and / or floating-point unit (FPU) circuits 709. ALU circuits 701 perform integer arithmetic and / or Boolean operations. Vector / SIMD circuits 703 perform vector / SIMD operations on packed data (such as SIMD / vector registers). Load / store circuits 705 execute load and store instructions to load data from memory into registers or store data from registers to memory. Load / store circuits 705 may also generate addresses. Branch / jump circuits 707 cause branches or jumps to memory addresses depending on the instructions. FPU circuits 709 perform floating-point arithmetic. The width of the execution unit circuitry 662 varies depending on the example and may range, for example, from 16 bits to 1024 bits. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0092] Program code can be applied to input information to perform the functions described herein and generate output information. Output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor, or any combination thereof.

[0093] Program code can be implemented with high-level process-oriented programming language or object-oriented programming language to communicate with the processing system. If necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described herein is not limited to the scope of any specific programming language. In any case, the language can be a compiled language or an interpreted language.

[0094] Examples of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Examples may be implemented as a computer program or program code executed on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0095] One or more aspects of at least one example may be implemented by representative instructions stored on a machine-readable medium, which represent various logic within a processor, which, when read by a machine, causes the machine to manufacture logic for performing the techniques described herein. Such representations, referred to as "intellectual property (IP) cores," may be stored on tangible machine-readable media and may be supplied to various customers or production facilities to be loaded into a manufacturing machine that actually manufactures the logic or processor.

[0096] Such machine-readable storage media may include, but are not limited to, non-transitory tangible arrangements of articles made or formed by a machine or apparatus, including storage media such as: a hard disk; any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks); semiconductor devices (such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM); phase change memory (PCM); magnetic or optical cards; or any other type of medium suitable for storing electronic instructions.

[0097] Therefore, the examples also include non-transitory tangible machine-readable media containing instructions or containing design data, such as hardware description language (HDL), which defines the structures, circuits, devices, processors and / or system features described herein. Such examples may also be referred to as program products.

[0098] Simulation (including binary translation, code deformation, etc.).

[0099] In some cases, the instruction converter can be used to convert instructions from a source instruction set architecture to a target instruction set architecture. For example, the instruction converter can translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), deform, simulate or otherwise convert instructions into one or more other instructions to be processed by the core. The instruction converter can be implemented in software, hardware, firmware, or a combination thereof. The instruction converter can be on the processor, outside the processor, or partly on the processor and partly outside the processor.

[0100] Figure 81 is a block diagram illustrating the use of a software instruction converter according to an example to convert binary instructions in a source ISA into binary instructions in a target ISA. In the illustrated example, the instruction converter is a software instruction converter, but alternatively, the instruction converter can be implemented in software, firmware, hardware, or various combinations thereof. Figure 8 804 to generate first ISA binary code 806 that can be natively executed by a processor 816 having at least one first ISA core. The processor 816 having at least one first ISA core represents any processor that can perform the same operations as a processor having at least one first ISA core by compatibly executing or otherwise processing the following: The first ISA compiler 804 represents a compiler that can be used to generate first ISA binary code 806 (e.g., object code) that can be executed on a processor 816 having at least one first ISA core with or without additional linking processing. Similarly, Figure 8 It is shown that an alternative ISA compiler 808 can be used to compile a program of a high-level language 802 to generate an alternative ISA binary code 810 that can be natively executed by a processor 814 without a first ISA core. An instruction converter 812 is used to convert the first ISA binary code 806 into a code that can be natively executed by a processor 814 without a first ISA core. The converted code need not be the same as the alternative ISA binary code 810; however, the converted code will complete general operations and consist of instructions from an alternative ISA. Thus, the instruction converter 812 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first ISA processor or core to execute the first ISA binary code 806 by emulation, simulation, or any other process.

[0101] References to "one example," "an example," "one embodiment," "an embodiment," etc. indicate that the described example or embodiment may include a particular feature, structure, or characteristic, but each example or embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same example or embodiment. Further, when a particular feature, structure, or characteristic is described in conjunction with an example or embodiment, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other examples or embodiments, whether or not explicitly described.

[0102] In addition, in the examples described above, unless otherwise specifically noted, delimited language such as phrases "at least one of A, B, or C" or "A, B, and / or C" is intended to be understood to mean A, B, or C, or any combination thereof (i.e., A and B, A and C, B and C, and A, B, and C). As used in this specification and claims, and unless otherwise specified, the use of ordinal adjectives "first," "second," "third," etc., used to describe elements merely indicates that a specific instance of an element or different instances of similar elements are being referenced, and is not intended to imply that the elements so described must be in a particular order in time, space, hierarchically, or in any other manner. In addition, as used in the description of the embodiments, the " / " character between items may mean that what is described may include the first item and / or the second item (and / or any other additional items), or may be implemented using, utilizing, and / or according to the first item and / or the second item (and / or any other additional items).

[0103] In addition, the terms "bit", "flag", "field", "entry", "indicator", etc. may be used to describe a storage location in a register, table, database, or other data structure of any type or content, whether implemented in hardware or software, and these terms are not intended to limit the embodiments to any particular type of storage location or the number of bits or other elements within any particular storage location. For example, the term "bit" may be used to refer to a bit position within a register and / or data stored or to be stored in the bit position. The term "clear" may be used to indicate storing a logic value of 0 in a storage location, or otherwise causing a logic value of 0 to be stored in a storage location; and the term "set" may be used to indicate storing a logic value of 1, all 1s, or some other specified value in a storage location, or otherwise causing a logic value of 1, all 1s, or some other specified value to be stored in a storage location; however, these terms are not intended to limit the embodiments to any particular logical convention, as any logical convention may be used within the embodiments.

[0104] Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the claims.

Claims

1. A processor device for initializing an explicit integrity check value, comprising: an instruction decoder for decoding a single instruction to set an integrity check value ICV corresponding to a destination location in the memory; as well as an execution circuit system coupled to the instruction decoder, the execution circuit system being configured to perform one or more operations corresponding to the single instruction, the one or more operations comprising: storing the data indicated by the single instruction in the destination location, and The ICV is stored in the memory.

2. The processor device according to claim 1, characterized in that The one or more operations also include performing an integrity check prior to storing the ICV.

3. The processor device according to claim 1, characterized in that The ICV is invalid.

4. The processor device according to claim 1, characterized in that The one or more operations also include generating the ICV based at least in part on the indicated data.

5. The processor device according to claim 4, characterized in that Generating the ICV based at least in part on the indicated data includes generating the ICV based at least in part on existing data already stored in a memory area that includes the destination location.

6. The processor device according to claim 4, characterized in that The one or more operations also include determining whether a memory region including the destination location is initialized.

7. The processor device according to claim 6, characterized in that The one or more operations also include setting a flag bit to indicate that the memory region including the destination location is not initialized.

8. The processor device according to claim 1, characterized in that The one or more operations also include: copying the indicated data from a source location in the memory, and Performs an integrity check on the indicated data.

9. A method for initializing an explicit integrity check value, comprising: decoding, with an instruction decoder of a processing device, a single instruction to set an integrity check value ICV corresponding to a destination location in a memory; as well as One or more operations corresponding to the single instruction are performed by the processing device, and the one or more operations include: storing the data indicated by the single instruction in the destination location, and The ICV is stored in the memory.

10. The method according to claim 9, characterized in that The one or more operations also include performing an integrity check prior to storing the ICV.

11. The method according to claim 9, characterized in that The ICV is invalid.

12. The method according to claim 9, characterized in that The one or more operations also include generating the ICV based at least in part on the indicated data.

13. The method according to claim 12, characterized in that Generating the ICV based at least in part on the indicated data includes generating the ICV based at least in part on existing data already stored in a memory area that includes the destination location.

14. The method according to claim 12, characterized in that The one or more operations also include determining whether a memory region including the destination location is initialized.

15. The method according to claim 14, characterized in that The one or more operations also include setting a flag bit to indicate that the memory region including the destination location is not initialized.

16. The method according to claim 9, characterized in that The one or more operations also include: copying the indicated data from a source location in the memory, and Performs an integrity check on the indicated data.

17. A non-transitory machine-readable medium storing at least a single instruction, which, when executed by a machine, causes the machine to perform a method for explicit integrity check value initialization, the method comprising: storing the data indicated by the single instruction into a destination location, and The ICV is stored in memory.

18. The non-transitory machine-readable medium of claim 17, wherein: The method further includes generating the ICV based at least in part on the indicated data.

19. The non-transitory machine-readable medium of claim 18, wherein: The method further includes generating the ICV based at least in part on the indicated data including generating the ICV based at least in part on existing data already stored in a memory area that includes the destination location.

20. The non-transitory machine-readable medium of claim 18, wherein: The method further comprises: determining whether a memory region including the destination location is initialized, and A flag bit is set to indicate that the memory region including the destination location is not initialized.

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