Thermal stress optimization system and method in chip baking process
Through finite element simulation and topological optimization technology, the chip baking parameters are optimized, and the structural problems caused by excessive thermal stress during chip baking are solved, and the chip quality and production efficiency are improved.
Patent Information
- Application Number
- CN202411313959.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2025-01-03
AI Technical Summary
During the chip baking process, due to the mismatch of thermal expansion coefficients between the materials of each layer, the thermal stress is too high, causing delamination and cracks in the chip structure, and reducing the chip quality.
The initial thermal stress is obtained through finite element simulation, and the topologically optimized geometric space design domain is generated based on the baking parameters through expansion technology, and finite element analysis and extreme difference analysis are performed. The minimum thermal stress value and baking parameters are selected to optimize the baking parameters to reduce the Low thermal stress.
It effectively reduces the thermal stress during chip baking, prevents structural failure, and improves chip quality and production efficiency.
Smart Images
Figure CN119249813A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of microelectronic technology, and in particular to a thermal stress optimization system and method in a chip baking process. Background Art
[0002] Chip, also known as microcircuit, microchip and integrated circuit (English: integrated circuit, IC), refers to a silicon wafer containing an integrated circuit. It is very small and is often a part of a computer or other electronic device. Chip production requires baking and curing in an oven. The purpose of baking and curing is to remove the diluent and other components in the glue. The effect of baking and curing directly affects the quality of the product's welding line, product stratification and product life.
[0003] Due to the mismatch of thermal expansion coefficients between the various layers of chip materials, during the baking and curing process, under a large temperature load, the degree of shrinkage and expansion of each layer of material will be very different, but because the two adjacent layers are closely fitted, the interface must have the same deformation, so thermal stress is generated. If the thermal stress exceeds the yield strength of the material at that location, it will cause delamination and cracking in the chip structure, which will lead to chip structure failure, thereby reducing the quality of the chip. Therefore, a thermal stress optimization system and method in the chip baking process is urgently needed to solve the impact of chip baking thermal stress. Summary of the invention
[0004] The purpose of the present invention is to provide a thermal stress optimization system and method in a chip baking process, aiming to solve the problem of chip structure failure caused by thermal stress during the existing chip baking and curing process, thereby reducing chip production materials.
[0005] To achieve the above objectives, in a first aspect, the present invention provides a method for optimizing thermal stress during chip baking, comprising the following steps:
[0006] Perform finite element simulation based on chip material and size to obtain the initial thermal stress of the chip;
[0007] Generate the geometric space design domain required for topology optimization through expansion technology based on the baked parameters;
[0008] Perform finite element analysis and range analysis based on the spatial design domain and the initial thermal stress to obtain analysis results;
[0009] The minimum thermal stress value is selected based on the analysis result and combined with the baking parameters to obtain the optimized parameters.
[0010] The specific method of producing the geometric space design domain required for topology optimization through expansion technology based on baking parameters is as follows:
[0011] Based on the baking parameters and chip strength analysis results, determine the stress concentration area;
[0012] A geometric space design domain is produced based on the chip size and the areas where stress concentrations occur.
[0013] The baking parameters include positive pressure, pressure holding time, baking time, baking temperature and residence time.
[0014] Wherein, the specific method of performing finite element analysis and range analysis based on the spatial design domain and the initial thermal stress to obtain the calculation result is:
[0015] Performing finite element analysis based on the spatial design domain and the initial thermal stress to obtain a maximum thermal stress value;
[0016] A range analysis is performed on the maximum thermal stress value to obtain an analysis result.
[0017] In a second aspect, the present invention further provides a thermal stress optimization system during chip baking, comprising a simulation module, a generation module, an analysis module and an optimization module, wherein the simulation module, the generation module, the analysis module and the optimization module are connected in sequence;
[0018] The simulation module performs finite element simulation based on chip material and size to obtain the initial thermal stress of the chip;
[0019] The generation module generates a geometric space design domain required for topology optimization through an expansion technique based on the baking parameters;
[0020] The analysis module performs finite element analysis and range analysis based on the spatial design domain and the initial thermal stress to obtain analysis results;
[0021] The optimization module selects a minimum thermal stress value based on the analysis result and combines it with the baking parameters to obtain optimization parameters.
[0022] Wherein, the simulation module includes an input unit and a simulation unit, and the input unit is connected to the simulation unit;
[0023] The input unit is used to input chip material and size parameters into the simulation unit;
[0024] The simulation unit performs finite element simulation based on the chip material and size parameters to obtain the initial thermal stress of the chip.
[0025] Wherein, the analysis module includes a finite element and a range element, and the finite element and the range element are connected;
[0026] The finite element performs finite element analysis based on the spatial design domain and the initial thermal stress to obtain a maximum thermal stress value;
[0027] The range unit performs range analysis based on the maximum thermal stress value to obtain an analysis result.
[0028] The present invention discloses a method for optimizing thermal stress during chip baking, which performs finite element simulation based on chip material and size to obtain chip initial thermal stress; generates a geometric space design domain required for topological optimization through expansion technology based on baking parameters; performs finite element analysis and range analysis based on the space design domain and the initial thermal stress to obtain analysis results; selects a minimum thermal stress value based on the analysis results, and combines it with the baking parameters to obtain optimization parameters. This method uses all information of the chip's structural size parameters to carry out topological optimization with minimum structural strain energy as the goal and volume as the constraint through a geometric space design domain to obtain an optimal topological optimization configuration, thereby being able to optimize thermal stress during chip baking by obtaining an optimization solution that is closest to chip thermal stress, thereby solving the problem of chip structure failure due to thermal stress during existing chip baking and curing processes, and reducing chip production materials. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0030] Figure 1 The present invention provides a flow chart of a method for optimizing thermal stress during chip baking.
[0031] Figure 2 It is a flowchart of the specific method of generating the geometric space design domain required for topology optimization through expansion technology based on baking parameters.
[0032] Figure 3 A flow chart of a specific method of obtaining analysis results by performing finite element analysis and range analysis based on the spatial design domain and the initial thermal stress.
[0033] Figure 4 It is a schematic diagram of a thermal stress optimization system in a chip baking process provided by the present invention.
[0034] In the figure: 1-simulation module, 2-generation module, 3-analysis module, 4-optimization module, 5-input unit, 6-simulation unit, 7-finite unit, 8-range unit. DETAILED DESCRIPTION
[0035] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.
[0036] See also Figures 1 to 3 In a first aspect, the present invention provides a method for optimizing thermal stress during chip baking, comprising the following steps:
[0037] S1 performs finite element simulation based on chip material and size to obtain the initial thermal stress of the chip;
[0038] S2 generates the geometric space design domain required for topology optimization through expansion technology based on the baking parameters;
[0039] Specific method:
[0040] S21 determines the stress concentration area based on the baking parameters and chip strength analysis results;
[0041] Specifically, the baking parameters include positive pressure, pressure holding time, baking time, baking temperature and residence time.
[0042] S22 produces a geometric space design domain based on the chip size and the stress concentration occurrence area.
[0043] Specifically, the geometric space design domain carries out topological optimization with the minimum structural strain energy as the goal and volume as the constraint to obtain the optimal topological optimization configuration, which is more conducive to reducing peak stress.
[0044] S3 performs finite element analysis and range analysis based on the spatial design domain and the initial thermal stress to obtain analysis results;
[0045] Specific method:
[0046] S31 performs finite element analysis based on the spatial design domain and the initial thermal stress to obtain a maximum thermal stress value;
[0047] S32 performs a range analysis on the maximum thermal stress value to obtain an analysis result.
[0048] S4: selecting a minimum thermal stress value based on the analysis result, and combining it with the baking parameters to obtain an optimized parameter.
[0049] See also Figure 4In a second aspect, the present invention further provides a thermal stress optimization system during chip baking, comprising a simulation module 1, a generation module 2, an analysis module 3 and an optimization module 4, wherein the simulation module 1, the generation module 2, the analysis module 3 and the optimization module 4 are connected in sequence;
[0050] The simulation module 1 performs finite element simulation based on chip material and size to obtain the initial thermal stress of the chip;
[0051] The generation module 2 generates a geometric space design domain required for topology optimization through expansion technology based on the baking parameters;
[0052] The analysis module 3 performs finite element analysis and range analysis based on the spatial design domain and the initial thermal stress to obtain analysis results;
[0053] The optimization module 4 selects the minimum thermal stress value based on the analysis result and combines it with the baking parameters to obtain the optimization parameters.
[0054] In this embodiment, the simulation module 1 performs finite element simulation according to the chip material and size to obtain the initial thermal stress of the chip; the generation module 2 generates the geometric space design domain required for topology optimization through expansion technology based on the baking parameters (positive pressure, holding time, baking time, baking temperature and residence time); the analysis module 3 performs finite element analysis and range analysis according to the space design domain and the initial thermal stress to obtain analysis results; the optimization module 4 selects the minimum thermal stress value according to the analysis results, and combines it with the baking parameters to obtain optimization parameters.
[0055] Further, the simulation module 1 includes an input unit 5 and a simulation unit 6, and the input unit 5 and the simulation unit 6 are connected;
[0056] The input unit 5 is used to input chip material and size parameters to the simulation unit 6;
[0057] The simulation unit 6 performs finite element simulation based on the chip material and size parameters to obtain the initial thermal stress of the chip.
[0058] In this embodiment, the chip material and size parameters are input to the simulation unit 6 through the input unit 5, and the simulation unit 6 performs finite element simulation based on the chip material and size parameters to obtain the initial thermal stress of the chip.
[0059] Further, the analysis module 3 includes a finite element 7 and a range element 8, and the finite element 7 and the range element 8 are connected;
[0060] The finite element 7 performs finite element analysis based on the spatial design domain and the initial thermal stress to obtain a maximum thermal stress value;
[0061] The range unit 8 performs range analysis based on the maximum thermal stress value to obtain an analysis result.
[0062] In this embodiment, the finite element 7 performs finite element analysis according to the spatial design domain and the initial thermal stress to obtain a maximum thermal stress value; the range unit 8 performs range analysis based on the maximum thermal stress value to obtain an analysis result.
[0063] The above disclosure is only a preferred embodiment of a thermal stress optimization system and method in a chip baking process of the present invention. Of course, this cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiments and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.
Claims
1. A method for optimizing thermal stress during chip baking, characterized in that: The following steps are involved: Perform finite element simulation based on chip material and size to obtain the initial thermal stress of the chip; Generate the geometric space design domain required for topology optimization through expansion technology based on the baked parameters; Perform finite element analysis and range analysis based on the spatial design domain and the initial thermal stress to obtain analysis results; The minimum thermal stress value is selected based on the analysis result and combined with the baking parameters to obtain the optimized parameters.
2. The method for optimizing thermal stress during chip baking as claimed in claim 1, characterized in that: The specific method of producing the geometric space design domain required for topology optimization through expansion technology based on baking parameters is as follows: Based on the baking parameters and chip strength analysis results, determine the stress concentration area; A geometric space design domain is produced based on the chip size and the areas where stress concentrations occur.
3. The method for optimizing thermal stress during chip baking according to claim 1, characterized in that: The baking parameters include positive pressure, pressure holding time, baking time, baking temperature and residence time.
4. The method for optimizing thermal stress during chip baking according to claim 1, characterized in that: The specific method of performing finite element analysis and range analysis based on the spatial design domain and the initial thermal stress to obtain the calculation results is: Performing finite element analysis based on the spatial design domain and the initial thermal stress to obtain a maximum thermal stress value; A range analysis is performed on the maximum thermal stress value to obtain an analysis result.
5. A thermal stress optimization system in a chip baking process, applied to a thermal stress optimization method in a chip baking process as claimed in any one of claims 1 to 4, characterized in that: It includes a simulation module, a generation module, an analysis module and an optimization module, wherein the simulation module, the generation module, the analysis module and the optimization module are connected in sequence; The simulation module performs finite element simulation based on chip material and size to obtain the initial thermal stress of the chip; The generation module generates a geometric space design domain required for topology optimization through an expansion technique based on the baking parameters; The analysis module performs finite element analysis and range analysis based on the spatial design domain and the initial thermal stress to obtain analysis results; The optimization module selects a minimum thermal stress value based on the analysis result and combines it with the baking parameters to obtain optimization parameters.
6. A thermal stress optimization system in a chip baking process as claimed in claim 5, characterized in that: The simulation module includes an input unit and a simulation unit, and the input unit is connected to the simulation unit; The input unit is used to input chip material and size parameters into the simulation unit; The simulation unit performs finite element simulation based on the chip material and size parameters to obtain the initial thermal stress of the chip.
7. A thermal stress optimization system in a chip baking process as claimed in claim 5, characterized in that: The analysis module includes a finite element and a range element, and the finite element and the range element are connected; The finite element performs finite element analysis based on the spatial design domain and the initial thermal stress to obtain a maximum thermal stress value; The range unit performs range analysis based on the maximum thermal stress value to obtain an analysis result.