Training system and method for high-speed parallel port IP

Abstract

The invention relates to the technical field of integrated circuits and provides a training system and method for a high-speed parallel port IP. The system comprises a high-speed transceiver used for receiving and transmitting data and command signals; the delay and reference voltage regulator is used for executing delay regulation and reference voltage regulation; a multi-branch generator to generate a command combination, a data sequence, and an adjustment signal, respectively; a microprocessor to control generation of the multi-branch generator based on the first combination of instructions; and the instruction memory is used for storing the first instruction combination. The microprocessor is further configured to generate a first scan policy including a first scan object based on the first instruction combination, which is determined based on the first high-speed parallel port IP. The microprocessor controls generation of the multi-branch generator so as to utilize the delay and reference voltage regulator to implement execution of a first scanning strategy on a first scanning object in the data and command signals to complete eye pattern adaptation. Therefore, flexibility and compatibility are realized.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a training system and method for high-speed parallel port IP. Background Art

[0002] The Intellectual Property Core (IP) of a chip, also called chip IP, refers to the mature design of a circuit module with independent functions. By combining the circuit module design contained in the chip IP with the independently designed circuit part, the overall design workload and development cycle can be reduced. With the development of artificial intelligence and high-performance computer technology, high-speed parallel IP with data storage and inter-chip interconnection features are facing higher and higher performance requirements. In addition to requiring higher overall performance, such as a data transmission rate of 3200 megabits per second (Mbps), a large amount of read and write eye diagram training is also required to increase system stability. In the prior art, several common high-speed parallel port IPs, such as double data rate synchronous dynamic random access memory (doubledata rate SDRAM, DDR SDRAM), abbreviated as DDR, high bandwidth memory (high bandwidth memory, HBM), low power double data rate memory (low power doubledata rateSDRAM, LPDDR), die-to-die (D2D), rely on a pure hardware training structure and perform eye diagram training by configuring a hardware state machine. This makes it difficult to adapt and solve problems beyond the initial design expectations, and it is also difficult to adapt different strategies based on different application scenarios, which is not conducive to meeting customer customization needs.

[0003] To this end, the present application provides a training system and method for high-speed parallel port IP, which are used to address the technical difficulties in the prior art. Summary of the invention

[0004] In a first aspect, the present application provides a training system for high-speed parallel port IP. The training system includes: a high-speed transceiver for receiving and transmitting data and command signals; a delay and reference voltage regulator connected to the high-speed transceiver for performing delay adjustment and reference voltage adjustment on the data and command signals; a multi-branch generator connected to the delay and reference voltage regulator for respectively generating a command combination for control path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training; a microprocessor connected to the multi-branch generator for controlling the generation of the multi-branch generator based on a first instruction combination; an instruction memory connected to the microprocessor for storing the first instruction combination, and the instruction memory is configured to be editable by issuing training firmware, and the microprocessor is further used to generate a first scanning strategy including a first scanning object based on the first instruction combination, the first scanning object and the first scanning strategy are determined based on a first high-speed parallel port IP, wherein the microprocessor controls the generation of the multi-branch generator so as to use the delay and reference voltage regulator to implement the first scanning strategy on the first scanning object in the data and command signals so as to complete the eye diagram adaptation of the high-speed transceiver relative to the first high-speed parallel port IP.

[0005] Through the first aspect of the present application, the combination of hardware and software is used to realize the combination of high-speed timing control and eye diagram adaptation training on hardware and programmability on software, so as to realize flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements. The training scheme is realized from three aspects: control path, data path and eye diagram adaptation, which simplifies the overall design complexity and is conducive to adapting to actual needs by issuing different instruction combinations. It realizes the determination of scanning objects and scanning strategies in combination with the characteristics and requirements of high-speed parallel port IP, and then can generate corresponding command combinations, data sequences and adjustment signals by controlling the generation of multi-branch generators, and realizes adaptation of real eye diagrams so as to find the best position by adjusting the eye height, eye width weight, etc., thereby improving the signal transmission quality, which is conducive to reducing hardware overhead and training complexity, and helps to be compatible with complex application environments and diversified supplier particles.

[0006] In a possible implementation of the first aspect of the present application, the data and command signals include address signals and control signals transmitted through an address control bus, transmit data signals transmitted through a transmit link, and receive data signals transmitted through a receive link.

[0007] In a possible implementation of the first aspect of the present application, when the first high-speed parallel port IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal and the first clock valid interval, and the first scanning strategy adapts to the data link mode, overall link delay, link voltage and packaging requirements associated with the bandwidth memory IP.

[0008] In a possible implementation of the first aspect of the present application, when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal and the second clock valid interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth and data transmission rate associated with the double data rate synchronous dynamic random access memory IP.

[0009] In a possible implementation manner of the first aspect of the present application, the microprocessor controls the generation of the multi-branch generator so that the multi-branch generator generates a first command combination, a first data sequence, and a first adjustment signal corresponding to the first instruction combination.

[0010] In a possible implementation of the first aspect of the present application, when the first high-speed parallel port IP is a high-bandwidth memory IP, the first command combination includes an address coding error correction mechanism; when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first command combination does not include an address coding error correction mechanism and includes an address error retry mechanism.

[0011] In a possible implementation manner of the first aspect of the present application, the delay adjustment is used to determine the eye width, and the reference voltage adjustment is used to determine the eye height and the signal voltage amplitude.

[0012] In a possible implementation manner of the first aspect of the present application, the command combination includes a bus command and a command sending and receiving timing.

[0013] In a possible implementation manner of the first aspect of the present application, the data sequence includes a pseudo-random binary sequence and a special symbol sequence determined based on the first high-speed parallel port IP.

[0014] In a possible implementation manner of the first aspect of the present application, the adjustment signal includes an increase or decrease amount and a polarity, and the increase or decrease amount and the polarity are used to control a delay chain in the delay and reference voltage regulator.

[0015] In a possible implementation of the first aspect of the present application, the multi-branch generator includes a command generator, a data generator, a data comparator and a training controller, wherein the command generator is used to generate the command combination under the control of the microprocessor, the data generator is used to generate the data sequence under the control of the microprocessor, the data comparator is used to generate a comparison result based on the data sequence, and the training controller is used to generate the adjustment signal under the control of the microprocessor.

[0016] In a possible implementation of the first aspect of the present application, the training firmware is a programmable specific state machine, the microprocessor is a general state machine and is configured to execute the specific state machine based on the training firmware sent to the instruction memory.

[0017] In a possible implementation manner of the first aspect of the present application, the first instruction combination stored in the instruction memory is configured to be editable in real time by issuing the training firmware.

[0018] In a possible implementation manner of the first aspect of the present application, the training system further includes a data storage device, the data storage device is connected to the microprocessor, and the microprocessor uses the data storage device to execute the first scanning strategy.

[0019] In the second aspect, the embodiment of the present application also provides a training method for high-speed parallel port IP. The training method is applied to a training system, which includes a high-speed transceiver, a delay and reference voltage regulator, a multi-branch generator, a microprocessor and an instruction memory. The training method includes: receiving and sending data and command signals through the high-speed transceiver; performing delay adjustment and reference voltage adjustment on the data and command signals through the delay and reference voltage regulator; generating a command combination for control path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training through the multi-branch generator; and controlling the multi-branch generator based on the first instruction combination through the microprocessor. Generate, and, based on the first instruction combination, generate a first scanning strategy including a first scanning object, wherein the first scanning object and the first scanning strategy are determined based on a first high-speed parallel port IP, the instruction memory is used to store the first instruction combination, and the instruction memory is configured to be editable by sending down training firmware; through the microprocessor, control the generation of the multi-branch generator so as to utilize the delay and reference voltage regulator to implement the first scanning strategy on the first scanning object in the data and command signal so as to complete the eye diagram adaptation of the high-speed transceiver relative to the first high-speed parallel port IP.

[0020] Through the second aspect of the present application, the combination of hardware and software is used to realize the combination of high-speed timing control and eye diagram adaptation training on hardware and programmability on software, so as to realize flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements. The training scheme is realized from three aspects: control path, data path and eye diagram adaptation, which simplifies the overall design complexity and is conducive to adapting to actual needs by issuing different instruction combinations. It realizes the determination of scanning objects and scanning strategies in combination with the characteristics and requirements of high-speed parallel port IP, and then can generate corresponding command combinations, data sequences and adjustment signals by controlling the generation of multi-branch generators, and realizes adaptation of real eye diagrams so as to find the best position by adjusting the eye height, eye width weight, etc., thereby improving the signal transmission quality, which is conducive to reducing hardware overhead and training complexity, and helps to be compatible with complex application environments and diversified supplier particles.

[0021] In a possible implementation of the second aspect of the present application, the data and command signals include address signals and control signals transmitted through an address control bus, transmit data signals transmitted through a transmit link, and receive data signals transmitted through a receive link.

[0022] In a possible implementation of the second aspect of the present application, when the first high-speed parallel port IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal and the first clock valid interval, and the first scanning strategy adapts to the data link mode, overall link delay, link voltage and packaging requirements associated with the bandwidth memory IP.

[0023] In a possible implementation of the second aspect of the present application, when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal and the second clock valid interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth and data transmission rate associated with the double data rate synchronous dynamic random access memory IP. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of a training system for high-speed parallel port IP according to a first implementation mode provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of a training system for a high-speed parallel port IP according to a second implementation mode provided in an embodiment of the present application;

[0027] Figure 3 A flowchart of a training method for a high-speed parallel port IP provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0029] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0030] Figure 1 Schematic diagram of a training system for high-speed parallel port IP according to a first embodiment of the present application. Figure 1 As shown, the training system A100 includes: a high-speed transceiver A102, for receiving and transmitting data and command signals; a delay and reference voltage regulator A104, connected to the high-speed transceiver A102, for performing delay adjustment and reference voltage adjustment on the data and command signals; a multi-branch generator A110, connected to the delay and reference voltage regulator A104, for respectively generating command combinations for control path training, data sequences for data path training, and adjustment signals for eye diagram adaptation training; a microprocessor A120, connected to the multi-branch generator A110, for controlling the generation of the multi-branch generator A110 based on a first instruction combination; an instruction memory A130, connected to the microprocessor A120, for storing the first instruction combination, and the instruction memory A130 is configured to be editable by issuing training firmware A101. The microprocessor A120 is also used to generate a first scanning strategy including a first scanning object based on the first instruction combination, wherein the first scanning object and the first scanning strategy are determined based on the first high-speed parallel port IP. The microprocessor A120 controls the generation of the multi-branch generator A110 so as to use the delay and reference voltage regulator A104 to implement the first scanning strategy on the first scanning object in the data and command signal so as to complete the eye diagram adaptation of the high-speed transceiver A102 relative to the first high-speed parallel port IP.

[0031] Figure 1The training system shown is used for eye diagram adaptation training of high-speed parallel IP, which can flexibly adapt to various application scenarios and different strategies, and can be applied to high-speed parallel IP such as double data rate synchronous dynamic random access memory (doubledatarate SDRAM, DDR SDRAM), high bandwidth memory (high bandwidth memory, HBM), low power double data rate memory (low power doubledata rate SDRAM, LPDDR), die-to-die (D2D), etc., and can also be applied to other interface circuit design, circuit module design, chip IP, etc. using high-speed parallel data transmission interface. In the use scenarios of artificial intelligence and high-performance computing, high-speed parallel IP needs to provide higher high-speed interface performance in data storage, inter-chip interconnection, etc., such as providing a data transmission rate of more than 3200 megabits per second (Mbps), and at the same time needs to adapt the real eye diagram so as to find the best position by adjusting the eye height and eye width weights, thereby improving the signal transmission quality. After the design of the high-speed parallel port IP is completed, it needs to be simulated, verified and tested. However, the scenario requirements and algorithm strategies considered during the design may not cover the actual situations encountered in actual applications. For example, the development of high-speed data transmission requirements may cause the increase in data bit width to exceed the upper limit assumed during the design. Another example is the application of new communication protocols and new communication frequency bands, and another example is the customization requirements proposed by customers. In addition, device failures, device aging, and other interference factors may cause the performance of the chip to deviate from the predictions during the design. To this end, eye diagram training is required to improve the overall transceiver performance of the system and increase system stability. However, most of the high-speed parallel port IP is hardware entity solidified on a highly integrated chip, such as integrated into a system-level chip as a chip interface circuit module. Therefore, the training scheme for high-speed parallel port IP needs to consider factors such as hardware overhead and training complexity. It is also necessary to consider the requirements for training accuracy put forward by the development of high-speed data transmission, as well as compatibility requirements including compatibility with complex application environments and diverse supplier particles. The following is combined with Figure 1 It is described in detail how the training system A100 for high-speed parallel port IP provided in the embodiment of the present application copes with these challenges.

[0032] See also Figure 1 , Figure 1The training system A100 shown includes two major parts. The first part is a microprocessor A120, a multi-branch generator A110, and a delay and reference voltage regulator A104 solidified in the hardware circuit. Here, the multi-branch generator A110 generates command combinations for control path training, data sequences for data path training, and adjustment signals for eye diagram adaptation training respectively. In this way, eye diagram adaptation training can be completed through a scanning algorithm using the generation of the multi-branch generator A110, and the delay adjustment and reference voltage adjustment of the delay and reference voltage regulator A104. The multi-branch generator A110 may include multiple branches, corresponding to the training of the control path, the training of the data path, and the eye diagram adaptation training. For example, a branch in the multi-branch generator A110 may be a command generator, which is used to generate various commands required in the training process, including command transmission and reception timing, that is, to generate a command combination for control path training. For another example, another branch in the multi-branch generator A110 can be used for data generation and data comparison, generating various vector sources required by the data path during the training process, such as the commonly used pseudo-random binary sequence (PRBS), etc., and for comparison of sent data and received data, that is, generating a data sequence for data path training. For another example, another branch in the multi-branch generator A110 can be a training controller, which is responsible for configuring the algorithm to execute the delay chain and the increase and decrease amount and polarity of the voltage. For example, the delay chain entity in the delay and reference voltage regulator A104 can be incremented or decremented by the training controller, and the reference voltage level in the delay and reference voltage regulator A104 can be adjusted by the training controller, that is, generating an adjustment signal for eye diagram adaptation training. Generally, the increase and decrease amount processing of the delay chain entity is used to determine the eye width, and the adjustment of the reference voltage level is used to determine the eye height and signal voltage amplitude, so it can be used to adapt the real eye diagram. The microprocessor A120 is used to control the hardware part. The microprocessor A120 controls the generation of the multi-branch generator A110 so as to use the delay and reference voltage regulator A104 to implement the first scanning strategy for the first scanning object in the data and command signal so as to complete the eye diagram adaptation of the high-speed transceiver A102 relative to the first high-speed parallel port IP. In this way, the hardware part is provided for realizing high-speed timing control and eye diagram adaptation training by using the microprocessor A120, the multi-branch generator A110 and the delay and reference voltage regulator A104 solidified in the hardware circuit.

[0033] Continue reading Figure 1 , Figure 1 The training system A100 shown includes two parts. The second part is the software part, corresponding to Figure 1The training firmware A101 shown in . The training firmware A101 is used to send instruction combinations to the instruction memory A130, and then the microprocessor A120 reads the instruction memory A130 to obtain the sent instruction combination, and the microprocessor A120 interprets the instruction combination, compiles and executes the instruction combination. The versatility of the microprocessor A120 and the compilability of the instruction set mean that different instruction combinations can be sent and executed by the microprocessor A120 to cover different usage scenarios, protocol coverage, etc., so it can flexibly adapt to high-speed data transmission requirements, changes in communication protocols, and user customization requirements through a combination of software and hardware. Therefore, Figure 1The training system A100 shown, through the software part mainly composed of training firmware A101, can schedule all resources of the physical layer for high-speed parallel port IP and downstream devices through microprocessor A120 to implement the training algorithm. The training firmware A101 can change the instruction combination in real time as needed, which is equivalent to a programmable state machine, and the microprocessor A120 is equivalent to a general state machine by executing the instruction combination in the instruction memory A130, and executes the cycle of the specific state machine according to the instruction combination. Here, by utilizing the generation characteristics of the multi-branch generator A110 (the multi-branch generator A110 generates command combinations for control path training, data sequences for data path training, and adjustment signals for eye diagram adaptation training respectively), the training scheme can be implemented from the three aspects of control path, data path and eye diagram adaptation, which simplifies the overall design complexity and is conducive to adapting to actual needs by issuing different instruction combinations. The microprocessor A120 is used to control the generation of the multi-branch generator A110 based on the first instruction combination. The microprocessor A120 is also used to generate a first scanning strategy including a first scanning object based on the first instruction combination. The first scanning object and the first scanning strategy are determined based on the first high-speed parallel port IP. In this way, the scanning object and the scanning strategy are determined in combination with the characteristics and requirements of the specific high-speed parallel port IP, and then the corresponding command combination, data sequence and adjustment signal can be generated by controlling the generation of the multi-branch generator A110. The combination of high-speed timing control in hardware and programmability in software is realized by combining software and hardware. The microprocessor A120 controls the generation of the multi-branch generator A110 so as to use the delay and reference voltage regulator A104 to implement the first scanning strategy for the first scanning object in the data and command signal so as to complete the eye diagram adaptation of the high-speed transceiver A102 relative to the first high-speed parallel port IP. In this way, the real eye diagram is adapted so as to find the best position by adjusting the eye height, eye width weight, etc., thereby improving the signal transmission quality. In addition, by optimizing the design of the hardware part (microprocessor A120, multi-branch generator A110 and delay and reference voltage regulator A104), the overall design complexity is simplified, and the design complexity of controlling the hardware through the software part (training firmware A101) is also simplified. The update of the training firmware A101 can cover new changes and new requirements encountered in actual applications. The eye height and eye width weights can be adjusted through the reverse compensation algorithm or the adjustment algorithm to adapt to the real eye diagram and improve the signal transmission quality, which is conducive to reducing hardware overhead and training complexity, and helps to be compatible with complex application environments and diverse supplier particles.

[0034] In conclusion, Figure 1The training system A100 shown in the figure uses a combination of hardware and software to realize the combination of high-speed timing control and eye diagram adaptation training in hardware and programmability in software, and realizes flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements. The training program is implemented from three aspects: control path, data path, and eye diagram adaptation, which simplifies the overall design complexity and is conducive to adapting to actual needs by issuing different instruction combinations. It realizes the determination of scanning objects and scanning strategies based on the characteristics and requirements of high-speed parallel port IP, and then can generate corresponding command combinations, data sequences, and adjustment signals by controlling the generation of multi-branch generator A110, and realizes adaptation of the real eye diagram so as to find the best position by adjusting the eye height, eye width, weight, etc., thereby improving the signal transmission quality, which is conducive to reducing hardware overhead and training complexity, and helps to be compatible with complex application environments and diverse supplier particles.

[0035] In a possible implementation, the data and command signals include address signals and control signals transmitted through an address control bus, transmission data signals transmitted through a transmission link, and reception data signals transmitted through a reception link. The high-speed transceiver A102 is used for sending and receiving data and command signals, and the high-speed transceiver A102 can be connected to the address control bus, the transmission link, and the reception link. In this way, the eye diagram adaptation training of the high-speed parallel port IP is realized, and it can flexibly adapt to the high-speed data transmission requirements, changes in the communication protocol, and user customization requirements.

[0036] In some embodiments, when the first high-speed parallel port IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal and the first clock valid interval, and the first scanning strategy adapts the data link mode, the overall link delay, the link voltage and the packaging requirements associated with the bandwidth memory IP. As described above, the combination of hardware and software realizes the combination of high-speed timing control and eye diagram adaptation training on hardware and programmability on software, realizes flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements, realizes the training scheme from three aspects of control path, data path and eye diagram adaptation, simplifies the overall design complexity, and is conducive to adapting to actual needs by issuing different instruction combinations, and realizes the combination of the characteristics and requirements of the high-speed parallel port IP to determine the scanning object and scanning strategy, and then can generate the corresponding command combination, data sequence and adjustment signal by controlling the generation of the multi-branch generator A110, and realizes the adaptation of the real eye diagram so as to find the best position by adjusting the eye height and eye width weights, thereby improving the signal transmission quality. Here, when the first high-speed parallel port IP is a high-bandwidth memory IP, it is necessary to adapt the characteristics of the high-bandwidth memory IP to formulate the scanning strategy and determine the scanning object. Therefore, for high-bandwidth memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal, and the first clock valid interval, and the first scanning strategy adapts the data link mode, overall link delay (e.g., 20 nanoseconds), link voltage, and packaging requirements associated with the bandwidth memory IP. In addition, the communication protocol for high-bandwidth memory IP generally specifies a maximum of sixteen channels, so a serial or parallel method can be selected to adapt the timing of multiple channels. In this way, it is helpful to reduce hardware overhead and training complexity, and help to be compatible with complex application environments and diverse supplier particles.

[0037] In some embodiments, when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal and the second clock valid interval, and the first scanning strategy adapts the short distance, long distance, data bandwidth and data transmission rate associated with the double data rate synchronous dynamic random access memory IP. As described above, the combination of hardware and software is used to realize the combination of high-speed timing control and eye diagram adaptation training on hardware and programmability on software, and realizes flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements. The training scheme is realized from three aspects: control path, data path and eye diagram adaptation, which simplifies the overall design complexity, is conducive to adapting to actual needs by issuing different instruction combinations, and realizes the combination of the characteristics and requirements of the high-speed parallel port IP to determine the scanning object and scanning strategy, and then can generate the corresponding command combination, data sequence and adjustment signal by controlling the generation of the multi-branch generator A110, and realizes the adaptation of the real eye diagram so as to find the best position by adjusting the eye height and eye width weights, thereby improving the signal transmission quality. Here, when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, it is necessary to adapt the characteristics of the double data rate synchronous dynamic random access memory IP to formulate a scanning strategy and determine the scanning object. Therefore, for the double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal and the second clock valid interval, and the first scanning strategy adapts the short distance, long distance, data bandwidth and data transmission rate associated with the double data rate synchronous dynamic random access memory IP. It should be understood that, as mentioned above, the first scanning object for the high-bandwidth memory IP includes the first clock valid interval, and here, the first scanning object for the double data rate synchronous dynamic random access memory IP includes the second clock valid interval, and the first clock valid interval is different from the second clock valid interval. In this way, it is achieved to determine the scanning object and scanning strategy in combination with the characteristics and requirements of the high-speed parallel port IP.

[0038] In a possible implementation, the microprocessor A120 controls the generation of the multi-branch generator A110 so that the multi-branch generator A110 generates a first command combination, a first data sequence, and a first adjustment signal corresponding to the first instruction combination. In this way, the scanning object and the scanning strategy are determined in combination with the characteristics and requirements of the specific high-speed parallel port IP, and then the corresponding command combination, data sequence, and adjustment signal can be generated by controlling the generation of the multi-branch generator A110, and the combination of high-speed timing control in hardware and programmability in software is realized by combining software and hardware.

[0039] In some embodiments, when the first high-speed parallel port IP is a high-bandwidth memory IP, the first command combination includes an address coding error correction mechanism, and when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first command combination does not include an address coding error correction mechanism and includes an address error retry mechanism. As mentioned above, corresponding scanning strategies and scanning objects are formulated for high-bandwidth memory IP and double data rate synchronous dynamic random access memory IP, respectively, so that the characteristics and requirements of the specific high-speed parallel port IP can be combined. Here, the protocol for high-bandwidth memory IP stipulates that there is a sound error correction mechanism in address coding, such as Advanced Error Report (AER). In contrast, the protocol for double data rate synchronous dynamic random access memory IP has no error correction mechanism in address coding, and does not feedback an error after a check value has a problem, but initiates another attempt through an address error retry mechanism. In this way, the scanning object and scanning strategy are determined in combination with the characteristics and requirements of the high-speed parallel port IP, and then the corresponding command combination, data sequence and adjustment signal can be generated by controlling the generation of the multi-branch generator A110, so as to adapt to the real eye diagram so as to find the best position by adjusting the eye height, eye width and weight, thereby improving the signal transmission quality, which is beneficial to reduce hardware overhead and training complexity, and helps to be compatible with complex application environments and diverse supplier particles.

[0040] In a possible implementation, the delay adjustment is used to determine the eye width, and the reference voltage adjustment is used to determine the eye height and the signal voltage amplitude. In this way, the real eye diagram is adapted, which helps to improve the signal transmission quality.

[0041] In a possible implementation, the command combination includes a bus command and a command receiving and sending sequence. In this way, a command combination for control path training is generated, which is conducive to implementing a training scheme from the control path aspect, simplifies the overall design complexity, and is conducive to adapting to actual needs by issuing different instruction combinations.

[0042] In a possible implementation, the data sequence includes a pseudo-random binary sequence and a special symbol sequence determined based on the first high-speed parallel port IP. In this way, the data sequence for data path training is generated, which is conducive to implementing the training scheme from the data path aspect, simplifies the overall design complexity, and is conducive to adapting to actual needs by issuing different instruction combinations.

[0043] In a possible implementation, the adjustment signal includes an increase or decrease amount and a polarity, and the increase or decrease amount and the polarity are used to control the delay chain in the delay and reference voltage regulator. In this way, the adjustment signal for eye diagram adaptation training is generated, which is conducive to implementing the training scheme from the aspect of eye diagram adaptation, simplifies the overall design complexity, and is conducive to adapting to actual needs by issuing different instruction combinations.

[0044] In a possible implementation, the multi-branch generator A110 includes a command generator, a data generator, a data comparator, and a training controller, wherein the command generator is used to generate the command combination under the control of the microprocessor A120, the data generator is used to generate the data sequence under the control of the microprocessor A120, the data comparator is used to generate a comparison result based on the data sequence, and the training controller is used to generate the adjustment signal under the control of the microprocessor A120. In this way, by utilizing the generation characteristics of the multi-branch generator A110, the training scheme can be implemented from three aspects: control path, data path, and eye diagram adaptation, which simplifies the overall design complexity, is conducive to adapting to actual needs by issuing different instruction combinations, and provides a hardware part for realizing high-speed timing control and eye diagram adaptation training.

[0045] In a possible implementation, the training firmware A101 is a programmable specific state machine, and the microprocessor A120 is a general state machine and is configured to execute the specific state machine based on the training firmware sent to the instruction memory A130. The training firmware A101 can change the instruction combination in real time as needed, which is equivalent to a programmable state machine, while the microprocessor A120 is equivalent to a general state machine by executing the instruction combination in the instruction memory A130, and executes the cycle of the specific state machine according to the instruction combination. Here, by utilizing the generation characteristics of the multi-branch generator A110 (the multi-branch generator A110 generates command combinations for control path training, data sequences for data path training, and adjustment signals for eye diagram adaptation training respectively), the training scheme can be implemented from three aspects: control path, data path, and eye diagram adaptation, which simplifies the overall design complexity and is conducive to adapting to actual needs by sending different instruction combinations.

[0046] In a possible implementation, the first instruction combination stored in the instruction memory A130 is configured to be editable in real time by issuing the training firmware, thereby achieving real-time response.

[0047] In a possible implementation, the training system A100 further includes a data storage device, the data storage device is connected to the microprocessor A120, and the microprocessor A120 uses the data storage device to execute the first scanning strategy. In this way, the scanning object and scanning strategy are determined in combination with the characteristics and requirements of the specific high-speed parallel port IP.

[0048] Figure 2 Schematic diagram of a training system for high-speed parallel port IP according to a second embodiment of the present application. Figure 2 As shown, the training system B200 includes: a high-speed transceiver B202, for receiving and sending data and command signals; a delay and reference voltage regulator B204, connected to the high-speed transceiver B202, for performing delay adjustment and reference voltage adjustment on the data and command signals; a multi-branch generator B210, connected to the delay and reference voltage regulator B204, for respectively generating command combinations for control path training, data sequences for data path training, and adjustment signals for eye diagram adaptation training; a microprocessor B220, connected to the multi-branch generator B210, for controlling the generation of the multi-branch generator B210 based on a first instruction combination; an instruction memory B230, connected to the microprocessor B220, for storing the first instruction combination, and the instruction memory B230 is configured to be editable by issuing training firmware B201. The microprocessor B220 is also used to generate a first scanning strategy including a first scanning object based on the first instruction combination, wherein the first scanning object and the first scanning strategy are determined based on the first high-speed parallel port IP. The microprocessor B220 controls the generation of the multi-branch generator B210 so as to use the delay and reference voltage regulator B204 to implement the first scanning strategy on the first scanning object in the data and command signal so as to complete the eye diagram adaptation of the high-speed transceiver B202 relative to the first high-speed parallel port IP.

[0049] Figure 2It is also shown that the multi-branch generator B210 includes a command generator B212, a data generator B214, a data comparator B216 and a training controller B218. The command generator B212 is used to generate the command combination under the control of the microprocessor B220, the data generator B214 is used to generate the data sequence under the control of the microprocessor B220, the data comparator B216 is used to generate a comparison result based on the data sequence, and the training controller B218 is used to generate the adjustment signal under the control of the microprocessor B220. The training system B200 also includes a data memory B232, which is connected to the microprocessor B220, and the microprocessor B220 uses the data memory B232 to execute the first scanning strategy. In this way, by utilizing the generation characteristics of the multi-branch generator B210, the training scheme can be implemented from three aspects: control path, data path and eye diagram adaptation, which simplifies the overall design complexity, facilitates adapting to actual needs by issuing different instruction combinations, and provides the hardware part for realizing high-speed timing control and eye diagram adaptation training.

[0050] In conclusion, Figure 2 The training system B200 shown utilizes a combination of hardware and software to realize a combination of high-speed timing control and eye diagram adaptation training on the hardware and programmability on the software, thereby realizing flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements, and realizing training programs from three aspects: control path, data path, and eye diagram adaptation, thereby simplifying the overall design complexity, and facilitating adaptation to actual needs by issuing different instruction combinations, and realizing the determination of scanning objects and scanning strategies in combination with the characteristics and requirements of the high-speed parallel port IP, and then being able to generate corresponding command combinations, data sequences, and adjustment signals by controlling the generation of the multi-branch generator B210, realizing adaptation to the real eye diagram so as to find the best position by adjusting the eye height, eye width, weight, etc., thereby improving the signal transmission quality, and facilitating reducing hardware overhead and training complexity, and facilitating compatibility with complex application environments and diverse supplier particles.

[0051] Figure 3 The present invention provides a flow chart of a training method for a high-speed parallel port IP. The training method is applied to a training system, which includes a high-speed transceiver, a delay and reference voltage regulator, a multi-branch generator, a microprocessor, and an instruction memory. Figure 3 As shown, the training method includes the following steps.

[0052] Step S302: sending and receiving data and command signals via the high-speed transceiver.

[0053] Step S304: performing delay adjustment and reference voltage adjustment on the data and command signals through the delay and reference voltage regulator.

[0054] Step S306: Generate, by means of the multi-branch generator, a command combination for control path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training, respectively.

[0055] Step S308: Through the microprocessor, the generation of the multi-branch generator is controlled based on the first instruction combination, and a first scanning strategy including a first scanning object is generated based on the first instruction combination, wherein the first scanning object and the first scanning strategy are determined based on the first high-speed parallel port IP, the instruction memory is used to store the first instruction combination, and the instruction memory is configured to be editable by issuing training firmware.

[0056] Step S310: Control the generation of the multi-branch generator through the microprocessor so as to use the delay and reference voltage regulator to implement the first scanning strategy on the first scanning object in the data and command signal so as to complete the eye diagram adaptation of the high-speed transceiver relative to the first high-speed parallel port IP.

[0057] In conclusion, Figure 3 The training method shown utilizes a combination of hardware and software to realize the combination of high-speed timing control and eye diagram adaptation training on hardware and programmability on software, thereby realizing flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements. The training scheme is realized from three aspects: control path, data path, and eye diagram adaptation, which simplifies the overall design complexity and is conducive to adapting to actual needs by issuing different instruction combinations. The scanning object and scanning strategy are determined in combination with the characteristics and requirements of the high-speed parallel port IP, and then the corresponding command combination, data sequence, and adjustment signal can be generated by controlling the generation of a multi-branch generator. The real eye diagram is adapted so that the best position can be found by adjusting the eye height, eye width, weight, etc., thereby improving the signal transmission quality. This is conducive to reducing hardware overhead and training complexity, and helps to be compatible with complex application environments and diverse supplier particles.

[0058] In a possible implementation, the data and command signals include address signals and control signals transmitted through an address control bus, transmission data signals transmitted through a transmission link, and reception data signals transmitted through a reception link. In this way, eye diagram adaptation training of high-speed parallel port IP is realized, and it can flexibly adapt to high-speed data transmission requirements, changes in communication protocols, and user customization requirements.

[0059] In some embodiments, when the first high-speed parallel port IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal and the first clock valid interval, and the first scanning strategy adapts the data link mode, the overall link delay, the link voltage and the packaging requirements associated with the bandwidth memory IP. As described above, the combination of hardware and software realizes the combination of high-speed timing control and eye diagram adaptation training on hardware and programmability on software, realizes flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements, realizes the training scheme from three aspects of control path, data path and eye diagram adaptation, simplifies the overall design complexity, and is conducive to adapting to actual needs by issuing different instruction combinations, realizes the combination of the characteristics and requirements of the high-speed parallel port IP to determine the scanning object and scanning strategy, and then can generate the corresponding command combination, data sequence and adjustment signal by controlling the generation of the multi-branch generator, realizes the adaptation of the real eye diagram so as to find the best position by adjusting the eye height and eye width weight, thereby improving the signal transmission quality. Here, when the first high-speed parallel port IP is a high-bandwidth memory IP, it is necessary to adapt the characteristics of the high-bandwidth memory IP to formulate the scanning strategy and determine the scanning object. Therefore, for high-bandwidth memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal, and the first clock valid interval, and the first scanning strategy adapts the data link mode, overall link delay (e.g., 20 nanoseconds), link voltage, and packaging requirements associated with the bandwidth memory IP. In addition, the communication protocol for high-bandwidth memory IP generally specifies a maximum of sixteen channels, so a serial or parallel method can be selected to adapt the timing of multiple channels. In this way, it is helpful to reduce hardware overhead and training complexity, and help to be compatible with complex application environments and diverse supplier particles.

[0060] In some embodiments, when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal and the second clock valid interval, and the first scanning strategy adapts the short distance, long distance, data bandwidth and data transmission rate associated with the double data rate synchronous dynamic random access memory IP. As described above, the combination of hardware and software is used to realize the combination of high-speed timing control and eye diagram adaptation training on hardware and programmability on software, and realizes flexible adaptation to high-speed data transmission requirements, changes in communication protocols, and user customization requirements. The training scheme is realized from three aspects: control path, data path and eye diagram adaptation, which simplifies the overall design complexity, is conducive to adapting to actual needs by issuing different instruction combinations, and realizes the combination of characteristics and requirements of high-speed parallel port IP to determine the scanning object and scanning strategy, and then can generate corresponding command combinations, data sequences and adjustment signals by controlling the generation of multi-branch generators, and realizes the adaptation of real eye diagrams so as to find the best position by adjusting eye height and eye width weights, thereby improving signal transmission quality. Here, when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, it is necessary to adapt the characteristics of the double data rate synchronous dynamic random access memory IP to formulate a scanning strategy and determine the scanning object. Therefore, for the double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the transmission data signal, the reception data signal and the second clock valid interval, and the first scanning strategy adapts the short distance, long distance, data bandwidth and data transmission rate associated with the double data rate synchronous dynamic random access memory IP. It should be understood that, as mentioned above, the first scanning object for the high-bandwidth memory IP includes the first clock valid interval, and here, the first scanning object for the double data rate synchronous dynamic random access memory IP includes the second clock valid interval, and the first clock valid interval is different from the second clock valid interval. In this way, it is achieved to determine the scanning object and scanning strategy in combination with the characteristics and requirements of the high-speed parallel port IP.

[0061] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0062] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0063] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A training system for high-speed parallel IP, characterized in that: The training system comprises: High-speed transceiver for sending and receiving data and command signals; A delay and reference voltage regulator, connected to the high-speed transceiver, for performing delay regulation and reference voltage regulation on the data and command signals; a multi-branch generator, connected to the delay and reference voltage regulator, for respectively generating a command combination for control path training, a data sequence for data path training, and a regulation signal for eye diagram adaptation training; a microprocessor, connected to the multi-branch generator, for controlling the generation of the multi-branch generator based on a first instruction combination; an instruction memory connected to the microprocessor and used to store the first instruction combination, and the instruction memory is configured to be editable by issuing training firmware, The microprocessor is further configured to generate a first scanning strategy including a first scanning object based on the first instruction combination, wherein the first scanning object and the first scanning strategy are determined based on the first high-speed parallel port IP. Wherein, the microprocessor controls the generation of the multi-branch generator so as to utilize the delay and reference voltage regulator to implement the first scanning strategy on the first scanning object in the data and command signal so as to complete the eye diagram adaptation of the high-speed transceiver relative to the first high-speed parallel port IP.

2. The training system according to claim 1, characterized in that The data and command signals include address signals and control signals transmitted through an address control bus, transmission data signals transmitted through a transmission link, and reception data signals transmitted through a reception link.

3. The training system according to claim 2, characterized in that When the first high-speed parallel port IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal and the first clock valid interval, and the first scanning strategy adapts to the data link mode, overall link delay, link voltage and packaging requirements associated with the bandwidth memory IP.

4. The training system according to claim 2, characterized in that: When the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the sending data signal, the receiving data signal and the second clock valid interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth and data transmission rate associated with the double data rate synchronous dynamic random access memory IP.

5. The training system according to claim 1, characterized in that: The microprocessor controls the generation of the multi-branch generator so that the multi-branch generator generates a first command combination, a first data sequence, and a first adjustment signal corresponding to the first instruction combination.

6. The training system according to claim 5, characterized in that When the first high-speed parallel port IP is a high-bandwidth memory IP, the first command combination includes an address coding error correction mechanism; when the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first command combination does not include an address coding error correction mechanism and includes an address error retry mechanism.

7. The training system according to claim 1, characterized in that The delay adjustment is used to determine the eye width, and the reference voltage adjustment is used to determine the eye height and the signal voltage amplitude.

8. The training system according to claim 1, characterized in that The command combination includes a bus command and a command sending and receiving timing.

9. The training system according to claim 1, characterized in that: The data sequence includes a pseudo-random binary sequence and a special symbol sequence determined based on the first high-speed parallel port IP.

10. The training system according to claim 1, characterized in that: The adjustment signal includes an increase or decrease amount and a polarity, and the increase or decrease amount and the polarity are used to control the delay chain in the delay and reference voltage regulator.

11. The training system according to claim 1, characterized in that: The multi-branch generator includes a command generator, a data generator, a data comparator and a training controller, wherein the command generator is used to generate the command combination under the control of the microprocessor, the data generator is used to generate the data sequence under the control of the microprocessor, the data comparator is used to generate a comparison result based on the data sequence, and the training controller is used to generate the adjustment signal under the control of the microprocessor.

12. The training system according to claim 1, characterized in that The training firmware is a programmable specific state machine, and the microprocessor is a general state machine and is configured to execute the specific state machine based on the training firmware issued to the instruction memory.

13. The training system according to claim 1, characterized in that The first instruction combination stored in the instruction memory is configured to be editable in real time by issuing the training firmware.

14. The training system according to claim 1, characterized in that The training system further comprises a data storage device connected to the microprocessor, and the microprocessor uses the data storage device to execute the first scanning strategy.

15. A training method for high-speed parallel port IP, characterized in that: The training method is applied to a training system, the training system comprising a high-speed transceiver, a delay and reference voltage regulator, a multi-branch generator, a microprocessor and an instruction memory, and the training method comprises: Sending and receiving data and command signals via the high-speed transceiver; By means of the delay and reference voltage regulator, delay adjustment and reference voltage adjustment are performed on the data and command signals; Generate, by means of the multi-branch generator, a command combination for control path training, a data sequence for data path training, and an adjustment signal for eye diagram adaptation training respectively; The microprocessor is used to control the generation of the multi-branch generator based on a first instruction combination, and a first scanning strategy including a first scanning object is generated based on the first instruction combination, wherein the first scanning object and the first scanning strategy are determined based on a first high-speed parallel port IP, the instruction memory is used to store the first instruction combination, and the instruction memory is configured to be editable by issuing training firmware; Through the microprocessor, the generation of the multi-branch generator is controlled so that the delay and reference voltage regulator is used to implement the first scanning strategy on the first scanning object in the data and command signal to complete the eye diagram adaptation of the high-speed transceiver relative to the first high-speed parallel port IP.

16. The training method according to claim 15, characterized in that: The data and command signals include address signals and control signals transmitted through an address control bus, transmission data signals transmitted through a transmission link, and reception data signals transmitted through a reception link.

17. The training method according to claim 16, characterized in that: When the first high-speed parallel port IP is a high-bandwidth memory IP, the first scanning object includes the address signal, the transmit data signal, the receive data signal and the first clock valid interval, and the first scanning strategy adapts to the data link mode, overall link delay, link voltage and packaging requirements associated with the bandwidth memory IP.

18. The training method according to claim 16, characterized in that: When the first high-speed parallel port IP is a double data rate synchronous dynamic random access memory IP, the first scanning object includes the address signal, the sending data signal, the receiving data signal and the second clock valid interval, and the first scanning strategy adapts to the short distance, long distance, data bandwidth and data transmission rate associated with the double data rate synchronous dynamic random access memory IP.

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