A method, system, and electronic device for checking the validity of voltage identification of a layout line

Abstract

The present invention discloses a method, a system and an electronic device for checking the validity of voltage identifiers of layout lines, belonging to the technical field of layout data processing. It includes obtaining the line voltage of a circuit, including the line name and the voltage value; obtaining the layout line voltage identifier, including the line name and the voltage value; comparing whether the layout line voltage identifier is consistent with the line voltage of the circuit, and generating a validity report of the voltage identifier of the layout line. The present invention verifies the correctness and validity of the layout line voltage identifier value through the line voltage value under the actual working condition of the circuit, avoids the unreasonable situation of the line voltage caused by the manual incorrect use of the identifier layer or voltage value, thereby avoiding affecting the result of the pitch requirement rule check caused by the line voltage difference, and improving the accuracy and reliability of the layout line voltage validity check.

Description

Technical Field

[0001] The present invention relates to the technical field of layout data processing, and in particular, to a method, a system, and an electronic device for checking the validity of voltage identifiers of layout lines. Background Art

[0002] In the design of integrated circuits (ICs), Design Rule Check (DRC) verification plays a crucial role in chip design. It mainly conducts multi-faceted analysis and verification of the physical design through rule checking of DRC Rule. These rules define a series of standards and restrictions that design objects (such as line width, spacing, etc.) should meet to ensure that the design meets the requirements of expected electrical performance, reliability, manufacturability, and testability, etc., and is an important step to ensure the reliability and manufacturability of the design. The voltage rule check in DRC verification is to prevent problems such as voltage conflicts and short circuits. If the spacing between regions with different voltage differences is too small, it may cause voltage interference with each other and even lead to a short circuit. Therefore, to ensure the safe operation of the circuit, DRC sets corresponding minimum spacing requirements according to the magnitude of the voltage difference.

[0003] As Figure 1 shown, DRC provides a dedicated voltage identification CAD hierarchy to determine the line voltage value, such as the voltage mark layer and the text layer. Appropriate voltage values are marked on the lines using these hierarchies in the layout. DRC calculates the voltage difference between adjacent lines according to the following formula: Delta V = MAX (Net1 Voltage High - Net2 Voltage Low, Net2 Voltage High - Net1 Voltage Low). Then, the DRC rules are run to check whether the voltage difference meets the corresponding spacing requirements.

[0004] Although the DRC rules can identify the voltage value of the line based on the mark layer or the text layer, the DRC rules cannot check whether the voltage value of the line is valid and conforms to the actual working conditions of the design. If the text layer or the mark layer is used incorrectly, or the voltage value is set unreasonably, it will affect the result of the voltage difference spacing check. Incorrect or invalid voltage value identifiers may result in a DRC clean, thus masking the real error. Summary of the Invention

[0005] To solve the problems existing in the above background art, the present invention adopts the following technical solutions:

[0006] The present application provides a method for checking the validity of voltage identifiers of layout lines, including the steps of:

[0007] Obtain the line voltage of the circuit, including the line name and voltage value;

[0008] Obtain the layout line voltage identification, including the line name and voltage value;

[0009] Compare whether the layout line voltage identification is consistent with the line voltage of the circuit, and generate a validity report on the voltage identification of the layout line.

[0010] As a preferred solution of this application, the obtaining of the voltage identification of the circuit line specifically includes:

[0011] Create a circuit;

[0012] Set test stimuli;

[0013] Run the simulation to obtain the simulation results;

[0014] Save the line name and voltage value in the circuit from the simulation results.

[0015] As a preferred solution of this application, the setting of the test stimuli is to create test stimuli according to the actual working conditions of the circuit, including designing the reference voltage of all lines in the circuit; the export format of the simulation results is a text file or a spreadsheet.

[0016] As a preferred solution of this application, the obtaining of the voltage identification of the layout line specifically includes:

[0017] Create a layout;

[0018] Define the line voltage identification layer; select the voltage identification layer to cover the corresponding physical layer;

[0019] Extract the line name and voltage value in the layout to generate a voltage report on the lines in the layout.

[0020] As a preferred solution of this application, the generation of the voltage report on the lines in the layout includes extracting the lines in the layout and identifying the line voltage according to the DRC rules to generate a voltage report on the lines in the layout, specifically including:

[0021] Layout parsing: Parse the layout file to obtain the physical layout, connection relationship and attribute information in the layout;

[0022] Line identification: The DRC tool identifies the lines in the layout, including their geometric features, connection relationships and other attributes;

[0023] Voltage identification extraction: The DRC tool extracts voltage identification information from the layout.

[0024] As a preferred solution of this application, after the voltage identification extraction, it further includes:

[0025] Voltage value association: Associate the extracted voltage identification information with the corresponding voltage value;

[0026] Data integration: Integrate the extracted line names and voltage values into a format that can be used to generate reports or for subsequent analysis.

[0027] As a preferred solution of the present application, compare whether the voltage identifiers of the lines in the layout and the circuit are consistent, and generating a validity report of the voltage identifiers of the layout lines specifically includes the steps of:

[0028] S301. Obtain the corresponding relationship between the layout and circuit line names by converting the LVS intermediate result data through an EDA tool;

[0029] S302. Run a script to compare the voltage values of the same line in the circuit and the layout, and generate a difference report;

[0030] S303. Determine the consistency between the circuit and the layout according to the difference report.

[0031] As a preferred solution of the present application, in step S303, if the layout and the circuit are inconsistent, then perform the following steps:

[0032] Fill in the voltage identifier as invalid in the validity report of the voltage identifier of the layout line;

[0033] Analyze the difference report to determine the reasons and impacts of the inconsistency;

[0034] Modify the corresponding voltage identifier of the layout.

[0035] As a preferred solution of the present application, when the layout and the circuit are inconsistent, it further includes iterative steps S301 - S303 until the voltage identifiers of all lines in the layout are consistent with those in the circuit.

[0036] The present application also provides a system for checking the validity of the voltage identifier of the layout line, which is applied to a method for checking the validity of the voltage identifier of the layout line as described above; the system includes:

[0037] A data acquisition module configured to acquire line voltage information data of the circuit and the layout, where the line voltage information data includes line names and voltage values;

[0038] A data processing module configured to compare and analyze the line names and voltage values of the circuit and the layout acquired by the data acquisition module;

[0039] A data optimization module configured to optimize the data that is inconsistent after comparison in the data processing module, specifically by modifying the corresponding voltage identifier of the layout until the voltage identifiers of all lines in the layout are consistent with those in the circuit.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] The present invention verifies the correctness and validity of the layout line voltage identification value through the line voltage value under the actual working condition of the circuit, thereby avoiding the situation where the line voltage is unreasonable due to the erroneous use of the identification layer or voltage value, thereby avoiding affecting the spacing requirement rule inspection result caused by the line voltage difference.

[0042] The present invention ensures that the voltage mark of the line in the layout is consistent with the actual voltage in the circuit by means of circuit simulation and layout extraction, which helps to find and solve the problem of inconsistency between the layout and the circuit during the design process, thereby ensuring the accuracy and reliability of the design.

[0043] The present invention also modifies the voltage marks of the lines in the inconsistent layout according to the difference report, and iterates the circuit and layout. Figure 1 The consistency check process is continued until the voltage identification of all lines in the layout is consistent with the circuit. This not only solves the problem of inconsistency between the layout and the circuit, but also improves the accuracy and reliability of the layout line voltage validity check. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A schematic diagram of a voltage identification layer of a layout in the background technology of the present invention;

[0046] Figure 2 A schematic flow chart of a method for checking the validity of voltage markings of layout lines provided in the first embodiment of the present invention;

[0047] Figure 3 This is a flow chart of step S1 of the first embodiment of the present invention;

[0048] Figure 4 This is a flow chart of step S2 of the first embodiment of the present invention;

[0049] Figure 5 This is a flow chart of step S3 of the first embodiment of the present invention;

[0050] Figure 6 A schematic diagram of the structure of a system for checking the validity of voltage markings of layout lines provided in the second embodiment of the present invention;

[0051] Figure 7 A schematic diagram of the structure of an electronic device provided in Embodiment 3 of the present invention; DETAILED DESCRIPTION

[0052] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. It should be noted that relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0053] The present invention provides a method, system and electronic device for checking the validity of the voltage identification of the layout line. The correctness and validity of the voltage identification value of the layout line is verified by the line voltage value under the actual working condition of the circuit, so as to avoid the situation where the line voltage is unreasonable due to the erroneous use of the identification layer or voltage value, thereby avoiding the spacing requirement rule inspection result caused by the line voltage difference. Through circuit simulation and layout extraction, it is ensured that the voltage identification of the line in the layout is consistent with the actual voltage in the circuit. This helps to discover and solve the problem of inconsistency between the layout and the circuit during the design process, so as to ensure the accuracy and reliability of the design. The voltage identification of the inconsistent layout line is also modified according to the differentiation report, and the circuit and layout are iterated. Figure 1 The consistency check process is repeated until the voltage identification of all lines in the layout is consistent with the circuit. This not only solves the problem of inconsistency between the layout and the circuit, but also improves the accuracy and reliability of the layout line voltage validity check. The technical solution of the present invention is described in detail below:

[0054] Embodiment 1

[0055] See also Figure 2 The present invention provides a method for checking the validity of voltage marking of a layout line, comprising the steps of:

[0056] S1. Obtain the line voltage of the circuit, including the line name and voltage value, wherein the line name refers to the name of the line in the circuit, and the voltage value refers to the voltage value of the corresponding line in the circuit.

[0057] like Figure 3 As shown, step S1, obtaining the line voltage of the circuit, including the line name and the voltage value, specifically includes the following steps:

[0058] S101, creating a circuit: according to the actual layout to be checked, creating a circuit corresponding to the layout in a circuit design tool. In an embodiment of the present invention, the circuit design tool adopts a commonly used circuit design tool in the art, such as an EDA tool, a Synopsys design tool, and an Altium Designer, etc., which is not limited here.

[0059] S102. Set test stimuli; create test stimuli according to the actual working conditions of the circuit. In this embodiment, setting test stimuli includes designing the reference voltages of all lines in the circuit.

[0060] Set reference voltages: According to the reference voltages of all lines in the circuit, these reference voltages can be power supply voltages, amplitudes of input signals, etc.

[0061] Set test stimuli: According to the reference voltages of all lines in the circuit, set a suitable test stimulus. Setting test stimuli means providing one or more sets of specific input signals for the input ports or other key nodes of the circuit in circuit simulation to simulate the response of the circuit under actual working conditions. These input signals can be voltage pulses, constant voltages, current injections or other forms of signals, used to stimulate the circuit and observe its response. By setting test stimuli, the performance of the circuit under different working conditions can be evaluated, the correctness of the design can be verified, the stability and robustness of the circuit can be analyzed, and potential problems and improvement spaces can be identified.

[0062] In actual engineering, setting test stimuli is usually achieved through simulation tools. The type, parameters and timing of test stimuli can be specified in the simulation tools, and then the simulation is run and the response of the circuit is analyzed. In this way, the performance and reliability of the circuit can be verified through simulation before actually manufacturing the circuit, thus saving time and cost.

[0063] S103. Run the simulation to obtain simulation results;

[0064] In the embodiments of the present invention, the simulation can use a SPICE simulator or other simulation tools, and then load the created circuit model and the set test stimuli into the SPICE simulator or other simulation tools, and then run the simulation to obtain the voltage response of the output lines.

[0065] S104. Save the line names and voltage values in the circuit from the simulation results to generate a file related to the high and low voltages of the lines in the circuit.

[0066] Saving the line names and voltage values in the circuit includes, after the simulation runs to completion, exporting the simulation results from the simulation tool. The simulation results can usually be exported as text files or spreadsheets. The content of the simulation result file includes the names of the output lines and the corresponding voltage values. Then extract the line names and their corresponding voltage values in the simulation result file to generate a file related to the high and low voltages of the lines in the circuit.

[0067] S2. Obtain the voltage identifiers of the layout lines, including line names and voltage values. Among them, the line name refers to the name of the line in the layout, and the voltage value refers to the voltage value of the corresponding line in the layout.

[0068] Such as Figure 4As shown in the figure, step S2, obtaining the voltage identification of the layout lines, including the line name and voltage value, specifically includes the following steps:

[0069] S201. Create a layout: Create the layout to be inspected in the DRC tool, including the definition of circuits and other physical layers.

[0070] S202. Define the line voltage identification layer: In the DRC tool, define the line voltage identification layer to identify the voltage information of the lines in the layout. Defining the line voltage identification layer can be completed through the graphical interface or script of the DRC tool.

[0071] Select a suitable voltage identification layer (mark layer / text layer) to cover the corresponding physical layer. Selecting a suitable voltage identification layer usually uses "mark layer" or "text layer" to identify the voltage information of the lines. These identification layers can be covered on the corresponding physical layers to display the voltage information of the lines in the layout.

[0072] S203. Extract the line name and voltage value in the layout to generate a voltage report for the lines in the layout; Extract the lines in the layout and identify the line voltage according to the DRC rules to generate a voltage report for the lines in the layout.

[0073] The embodiments of the present invention use the tools or scripts provided by the DRC tool to extract the line name and voltage value in the layout. Among them, extracting the lines in the layout and identifying the line voltage according to the DRC rules to generate a voltage report for the lines in the layout includes:

[0074] Layout parsing: Parse the layout file to obtain the physical layout, connection relationship, and attribute information in the layout.

[0075] Line identification: The DRC tool identifies the circuits in the layout, including their geometric features, connection relationships, and other attributes. The circuits in the layout may involve the analysis of the layers, geometric shapes, and components in the layout to identify the positions and features of the circuits.

[0076] Voltage identification extraction: Once the circuits are identified, the DRC tool extracts the voltage identification information from the layout. The voltage identification information includes the analysis of the identification layer, the extraction of text content, and the identification of other relevant attributes.

[0077] Voltage value association: The extracted voltage identification information is associated with the corresponding voltage value. It includes the analysis of the power supply, ground, and other voltage pins in the layout to determine the voltage value associated with each line.

[0078] Data integration: Integrate the extracted line name and voltage value into a format that can be used to generate a report or for subsequent analysis.

[0079] S3. Circuit and layoutFigure 1 Layout vs. Schematic (LVS) check is performed to compare whether the voltage labels of the lines in the layout and the circuit are consistent, and a validity report of the voltage labels of the layout lines is generated.

[0080] As Figure 5 shown, in step S3, it is checked whether the voltage labels of the lines in the layout and the circuit are consistent, and a validity report of the voltage labels of the layout lines is generated, which specifically includes the following steps:

[0081] S301. Obtain the correspondence between the layout and circuit line names by converting the LVS intermediate result data through an EDA tool; specifically: use the tools or scripts provided by the EDA tool to convert the LVS intermediate result data into a format for analysis, including extracting the line names, voltage labels, and layout information in the LVS intermediate results, comparing and analyzing the layout and circuit line names, and obtaining a correspondence table of the layout and circuit line names.

[0082] S302. Run a script to compare the voltage values of the same line in the circuit and the layout, and generate a difference report.

[0083] Specifically, it includes:

[0084] Find the same line in the circuit and the layout according to the correspondence table of the layout and circuit line names.

[0085] Compare the voltage values of the same line in the circuit simulation result and the layout extraction through a script or program. This comparison process includes matching, sorting, and comparing the two sets of voltage value data to determine whether there are differences in voltage values.

[0086] Generate a difference report. If the voltage values of the same line in the circuit and the layout are inconsistent, mark the line and its voltage value, and generate a difference report. The difference report includes the inconsistent line names, voltage values, and other relevant information.

[0087] S303. Judge the consistency between the circuit and the layout according to the difference report;

[0088] If the voltages of the same line in the circuit and the layout are inconsistent, it means that the layout and the circuit are inconsistent. At this time, the following processing is included:

[0089] Fill in the voltage label as invalid in the validity report of the voltage labels of the layout lines.

[0090] Analyze the difference report to determine the reasons and impacts of the inconsistency. By analyzing the reasons and impacts of the inconsistency, more accurate subsequent adjustments and modifications can be made.

[0091] Modify the voltage identifiers corresponding to the layout. According to the information in the differentiation report, modify the inconsistent voltage identifiers corresponding to the layout. This can be done by editing the layout file or using the tools provided by the EDA tool.

[0092] Iterate the process of steps S301 - S303 until the voltage identifiers of all lines in the layout are consistent with the circuit. The process of the iterative steps S301 - S303 includes repeatedly performing the above comparison, analysis, and modification processes until the voltage identifiers of all lines in the layout are consistent with the circuit. This iterative process can be completed by repeatedly running scripts, generating reports, and making corresponding modifications and adjustments.

[0093] In this embodiment, the correctness and effectiveness of the voltage identifier values of the layout lines are verified by the line voltage values under the actual working conditions of the circuit, avoiding the situation where the line voltage is unreasonable due to the incorrect use of the identification layer or voltage value by humans, thereby avoiding affecting the result of the pitch requirement rule check caused by the line voltage difference.

[0094] In this embodiment, by means of circuit simulation and layout extraction, it is ensured that the voltage identifiers of the lines in the layout are consistent with the actual voltages in the circuit. This helps to discover and solve the problems of inconsistency between the layout and the circuit during the design process, thereby ensuring the accuracy and reliability of the design.

[0095] In this embodiment, the voltage identifiers of the lines in the inconsistent layout are also modified according to the differentiation report, and the process of circuit and layout Figure 1 consistency check is iterated until the voltage identifiers of all lines in the layout are consistent with the circuit. This not only solves the problem of inconsistency between the layout and the circuit, but also improves the accuracy and reliability of the effectiveness check of the layout line voltage.

[0096] Embodiment 2

[0097] As Figure 6 shown, the present invention provides a system for checking the effectiveness of the voltage identifiers of layout lines, which is applied to a method for checking the effectiveness of the voltage identifiers of layout lines as in Embodiment 1. The system includes:

[0098] A data acquisition module configured to acquire the line voltage information data of the circuit and the layout, where the line voltage information data includes the line name and the voltage value;

[0099] A data processing module configured to compare and analyze the line names and voltage values of the circuit and the layout acquired by the data acquisition module;

[0100] A data optimization module configured to optimize the inconsistent data after comparison in the data processing module, specifically by modifying the voltage identifiers corresponding to the layout until the voltage identifiers of all lines in the layout are consistent with the circuit.

[0101] Embodiment 3

[0102] As shown in Figure 7 FIG. 5, the present invention further provides an electronic device 2, including a processor 21 and a memory 22. The memory 22 is used to store computer program code, and the computer program code includes computer instructions. When the processor 21 executes the computer instructions, the electronic device executes a cdm esd risk analysis method for an internal circuit of an SoC in the above embodiment.

[0103] The electronic device 2 further includes an input device 24 and an output device 23. The processor 21, the memory 22, the input device 24, and the output device 23 are coupled through a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling means being interconnected in a specific manner, including being directly connected or indirectly connected through other devices. For example, they can be connected through various interfaces, transmission lines, buses, etc.

[0104] The processor 21 can be one or more graphics processing units (GPUs). When the processor 21 is a single GPU, the GPU can be a single-core GPU or a multi-core GPU. Optionally, the processor 21 can be a processor group composed of multiple GPUs, and multiple processors are coupled to each other through one or more buses. Optionally, the processor can also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0105] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the solution of the present invention. Optionally, the memory includes, but is not limited to, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a compact disc read-only memory (CD-ROM), and the memory is used for relevant instructions and data.

[0106] The input device 24 is used to input data and / or signals, and the output device 23 is used to output data and / or signals. The output device 23 and the input device 24 can be independent devices or an integrated device.

[0107] In several embodiments provided by the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there can be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling, direct coupling, or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the modules can be in electrical, mechanical, or other forms.

[0108] The modules described as separate components may or may not be physically separated. The components shown as modules may or may not be physical modules, that is, they can be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0109] In addition, in each embodiment of the present application, the functional modules can be integrated into a processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0110] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, read-only memory), random access memories (RAM, random access memory), magnetic disks, or optical discs that can store program codes.

[0111] The above are only specific implementation manners of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for checking the validity of voltage identification of a layout line, characterized in that: Including the steps: Obtain the line voltage of the circuit, including the line name and voltage value; Obtain the layout line voltage identifier, including the line name and voltage value; Compare whether the layout line voltage identifier is consistent with the line voltage of the circuit, and generate a validity report of the voltage identifier of the layout line; The obtaining of the line voltage of the circuit, including the line name and voltage value, specifically includes: Create a circuit; Set test stimuli; Run the simulation to obtain simulation results; Save the line name and voltage value in the circuit from the simulation results; The setting of the test stimuli is to create test stimuli according to the actual working conditions of the circuit, including the reference voltages of all lines in the designed circuit; the format of the exported simulation results is a text file or a spreadsheet; The obtaining of the voltage identifier of the layout line specifically includes: Create a layout; Define the line voltage identifier layer; select the voltage identifier layer to cover the corresponding physical layer; Extract the line name and voltage value in the layout to generate a voltage report of the lines in the layout; The generating of the voltage report of the lines in the layout includes extracting the lines in the layout and identifying the line voltage according to the DRC rules to generate a voltage report of the lines in the layout, specifically including: Layout parsing: Parse the layout file to obtain the physical layout, connection relationship and attribute information in the layout; Line identification: The DRC tool identifies the lines in the layout, including their geometric features, connection relationship and other attributes; Voltage identifier extraction: The DRC tool extracts voltage identifier information from the layout; Comparing whether the layout line voltage identifier is consistent with the line voltage of the circuit and generating a validity report of the voltage identifier of the layout line specifically includes the steps: S301. Obtain the corresponding relationship between the layout and the circuit line names by converting the LVS intermediate result data through an EDA tool; S302. Run a script to compare the voltage values of the same line in the circuit and the layout to generate a difference report; S303. Judge the consistency between the circuit and the layout according to the difference report; In step S303, if the layout and the circuit are inconsistent, then perform the following steps: Fill in the voltage identifier as invalid in the generated validity report of the voltage identifier of the layout line; Analyze the difference report to determine the reasons and impacts of the inconsistency; Modify the corresponding voltage identifier of the layout; When the layout and the circuit are inconsistent, it also includes iterating steps S301 - S303 until the voltage identifiers of all lines in the layout are consistent with the circuit.

2. The method for checking the validity of voltage identification of layout lines according to claim 1, wherein: After the voltage identifier extraction, it also includes: Voltage value association: Associate the extracted voltage identifier information with the corresponding voltage value; Data integration: Integrate the extracted line name and voltage value into a format that can be used to generate a report or for subsequent analysis.

3. A system for checking the validity of voltage markings of a layout line, characterized in that: The system applies a method for checking the validity of the voltage identifier of the layout line as described in any one of claims 1 - 2; the system includes: A data acquisition module configured to collect the line voltage information data of the circuit and the layout, and the line voltage information data includes the line name and voltage value; A data processing module configured to compare and analyze the line names and voltage values of the circuit and the layout collected by the data acquisition module; A data optimization module configured to optimize the inconsistent data after comparison in the data processing module, specifically to modify the corresponding voltage identifier of the layout until the voltage identifiers of all lines in the layout are consistent with the circuit.

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