Vector graphics vision processing method and system based on FPGA acceleration

Abstract

The present invention belongs to the field of image processing technology, and specifically discloses a vector graphics visual processing method and system based on FPGA acceleration, wherein a host computer parses and segments a vector graphics to obtain a number of sub-vector graphics, and then converts the sub-vector graphics into bitmap integer data, and converts the integer data into a data string and transmits it to an FPGA processor, and accelerates the image processing process through the dual FIFO pipeline data operation and parallel processing of the FPGA, and feeds back the final image processing result to the host computer, which stores and outputs the image processing result for display. The present invention utilizes the technical advantages of the dual FIFO pipeline data operation and parallel processing of the FPGA to greatly accelerate the visual image processing process; and the system can be expanded to support the synchronous processing of multiple FPGA data, further improving the system processing efficiency; at the same time, the present invention creates a complete basic technical framework for vector graphics visual hardware acceleration processing based on data flow.

Description

Technical Field

[0001] The present invention belongs to the technical field of image processing, and in particular relates to a vector graphics vision processing method and system based on FPGA acceleration. Background Art

[0002] In recent years, with the development of deep convolutional neural network technology, computer vision processing has been increasingly widely used in various industries and fields, such as industrial automation, autonomous driving technology, and the integration of the Internet of Things. From a computer perspective, the data captured by the sensor is ultimately stored and processed in the form of a bitmap. However, vector graphics, as an indispensable and important role in the design industry, have always been the background support for graphic image formats of various design tools. Therefore, when performing computer vision processing on files in the format supported by the design tool, it is first necessary to convert the vector model or vector-like model into a bitmap, and then import it into the computer vision system for analysis and processing.

[0003] Vector graphics formats generally use functions with the help of markup language to describe a closed figure, which is scalable and distortion-free. Obviously, any closed figure can be described by multiple function expressions. Therefore, vector graphics described by markup language may not be consistent even when describing the same figure, which brings certain challenges to the direct processing and analysis of vector graphics. Bitmaps can be expressed in the form of array matrices through unified format constraints. Therefore, there is only one way to describe a unified bitmap in the same format, which is why bitmaps are particularly favored in computer vision analysis and processing. In short, when vector graphics are analyzed and processed with the help of computer vision, they must first be imported into the system in the form of bitmaps. This process is mainly implemented in the following ways: first, the vector graphics are read with the help of visual sensors and converted into bitmaps; second, in a way similar to screenshots; and the most commonly used method is to parse the vector graphics description language and then directly convert it into a bitmap according to the size.

[0004] However, all three mainstream methods have problems in various aspects. The first two methods will lose the size accuracy information when converting the format. Therefore, if you need to convert according to the user's goal, you may need to add many complicated steps, such as adding size calibration instructions, multi-image fusion, etc. Directly parsing the vector image and converting it into a bitmap can directly obtain the size information from the parsed data. However, this method requires a large amount of running memory in the process of converting large-size vector images, has high requirements on the hardware of the machine, and has a slow conversion speed and a long conversion time. Therefore, there is an urgent need for a method to efficiently process large-size vector images into bitmap results without losing details. Summary of the invention

[0005] The purpose of the present invention is to provide a vector graphics vision processing method and system based on FPGA acceleration to solve the above-mentioned problems existing in the prior art.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a vector graphics vision processing method based on FPGA acceleration, which is applied to a host computer and includes:

[0008] Get the input SVG vector file;

[0009] Perform vector graphics analysis and vector graphics segmentation processing on the SVG vector graphics file to obtain a number of sub-vector graphics data;

[0010] Convert each sub-vector image data into corresponding bitmap data, and convert the bitmap data into a one-dimensional array;

[0011] Performing data conversion processing on each one-dimensional array to obtain a corresponding first transmission data string;

[0012] Using the set frame header data to encapsulate each first transmission data string to obtain a corresponding transmission data frame, sending each data frame to the FPGA processor through the communication interface, so that the FPGA processor receives each data frame for parsing, obtains the frame header data and the first transmission data string, converts the first transmission data string into a corresponding hexadecimal array, and performs dual FIFO pipeline data parallel processing on each hexadecimal array according to the frame header data to obtain a corresponding processed array, and converts the processed array into a corresponding second transmission data string and feeds it back to the communication interface;

[0013] Receive a second transmission data string fed back by the FPGA processor through the communication interface, and convert the second transmission data string into a processed array;

[0014] The processed array is stored and output for display.

[0015] In a possible design, the SVG vector image file is subjected to vector image parsing and vector image segmentation processing to obtain a plurality of sub-vector image data, including:

[0016] The SVG vector image file is parsed to obtain corresponding vector image data and vector image size parameters, and the vector image data is divided into a number of sub-vector image data of the same size according to the vector image size parameters.

[0017] In a possible design, converting each sub-vector image data into corresponding bitmap data, and converting the bitmap data into a one-dimensional array includes:

[0018] Convert each sub-vector image data into corresponding RGB three-color channel data, and convert the RGB three-color channel data into a one-dimensional array.

[0019] In a possible design, performing data conversion processing on each one-dimensional array to obtain a corresponding first transmission data string includes:

[0020] Performing base conversion processing on each one-dimensional array to obtain a corresponding hexadecimal array, and converting each hexadecimal array into a corresponding first transmission data string.

[0021] In a second aspect, the present invention provides a vector graphics visual processing method based on FPGA acceleration, which is applied to an FPGA processor, comprising:

[0022] Receiving a data frame transmitted by a host computer through a communication interface, after the host computer obtains an input SVG vector image file, the SVG vector image file is subjected to vector image parsing and vector image segmentation processing to obtain a plurality of sub-vector image data, each sub-vector image data is converted into corresponding bitmap data, and the bitmap data is converted into a one-dimensional array, each one-dimensional array is subjected to data conversion processing to obtain a corresponding first transmission data string, and each first transmission data string is subjected to data encapsulation by using set frame header data to obtain;

[0023] Parsing the received data frame to obtain corresponding frame header data and a first transmission data string;

[0024] Convert the first transmission data string into a corresponding hexadecimal array, and perform dual FIFO pipeline data parallel processing on each hexadecimal array according to the frame header data to obtain a corresponding processed array;

[0025] The processed array is converted into a corresponding second transmission data string and fed back to the communication interface of the host computer, so that after the host computer receives the second transmission data string, it converts the second transmission data string into the processed array, and stores and outputs the processed array for display.

[0026] In one possible design, when the received data frame is parsed and no frame header data is obtained, the method further includes:

[0027] Return the corresponding data frame to the host computer, and receive the data frame retransmitted by the host computer through the communication interface.

[0028] In a third aspect, the present invention provides a vector graphics visual processing system based on FPGA acceleration, including a host computer and several FPGA processors, wherein a communication connection is established between the host computer and each FPGA processor, the host computer includes an SVG processing module, a data conversion module, an interface communication module and a storage display module, and the FPGA processor includes a data receiving module, a data sending module and a data processing module, wherein:

[0029] The SVG processing module is used to obtain an input SVG vector image file, perform vector image analysis on the SVG vector image file, obtain corresponding vector image data and vector image size parameters, and divide the vector image data into a number of sub-vector image data of the same size according to the vector image size parameters, convert each sub-vector image data into corresponding RGB three-color channel data, and convert the RGB three-color channel data into a one-dimensional array;

[0030] A data conversion module, used for performing base conversion processing on each one-dimensional array to obtain a corresponding hexadecimal array, and converting each hexadecimal array into a corresponding first transmission data string, and converting the second transmission data string into a processed array;

[0031] The interface communication module is used to encapsulate each first transmission data string using the set frame header data to obtain a corresponding transmission data frame, send each data frame to the FPGA processor, and receive a second transmission data string fed back by the FPGA processor;

[0032] The storage and display module is used to store and output the processed array;

[0033] A data receiving module, used for receiving data frames transmitted by the host computer through the interface communication module;

[0034] A data sending module, used for sending the second transmission data string to the interface communication module of the host computer;

[0035] The data processing module is used to parse the received data frame to obtain the corresponding frame header data and the first transmission data string, convert the first transmission data string into a corresponding hexadecimal array, and perform dual FIFO pipeline data parallel processing on each hexadecimal array according to the frame header data to obtain a corresponding processed array, and convert the processed array into a corresponding second transmission data string.

[0036] In one possible design, the interface communication module includes a serial port transceiver unit, a serial port configuration unit and a data encoding and decoding unit; the serial port transceiver unit is used to use the set frame header data to encapsulate each first transmission data string to obtain a corresponding transmission data frame, send each data frame to the FPGA processor, and receive a second transmission data string fed back by the FPGA processor; the serial port configuration unit is used to configure parameters of the serial port transceiver unit; the data encoding and decoding unit is used to encode the data frames sent by the serial port transceiver unit, and decode the second transmission data string received by the serial port transceiver unit.

[0037] In a possible design, the host computer further includes a human-computer interaction interface, and the human-computer interaction interface is used for human-computer interaction between the user and the host computer.

[0038] In one possible design, the FPGA processor also includes a display control module, which is used to display and output the processed array.

[0039] Beneficial effects: The present invention parses and segments the vector graph through the host computer to obtain several sub-vector graphs, then converts the sub-vector graphs into bitmap integer data, converts the integer data into a data string and transmits it to the FPGA processor, accelerates the image processing process through the dual FIFO pipeline data calculation and parallel processing of the FPGA, and feeds back the final image processing results to the host computer, which stores and outputs the image processing results to achieve a fast and efficient vector graph visual processing process. The present invention transfers the digital image processing process to the FPGA by taking advantage of the speed advantage of the FPGA, thereby utilizing the technical advantages of the dual FIFO pipeline data calculation and parallel processing of the FPGA to greatly accelerate the visual image processing process; and the system of the present invention can be expanded to support the synchronous processing of multiple FPGA data, further improving the system processing efficiency; at the same time, the present invention creates a complete basic technical framework for vector graph visual hardware acceleration processing based on data flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 A schematic diagram of the method steps provided in Example 1 of the present invention;

[0042] Figure 2 A schematic diagram of the system structure provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0043] It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention. The specific structures and functional details disclosed herein are only used to describe the exemplary embodiments of the present invention. However, the present invention can be embodied in many alternative forms, and it should not be understood that the present invention is limited to the embodiments set forth herein.

[0044] It should be understood that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments can be understood according to specific circumstances.

[0045] In the following description, certain details are provided to facilitate a complete understanding of the example embodiments. However, it will be appreciated by those of ordinary skill in the art that the example embodiments may be implemented without these certain details. For example, the system may be shown in a block diagram to avoid obscuring the example with unnecessary details. In other embodiments, well-known processes, structures, and techniques may not be shown in unnecessary detail to avoid obscuring the embodiments.

[0046] Embodiment 1:

[0047] This embodiment provides a vector graphics visual processing method based on FPGA acceleration, which can be applied to a corresponding vector graphics visual processing system. The vector graphics visual processing system includes a host computer and an FPGA (field programmable gate array) processor. The FPGA processor has significant advantages in digital image processing due to its high parallel processing capability, real-time pipeline operation and other advantages. Figure 1 As shown, the method comprises the following steps:

[0048] S1. The host computer obtains the input SVG vector image file.

[0049] In specific implementation, after the host computer and the FPGA processor are connected and started and the corresponding initialization configuration is completed, the SVG (Scalable Vector Graphics) vector graphics file to be processed is input to the host computer.

[0050] S2. parse the SVG vector image file to obtain corresponding vector image data and vector image size parameters, and divide the vector image data into a number of sub-vector image data with the same size according to the vector image size parameters.

[0051] In specific implementation, the host computer can parse the SVG vector image file through the corresponding vector image parsing tool to obtain the corresponding vector image data and vector image size parameters, which include vector image width and height parameters. Then, the width and height information of the sub-vector image data can be determined according to the vector image size parameters, and the vector image data can be divided into several sub-vector image data of the same size.

[0052] S3. Convert each sub-vector image data into corresponding RGB three-color channel data, and convert the RGB three-color channel data into a one-dimensional array.

[0053] During specific implementation, the host computer converts each sub-vector image data into corresponding bitmap data, and then converts the bitmap data into a one-dimensional array. Specifically, the host computer can convert each sub-vector image data into corresponding RGB three-color channel data, that is, RGB color space image data, and then organize the RGB three-color channel data into a one-dimensional array of the image.

[0054] S4. Performing base conversion processing on each one-dimensional array to obtain a corresponding hexadecimal array, and converting each hexadecimal array into a corresponding first transmission data string.

[0055] In specific implementation, the host computer can perform base conversion processing on each one-dimensional array to obtain the corresponding hexadecimal array so that the subsequent FPGA processor can process the hexadecimal image data. Then, each hexadecimal array is converted into a corresponding first transmission data string to comply with the corresponding serial port transmission protocol, and the data is transmitted to the FPGA processor through the high-speed serial port.

[0056] S5. The host computer uses the set frame header data to encapsulate each first transmission data string to obtain a corresponding transmission data frame, and sends each data frame to the FPGA processor through the communication interface.

[0057] In specific implementation, the host computer uses the set frame header data to encapsulate each first transmission data string to obtain a corresponding transmission data frame, and then sends each data frame to the FPGA processor through the communication interface. The frame header data corresponds to the corresponding image data processing method.

[0058] S6. The FPGA processor parses the received data frame to obtain the corresponding frame header data and the first transmission data string.

[0059] During specific implementation, the FPGA processor can connect to the host computer through the corresponding serial port receiving module to receive the data frame, and then parse the received data frame to obtain the corresponding frame header data and the first transmission data string. If the FPGA processor does not obtain the corresponding frame header data after parsing, the corresponding data frame is returned to the host computer, and the data frame retransmitted by the host computer through the communication interface is received for parsing.

[0060] S7. The FPGA processor converts the first transmission data string into corresponding hexadecimal arrays, and performs dual FIFO pipeline data parallel processing on each hexadecimal array according to the frame header data to obtain a corresponding processed array.

[0061] In specific implementation, the FPGA processor converts the first transmission data string obtained by parsing into a corresponding hexadecimal array, and then determines the corresponding image data processing method preset according to the frame header data, and performs dual FIFO pipeline data parallel processing on each hexadecimal array based on the image data processing method to obtain the corresponding processed array. Exemplarily, if it is necessary to perform SOBEL edge detection on the image data, the FPGA processor can cache the hexadecimal array into FIFO (first-in first-out queue) every two rows to perform dual FIFO three-row data summation to obtain Gx data. Similarly, every two columns of data are solved through the dual FIFO to obtain Gy data, and then the Gx data and Gy data are aggregated to finally obtain Gxy data. The final edge detection result is determined by comparing the Gxy data with the set threshold, and the processed array after edge detection is obtained.

[0062] S8. The FPGA processor converts the processed array into a corresponding second transmission data string and feeds it back to the communication interface of the host computer.

[0063] During specific implementation, the FPGA processor may convert the processed array into a corresponding second transmission data string, and then feed back the second transmission data string to the communication interface of the host computer through the serial port sending module.

[0064] S9. The host computer receives the second transmission data string fed back by the FPGA processor through the communication interface, and converts the second transmission data string into a processed array.

[0065] In a specific implementation, the host computer receives the second transmission data string fed back by the FPGA processor through the communication interface, and then decodes and converts the second transmission data string into a processed array.

[0066] S10. The host computer stores and outputs the processed array for display.

[0067] During specific implementation, the host computer can store and output the processed array for display, so that the user can intuitively view the image information composed of the processed array.

[0068] The method of this embodiment takes advantage of the speed of FPGA to transfer the digital image processing process to FPGA, thereby utilizing the technical advantages of FPGA's dual FIFO pipeline data calculation and parallel processing to greatly accelerate the visual image processing process. At the same time, the method of this embodiment creates a complete basic technical framework for vector graphics visual hardware acceleration processing based on data flow.

[0069] Embodiment 2:

[0070] This embodiment provides a vector graphics visual processing system based on FPGA acceleration, such as Figure 2As shown, it includes a host computer and several FPGA processors, and a communication connection is established between the host computer and each FPGA processor. The host computer includes an SVG processing module, a data conversion module, an interface communication module and a storage display module. The FPGA processor includes a data receiving module, a data sending module and a data processing module, wherein:

[0071] The SVG processing module is used to obtain the input SVG vector image file, perform vector image analysis on the SVG vector image file, obtain the corresponding vector image data and vector image size parameters, and divide the vector image data into several sub-vector image data of the same size according to the vector image size parameters, convert each sub-vector image data into the corresponding RGB three-color channel data, and convert the RGB three-color channel data into a one-dimensional array.

[0072] The data conversion module is used to perform base conversion processing on each one-dimensional array to obtain a corresponding hexadecimal array, and convert each hexadecimal array into a corresponding first transmission data string, and convert the second transmission data string into a processed array. The data processing module needs to complete the conversion between the actual image data and the communication interface transmission data. When the host computer sends data to the FPGA end, it is necessary to convert the integer pixel data in the array form into the corresponding transmission protocol data to realize communication input. Correspondingly, the data received by the host computer at the FPGA end is string information, which requires converting the string information into integer image data in a conventional array format, so as to facilitate the analysis and processing of subsequent processes.

[0073] The interface communication module is used to encapsulate each first transmission data string using the set frame header data to obtain the corresponding transmission data frame, send each data frame to the FPGA processor through the serial port communication module, and receive the second transmission data string fed back by the FPGA processor.

[0074] The storage and display module is used to store and output the processed array;

[0075] A data receiving module is used to receive data frames transmitted by the host computer through the serial communication module;

[0076] A data sending module, used for sending the second transmission data string to the interface communication module of the host computer;

[0077] The data processing module is used to parse the received data frame to obtain the corresponding frame header data and the first transmission data string, convert the first transmission data string into a corresponding hexadecimal array, and perform dual FIFO pipeline data parallel processing on each hexadecimal array according to the frame header data to obtain a corresponding processed array, and convert the processed array into a corresponding second transmission data string.

[0078] Further, a PCIE high-speed communication connection, a UART serial communication connection or an Ethernet communication connection can be established between the host computer and each FPGA processor, and the interface communication module of the host computer and the data receiving module and the data sending module of the FPGA processor can be configured according to the communication connection mode adopted. Exemplarily, when serial communication is adopted, the interface communication module may include a serial transceiver unit, a serial configuration unit and a data encoding and decoding unit; the serial transceiver unit is used to encapsulate each first transmission data string using the set frame header data to obtain a corresponding transmission data frame, send each data frame to the FPGA processor through the serial communication module, and receive the second transmission data string fed back by the FPGA processor; the serial configuration unit is used to configure the parameters of the serial transceiver unit, including port configuration, baud rate configuration and sending timeout configuration. The serial data receiving function needs to work after the serial port is opened, so it needs independent thread processing; the data encoding and decoding unit is used to encode the data frame sent by the serial transceiver unit, and decode the second transmission data string received by the serial transceiver unit, and so on.

[0079] Furthermore, the host computer also includes a human-computer interaction interface, and the human-computer interaction interface is used for human-computer interaction between the user and the host computer.

[0080] Furthermore, the FPGA processor also includes a display control module, which is used to display and output the processed array. The communication interface of the FPGA processor only has two data signals, namely, a sending signal TX and a receiving signal RX. Therefore, it is necessary to implement the conversion of serial data to image data on the FPGA. The data receiving module converts the serially transmitted data into hexadecimal image data to facilitate subsequent data processing. The data sending module implements the conversion of the result image data to serial data, thereby realizing serial communication. The data processing module of the FPGA processor is the core of the accelerator. After the data is transmitted to the FPGA processor through the interface, the module is responsible for parsing the data and performing data processing. The processing module can realize two-level FIFO pipeline operation and realize processing acceleration through a parallel state machine framework.

[0081] Embodiment 3:

[0082] This embodiment provides a host computer, including:

[0083] Data interface, used to establish data connection between the processor and external devices;

[0084] A memory for storing execution instructions;

[0085] The processor is used to read the execution instruction stored in the memory and execute the processing steps of the host computer in Example 1 according to the execution instruction.

[0086] Optionally, the system further includes an internal bus, through which the processor, the memory and the data interface can be interconnected, and the internal bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0087] The memory may include, but is not limited to, random access memory (RAM), read only memory (ROM), flash memory, first input first output (FIFO) and / or first in last out (FILO) memory, etc. The processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0088] Embodiment 4:

[0089] This embodiment provides a computer-readable storage medium, on which execution instructions are stored. When the execution instructions are executed on a computer, the computer executes the processing steps of the host computer in Embodiment 1. The computer-readable storage medium refers to a carrier for storing data, which may include but is not limited to a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash drive, and / or a memory stick, etc. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0090] This embodiment further provides a computer program product, which, when executed on a computer, executes the processing steps of the host computer in Embodiment 1. The computer may be a general-purpose computer, a special-purpose computer, a computer network or other programmable device.

[0091] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A vector graphics visual processing method based on FPGA acceleration is applied to a host computer, characterized in that: include: Get the input SVG vector file; Perform vector graphics analysis and vector graphics segmentation processing on the SVG vector graphics file to obtain a number of sub-vector graphics data; Convert each sub-vector image data into corresponding bitmap data, and convert the bitmap data into a one-dimensional array; Performing data conversion processing on each one-dimensional array to obtain a corresponding first transmission data string; Using the set frame header data to encapsulate each first transmission data string to obtain a corresponding transmission data frame, sending each data frame to the FPGA processor through the communication interface, so that the FPGA processor receives each data frame for parsing, obtains the frame header data and the first transmission data string, converts the first transmission data string into a corresponding hexadecimal array, and performs dual FIFO pipeline data parallel processing on each hexadecimal array according to the frame header data to obtain a corresponding processed array, and converts the processed array into a corresponding second transmission data string and feeds it back to the communication interface; Receive a second transmission data string fed back by the FPGA processor through the communication interface, and convert the second transmission data string into a processed array; The processed array is stored and output for display.

2. The vector graphics visual processing method based on FPGA acceleration according to claim 1 is characterized in that: The SVG vector image file is subjected to vector image parsing and vector image segmentation processing to obtain a plurality of sub-vector image data, including: The SVG vector image file is parsed to obtain corresponding vector image data and vector image size parameters, and the vector image data is divided into a number of sub-vector image data of the same size according to the vector image size parameters.

3. The vector graphics visual processing method based on FPGA acceleration according to claim 1 is characterized in that: The step of converting each sub-vector image data into corresponding bitmap data and converting the bitmap data into a one-dimensional array includes: Convert each sub-vector image data into corresponding RGB three-color channel data, and convert the RGB three-color channel data into a one-dimensional array.

4. The vector graphics visual processing method based on FPGA acceleration according to claim 1 is characterized in that: The step of performing data conversion processing on each one-dimensional array to obtain a corresponding first transmission data string includes: Performing base conversion processing on each one-dimensional array to obtain a corresponding hexadecimal array, and converting each hexadecimal array into a corresponding first transmission data string.

5. A vector graphics visual processing method based on FPGA acceleration, applied to an FPGA processor, characterized in that: include: Receiving a data frame transmitted by a host computer through a communication interface, after the host computer obtains an input SVG vector image file, the SVG vector image file is subjected to vector image parsing and vector image segmentation processing to obtain a plurality of sub-vector image data, each sub-vector image data is converted into corresponding bitmap data, and the bitmap data is converted into a one-dimensional array, each one-dimensional array is subjected to data conversion processing to obtain a corresponding first transmission data string, and each first transmission data string is subjected to data encapsulation by using set frame header data to obtain; Parsing the received data frame to obtain corresponding frame header data and a first transmission data string; Convert the first transmission data string into a corresponding hexadecimal array, and perform dual FIFO pipeline data parallel processing on each hexadecimal array according to the frame header data to obtain a corresponding processed array; The processed array is converted into a corresponding second transmission data string and fed back to the communication interface of the host computer, so that after the host computer receives the second transmission data string, it converts the second transmission data string into the processed array, and stores and outputs the processed array for display.

6. The vector graphics visual processing method based on FPGA acceleration according to claim 5 is characterized in that: When the received data frame is parsed and no frame header data is obtained, the method further includes: Return the corresponding data frame to the host computer, and receive the data frame retransmitted by the host computer through the communication interface.

7. The vector graphics visual processing system based on FPGA acceleration is characterized by: It includes a host computer and several FPGA processors, wherein a communication connection is established between the host computer and each FPGA processor, the host computer includes an SVG processing module, a data conversion module, an interface communication module and a storage display module, and the FPGA processor includes a data receiving module, a data sending module and a data processing module, wherein: The SVG processing module is used to obtain an input SVG vector image file, perform vector image analysis on the SVG vector image file, obtain corresponding vector image data and vector image size parameters, and divide the vector image data into a number of sub-vector image data of the same size according to the vector image size parameters, convert each sub-vector image data into corresponding RGB three-color channel data, and convert the RGB three-color channel data into a one-dimensional array; A data conversion module, used for performing base conversion processing on each one-dimensional array to obtain a corresponding hexadecimal array, and converting each hexadecimal array into a corresponding first transmission data string, and converting the second transmission data string into a processed array; The interface communication module is used to encapsulate each first transmission data string using the set frame header data to obtain a corresponding transmission data frame, send each data frame to the FPGA processor, and receive a second transmission data string fed back by the FPGA processor; The storage and display module is used to store and output the processed array; A data receiving module, used for receiving data frames transmitted by the host computer through the interface communication module; A data sending module, used for sending the second transmission data string to the interface communication module of the host computer; The data processing module is used to parse the received data frame to obtain the corresponding frame header data and the first transmission data string, convert the first transmission data string into a corresponding hexadecimal array, and perform dual FIFO pipeline data parallel processing on each hexadecimal array according to the frame header data to obtain a corresponding processed array, and convert the processed array into a corresponding second transmission data string.

8. The vector graphics visual processing system based on FPGA acceleration according to claim 7 is characterized in that: The interface communication module includes a serial port transceiver unit, a serial port configuration unit and a data encoding and decoding unit; the serial port transceiver unit is used to use the set frame header data to encapsulate each first transmission data string to obtain a corresponding transmission data frame, send each data frame to the FPGA processor, and receive a second transmission data string fed back by the FPGA processor; the serial port configuration unit is used to configure parameters of the serial port transceiver unit; the data encoding and decoding unit is used to encode the data frame sent by the serial port transceiver unit, and decode the second transmission data string received by the serial port transceiver unit.

9. The vector graphics visual processing system based on FPGA acceleration according to claim 7 is characterized in that: The host computer also includes a human-computer interaction interface, and the human-computer interaction interface is used for human-computer interaction between a user and the host computer.

10. The vector graphics visual processing system based on FPGA acceleration according to claim 7, characterized in that: The FPGA processor also includes a display control module, and the display control module is used to display and output the processed array.

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