A programmable ctt-based memory readout circuit mismatch cancellation system

Abstract

The application provides a memory readout circuit imbalance elimination system based on a programmable CTT, which comprises a programmable CTT, a memory readout circuit and a time-to-digital converter; the programmable CTT is arranged in the memory readout circuit, and the time-to-digital converter is connected with the memory readout circuit; the time-to-digital converter is configured to acquire readout data of the memory readout circuit, judge whether the memory readout circuit is imbalanced according to the readout data, and generate a judgment result; the memory readout circuit is configured to output the readout data; and whether the programmable CTT is programmed is judged according to the judgment result. The application solves the application limitation problem of the existing readout circuit imbalance elimination technology through the above system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and particularly relates to a memory readout circuit offset cancellation system based on a programmable CTT. BACKGROUND

[0002] In the design and operation of electronic systems, the offset cancellation of memory readout circuits has always been an important technical challenge. In order to ensure the accuracy and stability of data, the industry has adopted various methods to deal with this problem. Among them, the auto-zero technology has become one of the main methods for offset cancellation of memory readout circuits due to its unique working principle and high precision.

[0003] The auto-zero technology is a time-domain modulation method that mainly corrects the offset through sampling. This technology is often combined with a switched-capacitor circuit, which stores the offset voltage on the capacitor during the sampling stage, and then eliminates the offset during the signal operation stage. The offset voltage of this method can exist at the input or output of the operational amplifier, and its working principle depends on the high gain characteristics of the operational amplifier itself.

[0004] In the implementation process of the auto-zero technology, the circuit will go through two main stages: the Offset cancellation period (AZ stage) and the signal amplification period (AMP stage). In the AZ stage, the circuit will disconnect the signal input and connect the input of the operational amplifier to the AC ground (VCM). At this time, the switched-capacitor will store the charge generated by the offset voltage (Vos). In the AMP stage, the signal input will be connected to the loop, at this time, the offset voltage charge stored in the capacitor will participate in the operation together with the input signal, but since the offset voltage has been pre-sampled and stored in the capacitor, it will be eliminated during the signal amplification process, thereby achieving correction of the offset.

[0005] However, the auto-zero technology also has some obvious limitations. First, since this technology requires dynamic refreshing, it is not suitable for continuous time applications. This means that in some cases where continuous signal processing is required, the auto-zero technology may not meet the requirements. Second, the overall circuit structure of the auto-zero technology is relatively complex, which increases the difficulty of design and implementation. In addition, the sampling process can also cause noise to return to low frequency and produce aliasing, which manifests as high low-frequency noise. SUMMARY

[0006] The present application provides a memory readout circuit offset cancellation system based on a programmable CTT to solve the application limitations of existing readout circuit offset cancellation technologies.

[0007] The system comprises:

[0008] The programmable CTT is arranged in the memory readout circuit, and the time-to-digital converter is connected with the memory readout circuit.

[0009] The time-to-digital converter is configured to acquire readout data of the memory readout circuit, and determine whether the memory readout circuit is out of adjustment according to the readout data, and generate a determination result.

[0010] The memory readout circuit is configured to output the readout data, and determine whether to program the programmable CTT according to the determination result.

[0011] Preferably, the memory readout circuit comprises a positive output OUT, a negative output OUTB and a clock signal port CLK.

[0012] The memory readout circuit is further configured to:

[0013] respectively acquire a first voltage transformation condition of the positive output OUT and a second voltage transformation condition of the negative output OUTB;

[0014] acquire a signal value transformation condition of the clock signal port CLK;

[0015] calculate a first time from when the positive output OUT starts to appear the first voltage transformation condition to when the clock signal port CLK completes the signal value transformation condition;

[0016] calculate a second time from when the negative output OUTB starts to appear the second voltage transformation condition to when the clock signal port CLK completes the signal value transformation condition;

[0017] differ the first time from the second time to obtain the readout data.

[0018] Preferably, the memory readout circuit further comprises a first circuit input BL and a second circuit input BLB.

[0019] When a voltage difference appears between the first circuit input BL and the second circuit input BLB, the positive output OUT or the negative output OUTB appears a voltage transformation condition, and the clock signal port CLK appears a signal value transformation condition.

[0020] Preferably, when the voltage difference between the first circuit input BL and the second circuit input BLB is a negative voltage difference, the positive output OUT is converted from a high level to a low level; and the first voltage transformation condition is process information of the positive output OUT converted from the high level to the low level.

[0021] when the voltage difference between the first circuit input BL and the second circuit input BLB is a positive voltage difference, the inverted output OUTB is converted from high level to low level; the second voltage conversion condition is the process information of the inverted output OUTB being converted from high level to low level.

[0022] Preferably, the programmable CTT includes CTT1 and CTT2; the CTT1 is arranged at one end of the first circuit input BL, and the CTT2 is arranged at one end of the second circuit input BLB.

[0023] The memory readout circuit is further configured to:

[0024] According to the numerical value of the judgment result, it is judged whether to program the CTT1 or the CTT2.

[0025] Preferably, the time-to-digital converter is further configured to:

[0026] When the numerical value of the readout data is less than zero, a first judgment result is generated;

[0027] When the numerical value of the readout data is greater than zero, a second judgment result is generated;

[0028] The memory readout circuit is further configured to:

[0029] According to the first judgment result, the CTT1 is programmed;

[0030] According to the second judgment result, the CTT2 is programmed.

[0031] Preferably, the time-to-digital converter includes a quantization port STP, which is connected with the non-inverted output OUT and the inverted output OUTB respectively, and the quantization port STP is configured to:

[0032] Obtain first quantization data of the non-inverted output OUT and second quantization data of the inverted output OUTB;

[0033] Difference between the first quantization data and the second quantization data is obtained to obtain target quantization data;

[0034] According to the target quantization data, it is judged whether to program the CTT1 or the CTT2.

[0035] Preferably, the signal numerical value conversion condition is the process information of the clock signal port CLK being converted from low voltage to high voltage; the time-to-digital converter further includes a plurality of delay units d, and the frontmost delay unit d is connected with the clock signal port CLK.

[0036] The front delay unit d is configured to:

[0037] When the voltage of the clock signal port CLK changes, the signal value change of the clock signal port CLK is sent to the next delay unit d after a preset time.

[0038] Preferably, the time-to-digital converter further comprises a plurality of comparators A;

[0039] The comparator A is configured to:

[0040] The first quantization data and the second quantization data are subtracted to obtain target quantization data.

[0041] Preferably, the time-to-digital converter further comprises a plurality of interpolation circuits PI, all the interpolation circuits PI are connected in parallel, every three interpolation circuits PI are connected in parallel between two delay units d, and the interpolation circuits PI in the same group are connected with the corresponding comparators A.

[0042] The interpolation circuit PI is configured to:

[0043] The signal value change of the front delay unit d is sent to the comparator A after half of the preset time.

[0044] From the above, the application provides a memory readout circuit imbalance elimination system based on a programmable CTT, which comprises a programmable CTT, a memory readout circuit and a time-to-digital converter; the programmable CTT is arranged in the memory readout circuit, the time-to-digital converter is connected with the memory readout circuit; the time-to-digital converter is configured to acquire readout data of the memory readout circuit, and determine whether the memory readout circuit is imbalanced according to the readout data, and generate a determination result; the memory readout circuit is configured to output the readout data; and whether the programmable CTT is programmed is determined according to the determination result. The application solves the application limitation problem of the existing readout circuit imbalance elimination technology through the above system. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0046] Figure 1 A schematic diagram of the memory readout circuit imbalance elimination system based on a programmable CTT of the application;

[0047] Figure 2 Embodiment schematic diagram of a memory readout circuit in a memory readout circuit imbalance elimination system based on a programmable CTT according to the present application;

[0048] Figure 3 Embodiment schematic diagram of a time-to-digital converter in a memory readout circuit imbalance elimination system based on a programmable CTT according to the present application;

[0049] Figure 4 Embodiment schematic diagram of an interpolation circuit PI in a memory readout circuit imbalance elimination system based on a programmable CTT according to the present application;

[0050] Figure 5 Embodiment schematic diagram of a comparator A in a memory readout circuit imbalance elimination system based on a programmable CTT according to the present application;

[0051] Figure 6 Waveform diagram of quantization processing of a time-to-digital converter in a memory readout circuit imbalance elimination system based on a programmable CTT according to the present application. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0053] It should be noted that the brief description of the terms in the present application is only for the convenience of understanding the subsequently described embodiments, and is not intended to limit the embodiments of the present application. Unless otherwise specified, these terms should be understood according to their ordinary and general meanings.

[0054] The terms "first", "second", "third", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit the specific order or sequence, unless otherwise specified. It should be understood that the terms used in this way can be interchanged under appropriate circumstances.

[0055] Figure 1 Schematic diagram of a memory readout circuit imbalance elimination system based on a programmable CTT according to the present application.

[0056] Reference is made to Figure 1It can be known that the embodiment provides a memory readout circuit imbalance elimination system based on a programmable CTT, the system comprises a programmable CTT, a memory readout circuit and a time-to-digital converter; the programmable CTT is arranged in the memory readout circuit, and the time-to-digital converter is connected with the memory readout circuit; the time-to-digital converter is configured to acquire readout data of the memory readout circuit, and determine whether the memory readout circuit is imbalanced according to the readout data, and generate a determination result; the memory readout circuit is configured to output the readout data; and whether the programmable CTT is programmed is determined according to the determination result.

[0057] Specifically, in the embodiment, the embodiment is used to eliminate the mismatch characteristics (imbalanced voltage) of the memory readout circuit caused by process errors. By utilizing the different output delays of the readout '1' and '0' of the memory readout circuit caused by the imbalanced voltage, the programmable CTT in the memory readout circuit is programmed to make the output delays of the readout '1' and '0' consistent, so as to achieve the purpose of eliminating the imbalanced voltage.

[0058] Figure 2 An implementation schematic diagram of a memory readout circuit in a memory readout circuit imbalance elimination system based on a programmable CTT of the application.

[0059] Among them, Figure 2 T1 to T12 in the embodiment are CMOS tubes; CH and CHB are ports when the programmable CTT is programmed; when the programmable CTT is programmed, the CH port drops from 0.9V to 0V, and the CHB port rises from 0V to 0.9V; when normally working, the voltage of the CH port is 0.9V, and the voltage of the CHB port is 0V; CLK is the clock signal port CLK; OUT is the positive output OUT; OUTB is the inverted output OUTB; BL is the first circuit input BL; BLB is the second circuit input BLB; HV_CH is the programming port, when the programmable CTT is programmed, the HV_CH port drops from 1.8V to 0V, and when normally working, the voltage of the HV_CH port is 1.8V; HV_P1 and HV_P2 are both programming signal ends, if CTT1 is programmed, the voltage of HV_P1 is 1.8V, and the voltage of HV_P2 is 0V; if CTT2 is programmed, the voltage of HV_P1 is 0V, and the voltage of HV_P2 is 1.8V; P1 and P2 are thick gate oxide tubes, which can withstand 1.8V voltage.

[0060] Referring to Figure 2 It can be known that, further, in some embodiments, the memory readout circuit comprises a positive output OUT, an inverted output OUTB and a clock signal port CLK;

[0061] The memory readout circuit is further configured to:

[0062] respectively acquire a first voltage transformation condition of the positive output OUT and a second voltage transformation condition of the negative output OUTB;

[0063] acquire a signal value transformation condition of the clock signal port CLK;

[0064] calculate a first time from when the positive output OUT starts to appear the first voltage transformation condition to when the clock signal port CLK completes the signal value transformation condition;

[0065] calculate a second time from when the negative output OUTB starts to appear the second voltage transformation condition to when the clock signal port CLK completes the signal value transformation condition;

[0066] obtain the readout data by subtracting the first time from the second time.

[0067] Specifically, in the embodiment, since the clock signal of the clock signal port CLK reaches the positive output OUT and the negative output OUTB at different times, the readout circuit can output the readout '1' and '0' of the clock signal port CLK caused by the misadjustment voltage.

[0068] wherein the first time from when the positive output OUT starts to appear the first voltage transformation condition to when the clock signal port CLK completes the signal value transformation condition is the time required for the clock signal to reach the clock signal port CLK from the positive output OUT, and the second time from when the negative output OUTB starts to appear the second voltage transformation condition to when the clock signal port CLK completes the signal value transformation condition is the time required for the clock signal to reach the clock signal port CLK from the negative output OUTB.

[0069] The readout data obtained by subtracting the first time from the second time is used to identify whether the readout circuit has a circuit misadjustment problem.

[0070] wherein the memory readout circuit further comprises a first circuit input BL and a second circuit input BLB; when a voltage difference appears between the first circuit input BL and the second circuit input BLB, the positive output OUT or the negative output OUTB appears a voltage transformation condition, and the clock signal port CLK appears a signal value transformation condition.

[0071] wherein since the voltage difference between the first circuit input BL and the second circuit input BLB is not maintained constant, for different voltage differences, the embodiment has the following implementation manners:

[0072] When the voltage difference between the first circuit input BL and the second circuit input BLB is a negative voltage difference, the non-inverted output OUT transitions from high to low; the first voltage conversion case is the process information of the non-inverted output OUT transitioning from high to low;

[0073] When the voltage difference between the first circuit input BL and the second circuit input BLB is a positive voltage difference, the inverted output OUTB transitions from high to low; the second voltage conversion case is the process information of the inverted output OUTB transitioning from high to low.

[0074] According to Figure 2 It can be known that the programmable CTT includes CTT1 and CTT2; the CTT1 is arranged at one end of the first circuit input BL, and the CTT2 is arranged at one end of the second circuit input BLB. Since the readout data obtained by subtracting the second time from the first time has positive and complex cases, the CTT programming is different for different cases, and therefore it is necessary to judge whether to program the CTT1 or the CTT2 according to the corresponding judgment result generated by the time-to-digital converter through the memory readout circuit.

[0075] The time-to-digital converter generates the corresponding judgment result by judging the positive and negative values of the judgment result, specifically including: when the value of the readout data is less than zero, a first judgment result is generated; when the value of the readout data is greater than zero, a second judgment result is generated.

[0076] Similarly, when the memory readout circuit receives the first judgment result, the CTT1 is programmed; when the memory readout circuit receives the second judgment result, the CTT2 is programmed.

[0077] For example, when there is a voltage difference -ΔV between BL and BLB, CLK rises from 0 to 1, and OUT will change from high to low. The time from CLK rising to OUT falling is T C2OUT . Similarly, when there is a voltage difference ΔV between BL and BLB, CLK rises from 0 to 1, and OUTB will change from high to low. The time from CLK rising to OUTB falling is T C2OUTB . Δt COUT is equal to T C2OUT minus T C2OUTB , and Δt COUT is positively correlated with the offset voltage of the readout circuit. Therefore, by reading 0 and 1, Δt COUT can be obtained, so as to judge whether there is an offset voltage in the circuit.

[0078] The time-to-digital converter is used to determine whether there is an offset voltage, wherein T C2OUT and T C2OUTB The quantization of is achieved by a time-to-digital converter (TDC), which performs the quantization process. Figure 6 .

[0079] Figure 3 This is a schematic diagram of an implementation of a time-to-digital converter in a memory readout circuit offset cancellation system based on programmable CTT in the present application.

[0080] Figure 3 In the figure, d is a delay unit; PI is an interpolation circuit; A is a comparator; VDD can be understood as a power supply voltage; STP is a quantization port STP.

[0081] See also Figure 3 It can be seen that, further, in some embodiments, the time-to-digital converter includes a quantization port STP, the quantization port STP is connected to the positive phase output OUT and the negative phase output OUTB respectively, and the quantization port STP is configured as follows:

[0082] Acquire first quantized data of the positive phase output OUT and second quantized data of the negative phase output OUTB;

[0083] Subtracting the first quantized data from the second quantized data to obtain target quantized data;

[0084] Whether to program the CTT1 or the CTT2 is determined according to the target quantization data.

[0085] Specifically, in this embodiment, the read data generated by the memory read circuit needs to be quantized before effective data acquisition can be performed. Therefore, the data obtained from the positive-phase output OUT and the negative-phase output OUTB need to be quantized respectively through the quantization port STP on the time-to-digital converter. The specific method can be understood as follows:

[0086] The first quantized data of the positive phase output OUT and the second quantized data of the negative phase output OUTB are obtained respectively, and the difference between the two is processed. The obtained difference data is the final data for measuring whether the circuit is out of adjustment, programming CTT1 or programming CTT2.

[0087] For example, when CLK rises, the counting starts. If STP also rises, the time from CLK to the rising of STP will be converted into a 5-bit digital quantity. When reading 0, STP is the signal of OUT port; when reading 1, STP is the signal of OUTB port. By comparing the 5-bit data D0[4:0] quantified when reading 0 with the 5-bit data D1[4:0] quantified when reading 1, it can be determined whether there is a misadjustment voltage. If the two 5-bit data values are the same, it is considered that there is no misadjustment voltage; if they are different, the CTT1 or CTT2 of the reading circuit will be programmed to increase the VTH value thereof.

[0088] When D0[4:0] is less than D1[4:0], it indicates that ΔtCQ is less than 0, and thus CTT1 needs to be programmed. The specific operation is as follows: set HV_CH and CH voltage to 0V, set CHB to 0.9V, and apply a 1.8V voltage pulse to CTT1 through HV_P1 to program the VTH of CTT1 to rise. After the programming is completed, 0 and 1 are read again to obtain D0[4:0] and D1[4:0], and comparison is made. If they are equal, it is considered that the misadjustment voltage has been eliminated; if they are not equal, the programming is continued until they are equal.

[0089] Further, in some embodiments, the signal value conversion condition is the process information of the clock signal port CLK from low voltage to high voltage; the time-to-digital converter further comprises a plurality of delay units d, and the first delay unit d is connected with the clock signal port CLK;

[0090] The first delay unit d is configured to:

[0091] When the voltage of the clock signal port CLK changes, the clock signal port CLK in the signal value conversion condition is sent to the next delay unit d after a preset time.

[0092] Specifically, in the embodiment, if the clock signal CLK rises from low voltage to high voltage, the signal CLK1 after the delay unit d needs to rise after a fixed delay time t1. Subsequently, CLK2 can rise after another fixed delay time t1.

[0093] Figure 4 An implementation schematic diagram of the interpolation circuit PI in the misadjustment elimination system of the memory reading circuit based on the programmable CTT.

[0094] Figure 5 An implementation schematic diagram of the comparator A in the misadjustment elimination system of the memory reading circuit based on the programmable CTT.

[0095] Referring toFigure 4 and Figure 5 Further, in some embodiments, the time-to-digital converter further comprises a plurality of comparators A;

[0096] The comparators A are configured to:

[0097] Subtracting the first quantization data and the second quantization data, obtaining target quantization data;

[0098] The time-to-digital converter further comprises a plurality of interpolation circuits PI, all the interpolation circuits PI are connected in parallel, every three of the interpolation circuits PI are connected in parallel between two delay units d, and the interpolation circuits PI in the same group are connected with the corresponding comparators A;

[0099] The interpolation circuits PI are configured to:

[0100] The signal value transformation of the front delay unit d is sent to the comparator A after one-half of the preset time.

[0101] Since the time t1 in the integrated circuit has a minimum value, in order to obtain a smaller time t2, we need to process the CLK1 and CLK2 signals to achieve a smaller delay time t2. Therefore, we designed the interpolation circuit PI.

[0102] The interpolation circuit PI divides the delay t1 of CLK1 to CLK2 into two equal t2. For example, Figure 3 Among the outputs of CLK1 and CLK2, O<1> is the result of the interpolation circuit PI when both inputs are CLK1, O<3> is the result when both inputs are CLK2, and O<2> is the result when the two inputs are CLK1 and CLK2 respectively. Since the delay between CLK1 and CLK2 is t1, the interpolation circuit PI can divide t1 into two equal t2, so O<2> is delayed by 0.5t1 compared to O<1>, and is 0.5t1 faster than O<3>.

[0103] It can be understood that the phase interpolation circuit PI can divide the difference t between the rising time of PI1 and the rising time of PI2 into two equal parts. For example, when PI1 changes from low to high at time t1, and PI2 changes to high at time 2t1, then OUT will change from low to high at time 1.5t1.

[0104] The outputs O1 to O31 of the 31 interpolation circuits PI are connected to the CQ ports of the 31 comparators A, and the STP ports of the 31 comparators A are connected. When the voltage of the CQ port rises earlier than the voltage of the STP port, the output AOUT of the comparator A is high; otherwise, when the voltage of the CQ port rises later than the voltage of the STP port, the output AOUT of the comparator A is low. Therefore, when CLK rises, the CLK signal passes through a series of delay units d, is connected to the interpolation circuits PI, and is finally transmitted to the CQ ports of the comparators A. When the STP also rises, the time between CLK and STP will be converted into a digital signal. For example, if the time between CLK and STP is 6t1, the outputs of the first 12 comparators A will be high, and the outputs of 13 to 31 will be low. Finally, the 31 output levels are converted into 5-bit data D[4:0] by the thermometer code to binary code conversion circuit (T2B).

[0105] It can be understood that, in the comparator A, when the rising time of the CQ is earlier than that of the STP, the output of the AOUT is high; if the rising time of the CQ is later than that of the STP, the output of the AOUT is low.

[0106] The embodiment has the following advantages:

[0107] The high-precision offset elimination of the memory readout circuit is realized by a simple and efficient method, and the problem that the circuit offset elimination cannot be performed on continuous time, continuous signal or complex circuit due to the limitation of the auto-zero technology is avoided.

[0108] The similar parts among the embodiments provided in the application can be referred to each other, the specific embodiments provided above are only several examples under the general concept of the application, and do not limit the protection scope of the application. For those skilled in the art, any other embodiments extended according to the application scheme without creative labor are within the protection scope of the application.

Claims

1. A programmable CTT-based memory sense circuit skew cancellation system, comprising: The system comprises a programmable CTT, a memory readout circuit and a time-to-digital converter; the programmable CTT is arranged in the memory readout circuit, and the time-to-digital converter is connected with the memory readout circuit; the programmable CTT comprises a plurality of NMOS transistors; The time-to-digital converter is configured to acquire readout data of the memory readout circuit, and determine whether the memory readout circuit is out of adjustment according to the readout data, and generate a determination result; the determination of whether the circuit is out of adjustment comprises determining whether the forward output result of the time-to-digital converter is the same as the reverse output result; The memory readout circuit is configured to output the readout data; and determine whether to program the programmable CTT according to the determination result; The memory readout circuit comprises a positive output OUT, a negative output OUTB and a clock signal port CLK; The memory readout circuit is further configured to: acquire a first voltage transformation condition of the positive output OUT and a second voltage transformation condition of the negative output OUTB, respectively; acquire a signal value transformation condition of the clock signal port CLK; calculate a first time from when the positive output OUT starts to appear the first voltage transformation condition to when the clock signal port CLK completes the signal value transformation condition; calculate a second time from when the negative output OUTB starts to appear the second voltage transformation condition to when the clock signal port CLK completes the signal value transformation condition; obtain the readout data by subtracting the first time from the second time; The time-to-digital converter is further configured to: compare the value of the readout data with zero, and generate a corresponding determination result; The memory readout circuit is further configured to: program the programmable CTT differently according to the determination result.

2. A programmable CTT-based memory read channel offset cancellation system as claimed in claim 1, wherein, The memory readout circuit further comprises a first circuit input BL and a second circuit input BLB; When a voltage difference appears between the first circuit input BL and the second circuit input BLB, the positive output OUT or the negative output OUTB appears a voltage transformation condition, and the clock signal port CLK appears a signal value transformation condition.

3. A programmable CTT-based memory read channel offset cancellation system as claimed in claim 2, wherein, When the voltage difference between the first circuit input BL and the second circuit input BLB is a negative voltage difference, the positive output OUT is converted from high level to low level; the first voltage transformation condition is the process information of the positive output OUT converted from high level to low level; When the voltage difference between the first circuit input BL and the second circuit input BLB is a positive voltage difference, the negative output OUTB is converted from high level to low level; the second voltage transformation condition is the process information of the negative output OUTB converted from high level to low level.

4. A programmable CTT-based memory read circuit mismatch cancellation system as claimed in claim 3, wherein, The programmable CTT comprises a CTT1 and a CTT2; the CTT1 is arranged at one end of the first circuit input BL, and the CTT2 is arranged at one end of the second circuit input BLB; The memory readout circuit is further configured to: According to the value of the judgment result, it is determined whether to program the CTT1 or the CTT2.

5. A programmable CTT-based memory read circuit mismatch cancellation system as claimed in claim 4, wherein, The time-to-digital converter is further configured to: When the value of the readout data is less than zero, a first judgment result is generated; When the value of the readout data is greater than zero, a second judgment result is generated; The memory readout circuit is further configured to: According to the first judgment result, the CTT1 is programmed; According to the second judgment result, the CTT2 is programmed.

6. A programmable CTT-based memory read circuit mismatch cancellation system as claimed in claim 5, wherein, The time-to-digital converter includes a quantization port STP connected with the non-inverted output OUT and the inverted output OUTB respectively, and the quantization port STP is configured to: Obtain first quantization data of the non-inverted output OUT and second quantization data of the inverted output OUTB; Subtract the first quantization data from the second quantization data to obtain target quantization data; According to the target quantization data, it is determined whether to program the CTT1 or the CTT2.

7. A programmable CTT-based memory read circuit mismatch cancellation system as claimed in claim 6, wherein, The signal value change condition is the process information of the clock signal port CLK from low voltage to high voltage; the time-to-digital converter further includes a plurality of delay units d, and the frontmost delay unit d is connected with the clock signal port CLK; The frontmost delay unit d is configured to: When the clock signal port CLK appears voltage conversion, the clock signal port CLK appears the signal value change condition after a preset time and is sent to the next delay unit d.

8. A programmable CTT-based memory read circuit skew cancellation system according to claim 7, wherein, The time-to-digital converter further includes a plurality of comparators A; The comparator A is configured to: Subtract the first quantization data from the second quantization data to obtain target quantization data.

9. A programmable CTT-based memory read circuit mismatch cancellation system as claimed in claim 8, wherein, The time-to-digital converter further includes a plurality of interpolation circuits PI, all the interpolation circuits PI are connected in parallel, every three interpolation circuits PI are connected in parallel between two delay units d, and the interpolation circuits PI in the same group are connected with the corresponding comparator A; The interpolation circuit PI is configured to: Send the signal value change condition output by the frontmost delay unit d to the comparator A after one-half of the preset time.

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