High-string-number battery BMS control system based on low-voltage analog front end
By using a high string battery BMS control system with low voltage analog front end in the electric drive system, using multi-stage BMS module and cascade MOS control circuit, the problem of AFE chip support limitation at high voltage is solved, and efficient battery voltage sampling is achieved and current sensing reduces power consumption and improves fault handling capabilities.
Patent Information
- Application Number
- CN202411401849.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-01-03
AI Technical Summary
In existing electric drive systems, high voltage leads to a limit on the number of battery strings supported by the AFE chip, requiring cascade chip communication, high cost, large power consumption, and insufficient short-circuit fault handling capabilities.
Adopt a high string-number battery BMS control system based on low voltage analog front end, connect the AFE chip in parallel through multi-stage BMS modules, and use cascade MOS control circuit and MCU module to realize communication and current sampling between the AFE chips, reducing power consumption and increasing faults Processing capability.
It realizes high string battery voltage sampling and current detection, reduces system power consumption, improves short-circuit fault handling capabilities, and avoids high-cost cascade chip communication solutions.
Smart Images
Figure CN119253099A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of battery management systems, and in particular to a control system for a high-number-of-batteries BMS based on a low-voltage analog front end. Background Art
[0002] In the market, in the electric drive system composed of the motor controller, motor and battery pack, the higher the voltage, the higher the system energy efficiency, the smaller the wire diameter required at the same power, the number of three-phase bridge MOS of the motor controller can be effectively reduced, and the system heating can also be suppressed. Electric motorcycles and electric tricycles have a large driving power, which will increase the system voltage, and the number of battery pack strings will also increase, which may exceed 16 strings. In the battery pack, the voltage sampling of each string of batteries is completed using an analog front end. Generally, a front-end battery cell voltage sampling chip (hereinafter referred to as AFE chip) supports sampling 16 strings or less of battery cell strings, and measures the voltage and current of the battery cells. When the number of strings exceeds the number supported by the AFE chip, the AFE chips need to be stacked and cascaded. The communication between cascaded chips uses a dedicated daisy chain or discrete component circuits.
[0003] Automobiles use AFE (analog signal sampling front end) cascade solution daisy chain communication to make high-voltage battery packs, but daisy chain is generally a proprietary solution proposed by chip manufacturers, and the chips are limited and costly. For power devices, automotive battery packs use relays as power circuit control devices. The power device relays have high power consumption when continuously energized, which is not power friendly. There will be arcing when they are turned off. Long-term current-carrying shutdown will cause the relays to stick, and their ability to handle short-circuit faults is poor. Summary of the invention
[0004] The present invention provides a control system for a high-number-of-batteries BMS based on a low-voltage analog front end to solve the problems in the prior art.
[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is a control system for a high-number-of-batteries BMS based on a low-voltage analog front end, including a multi-level BMS module, wherein: Each level of the BMS module includes a battery pack and an AFE chip. The AFE chip is connected in parallel to both ends of the battery pack. The battery packs of two adjacent BMS modules are arranged in series, wherein the AFE chip located at the negative pole of the power supply is the lowest level AFE chip, and the AFE chip located at the positive pole of the power supply is the highest level AFE chip. The AFE chip includes: a CHG pin for controlling the charging MOS drive. A DSG pin for controlling the discharging MOS drive. A DFETOFF pin for controlling the discharging MOS shutdown. A CFETOFF pin for controlling the charging MOS shutdown.
[0006] The CHG pin of the AFE chip of the previous level is connected to the CFETOFF pin of the AFE chip of the next level, and the DSG pin of the AFE chip of the previous level is connected to the DFETOFF pin of the AFE chip of the next level. A DFET main power MOS and a CFET main power MOS are provided on the negative side of the power supply, the CHG pin of the lowest level AFE chip is connected to the gate of the CFET main power MOS, and the DSG pin is connected to the gate of the DFET main power MOS, so that when the protection of any level of the AFE chip is triggered, it will be transmitted to the lowest level AFE chip, and then the DFET main power MOS and the CFET main power MOS will be switched on and off.
[0007] Preferably, the control system further comprises a cascade MOS control circuit, the cascade MOS control circuit comprises a first transfer circuit, the first transfer circuit comprises a first transistor Q58, a first resistor R244, a second resistor R235, a third resistor R232, a second transistor Q55, a fourth resistor R242, a sixth resistor R249, and a first capacitor C119. The base of the first transistor Q58 is connected to one end of the sixth resistor R249, the emitter is grounded UP-GND, and the collector is connected in series with the first resistor R244, the second resistor R235, and the third resistor R232 in sequence. The node between the second resistor R235 and the third resistor R232 is connected to the register terminal UP-REGI. The base of the second transistor Q55 is connected to the node between the first resistor R244 and the second resistor R235, the emitter is connected to the other end of the third resistor R232, and the collector is connected in series with the fourth resistor R242 and the first capacitor C119 in sequence and grounded GND.
[0008] Preferably, the first transfer circuit further includes a first voltage stabilizing diode D44 and a fifth resistor R253, and the first voltage stabilizing diode D44 and the fifth resistor R253 are connected in parallel to both ends of the first capacitor C119. The other end of the seventh resistor R249 is a UP-DSG electrical network, which is used to connect to the DSG pin of the previous AFE chip, and the node between the fourth resistor R242 and the first capacitor C119 is a BOT-DFETOFF network, which is used to connect to the DFETOFF pin of the next AFE chip.
[0009] Preferably, the cascade MOS control circuit further includes a second transfer circuit, which includes a third transistor Q59, a seventh resistor R245, an eighth resistor R234, a ninth resistor R231, a fourth transistor Q54, a tenth resistor R246, a twelfth resistor R250 and a second capacitor C118. The base of the third transistor Q59 is connected to one end of the twelfth resistor R250, the emitter is connected to the ground UP-GND, and the collector is connected in series with the seventh resistor R245, the eighth resistor R234 and the ninth resistor R231 in sequence. The node between the eighth resistor R234 and the ninth resistor R231 is connected to the register terminal UP-REGI. The base of the fourth transistor Q54 is connected to the node between the seventh resistor R245 and the eighth resistor R234, the emitter is connected to the other end of the ninth resistor R231, and the collector is connected in series with the tenth resistor R246 and the second capacitor C118 in sequence and is grounded GND.
[0010] Preferably, the second transfer circuit includes a second voltage stabilizing diode D43 and an eleventh resistor R251, and the second voltage stabilizing diode D43 and the eleventh resistor R251 are connected in parallel to both ends of the first capacitor C119. The other end of the twelfth resistor R250 is a UP-CHG electrical network, which is used to connect the CHG pin of the previous AFE chip, and the node between the tenth resistor R246 and the second capacitor C118 is a BOT-CFETOFF network, which is used to connect the CFETOFF pin of the next AFE chip.
[0011] Preferably, the control system further comprises an MCU module, wherein the MCU module comprises an MCU and a plurality of isolation chips ISO-IIC. The plurality of isolation chips ISO-IIC are connected and arranged correspondingly to the multi-stage BMS module, so as to enable the AFE chip to communicate with the MCU.
[0012] Preferably, among the multiple AFE chips, the lowest-level AFE chip is directly connected to the MCU, which is a non-isolated direct-connection IIC communication mode. The other AFE chips communicate with the MCU through the isolation chip ISO-IIC.
[0013] Preferably, the control system also includes a current sampling circuit, and the lowest-level AFE chip also includes a current sampling positive pin SRP and a current sampling negative pin SRN, and the current sampling positive pin SRP and the current sampling negative pin SRN are respectively connected to the two ends of the current sampling circuit, for detecting and recording the current value, and transmitting the current value to the MCU.
[0014] Preferably, the current sampling circuit includes an RC filter and a current detection circuit. The current detection circuit includes a thirteenth resistor R595, a fourteenth resistor R596 and a fifteenth resistor R597 arranged in parallel. The RC filter circuit is arranged in parallel at both ends of the current detection circuit and is respectively connected to the current sampling positive pin SRP and the current sampling negative pin SRN.
[0015] Preferably, the AFE chip is a BQ769X2 chip from TI. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work, among which: Figure 1 This is a scheme overall architecture diagram of a control system of a high-number-of-batteries BMS based on a low-voltage analog front end provided by the present invention; Figure 2 It is a non-lowest level AFE chip isolation communication schematic diagram of a control system of a high-number-of-batteries BMS based on a low-voltage analog front end provided by the present invention; Figure 3 It is a cascade MOS control circuit diagram of a control system of a high-number-of-batteries BMS based on a low-voltage analog front end provided by the present invention; Figure 4 It is a lowest-level AFE chip current sampling diagram of a control system of a high-number-of-batteries BMS based on a low-voltage analog front end provided by the present invention; DETAILED DESCRIPTION The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0017] See also Figures 1 to 4 As shown, Figure 1 The overall architecture diagram of a control system for a high-number-of-batteries BMS based on a low-voltage analog front end provided by the present application is shown; Figure 2 A schematic diagram of non-lowest-level AFE chip isolation communication of a control system of a high-number-of-batteries BMS based on a low-voltage analog front end provided by the present application is shown; Figure 3A cascade MOS control circuit diagram of a control system of a high-number-of-batteries BMS based on a low-voltage analog front end provided by the present application is shown; Figure 4 The lowest-level AFE chip current sampling diagram of a control system of a high-string battery BMS based on a low-voltage analog front end provided by the present application is shown.
[0018] Combination Figure 1 and Figure 2 As shown, the technical solution provided by the present application is a control system for a high-number-of-batteries BMS based on a low-voltage analog front end, including a multi-level BMS module, wherein: Each level of BMS module includes a battery pack and an AFE chip. The AFE chip is connected in parallel to both ends of the battery pack. The battery packs of two adjacent BMS modules are arranged in series. Among them, the AFE chip located at the negative pole of the power supply is the lowest level AFE chip, and the AFE chip located at the positive pole of the power supply is the highest level AFE chip. The AFE chip includes: CHG pin, used to control the charging MOS drive. DSG pin, used to control the discharge MOS drive. DFETOFF pin, used to control the discharge MOS shutdown. CFETOFF pin, used to control the charging MOS shutdown.
[0019] The CHG pin of the previous AFE chip is connected to the CFETOFF pin of the next AFE chip, and the DSG pin of the previous AFE chip is connected to the DFETOFF pin of the next AFE chip. A DFET main power MOS and a CFET main power MOS are provided on the negative side of the power supply, and the CHG pin of the lowest AFE chip is connected to the gate of the CFET main power MOS, and the DSG pin is connected to the gate of the DFET main power MOS. When any AFE chip triggers the protection, it will be transmitted to the lowest AFE chip, and then the DFET main power MOS and the CFET main power MOS will be switched.
[0020] In the embodiments of the present application, for example, Figure 1 The leftmost part represents each battery string. Each battery string has a collection cable connected to the AFE chip (front-end sampling chip) on the right, which mainly collects the voltage of each battery and can also realize the passive voltage balancing function. Each BQ769X2 chip supports up to 16 battery strings for sampling. These AFE chips can be stacked for use, but the ground levels of each AFE chip will be different. When communicating with the AFE chip, an isolation chip is required, that is, the ISO-IIC isolation chip in the figure, which can realize the MCU to configure the AFE chip and pass the battery data collected by the AFE chip to the MCU.
[0021] The SRP and SRN pins of the lowest-level AFE chip sample the current of the shunt and measure the current of the power loop. In this embodiment, the AFE chips can be cascaded without relying on the MCU, and the AFE chips can control the MOS switch by themselves. As shown in the figure, through CHG, DSG, DFETOFF pins, and CFETOFF pins, there is a trigger protection in the middle that will be transmitted to the lowest level to realize the switch main power MOS.
[0022] The lowest level AFE chip communication is non-isolated direct IIC, and other AFE chips and MCU communication is isolated IIC, as shown in the figure below. The MCU acts as the master and the AFE chip acts as the slave. The MCU can configure the AFE chip and transmit the voltage of each battery to the MCU. U9 is an IIC isolation device. The left side is the connection end of the IIC slave device AFE chip, and the right side is the connection end of the IIC master device and MCU. Resistors R170 and R171 are pull-up resistors, and the power supply is the 3.3V power supply corresponding to the AFE chip.
[0023] In some embodiments, the AFE chip is a BQ769X2 chip from TI.
[0024] Combination Figure 3 As shown, in some embodiments, the control system further includes a cascade MOS control circuit, the cascade MOS control circuit includes a first transfer circuit, the first transfer circuit includes a first transistor Q58, a first resistor R244, a second resistor R235, a third resistor R232, a second transistor Q55, a fourth resistor R242, a sixth resistor R249, and a first capacitor C119. The base of the first transistor Q58 is connected to one end of the sixth resistor R249, the emitter is grounded UP-GND, and the collector is connected in series with the first resistor R244, the second resistor R235, and the third resistor R232 in sequence. The node between the second resistor R235 and the third resistor R232 is connected to the register terminal UP-REGI. The base of the second transistor Q55 is connected to the node between the first resistor R244 and the second resistor R235, the emitter is connected to the other end of the third resistor R232, and the collector is connected in series with the fourth resistor R242 and the first capacitor C119 in sequence and grounded GND.
[0025] The first transfer circuit also includes a first voltage stabilizing diode D44 and a fifth resistor R253, and the first voltage stabilizing diode D44 and the fifth resistor R253 are connected in parallel to both ends of the first capacitor C119. The other end of the seventh resistor R249 is a UP-DSG electrical network, which is used to connect to the DSG pin of the previous AFE chip, and the node between the fourth resistor R242 and the first capacitor C119 is a BOT-DFETOFF network, which is used to connect to the DFETOFF pin of the next AFE chip.
[0026] Combination Figure 3 As shown, in some embodiments, the cascade MOS control circuit further includes a second transfer circuit, which includes a third transistor Q59, a seventh resistor R245, an eighth resistor R234, a ninth resistor R231, a fourth transistor Q54, a tenth resistor R246, a twelfth resistor R250 and a second capacitor C118. The base of the third transistor Q59 is connected to one end of the twelfth resistor R250, the emitter is connected to the ground UP-GND, and the collector is connected in series with the seventh resistor R245, the eighth resistor R234 and the ninth resistor R231 in sequence. The node between the eighth resistor R234 and the ninth resistor R231 is connected to the register terminal UP-REGI. The base of the fourth transistor Q54 is connected to the node between the seventh resistor R245 and the eighth resistor R234, the emitter is connected to the other end of the ninth resistor R231, and the collector is connected in series with the tenth resistor R246 and the second capacitor C118 in sequence and is grounded GND.
[0027] The second transfer circuit includes a second voltage stabilizing diode D43 and an eleventh resistor R251, and the second voltage stabilizing diode D43 and the eleventh resistor R251 are connected in parallel to both ends of the first capacitor C119. The other end of the twelfth resistor R250 is a UP-CHG electrical network for connecting to the CHG pin of the previous AFE chip, and the node between the tenth resistor R246 and the second capacitor C118 is a BOT-CFETOFF network for connecting to the CFETOFF pin of the next AFE chip.
[0028] In the embodiment of the present application, illustratively, the DSG of the upper-level AFE chip is passed to the lower-level DFETOFF (dischargeFETOFF, discharge MOS is turned off). The CHG of the upper level is passed to CFETOFF, and the power MOS is controlled by the logic level conversion circuit to control the main power circuit to be turned on or off. When each level of the AFE chip samples that the battery cell has a minor fault and needs to turn off the MOS, DSG / CHG will change from a high level to a low level (high level is valid). At the same time, it is output to the next level DFETOFF / CFETOFF, so that it can be passed to the DSG / CHG pin of this level. The above is the power device control loop of the main loop.
[0029] In the first transfer circuit, the UP-DSG electrical network is connected to the DSG pin of the higher-level AFE chip. When the level is high, the MOS is turned on, that is, the high level is valid. The resistor and power device in the middle serve as a level transfer circuit. Because the upper and lower AFE chips are not at the same ground level, there is a voltage difference between the two grounds, so a level transfer circuit is required. C119 is a signal filtering capacitor. One end of the BOT-DFETOFF network is connected to the level transfer circuit, and the other end is connected to the lower-level DFETOFF.
[0030] In the second transfer circuit, one end of the UP-CHG electrical network is connected to the CHG pin of the previous level, that is, the output control circuit; R250 is a current limiting resistor, and the middle resistor and power device serve as a level transfer circuit because there is a level difference between the upper and lower level AFE chips; the BOT-CFETOFF electrical network is the CFETOFF pin of the next level AFE chip, that is, the input circuit of the next level.
[0031] Combination Figure 4 As shown, in some implementation schemes, the lowest-level AFE chip turns on the current sampling function, SRP, SRN. The BQ769X2 series integrates an operational amplifier for collecting current and a short-circuit protection function. The lowest-level AFE chip also includes a current sampling positive pin SRP and a current sampling negative pin SRN. The current sampling positive pin SRP and the current sampling negative pin SRN are respectively connected to the two ends of the current sampling circuit to detect and record the current value and pass the current value to the MCU.
[0032] The current sampling part is composed of an RC filtering part and a current detection part. The current detection part is composed of three resistors, the thirteenth resistor R595, the fourteenth resistor R596 and the fifteenth resistor R597, connected in parallel, that is, the left side of the current detection resistor is connected to B-, and the right side is connected to the main circuit control MOS. Then, an RC filtering circuit is connected to both ends of the current detection resistor, that is, a circuit composed of resistor R392, resistor R393, capacitor C231, capacitor C232, capacitor C229, and capacitor C224, and then connected to the SRP and SRN pins of the AFE chip after filtering, that is, the SRP and SRN networks in the figure.
[0033] Furthermore, in the software configuration part of the present invention, in order to save MCU-IIC resources, the IIC of the upper and lower AFE chips are connected together, both act as slaves, and the MCU acts as the host. However, the chips have the same default IIC address, and the BQ769X2 chip OTP function will be used to configure different IIC addresses.
[0034] Furthermore, since this solution does not burn data into OTP, the initial power-on configuration process is as follows: S1: MCU first resets the register of the AFE chip; S2: MCU initializes the registers of the AFE chip, that is, configures the registers; S3: The AFE chip collects data normally, that is, starts normal work.
[0035] In addition, this solution architecture provides multiple ways to control the FET register, that is, to switch C-MOS (charging MOSFET), D-MOS (discharging MOSFET), with fully autonomous mode, partially autonomous mode and manual control mode, as described below: 1) In fully autonomous mode, the BQ769X2 devices can detect faults and automatically shut down the MOSFET, monitor recovery conditions and automatically re-enable the MOSFET without MCU involvement.
[0036] 2) In partial autonomous mode, the BQ769X2 device can detect a protection fault and automatically turn off the MOSFET. When the host receives an interrupt and identifies a fault, the host can write a command to keep the MOSFET off until the host decides to release it. Subcommands can also be used to enable or disable each MOSFET individually.
[0037] In manual control mode, the BQ769X2 device can detect protection faults and provide an interrupt to the host processor through the ALERT pin. The host processor can read the status information of the fault through the communication bus (if necessary) and can quickly force the MOSFET of CHG or DSG to turn off by driving the CFETOFF or DFETOFF pin of the host processor or using a subcommand.
[0038] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly used in other related technical fields, should be included in the protection scope of the present invention.
Claims
1. A control system for a high-number-of-batteries BMS based on a low-voltage analog front end, characterized in that: It includes multi-level BMS modules, including: Each level of the BMS module includes a battery pack and an AFE chip, the AFE chip is connected in parallel to both ends of the battery pack, and the battery packs of two adjacent BMS modules are arranged in series, wherein the AFE chip located at the negative pole of the power supply is the lowest level AFE chip, and the AFE chip located at the positive pole of the power supply is the highest level AFE chip; the AFE chip includes: a CHG pin for controlling the charging MOS drive; a DSG pin for controlling the discharging MOS drive; a DFETOFF pin for controlling the discharging MOS shutdown; and a CFETOFF pin for controlling the charging MOS shutdown; The CHG pin of the AFE chip at the previous level is connected to the CFETOFF pin of the AFE chip at the next level, and the DSG pin of the AFE chip at the previous level is connected to the DFETOFF pin of the AFE chip at the next level; a DFET main power MOS and a CFET main power MOS are provided on the negative pole side of the power supply, the CHG pin of the lowest level AFE chip is connected to the gate of the CFET main power MOS, and the DSG pin is connected to the gate of the DFET main power MOS, so that when the protection of the AFE chip at any level is triggered, it will be transmitted to the lowest level AFE chip, thereby realizing the switching of the DFET main power MOS and the CFET main power MOS.
2. The control system according to claim 1, characterized in that: It also includes a cascade MOS control circuit, which includes a first transfer circuit, which includes a first transistor Q58, a first resistor R244, a second resistor R235, a third resistor R232, a second transistor Q55, a fourth resistor R242, a sixth resistor R249, and a first capacitor C119; the base of the first transistor Q58 is connected to one end of the sixth resistor R249, the emitter is grounded UP-GND, and the collector is connected in series with the first resistor R244, the second resistor R235 and the third resistor R232 in sequence; the node between the second resistor R235 and the third resistor R232 is connected to the register end UP-REGI; the base of the second transistor Q55 is connected to the node between the first resistor R244 and the second resistor R235, the emitter is connected to the other end of the third resistor R232, and the collector is connected in series with the fourth resistor R242 and the first capacitor C119 in sequence and grounded GND.
3. The control system according to claim 2, characterized in that: The first transfer circuit also includes a first voltage zener diode D44 and a fifth resistor R253, and the first voltage zener diode D44 and the fifth resistor R253 are connected in parallel to the two ends of the first capacitor C119; the other end of the seventh resistor R249 is a UP-DSG electrical network, which is used to connect the DSG pin of the previous level AFE chip, and the node between the fourth resistor R242 and the first capacitor C119 is a BOT-DFETOFF network, which is used to connect the DFETOFF pin of the next level AFE chip.
4. The control system according to claim 1, characterized in that: The cascade MOS control circuit also includes a second transfer circuit, which includes a third transistor Q59, a seventh resistor R245, an eighth resistor R234, a ninth resistor R231, a fourth transistor Q54, a tenth resistor R246, a twelfth resistor R250 and a second capacitor C118; the base of the third transistor Q59 is connected to one end of the twelfth resistor R250, the emitter is grounded UP-GND, and the collector is connected in series with the seventh resistor R245, the eighth resistor R234 and the ninth resistor R231 in sequence; the node between the eighth resistor R234 and the ninth resistor R231 is connected to the register end UP-REGI; the base of the fourth transistor Q54 is connected to the node between the seventh resistor R245 and the eighth resistor R234, the emitter is connected to the other end of the ninth resistor R231, and the collector is connected in series with the tenth resistor R246 and the second capacitor C118 in sequence and grounded GND.
5. The control system according to claim 4, characterized in that: The second transfer circuit includes a second voltage zener diode D43 and an eleventh resistor R251, and the second voltage zener diode D43 and the eleventh resistor R251 are connected in parallel to the two ends of the first capacitor C119; the other end of the twelfth resistor R250 is a UP-CHG electrical network, which is used to connect the CHG pin of the previous level AFE chip, and the node between the tenth resistor R246 and the second capacitor C118 is a BOT-CFETOFF network, which is used to connect the CFETOFF pin of the next level AFE chip.
6. The control system according to claim 1, characterized in that: It also includes an MCU module, which includes an MCU and multiple isolation chips ISO-IIC; the multiple isolation chips ISO-IIC are connected and arranged correspondingly to the multi-level BMS module, so as to enable the AFE chip to communicate with the MCU.
7. The control system according to claim 1, characterized in that: Among the multiple AFE chips, the lowest-level AFE chip is directly connected to the MCU, which is a non-isolated direct-connection IIC communication mode; the other AFE chips communicate with the MCU through the isolation chip ISO-IIC.
8. The control system according to claim 1, characterized in that: It also includes a current sampling circuit. The lowest-level AFE chip also includes a current sampling positive pin SRP and a current sampling negative pin SRN. The current sampling positive pin SRP and the current sampling negative pin SRN are respectively connected to the two ends of the current sampling circuit for detecting and recording current values and transmitting the current values to the MCU.
9. The control system according to claim 1, characterized in that: The current sampling circuit includes an RC filter circuit and a current detection circuit; the current detection circuit includes a thirteenth resistor R595, a fourteenth resistor R596 and a fifteenth resistor R597 arranged in parallel; the RC filter circuit is arranged in parallel at both ends of the current detection circuit and is respectively connected to the current sampling positive pin SRP and the current sampling negative pin SRN.
10. The control system according to claim 1, characterized in that: The AFE chip is the BQ769X2 chip of TI.