Charge pump circuit based on closed-loop feedback control

Abstract

The invention discloses a charge pump circuit based on closed-loop feedback control, and relates to the technical field of analog integrated circuit power management. Comprising a two-phase non-overlapping clock generation circuit, a control signal generation circuit and a charge pump main body circuit. The charge pump main body circuit comprises a cross coupling circuit, a feedback circuit and an operational amplifier circuit. And the output voltage of the cross coupling circuit is output through an output port VCP, and the voltage at the output port VCP is fed back to the control signal generation circuit through an operational amplifier output port VPVB after being sequentially processed by the feedback circuit and the operational amplifier circuit, so that feedback control of the charge pump main body circuit is realized, and a high-voltage voltage source is obtained. The high-voltage source is high in voltage precision, and the absolute value of the voltage of the high-voltage source does not change along with the error of an integrated circuit manufacturing process and the change of temperature.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuit power management, and in particular to a charge pump circuit based on closed-loop feedback control. Background Art

[0002] The integrated circuit industry is the core of the information technology industry. It is a strategic, basic and leading industry that supports economic and social development and ensures national security. With the rapid development of electronic technology, inertial sensors are widely used in navigation, vibration measurement, attitude monitoring and other fields. In practical applications, due to various external interferences (such as temperature changes, humidity changes, electromagnetic interference, etc.) and internal factors (such as component aging, manufacturing errors, etc.), the output of inertial sensors may deviate or fluctuate.

[0003] In the prior art, inertial sensors often use traditional charge pump circuits, such as Dickson charge pumps, to generate high-voltage voltage sources. In order to accurately feedback control the inertial sensor, a high-precision, low-temperature drift high-voltage source is required, and the high-precision, low-temperature drift high-voltage source is electrically connected to the inertial sensor. Finally, the high-precision, low-temperature drift high-voltage source is monitored and adjusted in real time during the power supply process to ensure that the power supply voltage and current are always kept within the specified range.

[0004] The defects of the above-mentioned prior art are: the traditional charge pump circuit will generate a high-voltage source voltage, and the absolute value of the high-voltage source voltage will change with the error of the integrated circuit manufacturing process and the change of temperature. Summary of the invention

[0005] Based on this, it is necessary to provide a charge pump circuit based on closed-loop feedback control to address the above technical issues.

[0006] The embodiment of the present invention provides a charge pump circuit based on closed-loop feedback control, comprising: a two-phase non-overlapping clock generating circuit, a control signal generating circuit and a charge pump main circuit;

[0007] The charge pump main circuit includes: a cross-coupling circuit, a feedback circuit and an operational amplifier circuit;

[0008] The input end of the cross-coupling circuit is connected to the power supply VDD, the output end of the cross-coupling circuit is connected to the output port VCP and the input end of the feedback circuit, and the output end of the feedback circuit is connected to the operational amplifier circuit;

[0009] The feedback circuit includes a first adjustable resistor R1 and a second adjustable resistor R2; one end of the first adjustable resistor R1 is connected to the output end of the cross-coupling circuit, and the other end of the first adjustable resistor R1 is connected to one end of the second adjustable resistor R2 and the operational amplifier circuit; the other end of the second adjustable resistor R2 is grounded;

[0010] The operational amplifier circuit includes a first operational amplifier OP1 and a second operational amplifier OP2; the non-inverting input terminal IN+ of the first operational amplifier OP1 is connected to the feedback circuit, the inverting input terminal IN- of the first operational amplifier OP1 is connected to the reference source port VREF, the output terminal OUT of the first operational amplifier OP1 is connected to the non-inverting input terminal IN+ of the second operational amplifier OP2; the inverting input terminal IN- and the output terminal OUT of the second operational amplifier OP2 are connected to the operational amplifier output port VPVB, and the operational amplifier output port VPVB is connected to the control signal generating circuit;

[0011] The output voltage of the cross-coupling circuit is output through the output port VCP. The voltage at the output port VCP is processed by the feedback circuit and the operational amplifier circuit in sequence and then fed back to the control signal generating circuit through the operational amplifier output port VPVB to realize feedback control of the charge pump main circuit and obtain a high voltage source.

[0012] Optionally, the input end of the two-phase non-overlapping clock generating circuit is connected to the input port CLKIN, and the two-phase non-overlapping clock generating circuit is connected to the input end of the control signal generating circuit through the first output port CLK1, the first inverting output port CLK1N, the second output port CLK2 and the second inverting output port CLK2N;

[0013] The control signal generating circuit is connected to the input end of the charge pump main circuit through the first output port CKOUT1, the first inverting output port CKNOUT1, the second output port CKOUT2 and the second inverting output port CKNOUT2;

[0014] The two-phase non-overlapping clock generating circuit, the control signal generating circuit and the charge pump main circuit are all connected to the power supply VDD and the ground.

[0015] Optionally, the cross-coupling circuit includes: an A1 module, an A2 module and an A3 module; the input end of the A1 module is connected to the power supply VDD, the output end of the A1 module is connected to the input end of the A2 module, the output end of the A2 module is connected to the input end of the A3 module, and the output end of the A3 module is connected to the output port VCP.

[0016] Optionally, the A1 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4;

[0017] The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, and the C1The other end of the capacitor C is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2, the D end of the third N-type MOS transistor NM3 and the power supply VDD; the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A1 module.

[0018] Optionally, the A2 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4;

[0019] The first capacitor C C1 One end of the first capacitor C is connected to the first output port CKOUT1 of the control signal generating circuit, and the first capacitor C C1 The other end of the A1 module is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A1 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the first inverting output port CKNOUT1 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A2 module.

[0020] Optionally, the A3 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4;

[0021] The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, and the C1The other end of the A2 module is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the second N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A2 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT2 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 are connected to the output port VCP as the output end of the A3 module.

[0022] Optionally, the control signal generating circuit includes: a seventh P-type MOS transistor PM7, an eighth P-type MOS transistor PM8, a ninth P-type MOS transistor PM9, a fifth N-type MOS transistor NM5, a sixth N-type MOS transistor NM6, a tenth P-type MOS transistor PM10, an eleventh P-type MOS transistor PM11, a twelfth P-type MOS transistor PM12, a seventh N-type MOS transistor NM7 and an eighth N-type MOS transistor NM8;

[0023] The S end of the seventh P-type MOS transistor PM7 is connected to the power supply VDD, the G end of the seventh P-type MOS transistor PM7 is connected to the operational amplifier output port VPVB, the D end of the seventh P-type MOS transistor PM7 is connected to the S end of the eighth P-type MOS transistor PM8 and the S end of the ninth P-type MOS transistor PM9; the G end of the eighth P-type MOS transistor PM8 is connected to the first output port CLK1 of the two-phase non-overlapping clock generating circuit, the D end of the eighth P-type MOS transistor PM8 and the D end of the fifth N-type MOS transistor NM5 are connected to the second output port CKOUT2 of the control signal generating circuit, and the G end of the fifth N-type MOS transistor NM5 is connected to the second output port CKOUT2 of the control signal generating circuit. The first terminal of the control signal generating circuit is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, and the S terminal of the fifth N-type MOS transistor NM5 is grounded; the G terminal of the ninth P-type MOS transistor PM9 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, and the D terminal of the ninth P-type MOS transistor PM9 and the D terminal of the sixth N-type MOS transistor NM6 are connected to the second inverting output port CKNOUT2 of the control signal generating circuit; the G terminal of the sixth N-type MOS transistor NM6 is connected to the first output port CLK1 of the two-phase non-overlapping clock generating circuit, and the S terminal of the sixth N-type MOS transistor NM6 is grounded;

[0024] The S terminal of the tenth P-type MOS transistor PM10 is connected to VDD, the G terminal of the tenth P-type MOS transistor PM10 is connected to the operational amplifier output port VPVB, the D terminal of the tenth P-type MOS transistor PM10 is connected to the S terminal of the eleventh P-type MOS transistor PM11 and the S terminal of the twelfth P-type MOS transistor PM12; the G terminal of the eleventh P-type MOS transistor PM11 is connected to the second output port CLK2 of the two-phase non-overlapping clock generating circuit, the D terminal of the eleventh P-type MOS transistor PM11 and the D terminal of the seventh N-type MOS transistor NM7 are connected to the first output port CKOUT1 of the control signal generating circuit; the seventh N-type MOS transistor NM7 is connected to the first output port CKOUT1 of the control signal generating circuit. The G terminal of M7 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generating circuit, the S terminal of the seventh N-type MOS transistor NM7 is grounded, and the G terminal of the twelfth P-type MOS transistor PM12 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generating circuit; the D terminal of the twelfth P-type MOS transistor PM12 and the D terminal of the eighth N-type MOS transistor NM8 are connected to the first output port CKNOUT1 of the control signal generating circuit, the G terminal of the eighth N-type MOS transistor NM8 is connected to the second output port CLK2 of the two-phase non-overlapping clock generating circuit, and the S terminal of the eighth N-type MOS transistor NM8 is grounded.

[0025] Compared with the prior art, the above-mentioned charge pump circuit based on closed-loop feedback control provided by the embodiment of the present invention has the following beneficial effects:

[0026] The output voltage of the cross-coupling circuit of the present invention is output through the output port VCP. The voltage at the output port VCP is processed by the feedback circuit and the operational amplifier circuit in sequence and then fed back to the control signal generating circuit through the operational amplifier output port VPVB to realize feedback control of the charge pump main circuit and obtain a high voltage source.

[0027] In the above process, the output voltage of the cross-coupling circuit is determined by the resistance values ​​of the first adjustable resistor R1 and the second adjustable resistor R2, and the voltage value at the output port VCP can be adjusted by changing the resistance values ​​of the first adjustable resistor R1 and the second adjustable resistor R2, and is insensitive to power supply voltage fluctuations and process temperature fluctuations of other devices. Therefore, the high-voltage source voltage of the present invention has high accuracy, and the absolute value of the high-voltage source voltage will not change with the error of the integrated circuit manufacturing process and the change of temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A circuit diagram of a charge pump circuit based on closed-loop feedback control provided in one embodiment;

[0029] Figure 2 A schematic diagram of a control signal generating circuit of a charge pump circuit based on closed-loop feedback control provided in one embodiment;

[0030] Figure 3A schematic diagram of a charge pump main circuit of a charge pump circuit based on closed-loop feedback control provided in an embodiment. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0032] In one embodiment, a charge pump circuit based on closed-loop feedback control is provided, such as Figure 1 As shown, it includes: a two-phase non-overlapping clock generating circuit, a control signal generating circuit and a charge pump main circuit.

[0033] Among them, the input end of the two-phase non-overlapping clock generating circuit is connected to the input port CLKIN, and the two-phase non-overlapping clock generating circuit is connected to the input end of the control signal generating circuit through the first output port CLK1, the first inverting output port CLK1N, the second output port CLK2 and the second inverting output port CLK2N.

[0034] The control signal generating circuit is connected to the input end of the charge pump main circuit through the first output port CKOUT1, the first inverting output port CKNOUT1, the second output port CKOUT2 and the second inverting output port CKNOUT2.

[0035] In addition, the two-phase non-overlapping clock generating circuit, the control signal generating circuit and the charge pump main circuit are all connected to the power supply VDD and the ground (GND).

[0036] 1. Control signal generating circuit

[0037] like Figure 2 As shown, the control signal generating circuit includes: a seventh P-type MOS transistor PM7, an eighth P-type MOS transistor PM8, a ninth P-type MOS transistor PM9, a fifth N-type MOS transistor NM5, a sixth N-type MOS transistor NM6, a tenth P-type MOS transistor PM10, an eleventh P-type MOS transistor PM11, a twelfth P-type MOS transistor PM12, a seventh N-type MOS transistor NM7 and an eighth N-type MOS transistor NM8;

[0038] Among them, the S end of the seventh P-type MOS transistor PM7 is connected to the power supply VDD, the G end of the seventh P-type MOS transistor PM7 is connected to the operational amplifier output port VPVB, the D end of the seventh P-type MOS transistor PM7 is connected to the S end of the eighth P-type MOS transistor PM8 and the S end of the ninth P-type MOS transistor PM9; the G end of the eighth P-type MOS transistor PM8 is connected to the first output port CLK1 of the two-phase non-overlapping clock generating circuit, the D end of the eighth P-type MOS transistor PM8 and the D end of the fifth N-type MOS transistor NM5 are connected to the second output port CKOUT2 of the control signal generating circuit, and the fifth N-type MOS transistor NM5 is connected to the second output port CKOUT2 of the control signal generating circuit. The G terminal of the ninth P-type MOS transistor PM9 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, and the S terminal of the fifth N-type MOS transistor NM5 is grounded; the G terminal of the ninth P-type MOS transistor PM9 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, and the D terminal of the ninth P-type MOS transistor PM9 and the D terminal of the sixth N-type MOS transistor NM6 are connected to the second inverting output port CKNOUT2 of the control signal generating circuit; the G terminal of the sixth N-type MOS transistor NM6 is connected to the first output port CLK1 of the two-phase non-overlapping clock generating circuit, and the S terminal of the sixth N-type MOS transistor NM6 is grounded.

[0039] The S terminal of the tenth P-type MOS transistor PM10 is connected to VDD, the G terminal of the tenth P-type MOS transistor PM10 is connected to the operational amplifier output port VPVB, the D terminal of the tenth P-type MOS transistor PM10 is connected to the S terminal of the eleventh P-type MOS transistor PM11 and the S terminal of the twelfth P-type MOS transistor PM12; the G terminal of the eleventh P-type MOS transistor PM11 is connected to the second output port CLK2 of the two-phase non-overlapping clock generating circuit, the D terminal of the eleventh P-type MOS transistor PM11 and the D terminal of the seventh N-type MOS transistor NM7 are connected to the first output port CKOUT1 of the control signal generating circuit; the seventh N-type MOS transistor NM7 is connected to the first output port CKOUT1 of the control signal generating circuit. The G terminal of M7 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generating circuit, the S terminal of the seventh N-type MOS transistor NM7 is grounded, and the G terminal of the twelfth P-type MOS transistor PM12 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generating circuit; the D terminal of the twelfth P-type MOS transistor PM12 and the D terminal of the eighth N-type MOS transistor NM8 are connected to the first output port CKNOUT1 of the control signal generating circuit, the G terminal of the eighth N-type MOS transistor NM8 is connected to the second output port CLK2 of the two-phase non-overlapping clock generating circuit, and the S terminal of the eighth N-type MOS transistor NM8 is grounded.

[0040] 2. Charge pump main circuit

[0041] like Figure 3 As shown, the charge pump main circuit includes a cross-coupling circuit, a feedback circuit and an operational amplifier circuit.

[0042] 2.1 Cross-coupled circuit

[0043] The cross-coupling circuit includes: A1 module, A2 module and A3 module. The input end of A1 module is connected to the power supply VDD, the output end of A1 module is connected to the input end of A2 module, the output end of A2 module is connected to the input end of A3 module, and the output end of A3 module is connected to the output port VCP.

[0044] 2.1.1A1 Module

[0045] The A1 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4;

[0046] The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, and the C1 The other end is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4. The D end of the second N-type MOS transistor NM2, the D end of the third N-type MOS transistor NM3 and the power supply VDD are connected. The G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A1 module.

[0047] 2.1.2A2 Module

[0048] The A2 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4;

[0049] The first capacitor C C1 One end of the first capacitor C is connected to the first output port CKOUT1 of the control signal generating circuit, and the first capacitor C C1The other end of the A1 module is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A1 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the first inverting output port CKNOUT1 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A2 module.

[0050] 2.1.3A3 module

[0051] The A3 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4;

[0052] The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, and the C1 The other end of the A2 module is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the second N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A2 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT2 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 are connected to the output port VCP as the output end of the A3 module.

[0053] 2.2 Feedback Circuit

[0054] The feedback circuit includes a first adjustable resistor R1 and a second adjustable resistor R2. One end of the first adjustable resistor R1 is connected to the output end of the cross-coupling circuit, the other end of the first adjustable resistor R1 is connected to one end of the second adjustable resistor R2 and the operational amplifier circuit, and the other end of the second adjustable resistor R2 is grounded.

[0055] 2.3 Op amp circuit

[0056] The operational amplifier circuit includes a first operational amplifier OP1 and a second operational amplifier OP2. The non-inverting input terminal IN+ of the first operational amplifier OP1 is connected to the feedback circuit, the inverting input terminal IN- of the first operational amplifier OP1 is connected to the reference source port VREF, and the output terminal OUT of the first operational amplifier OP1 is connected to the non-inverting input terminal IN+ of the second operational amplifier OP2. The inverting input terminal IN- and the output terminal OUT of the second operational amplifier OP2 are connected to the operational amplifier output port VPVB, and the operational amplifier output port VPVB is connected to the control signal generating circuit.

[0057] 3. Working Principle

[0058] The specific structure of the operational amplifier circuit can be selected according to the accuracy requirements of VCP, and the voltage at the reference source port VREF is generated by a low temperature drift reference source. The circuit can generate a high-precision high-voltage voltage source whose absolute value is independent of power supply and process.

[0059] The basic principles of the above technical solution are as follows:

[0060] (1) The overall circuit is divided into three modules. The first module is the charge pump main circuit, which functions to alternately charge the charge storage capacitor CC and output VCP under the control of the control signal, and detect the circuit output voltage to generate VPVB; the second module is the control signal generating circuit, which functions to adjust the amplitude of the charge pump control signal under the control of VPVB and the two-phase non-overlapping clock, and output it to the charge pump main circuit; the third module is the two-phase non-overlapping clock generating module, which functions to generate a two-phase non-overlapping clock and output it to the charge pump control signal generating module.

[0061] (2) The overall circuit is a closed-loop structure. The output voltage of the cross-coupling circuit is output through the output port VCP, and the voltage at the output port VCP is determined by the feedback coefficient formed by the first adjustable resistor R1 and the second adjustable resistor R2. Among them, V CP is the voltage value at the output port VCP, V REF is the voltage value at the reference source port VREF, R1 is the resistance value of the first adjustable resistor R1, and R2 is the resistance value of the second adjustable resistor R2. The voltage value at the output port VCP can be adjusted by changing the resistance values ​​of the first adjustable resistor R1 and the second adjustable resistor R2.

[0062] (3) The first adjustable resistor R1 and the second adjustable resistor R2 as well as the first operational amplifier OP1 and the second operational amplifier OP2 are adjusted according to the voltage of the output port VCP to achieve dynamic adjustment of the voltage at the output port VPVB of the operational amplifier, and at the same time adjust the charge stored on CC in each clock cycle.

[0063] (4) The main circuit of the charge pump adopts a cross-coupling circuit, which can effectively reduce the ripple size and improve efficiency. It should be noted that in order to eliminate the body effect and reduce the leakage current, the substrate of the NMOS tube and the PMOS tube need to be connected to the source end, so the performance is better when using the BCD process.

[0064] (5) The op amp structure, clock frequency and CC capacitor size in this patent can be designed based on the voltage accuracy of the output port VCP, load current size and other requirements.

[0065] The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A charge pump circuit based on closed-loop feedback control, characterized in that: include: A two-phase non-overlapping clock generating circuit, a control signal generating circuit and a charge pump main circuit; The charge pump main circuit comprises: a cross-coupling circuit, a feedback circuit and an operational amplifier circuit; The input end of the cross-coupling circuit is connected to the power supply VDD, the output end of the cross-coupling circuit is connected to the output port VCP and the input end of the feedback circuit, and the output end of the feedback circuit is connected to the operational amplifier circuit; The feedback circuit includes a first adjustable resistor R1 and a second adjustable resistor R2; one end of the first adjustable resistor R1 is connected to the output end of the cross-coupling circuit, and the other end of the first adjustable resistor R1 is connected to one end of the second adjustable resistor R2 and the operational amplifier circuit; the other end of the second adjustable resistor R2 is grounded; The operational amplifier circuit comprises a first operational amplifier OP1 and a second operational amplifier OP2; the non-inverting input terminal IN+ of the first operational amplifier OP1 is connected to the feedback circuit, the inverting input terminal IN- of the first operational amplifier OP1 is connected to the reference source port VREF, the output terminal OUT of the first operational amplifier OP1 is connected to the non-inverting input terminal IN+ of the second operational amplifier OP2; the inverting input terminal IN- and the output terminal OUT of the second operational amplifier OP2 are connected to the operational amplifier output port VPVB, and the operational amplifier output port VPVB is connected to the control signal generating circuit; The output voltage of the cross-coupling circuit is output through the output port VCP. The voltage at the output port VCP is processed by the feedback circuit and the operational amplifier circuit in sequence and then fed back to the control signal generating circuit through the operational amplifier output port VPVB to realize feedback control of the charge pump main circuit and obtain a high voltage source.

2. A charge pump circuit based on closed-loop feedback control as claimed in claim 1, characterized in that: The input end of the two-phase non-overlapping clock generating circuit is connected to the input port CLKIN, and the two-phase non-overlapping clock generating circuit is connected to the input end of the control signal generating circuit through the first output port CLK1, the first inverting output port CLK1N, the second output port CLK2 and the second inverting output port CLK2N; The control signal generating circuit is connected to the input end of the charge pump main circuit through the first output port CKOUT1, the first inverting output port CKNOUT1, the second output port CKOUT2 and the second inverting output port CKNOUT2; The two-phase non-overlapping clock generating circuit, the control signal generating circuit and the charge pump main circuit are all connected to a power source VDD and ground.

3. A charge pump circuit based on closed-loop feedback control as claimed in claim 2, characterized in that: The cross-coupling circuit includes: an A1 module, an A2 module and an A3 module; the input end of the A1 module is connected to the power supply VDD, the output end of the A1 module is connected to the input end of the A2 module, the output end of the A2 module is connected to the input end of the A3 module, and the output end of the A3 module is connected to the output port VCP.

4. A charge pump circuit based on closed-loop feedback control as claimed in claim 3, characterized in that: The A1 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, and the first capacitor C C1 The other end of the second N-type MOS tube NM2 is connected to the S end of the second N-type MOS tube NM2, the S end of the third P-type MOS tube PM3, the G end of the third N-type MOS tube NM3 and the G end of the fourth P-type MOS tube PM4; the D end of the second N-type MOS tube NM2, the D end of the third N-type MOS tube NM3 and the power supply VDD are connected; the G end of the second N-type MOS tube NM2, the S end of the third N-type MOS tube NM3, the S end of the fourth P-type MOS tube PM4 and the G end of the third P-type MOS tube PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A1 module.

5. A charge pump circuit based on closed-loop feedback control as claimed in claim 3, characterized in that: The A2 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to control the first output port CKOUT1 of the signal generating circuit, and the first capacitor C C1 The other end of the second N-type MOS transistor NM2 is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A1 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the first inverting output port CKNOUT1 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A2 module.

6. A charge pump circuit based on closed-loop feedback control as claimed in claim 3, characterized in that: The A3 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, and the first capacitor C C1 The other end of the A2 module is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the second N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A2 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT2 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 are connected to the output port VCP as the output end of the A3 module.

7. A charge pump circuit based on closed-loop feedback control as claimed in claim 1, characterized in that: The control signal generating circuit comprises: a seventh P-type MOS transistor PM7, an eighth P-type MOS transistor PM8, a ninth P-type MOS transistor PM9, a fifth N-type MOS transistor NM5, a sixth N-type MOS transistor NM6, a tenth P-type MOS transistor PM10, an eleventh P-type MOS transistor PM11, a twelfth P-type MOS transistor PM12, a seventh N-type MOS transistor NM7 and an eighth N-type MOS transistor NM8; The S end of the seventh P-type MOS transistor PM7 is connected to the power supply VDD, the G end of the seventh P-type MOS transistor PM7 is connected to the operational amplifier output port VPVB, and the D end of the seventh P-type MOS transistor PM7 is connected to the S end of the eighth P-type MOS transistor PM8 and the S end of the ninth P-type MOS transistor PM9; the G end of the eighth P-type MOS transistor PM8 is connected to the first output port CLK1 of the two-phase non-overlapping clock generating circuit, the D end of the eighth P-type MOS transistor PM8 and the D end of the fifth N-type MOS transistor NM5 are connected to the second output port CKOUT2 of the control signal generating circuit, and the fifth N-type MOS transistor NM5 is connected to the first output port CLK1 of the two-phase non-overlapping clock generating circuit. The G end of the ninth P-type MOS transistor PM9 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, and the S end of the fifth N-type MOS transistor NM5 is grounded; the G end of the ninth P-type MOS transistor PM9 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, and the D end of the ninth P-type MOS transistor PM9 and the D end of the sixth N-type MOS transistor NM6 are connected to the second inverting output port CKNOUT2 of the control signal generating circuit; the G end of the sixth N-type MOS transistor NM6 is connected to the first output port CLK1 of the two-phase non-overlapping clock generating circuit, and the S end of the sixth N-type MOS transistor NM6 is grounded; The S terminal of the tenth P-type MOS transistor PM10 is connected to VDD, the G terminal of the tenth P-type MOS transistor PM10 is connected to the operational amplifier output port VPVB, the D terminal of the tenth P-type MOS transistor PM10 is connected to the S terminal of the eleventh P-type MOS transistor PM11 and the S terminal of the twelfth P-type MOS transistor PM12; the G terminal of the eleventh P-type MOS transistor PM11 is connected to the second output port CLK2 of the two-phase non-overlapping clock generating circuit, the D terminal of the eleventh P-type MOS transistor PM11 and the D terminal of the seventh N-type MOS transistor NM7 are connected to the first output port CKOUT1 of the control signal generating circuit; the seventh N-type MOS transistor The G terminal of NM7 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generating circuit, the S terminal of the seventh N-type MOS transistor NM7 is grounded, and the G terminal of the twelfth P-type MOS transistor PM12 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generating circuit; the D terminal of the twelfth P-type MOS transistor PM12 and the D terminal of the eighth N-type MOS transistor NM8 are connected to the first output port CKNOUT1 of the control signal generating circuit, the G terminal of the eighth N-type MOS transistor NM8 is connected to the second output port CLK2 of the two-phase non-overlapping clock generating circuit, and the S terminal of the eighth N-type MOS transistor NM8 is grounded.

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