Burr optimization system and method applied to DAC
By designing the combination of I/O clock module, input data register, DAC register, sampling and holding circuit, logic control module, maintenance control module and analog delay module in the DAC system, the timing control and signal delay are optimized, and the DAC glitch is solved. Eliminate the problem of clock interference in the method, significantly reduces the glitches of the DAC output voltage and improves signal quality.
Patent Information
- Application Number
- CN202411301450.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-18
- Publication Date
- 2025-01-03
AI Technical Summary
In the existing DAC glitch elimination method, the sampling and holding signal is synchronized with the data update signal, which cannot effectively eliminate interference of the data update signal on the sampling voltage, and it is impossible to avoid the sampling and holder being disturbed by the internal clock of the chip when the sampling state is switched to the holding state.
A system including I/O clock module, input data register, DAC register, DAC digital-to-analog converter, sampling and holding circuit, logic control module, acquisition and maintenance control module and analog delay module was designed. By setting the DAC register to transfer the input Data is directly converted into digital-to-analog data to avoid the influence of the input data register on the DAC output voltage when data is updated. The analog delay module delays the sampling and holding control signal to set the phase difference, optimize timing control, and enable the sampling and holding signal and data. The update signal is performed in sequence, eliminating interference from the data update signal on the sampling voltage, and avoiding the sampling voltage being disturbed by the internal clock of the chip through the analog delay module.
It effectively eliminates the interference of data update signal on the sampling voltage, reduces glitches in the DAC output, improves the clarity and fluency of the signal, and avoids the impact of clock interference on the sampling and holding voltage.
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Figure CN119254223A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of digital-to-analog conversion technology, and more specifically, to a glitch optimization system and method applied to DAC. Background Art
[0002] Digital to Analog Converter (DAC) is the bridge between the digital world and the analog world. It is precisely because of the rapid development of digital signal processing devices that the requirements for high-speed DAC are getting higher and higher in various systems that need to convert digital signals to analog signals. In mobile communication systems, DAC is required not only to have a high conversion speed, but also to have extremely low noise and a very high signal-to-noise ratio to avoid signal aliasing. In image acquisition systems, such as cameras, DV devices, and LCD display devices, DAC is required to have high resolution while maintaining high speed to ensure the clarity and smoothness of the picture.
[0003] In the development process of signal converters, in addition to considering the static performance of DAC, designers should also pay special attention to its dynamic performance indicators, including glitches, settling time, slew rate, etc. Experiments show that in high-speed, high-precision digital-to-analog conversion systems, the distortion caused by output glitches cannot be ignored. Glitches refer to spikes that appear at the output when the DAC input data changes. This is due to the difference between the on-time and off-time of the analog switch inside the DAC, and due to the influence of distributed parameters, the logic level of each bit of the parallel input data, the leading and trailing edges of the data waveform, and the phase, resulting in input data feed delay. This causes the DAC to have an analog output that is unrelated to the input data at the output for a short period of time during its output transition. Only when the switch state of each bit is switched, can the output be restored to the target value. In the existing glitch elimination method, the sampling and holding signal is synchronized with the data update signal, and the interference of the data update signal on the sampling voltage cannot be eliminated. At the same time, it cannot avoid the interference of the sample and hold device by the internal clock of the chip when the sampling state is converted to the holding state. Summary of the invention
[0004] The purpose of the embodiments of the present application is to provide a glitch optimization system and method for DAC, so as to solve the problem that in the existing glitch elimination method, the sampling and holding signal is synchronized with the data update signal, the interference of the data update signal on the sampling voltage cannot be eliminated, and the sample holder cannot be prevented from being interfered by the internal clock of the chip when the sampling state is converted to the holding state.
[0005] In a first aspect, an embodiment of the present application provides a burr optimization system applied to a DAC, comprising an I / O clock module, an input data register, a DAC register, a DAC digital-to-analog converter, and a sample-and-hold circuit connected in sequence, and further comprising a logic control module, a sample-and-hold control module, and an analog delay module, wherein the logic control module is connected to the input data register, the DAC register, and the sample-and-hold control module, and the analog delay module is connected to the sample-and-hold control module and the sample-and-hold circuit;
[0006] Among them, the logic control module is used to control the DAC register to receive the input data of the input data register, and control the state of the sample and hold circuit to adjust the voltage output of the DAC; the output control signal of the sample and hold control module is sent to the sample and hold circuit after being delayed by the analog delay module to set the phase difference.
[0007] In the above implementation process, the DAC register is set to transfer the input data, and the digital-to-analog conversion is directly performed through the DAC to obtain the converted voltage, so as to avoid the input data register from affecting the output voltage of the DAC when the data is updated. By setting the internal clock and the analog delay module, the sampling and holding control signal is delayed by a set phase difference and sent to the sampling and holding circuit; the timing control is optimized so that the sampling and holding signal and the data update signal are performed in sequence, eliminating the interference of the data update signal on the sampling voltage, and at the same time, the analog delay module is used to make the control signal of the sampling and holding circuit produce a phase difference with various clock signals inside the chip, thereby avoiding the sampling voltage being interfered by the internal clock of the chip.
[0008] Furthermore, it also includes an amplifier, which is connected to the sample and hold circuit.
[0009] In the above implementation process, an amplifier is provided to amplify the output voltage of the sampling and holding circuit.
[0010] Further, the sample-and-hold circuit includes a first sampling switch, a second sampling switch, a third sampling switch and a sampling capacitor, the first end of the first sampling switch and the first end of the third sampling switch are connected to a voltage input end, the second end of the first sampling switch is connected to the first end of the second sampling switch and the first end of the sampling capacitor, the second end of the third sampling switch and the second end of the second sampling switch are connected to a voltage output end, and the second end of the sampling capacitor is connected to a ground end.
[0011] In the above implementation process, a sample-and-hold circuit is provided, so that the sample-and-hold circuit can be in a holding state or a sampling state by controlling a sampling switch.
[0012] Furthermore, the sampling and holding circuit also includes an amplifier input parasitic capacitor, and the amplifier input parasitic capacitor is arranged at the voltage output end.
[0013] In a second aspect, an embodiment of the present application provides a glitch optimization method applied to a DAC, which is applied to the above-mentioned glitch optimization system applied to a DAC, and specifically includes:
[0014] The logic control module controls the DAC register to receive the input data of the input data register, and controls the state of the sample and hold circuit to adjust the voltage output of the DAC;
[0015] The output control signal of the sampling and holding control module is sent to the sampling and holding circuit after being delayed by the analog delay module to set the phase difference.
[0016] Furthermore, before the logic control module controls the DAC register to receive the input data of the input data register and controls the state of the sample and hold circuit to adjust the voltage output of the DAC, it also includes:
[0017] The input data register receives and stores input data.
[0018] Further, the logic control module controls the DAC register to receive the input data of the input data register, and controls the state of the sample and hold circuit to adjust the voltage output of the DAC, including:
[0019] Before the logic control module sends an update signal, the sample-and-hold circuit enters a holding state;
[0020] Upon receiving the update signal sent by the logic control module, the input data register transfers the data to the DAC register;
[0021] Before the next update signal sent by the logic control module, when the DAC output voltage is stable, the sample and hold circuit enters a sampling state to obtain the updated conversion voltage of the DAC.
[0022] Furthermore, the output control signal of the sampling and holding control module is sent to the sampling and holding circuit after being delayed by the analog delay module to set the phase difference, including:
[0023] The internal clock samples the clock cycle of the I / O clock, and after delaying one internal clock cycle, generates a rising edge of a sampling and holding control signal and sends it to the analog delay module;
[0024] When the analog delay module receives the rising edge of the sampling and holding control signal, the output control signal of the sampling and holding control module is sent to the sampling and holding circuit after delay.
[0025] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor; the memory is coupled to the processor, and the processor implements the glitch optimization method applied to DAC as described above when executing the computer program.
[0026] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored computer program; wherein, when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the glitch optimization method applied to DAC as described above. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0028] Figure 1 A schematic diagram of the structure of a glitch optimization system applied to DAC provided in an embodiment of the present application;
[0029] Figure 2 A sampling and holding circuit diagram of a glitch optimization system applied to a DAC provided in an embodiment of the present application;
[0030] Figure 3 A glitch cancel timing control block diagram of a glitch optimization system applied to a DAC provided in an embodiment of the present application;
[0031] Figure 4 A DAC output voltage waveform diagram of a glitch cancel function disabled in a glitch optimization system for a DAC provided in an embodiment of the present application;
[0032] Figure 5 A DAC output voltage waveform diagram of a glitch cancel function enabled in a glitch optimization system for DAC provided in an embodiment of the present application;
[0033] Figure 6 A flowchart of a glitch optimization method applied to a DAC provided in an embodiment of the present application;
[0034] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.
[0036] It should be noted that in the description of the embodiments of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. At the same time, the step numbers in the text are only for the convenience of explaining the embodiments of the present application and do not serve to limit the order of execution of the steps. The method provided in the embodiments of the present application can be executed by the relevant terminal device, and the following description will be given by taking the control system of a hybrid vehicle as the execution subject as an example.
[0037] Please see Figure 1 , Figure 1 A structural diagram of a glitch optimization system applied to a DAC provided in an embodiment of the present application. The glitch optimization system applied to a DAC includes: an I / O clock module, an input data register, a DAC register, a DAC digital-to-analog converter, and a sample-and-hold circuit connected in sequence, and also includes a logic control module, a sample-and-hold control module, and an analog delay module, wherein the logic control module connects the input data register, the DAC register, and the sample-and-hold control module, and the analog delay module connects the sample-and-hold control module and the sample-and-hold circuit;
[0038] Among them, the logic control module is used to control the DAC register to receive the input data of the input data register, and control the state of the sample and hold circuit to adjust the voltage output of the DAC; the output control signal of the sample and hold control module is sent to the sample and hold circuit after being delayed by the analog delay module to set the phase difference.
[0039] As described above, the embodiment of the present application transfers input data by setting a DAC register and directly performs digital-to-analog conversion through the DAC to obtain the converted voltage, thereby avoiding the input data register from affecting the output voltage of the DAC when the data is updated. By setting an internal clock and an analog delay module, the sampling and holding control signal is delayed by a set phase difference and sent to the sampling and holding circuit; the timing control is optimized so that the sampling and holding signal and the data update signal are executed sequentially, eliminating the interference of the data update signal on the sampling voltage, and at the same time, through the analog delay module, the control signal of the sampling and holding circuit is caused to have a phase difference with various clock signals inside the chip, thereby avoiding the sampling voltage being interfered by the internal clock of the chip.
[0040] In some embodiments, an amplifier is also included, and the amplifier is connected to the sample and hold circuit; the amplifier is configured to amplify the output voltage of the sample and hold circuit.
[0041] Specifically, the input data is stored in the input data register through the control of the I / O clock and logic control module, and the DAC output voltage does not change at this time. When the logic control module sends an update signal, the data in the input data register will be transferred to the DAC register (the data in the DAC register is directly sent to the DAC for direct digital-to-analog conversion), and the DAC output voltage changes to the target value. Before the logic control module sends an update signal, the sample-and-hold circuit enters the hold state in advance; when the DAC output voltage is stable, the sample-and-hold circuit enters the sampling state. In addition, an analog delay module is added to make the sample-and-hold circuit control signal produce a phase difference with the chip clock to avoid the influence of the clock signal on the sampling voltage.
[0042] Specific timing control such as Figure 3 As shown in the figure, when the DAC register data is updated, a large number of digital circuits inside the chip will flip, and the buffer for digital signals inside the analog circuit will also flip, which will cause the DAC output voltage to fluctuate. If the sample-and-hold circuit samples at this moment, it is possible to sample the wrong voltage. Therefore, the sampling and holding control timing is adjusted to make the sample-and-hold circuit enter the holding state at the falling edge of the internal clock, and update the DAC register data at the next rising edge to avoid the sample-and-hold circuit outputting the wrong voltage due to the DAC data update.
[0043] Due to the parasitic problems of the bonding wire and the power ground routing inside the chip, the I / O clock and the internal clock will also cause certain interference to the DAC output voltage when they flip. Therefore, an analog delay module is added to the signal path from the sampling and holding control output to the sampling and holding circuit, so that the actual control signal of the sampling and holding circuit and the signal sent by the sampling and holding control have a certain phase difference. As long as the internal delay of the analog delay module is reasonably controlled, the actual control signal of the sampling and holding circuit can be staggered with the I / O clock edge and the internal clock edge, avoiding the sampling and holding circuit outputting an erroneous voltage due to the clock flip.
[0044] In some embodiments, please refer to Figure 2 The sampling and holding circuit includes a first sampling switch, a second sampling switch, a third sampling switch and a sampling capacitor, wherein the first end of the first sampling switch and the first end of the third sampling switch are connected to a voltage input end, the second end of the first sampling switch is connected to the first end of the second sampling switch and the first end of the sampling capacitor, the second end of the third sampling switch and the second end of the second sampling switch are connected to a voltage output end, and the second end of the sampling capacitor is connected to a ground end; the sampling and holding circuit is set so that the sampling and holding circuit can be in a holding state or a sampling state by controlling the sampling switch.
[0045] In some embodiments, the sample-and-hold circuit further includes an amplifier input parasitic capacitor, and the amplifier input parasitic capacitor is disposed at the voltage output terminal.
[0046] Specifically, the sample-and-hold circuit is as follows: Figure 5 As shown. Among them, the voltage input terminal (In terminal) is the input terminal of the sampling and holding circuit, which is connected to the output of the DAC in the system, and the voltage output terminal (Out terminal) is the output terminal, which is connected to the input terminal of the amplifier. S1 is the first sampling switch, S2 is the second sampling switch, S3 is the third sampling switch, Cs is the sampling capacitor, and the node P is the upper plate of the sampling capacitor. In the high-precision DAC circuit, the input offset error of the amplifier will directly affect the offset error of the DAC after amplification, so the input parasitic capacitance of the amplifier cannot be ignored. In the figure, Cp is the input parasitic capacitance of the amplifier. When CLK is high, the first sampling switch S1 and the third sampling switch S3 are turned on, and the circuit is in the sampling state; when CLK is low, the circuit is in the holding state.
[0047] The first sampling switch S1, the second sampling switch S2, and the third sampling switch S3 are identical switches. When the sampling and holding circuit switches from the sampling state to the holding state, the two switch control signals at the node P are in opposite phases, so the clock feedthrough and charge injection phenomena of the switch can be offset, and the above phenomena can be prevented from affecting the output voltage of the sampling and holding circuit. The same is true for the Out end. At the same time, the first sampling switch S1, the second sampling switch S2, and the third sampling switch S3 are all CMOS switches, that is, they are composed of PMOS tubes and NMOS tubes. Therefore, there is an inverted clock inside the switch, and the channel charge type is opposite, which can weaken the clock feedthrough and charge injection phenomena to a certain extent when the switch state is switched. As described above, the sampling and holding circuit of the embodiment of the present application can effectively reduce the deterioration of the switch parasitics on the DAC output voltage burrs.
[0048] For example, Figure 4 and Figure 5 This is the chip glitch energy test result using the technology of the embodiment of the present application. Figure 4 The DAC output voltage waveform with the glitch cancel function turned off is shown. Figure 5 The DAC output voltage waveform with the glitch cancel function turned on is shown. It can be seen that the DAC output voltage glitch is significantly reduced when the glitch cancel function is turned on.
[0049] As described above, the embodiments of the present application eliminate the glitches generated by the data update signal when the DAC output voltage is converted by optimizing the timing; the phase difference between the sample and hold control signal and the various clock signals inside the chip is caused by the analog delay circuit to reduce the glitches; and the influence of clock feedthrough and charge injection on the sampling voltage is eliminated by optimizing the sample and hold circuit structure, thereby reducing the DAC output glitches.
[0050] In the second aspect, based on the above embodiments, Figure 6 A flowchart of a glitch optimization method for DAC provided in an embodiment of the present application. Figure 6 The glitch optimization method for DAC provided in the embodiment of the present application is applied to the above-mentioned glitch optimization system for DAC, and specifically includes:
[0051] 100. The logic control module controls the DAC register to receive input data from the input data register, and controls the state of the sample and hold circuit to adjust the voltage output of the DAC.
[0052] 200. The output control signal of the sampling and holding control module is delayed by the analog delay module to set the phase difference and then sent to the sampling and holding circuit.
[0053] As described above, the embodiment of the present application transfers input data by setting a DAC register and directly performs digital-to-analog conversion through the DAC to obtain the converted voltage, thereby avoiding the input data register from affecting the output voltage of the DAC when the data is updated. By setting an internal clock and an analog delay module, the sampling and holding control signal is delayed by a set phase difference and sent to the sampling and holding circuit; the timing control is optimized so that the sampling and holding signal and the data update signal are executed sequentially, eliminating the interference of the data update signal on the sampling voltage, and at the same time, through the analog delay module, the control signal of the sampling and holding circuit is caused to have a phase difference with various clock signals inside the chip, thereby avoiding the sampling voltage being interfered by the internal clock of the chip.
[0054] In some embodiments, before the logic control module controls the DAC register to receive the input data of the input data register and controls the state of the sample and hold circuit to adjust the voltage output of the DAC, it also includes:
[0055] The input data register receives and stores input data.
[0056] In some embodiments, the logic control module controls the DAC register to receive the input data of the input data register and controls the state of the sample and hold circuit to adjust the voltage output of the DAC, including:
[0057] 110. Before the logic control module sends an update signal, the sample and hold circuit enters a holding state.
[0058] 120. After receiving the update signal sent by the logic control module, the input data register transfers the data to the DAC register.
[0059] 130. Before the next update signal sent by the logic control module, when the DAC output voltage is stable, the sample and hold circuit enters a sampling state to obtain the updated conversion voltage of the DAC.
[0060] In some embodiments, the output control signal of the sampling and holding control module is sent to the sampling and holding circuit after being delayed by the analog delay module to set the phase difference, including:
[0061] 210. Sample the clock cycle of the I / O clock through the internal clock, and after delaying one internal clock cycle, generate a rising edge of the sampling and holding control signal and send it to the analog delay module.
[0062] 220. When the analog delay module receives the rising edge of the sampling and holding control signal, the output control signal of the sampling and holding control module is sent to the sampling and holding circuit after delay.
[0063] Specifically, the input data is stored in the input data register through the control of the I / O clock and logic control module, and the DAC output voltage does not change at this time. When the logic control module sends an update signal, the data in the input data register will be transferred to the DAC register (the data in the DAC register is directly sent to the DAC for direct digital-to-analog conversion), and the DAC output voltage changes to the target value. Before the logic control module sends an update signal, the sample-and-hold circuit enters the hold state in advance; when the DAC output voltage is stable, the sample-and-hold circuit enters the sampling state. In addition, an analog delay module is added to make the sample-and-hold circuit control signal produce a phase difference with the chip clock to avoid the influence of the clock signal on the sampling voltage.
[0064] Specific timing control such as Figure 3 As shown in the figure, when the DAC register data is updated, a large number of digital circuits inside the chip will flip, and the buffer for digital signals inside the analog circuit will also flip, which will cause the DAC output voltage to fluctuate. If the sample-and-hold circuit samples at this moment, it is possible to sample the wrong voltage. Therefore, the sampling and holding control timing is adjusted to make the sample-and-hold circuit enter the holding state at the falling edge of the internal clock, and update the DAC register data at the next rising edge to avoid the sample-and-hold circuit outputting the wrong voltage due to the DAC data update.
[0065] Due to the parasitic problems of the bonding wire and the power ground routing inside the chip, the I / O clock and the internal clock will also cause certain interference to the DAC output voltage when they flip. Therefore, an analog delay module is added to the signal path from the sampling and holding control output to the sampling and holding circuit, so that the actual control signal of the sampling and holding circuit and the signal sent by the sampling and holding control have a certain phase difference. As long as the internal delay of the analog delay module is reasonably controlled, the actual control signal of the sampling and holding circuit can be staggered with the I / O clock edge and the internal clock edge, avoiding the sampling and holding circuit outputting an erroneous voltage due to the clock flip.
[0066] For example, Figure 4 and Figure 5 This is the chip glitch energy test result using the technology of the embodiment of the present application. Figure 4 The DAC output voltage waveform with the glitch cancel function turned off is shown. Figure 5 The DAC output voltage waveform with the glitch cancel function turned on is shown. It can be seen that the DAC output voltage glitch is significantly reduced when the glitch cancel function is turned on.
[0067] As described above, the embodiments of the present application eliminate the glitches generated by the data update signal when the DAC output voltage is converted by optimizing the timing; the phase difference between the sample and hold control signal and the various clock signals inside the chip is caused by the analog delay circuit to reduce the glitches; and the influence of clock feedthrough and charge injection on the sampling voltage is eliminated by optimizing the sample and hold circuit structure, thereby reducing the DAC output glitches.
[0068] In a third aspect, based on the above embodiments, the embodiments of the present application further provide an electronic device, which can integrate the glitch optimization device applied to DAC provided in the embodiments of the present application. Figure 7 Schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Figure 7 The electronic device includes: an input device 73, an output device 74, a memory 72 and one or more processors 71; the memory 72 is used to store one or more programs; when the one or more programs are executed by the one or more processors 71, the one or more processors 71 implement the glitch optimization method for DAC provided in the above embodiment. The input device 73, the output device 74, the memory 72 and the processor 71 can be connected by a bus or other means. Figure 7 The example of connecting through bus is taken in the following.
[0069] The processor 71 executes various functional applications and data processing of the device by running the software programs, instructions and modules stored in the memory 72, that is, implements the above-mentioned glitch optimization method applied to DAC.
[0070] The electronic device provided above can be used to execute the glitch optimization method applied to DAC provided in the above embodiment, and has corresponding functions and beneficial effects.
[0071] In a fourth aspect, based on the above embodiments, the embodiments of the present application also provide a computer-readable storage medium, the computer-readable storage medium including a stored computer program; wherein, when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the burr optimization method applied to DAC as described above, and can achieve the same beneficial effects.
[0072] Of course, the storage medium containing computer executable instructions provided in an embodiment of the present application is not limited to the glitch optimization method applied to DAC as described above, and can also execute related operations in the glitch optimization method applied to DAC provided in any embodiment of the present application.
[0073] In a fifth aspect, based on the above embodiments, the embodiments of the present application also provide a computer program product, and the methods described in the various embodiments of the present application can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the processes or functions described in the various embodiments of the present application are executed in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, a core network device, an OAM (Open Application Model) or other programmable device.
[0074] In several embodiments provided in the embodiments of the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to the embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.
[0075] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part.
[0076] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program code.
[0077] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the embodiment of the present application, which should be included in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiment of the present application shall be based on the protection scope of the claims.
Claims
1. A glitch optimization system for DAC, characterized in that: include: An I / O clock module, an input data register, a DAC register, a DAC digital-to-analog converter and a sample-and-hold circuit connected in sequence, and also includes a logic control module, a sample-and-hold control module and an analog delay module, wherein the logic control module is connected to the input data register, the DAC register and the sample-and-hold control module, and the analog delay module is connected to the sample-and-hold control module and the sample-and-hold circuit; The logic control module is used to control the DAC register to receive the input data of the input data register, and control the state of the sample and hold circuit to adjust the voltage output of the DAC; The output control signal of the sampling and holding control module is sent to the sampling and holding circuit after being delayed by the analog delay module to set the phase difference.
2. The glitch optimization system for DAC according to claim 1, characterized in that: An amplifier is also included, and the amplifier is connected to the sample-and-hold circuit.
3. The glitch optimization system for DAC according to claim 1, characterized in that: The sample-and-hold circuit includes a first sampling switch, a second sampling switch, a third sampling switch and a sampling capacitor, wherein a first end of the first sampling switch and a first end of the third sampling switch are connected to a voltage input end, a second end of the first sampling switch is connected to a first end of the second sampling switch and a first end of the sampling capacitor, a second end of the third sampling switch and a second end of the second sampling switch are connected to a voltage output end, and a second end of the sampling capacitor is connected to a ground end.
4. The glitch optimization system for DAC according to claim 3, characterized in that: The sampling and holding circuit further includes an amplifier input parasitic capacitor, and the amplifier input parasitic capacitor is arranged at the voltage output end.
5. A glitch optimization method applied to DAC, characterized in that: Applied to the glitch optimization system for DAC according to any one of claims 1 to 4, the method comprising: The logic control module controls the DAC register to receive the input data of the input data register, and controls the state of the sample and hold circuit to adjust the voltage output of the DAC; The output control signal of the sampling and holding control module is sent to the sampling and holding circuit after being delayed by the analog delay module to set the phase difference.
6. The glitch optimization method applied to DAC according to claim 5, characterized in that: Before the logic control module controls the DAC register to receive the input data of the input data register and controls the state of the sample and hold circuit to adjust the voltage output of the DAC, the logic control module further includes: The input data register receives and stores input data.
7. The glitch optimization method for DAC according to claim 6, characterized in that: The logic control module controls the DAC register to receive the input data of the input data register and controls the state of the sample and hold circuit to adjust the voltage output of the DAC, including: Before the logic control module sends an update signal, the sample-and-hold circuit enters a holding state; Upon receiving the update signal sent by the logic control module, the input data register transfers the data to the DAC register; Before the next update signal sent by the logic control module, when the DAC output voltage is stable, the sample and hold circuit enters a sampling state to obtain the updated conversion voltage of the DAC.
8. The glitch optimization method for DAC according to claim 5, characterized in that: The output control signal of the sampling and holding control module is sent to the sampling and holding circuit after being delayed by the analog delay module to set the phase difference, including: The internal clock samples the clock cycle of the I / O clock, and after delaying one internal clock cycle, generates a rising edge of a sampling and holding control signal and sends it to the analog delay module; When the analog delay module receives the rising edge of the sampling and holding control signal, the output control signal of the sampling and holding control module is sent to the sampling and holding circuit after delay.
9. An electronic device, characterized in that: It includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor; the memory is coupled to the processor, and when the processor executes the computer program, it implements the glitch optimization method applied to DAC as described in any one of claims 5-8.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program; wherein, when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the glitch optimization method applied to DAC according to any one of claims 5 to 8.