A flexible and efficient multi-channel parallel ADC scheduling method

Abstract

The invention relates to the technical field of data acquisition, and discloses a flexible and efficient multi-channel parallel ADC scheduling method. The timing processing unit executes the configuration of all channels according to the principle of first trigger first process according to different trigger events; the channel buffer unit caches the channel configuration of the timing processing unit; the ADC control logic unit starts after receiving the channel configuration information of the channel buffer unit; the ADC module outputs the sampling value of the channel according to the control logic signal and transmits it to the data filtering unit; the data filtering unit judges the channel acquisition data; the acquisition data buffer unit caches the channel number and the acquisition data; the data is transmitted to the receiving end through the CPU unit to perform periodic data sampling according to the interrupt information, and the acquisition data of different channels are collected into different memories, and the CPU unit processes them uniformly. The external part of the present invention can simultaneously issue multi-channel parallel and independent mobilization instructions, and the converter processes serially according to the priority without occupying public resources.

Description

Technical Field

[0001] The present invention relates to the technical field of data acquisition, and in particular to a flexible and efficient multi-channel parallel ADC scheduling method. Background Art

[0002] Multi-channel data acquisition systems are increasingly used in fields such as electric vehicles, communications, and medical treatment. Multiple ADC units are bound to increase PCB routing and power consumption. There is an urgent need to reduce the number of ADC units while requiring as much multi-channel data to be collected as possible. In view of the scenario where ADC converters are reduced, the current ADC acquisition uses the CPU to control the sampling cycle, add analog selectors, and set channel priorities to achieve multi-channel ADC sampling.

[0003] In the existing method, regarding multi-channel parallel ADC scheduling, multiple ADC channels are allocated to two or more ADC devices to meet different application scenarios, and application requirements under differentiated dynamic hardware flexible configuration are realized; dynamic configuration of input channel selection is realized through software and hardware configuration of working state sequence and channel conversion sequence, so that different ADCs can collect the same ADC channel and realize redundant functional safety. However, in the existing method, software participation is required to realize multi-channel ADC acquisition, and multiple timers or trigger mechanisms are started. The acquisition data management is complex, CPU distribution processing is required, and scheduling takes a long time; at the same time, the current multi-channel parallel data acquisition system will occupy more PCB wiring and power consumption, and the size cannot be maximized, resulting in an increase in the total bill of materials (BOM). Summary of the invention

[0004] The present invention provides a flexible and efficient multi-channel parallel ADC scheduling method, which is applied to an IC chip application scenario in which a single ADC converter has a large number of channels and multiple channels need to be time-division multiplexed to the ADC converter. In addition, the external device can independently issue dispatching instructions for multiple channels in parallel at the same time, and the converters process them serially according to priority without occupying public resources.

[0005] The present invention provides a flexible and efficient multi-channel parallel ADC scheduling method, a data acquisition system based on multi-channel parallel ADC scheduling, the data acquisition system comprises a timing processing unit, a channel buffer unit, an ADC control logic unit, an ADC module, a data filtering unit, a collection data buffer unit, a CPU unit and a DMA module (Direct Memory Access), the timing processing unit is respectively connected to a plurality of timers, each of the timers is connected to a channel;

[0006] The method specifically comprises:

[0007] S1, preset the sampling rate and number of channels of different channels, and configure the timers of all channels, and the timers start working after the ADC module is started;

[0008] S2, the timing processing unit performs configuration of all channels according to the principle of first trigger first process according to different trigger events;

[0009] S3, the channel cache unit caches the channel configuration of the timing processing unit, the cached configuration is cleared by the channel disable signal, the cached configuration follows the first-in-first-out principle, and the channel configuration is taken away when the ADC module is not working;

[0010] S4, the ADC control logic unit starts after receiving the channel configuration information of the channel buffer unit, and the timing strictly complies with the work flow of the ADC module;

[0011] S5, the ADC module outputs the sampling value of the channel according to the control logic signal and transmits it to the data filtering unit;

[0012] S6, the data filtering unit judges the channel acquisition data, and transmits the expected data to the acquisition data buffer unit; wherein the judgment method includes taking averages multiple times, setting high and low thresholds, and data filtering;

[0013] S7, the collected data cache unit caches the channel number and the collected data, transmits the data to the data receiving end according to the trigger mechanism in accordance with the first-in-first-out principle, and reports the interrupt information at the same time;

[0014] S8. The data is transmitted to the receiving end by periodic data sampling by the CPU unit according to the interrupt information, or by sending a DMA request through the data acquisition module trigger mechanism to collect the acquired data of different channels into different memories. When the set number is reached, the CPU unit processes it uniformly to complete the fast acquisition of multi-channel single ADC.

[0015] Further, in the data acquisition system, the CPU unit is respectively connected to the timing processing unit, the channel cache unit, the ADC control logic unit, the data filtering unit, the acquisition data cache unit and the DMA module, the timing processing unit is also connected to the channel cache unit, the channel cache unit is also connected to the ADC control logic unit, the ADC control logic unit is also connected to the ADC module, the ADC module is also connected to the data filtering unit, the data filtering unit is also connected to the acquisition data cache unit, and the acquisition data cache unit is also connected to the DMA module.

[0016] Furthermore, the sampling rate range of the ADC module is between 1Ksps and 1Msps, the number of channels is 11, and the working clock of the ADC module is 24Mhz.

[0017] Furthermore, step S2 specifically includes:

[0018] Each channel uses a different timer to count respectively. When two channels trigger the timer clearing action at the same time, the timing processing unit first executes the channel with a higher priority according to the priority sequence table, and then executes the other channel in sequence;

[0019] When abnormal sampling occurs in a channel, the timing processing unit does not execute the configuration of the channel. When there are no abnormalities or conflicts in other channels, the principle of first trigger first process is followed.

[0020] Furthermore, in step S3, the channel cache unit also has a monitoring function, and reports interrupt information when the cache data is always empty or the cache data exceeds the cache warning upper limit. The CPU unit monitors the interrupt to determine the state of the cache unit and performs macro-control;

[0021] Furthermore, the macro-control method is as follows: suppose the interrupt numbers include 1 and 2, 1 indicates that the cache data is always empty, and 2 indicates that the cache data exceeds the warning. The CPU unit obtains the corresponding interrupt number in the interface. If the cache data is always empty, the CPU unit alarms and checks whether the channel timer is successfully configured and whether the ADC working clock is working, so as to reset and reprocess the ADC system; if the cache data exceeds the warning, check whether the ADC module and the ADC control logic unit are working normally, and check whether the channel timer configuration exceeds the processing capacity of the ADC module, so as to reset the ADC system.

[0022] Furthermore, in step S3, the cache configuration is cleared through a channel disable signal, including: each channel has a corresponding enable signal, after the channel is enabled, the channel configuration is cached, and if a channel does not need to collect data, the corresponding channel is disabled, and the cache clears the corresponding channel configuration.

[0023] Furthermore, in step S4, the ADC module is powered separately and enabled independently, including fast process configuration and regular configuration. The fast process configuration is applied in scenarios where the number of channels exceeds the set number and the sampling frequency exceeds the set frequency. Otherwise, it works in the regular configuration.

[0024] Furthermore, in the step S6, taking the average multiple times is: taking the average of multiple data of the channel, and delivering the average value to the next processing unit; setting the high and low thresholds is: setting a theoretical maximum and minimum value of the channel, filtering out channel data that is greater than the maximum value or less than the minimum value, and delivering the data that meets the requirements to the next processing unit; data filtering is to use a smoothing algorithm to make the filtered data smoother.

[0025] Furthermore, in step S8, the memory space sizes of different channels are pre-allocated to map the data of different channels into corresponding memory spaces.

[0026] The beneficial effects of the present invention are:

[0027] 1. The present invention multiplexes the data acquisition of multiple channels into one ADC, eliminating the need for multiple ADCs for acquisition, reducing BOM costs, and meeting the development needs of low-power, small-size integrated data acquisition solutions.

[0028] 2. Multiple channels are timed individually through independent parallel timers and a unique trigger mechanism, which not only efficiently meets the ADC data collection requirements, but also cleverly avoids sampling conflicts between different channels when the sampling rates of different channels are different.

[0029] 3. Multi-task processing such as timers, trigger mechanisms, and data collection management of multiple channels can work independently when the working mode is enabled, without occupying CPU resources, thereby improving system performance.

[0030] 4. During the ADC scheduling process, each processing unit is monitored by the CPU, and the fault can be reported in time under abnormal working conditions, and the ADC scheduling can be re-performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of multi-channel parallel ADC scheduling in the present invention.

[0032] Figure 2 It is a schematic diagram of the processing mechanism of the timing processing unit in the present invention.

[0033] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0034] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0035] The present invention is applied to an IC chip application scenario in which the ADC converter is single, the number of channels is large, and multiple channels need to be time-division multiplexed to the ADC converter; and externally, multiple channels can simultaneously and independently issue mobilization instructions in parallel, and the converter processes them serially according to priority without occupying public resources.

[0036] The present invention provides a multi-channel parallel ADC scheduling method, which can flexibly allocate acquisition strategies for different channels under very low power consumption support to realize data acquisition of different channels in different scenarios to cope with space-constrained application scenarios such as wearable devices, Internet of Things (IoT) and portable instruments. At the same time, the sampling rates of multiple channels can be independently and flexibly configured, and DMA can be used to move data to a specified memory. When a certain number is reached, CPU processing is triggered, thereby releasing CPU space.

[0037] The present invention provides a flexible and efficient multi-channel parallel ADC scheduling method, a data acquisition system based on multi-channel parallel ADC scheduling, the data acquisition system comprises a timing processing unit, a channel buffer unit, an ADC control logic unit, an ADC module, a data filtering unit, a collection data buffer unit, a CPU unit and a DMA module, the timing processing unit is respectively connected to a plurality of timers, each of the timers is connected to a channel, such as Figure 1 As shown, the number of channels is the same as the number of timers, such as channel 1 is connected to timer 1, channel 2 is connected to timer 2, channel 3 is connected to timer 3, and so on, channel N-2 is connected to timer N-2, channel N-1 is connected to timer N-1, and channel N is connected to timer N.

[0038] The CPU unit is respectively connected to the timing processing unit, the channel cache unit, the ADC control logic unit, the data filtering unit, the acquisition data cache unit and the DMA module; the timing processing unit is also connected to the channel cache unit; the channel cache unit is also connected to the ADC control logic unit; the ADC control logic unit is also connected to the ADC module; the ADC module is also connected to the data filtering unit; the data filtering unit is also connected to the acquisition data cache unit; and the acquisition data cache unit is also connected to the DMA module.

[0039] The sampling rate of the ADC unit of the present invention ranges from 1Ksps to 1Msps, the number of channels supports sampling of up to 11 (N=11) channels, the working clock of the ADC module is 24Mhz, and the ADC acquisition method of the present invention is as follows: Figure 1 As shown, the workflow of the method of the present invention specifically includes:

[0040] S1. Set the sampling rate and number of channels of different channels in advance according to the requirements. Assume that the sampling rate of channel 1 is 500Khz, and the timer is set to clear after 48 cycles and re-count. Similarly, configure all timers. The timer starts working after the ADC is started.

[0041] S2. The timing processing unit needs to flexibly process according to different trigger events. Figure 2 Taking the timing trigger channel as an example, channel 1 and channel 2 are counted separately using different timers. When both trigger the timer clearing action at the same time, the timing processing unit shall execute channel 2 with a higher priority according to the priority sequence table, and then execute channel 1 in sequence. When channel 4 has channel abnormal sampling, the timing processing unit does not execute the configuration of channel 4. When there is no abnormality or conflict in other channels, the principle of first trigger first process is followed.

[0042] S3. The channel cache unit caches the channel configuration of the timing processing unit. The cached configuration can be cleared by the channel disable signal. The cached configuration follows the first-in-first-out principle. The channel configuration is removed when the ADC module is not working. The channel cache unit also has a monitoring function. When the cache data is always empty or the cache data exceeds the cache warning upper limit, an interrupt information is reported. The CPU determines the state of the cache unit by monitoring the interrupt and performs macro-control.

[0043] The cache configuration is cleared through the channel disable signal: Assuming there are eleven channels, these eleven channels have corresponding enable signals. After the channels are enabled, the channel configuration can be cached. If a channel does not need to collect data, the corresponding channel can be disabled, so that the cache will clear the corresponding channel configuration.

[0044] Macroeconomic control: Assume that the reported interrupt forms are numbered 1 and 2, 1 means that the cache data is always empty, and 2 means that the cache data exceeds the warning. The CPU can obtain the corresponding interrupt number in the interface. If the cache data is always empty, the CPU will alarm and check whether the channel timer is successfully configured and whether the ADC working clock is working. If necessary, reset the ADC system and reprocess it; if the cache data exceeds the warning, check whether the ADC and the control logic unit are working properly, check whether the channel timer configuration is too fast and exceeds the processing capacity of the ADC unit, and reset the ADC system if necessary.

[0045] S4. The ADC control logic unit starts after receiving the channel configuration information of the channel cache unit. The timing must strictly comply with the workflow of the ADC module. The ADC module can be powered separately and enabled independently. It supports fast process configuration and conventional configuration. The fast process configuration is used in high-demand scenarios such as a large number of channels (i.e., exceeding the set number) and a high sampling frequency (i.e., exceeding the set frequency). Otherwise, it works in conventional configuration.

[0046] S5. The ADC module outputs the sampling value of the channel according to the control logic signal and passes it to the data filtering unit; that is, it is understood as a black box, which has a corresponding interface provided to the outside. The outside only needs to configure the corresponding channel information according to the provided interface timing, and the channel can spit out the collection value of the corresponding channel. The corresponding channel is connected to the external sensor, and the internal is the AD / DA conversion module.

[0047] S6. The data filtering unit judges the channel acquisition data and transmits the expected data to the acquisition data buffer unit; wherein the judgment method includes taking averages multiple times, setting high and low thresholds, and data filtering.

[0048] 1) Take the average value multiple times: take the average of multiple data of the channel and pass the average value to the next processing unit;

[0049] 2) Setting the high and low thresholds: Setting a theoretical maximum and minimum value for the channel, filtering out channel data that is greater than the maximum value or less than the minimum value, and copying the data that meets the requirements to the next processing unit;

[0050] 3) Data filtering uses a smoothing algorithm to make the filtered data smoother.

[0051] S7, the data acquisition buffer unit performs buffer processing on the channel number and the acquired data, and transmits the data to the data receiving end according to the first-in-first-out principle and the trigger mechanism. Meanwhile, the data acquisition module reports the interrupt information.

[0052] First in, first out: The channel that first meets the timer trigger condition will be processed by ADC first, and the processed channel will be placed in the acquisition data cache unit first, and so on. When the CPU sends a receive instruction, the channel data with a high priority can be processed first.

[0053] S8. The way to transmit data to the receiving end is that the CPU performs periodic data sampling according to the interrupt information, or sends a DMA data transfer request through the data acquisition module trigger mechanism, collects the acquired data of different channels into different memories, and when a certain number is reached, the CPU processes them uniformly. In this way, fast acquisition of multi-channel single ADC can be completed with minimal CPU involvement.

[0054] When storing, allocate memory space in advance. Assume that there is 1K space to store the collected data of different channels. The space range of channel 1 is 0~50BYTE, the space range of channel 2 is 51~100BYTE, and so on. The data of different channels should be mapped to the corresponding memory space.

[0055] The present invention is not limited to a multi-channel parallel sampling mode. The CPU can also independently schedule each channel, and the trigger mode can also trigger data collection through software events and IO status.

[0056] The present invention multiplexes the data acquisition of multiple channels to one ADC, and does not need multiple ADCs for acquisition, thereby reducing BOM costs and meeting the development needs of low-power, small-size integrated data acquisition solutions. Multiple channels are individually timed through independent parallel timers, and the unique trigger mechanism can efficiently meet the ADC acquisition data while cleverly avoiding sampling conflicts between different channels when the channels have different sampling rates. The timers, trigger mechanisms, acquisition data management and other multi-task processing of multiple channels can work independently when the working mode is enabled, without occupying CPU resources, thereby improving system performance. During the ADC scheduling process, each processing unit is monitored by the CPU, and faults can be reported in time in an abnormal working state, and ADC scheduling can be re-performed.

[0057] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0058] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A flexible and efficient multi-channel parallel ADC scheduling method, characterized in that: A data acquisition system based on multi-channel parallel ADC scheduling, the data acquisition system includes a timing processing unit, a channel buffer unit, an ADC control logic unit, an ADC module, a data filtering unit, a collection data buffer unit, a CPU unit and a DMA module, the timing processing unit is respectively connected to a plurality of timers, each of which is connected to a channel; The method specifically comprises: S1, preset the sampling rate and number of channels of different channels, and configure the timers of all channels, and the timers start working after the ADC module is started; S2, the timing processing unit performs configuration of all channels according to the principle of first trigger first process according to different trigger events; specifically including: Each channel uses a different timer to count respectively. When two channels trigger the timer clearing action at the same time, the timing processing unit first executes the channel with a higher priority according to the priority sequence table, and then executes the other channel in sequence; When a channel has abnormal sampling, the timing processing unit does not execute the configuration of the channel. When there is no abnormality or conflict in other channels, the principle of first trigger first process is followed. S3, the channel cache unit caches the channel configuration of the timing processing unit, the cached configuration is cleared by the channel disable signal, the cached configuration follows the first-in-first-out principle, and the channel configuration is taken away when the ADC module is not working; S4, the ADC control logic unit starts after receiving the channel configuration information of the channel buffer unit, and the timing strictly complies with the work flow of the ADC module; S5, the ADC module outputs the sampling value of the channel according to the control logic signal and transmits it to the data filtering unit; S6, the data filtering unit judges the channel acquisition data, and transmits the expected data to the acquisition data buffer unit; wherein the judgment method includes taking averages multiple times, setting high and low thresholds, and data filtering; S7, the collected data cache unit caches the channel number and the collected data, transmits the data to the data receiving end according to the trigger mechanism in accordance with the first-in-first-out principle, and reports the interrupt information at the same time; S8. The data is transmitted to the receiving end by periodic data sampling by the CPU unit according to the interrupt information, or by sending a DMA request through the data acquisition module trigger mechanism to collect the acquired data of different channels into different memories. When the set number is reached, the CPU unit processes it uniformly to complete the fast acquisition of multi-channel single ADC.

2. The flexible and efficient multi-channel parallel ADC scheduling method according to claim 1, characterized in that: In the data acquisition system, the CPU unit is respectively connected to the timing processing unit, the channel cache unit, the ADC control logic unit, the data filtering unit, the acquisition data cache unit and the DMA module, the timing processing unit is also connected to the channel cache unit, the channel cache unit is also connected to the ADC control logic unit, the ADC control logic unit is also connected to the ADC module, the ADC module is also connected to the data filtering unit, the data filtering unit is also connected to the acquisition data cache unit, and the acquisition data cache unit is also connected to the DMA module.

3. The flexible and efficient multi-channel parallel ADC scheduling method according to claim 2, characterized in that: The sampling rate of the ADC module ranges from 1Ksps to 1Msps, the number of channels is 11, and the working clock of the ADC module is 24Mhz.

4. The flexible and efficient multi-channel parallel ADC scheduling method according to claim 1, characterized in that: In step S3, the channel cache unit also has a monitoring function, and reports interrupt information when the cache data is always empty or the cache data exceeds the cache warning upper limit. The CPU unit determines the state of the cache unit by monitoring the interrupt and performs macro-control.

5. The flexible and efficient multi-channel parallel ADC scheduling method according to claim 4, characterized in that: The macro-control method is as follows: the interrupt numbers include 1 and 2, 1 indicates that the cache data is always empty, and 2 indicates that the cache data exceeds the warning. The CPU unit obtains the corresponding interrupt number in the interface. If the cache data is always empty, the CPU unit alarms and checks whether the channel timer is successfully configured and whether the ADC working clock is working, so as to reset and reprocess the ADC system; if the cache data exceeds the warning, check whether the ADC module and the ADC control logic unit are working normally, and check whether the channel timer configuration exceeds the processing capacity of the ADC module, so as to reset the ADC system.

6. The flexible and efficient multi-channel parallel ADC scheduling method according to claim 1, characterized in that: In the step S3, the cache configuration is cleared by a channel disable signal, including: each channel has a corresponding enable signal, after the channel is enabled, the channel configuration is cached, and if a channel does not need to collect data, the corresponding channel is disabled, and the cache clears the corresponding channel configuration.

7. The flexible and efficient multi-channel parallel ADC scheduling method according to claim 1, characterized in that: In step S4, the ADC module is powered independently and enabled independently, including fast process configuration and conventional configuration. The fast process configuration is applied when the number of channels exceeds the set number and the sampling frequency exceeds the set frequency. Otherwise, it works in the conventional configuration.

8. The flexible and efficient multi-channel parallel ADC scheduling method according to claim 1, characterized in that: In step S6, taking the average multiple times is: taking the average of multiple data of the channel, and delivering the average value to the next processing unit; setting the high and low thresholds is: setting a theoretical maximum and minimum value of the channel, filtering out channel data greater than the maximum value or less than the minimum value, and copying the data that meets the requirements to the next processing unit; Data filtering uses a smoothing algorithm to make the filtered data smoother.

9. The flexible and efficient multi-channel parallel ADC scheduling method according to claim 1, characterized in that: In the step S8, the memory space sizes of different channels are pre-allocated to map the data of different channels into the corresponding memory space.

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