Partitioned Sleep Mode Tunable Resolution Capacitive Array Analog-to-Digital Converter and Its Method

Abstract

A capacitive array analog-to-digital converter with partitioned sleep mode and adjustable resolution, comprising: a positive-phase conversion capacitive array, including a positive-phase high-capacitance array and a positive-phase low-capacitance array; a negative-phase conversion capacitive array, including a negative-phase high-capacitance array and a negative-phase low-capacitance array; a sampling module for initially sampling an input signal from the top plates of all capacitive units; a comparator for comparing the input signal or the states of the positive-phase conversion capacitive array and the negative-phase conversion capacitive array and outputting bit data; a shift register for storing the bit data; and a state switching module for cooperating with a bridge switch to control the circuit connection states of all capacitive units, where the circuit connection states include a connection state and a voltage state. By means of partitioned sleep mode, the present invention reduces the energy consumption required by capacitive units, reduces the number of unit capacitors, and thus reduces the overall power consumption of the analog-to-digital converter.

Description

Technical Field

[0001] The present invention relates to the field of analog-to-digital converters, and specifically to a capacitor array analog-to-digital converter with partitioned sleep and adjustable resolution and its method. Background Art

[0002] An analog-to-digital converter is an electronic component that converts an analog signal into a digital signal. Analog-to-digital converters can generally be divided into two types: direct type and indirect type. Among direct-type analog-to-digital converters, the successive approximation analog-to-digital converter is a type with medium resolution, medium speed, and simple structure.

[0003] The successive approximation analog-to-digital converter has advantages such as high digitization degree and low power consumption. Specifically, the basic structure of the successive approximation analog-to-digital converter only includes a shift register, a comparator, and a capacitor array, and does not require a circuit for providing gain. Therefore, it can be applied in low-power Internet of Things fields such as sensors, portable devices, and biometric signal acquisition.

[0004] However, with the gradual reduction of the process size of electronic components in the prior art, the proportion of power consumption of digital circuits continues to decrease, while the power consumption of the successive approximation analog-to-digital converter of pure analog circuits is difficult to decrease with the progress of the process, resulting in a limitation of the applicable range of the successive approximation analog-to-digital converter. Summary of the Invention

[0005] To solve the deficiencies in the prior art, the present invention provides a capacitor array analog-to-digital converter with partitioned sleep and adjustable resolution and its method. By means of partitioned sleep, the energy consumption required by the capacitor units is reduced, the number of unit capacitors is decreased, and the overall power consumption of the analog-to-digital converter is reduced.

[0006] To achieve the above object, the specific solution adopted by the present invention is as follows:

[0007] A capacitor array analog-to-digital converter with partitioned sleep and adjustable resolution, comprising:

[0008] A positive-phase conversion capacitor array, including a positive-phase high-capacitance array and a positive-phase low-capacitance array;

[0009] A negative-phase conversion capacitor array, including a negative-phase high-capacitance array and a negative-phase low-capacitance array;

[0010] The positive-phase high-capacitance array, the positive-phase low-capacitance array, the negative-phase high-capacitance array, and the negative-phase low-capacitance array all include a plurality of capacitor units arranged in sequence, and a bridging switch is provided between two adjacent capacitor units;

[0011] Among multiple sequentially arranged capacitor units, the first capacitor unit includes two unit capacitors and an extended capacitor, and the two unit capacitors are in parallel and then in series with the extended capacitor. The capacitance value of the extended capacitor is twice that of the unit capacitor. The second capacitor unit includes one unit capacitor. Starting from the third capacitor unit, each subsequent capacitor unit includes all of the previous capacitor unit and a high-value capacitor with a capacitance value equal to the total capacitance value of the previous capacitor unit.

[0012] A sampling module for initially sampling the input signal from the top plates of all capacitor units;

[0013] A comparator for comparing the input signal or the states of the positive-phase conversion capacitor array and the negative-phase conversion capacitor array and outputting bit data;

[0014] A shift register for storing the bit data;

[0015] A state switching module for cooperating with the bridge switch to control the circuit connection states of all capacitor units. The circuit connection states include connection states and voltage states.

[0016] Preferably, the positive-phase high-capacitance array, the positive-phase low-capacitance array, the negative-phase high-capacitance array, and the negative-phase low-capacitance array all include N - 3 sequentially arranged capacitor units, where N is the number of bits of the analog-to-digital converter.

[0017] Preferably, the analog-to-digital converter further includes two power modules. The state switching module includes multiple state switching units, and the power modules are correspondingly connected to the capacitor units through the state switching units.

[0018] Preferably, the state switching unit includes multiple switching switches, and the switching switches are correspondingly connected to the capacitors in the capacitor units.

[0019] Preferably, the power module includes a ground terminal gnd, a reference voltage terminal V ref and a common-mode voltage terminal V cm .

[0020] A capacitance array analog-to-digital conversion method with partitioned sleep and adjustable resolution, based on the above capacitance array analog-to-digital converter with partitioned sleep and adjustable resolution, the method includes the following steps:

[0021] Using the sampling module to initially sample the input signal;

[0022] Making a first adjustment to the circuit connection states of all capacitor units, so that the first capacitor unit is connected to the comparator, and the comparator makes a first comparison of the input signal and outputs bit data D 0 ;

[0023] Based on D0 Make a second adjustment to the circuit connection state of the capacitor unit, change the voltage state of the first capacitor unit, and after the adjustment, perform a second comparison by the comparator and output the bit data D 1 ;

[0024] Based on D 1 Make a third adjustment to the voltage states of the capacitor units in the positive low-capacitance array and the negative low-capacitance array, and after the adjustment, perform a third comparison by the comparator and output the bit data D 2 ;

[0025] Based on D 0 、D 1 and D 2 Make a fourth adjustment to the circuit connection states of all the capacitor units, and after the adjustment, perform a fourth comparison by the comparator and output the bit data D 3 ;

[0026] Based on D 2 and D 3 Make a fifth adjustment to the circuit connection states of all the capacitor units, and after the adjustment, perform a fifth comparison by the comparator and output the bit data D 4 ;

[0027] Based on D 2 and D n-2 Make an nth adjustment to the circuit connection states of all the capacitor units, and after the adjustment, perform an nth comparison by the comparator and output the bit data D n-1 , until the bit data D N-1 is obtained, where N is the number of bits of the analog-to-digital converter.

[0028] Preferably, when the input signal is initially sampled by the sampling module, the voltage states of all the capacitor units in the positive high-capacitance array and the negative high-capacitance array are adjusted to V ref , and the voltage states of all the capacitor units in the positive low-capacitance array and the negative low-capacitance array are adjusted to gnd.

[0029] Preferably, the method for making the first adjustment to the circuit connection states of all the capacitor units includes:

[0030] Among the multiple capacitor units, use the state switching module to switch the connection states of all the capacitor units except the first capacitor unit to the disconnected state.

[0031] Preferably, the specific method for making the second adjustment to the circuit connection state of the capacitor unit based on D 0 includes:

[0032] If D 0= 1, use the state switching module to switch the connection state of the first capacitor unit in the positive low-capacitance array and the negative high-capacitance array to disconnected. If D 0 = 0, switch the connection state of the first capacitor unit in the positive high-capacitance array and the negative low-capacitance array to disconnected;

[0033] Adjust the voltage state of the first capacitor unit whose connection state remains connected to V cm .

[0034] Preferably, for each generated bit of data, store the bit of data into the shift register in sequence.

[0035] The present invention adopts the technology of capacitive array partitioned sleep, enabling the analog-to-digital converter to process the same input signal swing with only half of the power supply voltage. Therefore, the required energy consumption is greatly reduced, the number of unit capacitors is reduced, the switching scheme of the capacitive array is optimized, and the overall power consumption of the analog-to-digital converter is reduced;

[0036] For the analog-to-digital converter with N-bit resolution of the present invention, the required output resolution can be freely adjusted, that is, it can be adjusted within the range of 5 - N bits, with higher flexibility and a wider application range. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0038] Figure 1 is a schematic structural diagram of the analog-to-digital converter of the present invention;

[0039] Figure 2 is a schematic diagram of the first-stage voltage state switching method of the analog-to-digital conversion method of the present invention when the number of data bits is 6;

[0040] Figure 3 is a schematic diagram of the second-stage voltage state switching method of the analog-to-digital conversion method of the present invention when the number of data bits is 6;

[0041] Figure 4 is a schematic diagram of the third-stage voltage state switching method of the analog-to-digital conversion method of the present invention when the number of data bits is 6;

[0042] Figure 5 is a schematic diagram of the fourth-stage voltage state switching method of the analog-to-digital conversion method of the present invention when the number of data bits is 6;

[0043] Figure 6 It is the first - part schematic diagram of the voltage - state switching method in the fifth stage of the analog - to - digital conversion method of the present invention when the number of data bits is 6;

[0044] Figure 7 It is the second - part schematic diagram of the voltage - state switching method in the fifth stage of the analog - to - digital conversion method of the present invention when the number of data bits is 6;

[0045] Figure 8 It is the first - part schematic diagram of the voltage - state switching method in the sixth stage of the analog - to - digital conversion method of the present invention when the number of data bits is 6;

[0046] Figure 9 It is the second - part schematic diagram of the voltage - state switching method in the sixth stage of the analog - to - digital conversion method of the present invention when the number of data bits is 6;

[0047] Figure 10 It is the third - part schematic diagram of the voltage - state switching method in the sixth stage of the analog - to - digital conversion method of the present invention when the number of data bits is 6;

[0048] Figure 11 It is the fourth - part schematic diagram of the voltage - state switching method in the sixth stage of the analog - to - digital conversion method of the present invention when the number of data bits is 6. Detailed implementation manners

[0049] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0050] As Figure 1 shown, a partitioned - sleep adjustable - resolution capacitive - array analog - to - digital converter includes a total capacitive array, a sampling module, a comparator, a shift register, a state - switching module, and two power - supply modules, wherein the total capacitive array includes a positive - phase conversion capacitive array and an anti - phase conversion capacitive array.

[0051] The positive-phase conversion capacitor array includes a positive-phase high-capacitance array and a positive-phase low-capacitance array, and the negative-phase conversion capacitor array includes a negative-phase high-capacitance array and a negative-phase low-capacitance array. The positive-phase high-capacitance array, the positive-phase low-capacitance array, the negative-phase high-capacitance array, and the negative-phase low-capacitance array all include a plurality of sequentially arranged capacitor units, and a bridging switch is provided between two adjacent capacitor units. Among the plurality of sequentially arranged capacitor units, the first capacitor unit includes two unit capacitors and an extended capacitor, and the two unit capacitors are connected in parallel and then connected in series with the extended capacitor. The capacitance value of the extended capacitor is twice that of the unit capacitor. The second capacitor unit includes one unit capacitor. Starting from the third capacitor unit, each subsequent capacitor unit includes all of the previous capacitor unit and a high-value capacitor whose capacitance value is equal to the total capacitance value of the previous capacitor unit.

[0052] More specifically, the positive-phase high-capacitance array, the positive-phase low-capacitance array, the negative-phase high-capacitance array, and the negative-phase low-capacitance array all include N - 3 sequentially arranged capacitor units, where N is the number of bits of the analog-to-digital converter. Denote the capacitance value of the unit capacitor as C. Then the capacitance value of the extended capacitor in the first capacitor unit is 2C; the second capacitor unit includes one unit capacitor; the third capacitor unit includes two unit capacitors; the fourth capacitor unit includes two unit capacitors and a high-value capacitor with a capacitance value of 2C; the fifth capacitor unit includes two unit capacitors, a high-value capacitor with a capacitance value of 2C, and a high-value capacitor with a capacitance value of 4C, and so on. The capacitance composition of the (N - 3)-th capacitor unit can be expressed as C, C, 2C, … 2 N-6 C. For the convenience of distinction, in Figure 1 the capacitor units are marked as partitions, the high-capacitance array is marked as the high array, and the low-capacitance array is marked as the low array.

[0053] A sampling module for initially sampling the input signal from the top plates of all capacitor units.

[0054] A comparator for comparing the input signal or the states of the positive-phase conversion capacitor array and the negative-phase conversion capacitor array and outputting bit data.

[0055] A shift register for storing bit data.

[0056] Both power modules include a ground terminal gnd, a reference voltage terminal V ref and a common-mode voltage terminal V cm。The state switching module is used to cooperate with the bridging switch to control the circuit connection states of all capacitor units. The circuit connection states include the connection state and the voltage state. The state switching module includes a plurality of state switching units, and the power supply module is correspondingly connected to the capacitor units through the state switching units. The state switching unit includes a plurality of switching switches, and the switching switches are correspondingly connected to the capacitors in the capacitor units. By changing the states of the switching switches, the connection states between the capacitors and the power supply module can be changed. That is, by changing the states of the switching switches, the capacitors can be connected to the ground terminal GND, the reference voltage terminal V ref or the common-mode voltage terminal V cm connections. Among them, the connection state is connected or disconnected, and the voltage state is GND, V ref or V cm .

[0057] It should be noted that in the present invention, the specific structures and working principles of the sampling module, the comparator, and the shift register belong to the conventional technical means in the art and will not be elaborated here.

[0058] The present invention further provides a partitioned sleep adjustable-resolution capacitive array analog-to-digital conversion method. Based on the above-mentioned partitioned sleep adjustable-resolution capacitive array analog-to-digital converter, the method includes six stages, which are as follows.

[0059] In the first stage, the sampling module is used to perform an initial sampling on the input signal. When using the sampling module to perform an initial sampling on the input signal, all the bridging switches and switching switches are closed, and the input signal is sampled on the top plates of all the capacitors through the sampling module. Moreover, the voltage states of all the capacitor units in the positive high-capacitance array and the negative high-capacitance array are adjusted to V ref , and the voltage states of all the capacitor units in the positive low-capacitance array and the negative low-capacitance array are adjusted to GND.

[0060] After the sampling is completed, the circuit connection states of all the capacitor units are adjusted for the first time, so that the first capacitor unit is connected to the comparator, and the comparator performs the first comparison on the input signal and outputs the bit data D 0 . The method for adjusting the circuit connection states of all the capacitor units for the first time includes: among the plurality of capacitor units, the state switching module is used to switch the connection states of all the capacitor units except the first capacitor unit to the disconnected state. At this time, the disconnected capacitor units enter the sleep state, and only the first capacitor unit in each capacitor array remains in the connected state, so that the comparator can perform the first comparison without consuming switch energy and output the most significant bit data D 0 .

[0061] In the second stage, based on D 0The circuit connection state of the capacitor unit is adjusted for the second time to change the voltage state of the first capacitor unit, and after the adjustment, the comparator performs a second comparison and outputs the bit data D 1 . Based on D 0 The specific method for the second adjustment of the circuit connection state of the capacitor unit includes: if D 0 = 1, the state switching module is used to switch the connection state of the first capacitor unit in the positive-phase low-capacitance array and the negative-phase high-capacitance array to disconnected. If D 0 = 0, the connection state of the first capacitor unit in the positive-phase high-capacitance array and the negative-phase low-capacitance array is switched to disconnected; the voltage state of the first capacitor unit whose connection state remains connected is adjusted to V cm . After the voltage state adjustment is completed, the voltage of the first capacitor unit in the two high-capacitance arrays drops by V ref / 2, and the voltage of the first capacitor unit in the two low-capacitance arrays rises by V ref / 2, so the second comparison does not consume switching energy. Then the comparator performs the second comparison and outputs the second-highest significant bit data D 1 .

[0062] In the third stage, based on D 1 the voltage states of the capacitor units in the positive-phase low-capacitance array and the negative-phase low-capacitance array are adjusted for the third time, and after the adjustment, the comparator performs a third comparison and outputs the bit data D 2 . More specifically, in the third stage, according to the result of the previous comparison, the overall reference voltage connected to the two low-capacitance arrays switches from V cm to V ref , causing the voltage of the two high-capacitance arrays to rise by V ref / 2, so the third comparison does not consume switching energy. And, in the subsequent comparison stage, the capacitor arrays changed this time will remain unchanged, and only the voltage states of the remaining capacitor arrays are adjusted to achieve the successive approximation effect. Then the comparator performs the third comparison and outputs the significant bit data D 2 .

[0063] In the fourth stage, based on D 0 , D 1 and D 2 the circuit connection states of all capacitor units are adjusted for the fourth time, and after the adjustment, the comparator performs a fourth comparison and outputs the bit data D 3 . More specifically, in the fourth stage, if D 0 D 1 = 11, the subsequent comparison stage is completed by switching the voltage state of the positive-phase high-capacitance array of the positive-phase conversion capacitor array for successive approximation; if D 0 D 1If D = 10, it is completed by the inverting low - capacitance array of the inverting conversion capacitor array; if D 0 D 1 = 01, it is completed by the inverting high - capacitance array of the inverting conversion capacitor array; if D 0 D 1 = 00, it is completed by the non - inverting low - capacitance array of the non - inverting conversion capacitor array. If D 2 = 1, the voltage state of the capacitance of the first capacitor unit in the non - inverting conversion capacitor array is switched from V cm to gnd, or the voltage state of the capacitance of the first capacitor unit in the inverting conversion capacitor array is switched from V cm to V ref ; if D 2 = 0, the operation is opposite, that is, the voltage state of the capacitance of the first capacitor unit in the inverting conversion capacitor array is switched from V cm to V ref , or the voltage state of the capacitance of the first capacitor unit in the non - inverting conversion capacitor array is switched from V cm to gnd. Then the fourth comparison is performed and the valid - bit data D 3 is output.

[0064] In the fourth stage, the switching energy consumption of the total capacitance array is:

[0065] .

[0066] In the fifth stage, based on D 2 and D 3 , the circuit connection states of all capacitor units are adjusted for the fifth time, and after the adjustment, the fifth comparison is performed by the comparator and the bit data D 4 is output. More specifically, in the fifth stage, when the data D 2 D 3 output by the previous two comparisons are the same and both are 11, if the non - inverting conversion capacitor array is used, the voltage unit of the capacitance of the second capacitor unit is switched to gnd, if the inverting conversion capacitor array is used, the voltage unit of the capacitance of the second capacitor unit is switched to V ref ; when D 2 D 3 = 00, if the non - inverting conversion capacitor array is used, the voltage unit of the capacitance of the second capacitor unit is switched to Vref, if the inverting conversion capacitor array is used, the voltage unit of the capacitance of the second capacitor unit is switched to gnd. If D 2 D 3 are different, the voltage states of the capacitances of all the second capacitor units are switched to V cmThis voltage switching will also affect the switching selection of the reference voltage connected to one of the unit capacitors C in the subsequent third capacitor unit. After the voltage state switching is completed, close the bridging switch of the second capacitor unit to reconnect the second capacitor unit to the circuit, change the voltage state, and then perform the fifth comparison and output the valid bit data D 4 。

[0067] In the fifth stage, the switching energy consumption of the total capacitor array is:

[0068] 。

[0069] In the sixth stage, based on D 2 and D n-2 perform the nth adjustment on the circuit connection states of all capacitor units, and after the adjustment, perform the nth comparison by the comparator and output the bit data D n-1 , until the bit data D N-1 is obtained, where N is the number of bits of the analog-to-digital converter. After the fifth comparison, the subsequent comparison conditions are similar to those of the fifth comparison. If the compared output data D 2 D N-2 are the same and are 11, if a positive-phase conversion capacitor array is used, the voltage state of the minimum capacitance of the (N - 3)th capacitor unit is switched to gnd; if an inverting-phase conversion capacitor array is used, the voltage state is switched to V ref ; when D 2 D N-2 = 00, if a positive-phase conversion capacitor array is used, the voltage state is switched to V ref , if an inverting-phase conversion capacitor array is used, the voltage state is switched to gnd. If D 2 D N-2 are different, the voltage state of the minimum capacitance of the (N - 3)th capacitor unit is switched to V cm . The remaining capacitors correspond to the results of the previous comparison and switch to the same voltage state. After the voltage state switching is completed, close the bridging switch of the used partition to reconnect the capacitor units in the partition to the circuit, change the voltage state, and then perform the Nth comparison and output the valid bit data D N-1 。

[0070] Furthermore, in each stage, the switching process of the capacitor voltage state is shown in Table 1.

[0071] Table 1 Summary Table of Voltage State Switching Methods

[0072]

[0073] The sixth stage needs to be carried out until the selected resolution (5 - N bits) is completed, that is, the 5 - Nth comparison is completed. During the whole process, every time a bit of data is generated, the bit data is stored into the shift register in sequence. The average switching energy consumption corresponding to each bit resolution of the total capacitance array is:

[0074] 。

[0075] In a specific embodiment of the present invention, the number of data bits of the analog - to - digital converter is set to 6. Then, in the sixth comparison, the switching energy consumption of the total capacitance array is:

[0076] 。

[0077] In this embodiment, the average switching energy consumption of the total capacitance array is:

[0078] 。

[0079] In this embodiment, the method of switching the voltage state in each stage is as Figures 2 - 11 shown.

[0080] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0081] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A partitioned dormant capacitor array analog-to-digital converter with adjustable resolution, characterized in that: include: A positive phase conversion capacitor array, including a positive phase high capacitance array and a positive phase low capacitance array; An inverting conversion capacitor array, including an inverting high capacitance array and an inverting low capacitance array; The positive phase high capacitance array, the positive phase low capacitance array, the negative phase high capacitance array and the negative phase low capacitance array all include a plurality of capacitance units arranged in sequence, and a bridge switch is provided between two adjacent capacitance units; Among the plurality of capacitor units arranged in sequence, the first capacitor unit includes two unit capacitors and one extended capacitor, and the two unit capacitors are connected in parallel and in series with the extended capacitor, and the capacitance of the extended capacitor is twice that of the unit capacitor, the second capacitor unit includes one unit capacitor, and starting from the third capacitor unit, the subsequent capacitor unit includes the entirety of the previous capacitor unit and a high-value capacitor whose capacitance is equal to the total capacitance of the previous capacitor unit; A sampling module, used for initially sampling input signals from the top plates of all capacitor units; A comparator, used to compare the input signal or the state of the positive phase conversion capacitor array and the negative phase conversion capacitor array and output bit data; Shift registers, used to store bit data; The state switching module is used to cooperate with the bridge switch to control the circuit connection state of all capacitor units, and the circuit connection state includes a connection state and a voltage state.

2. The partitioned dormant capacitor array analog-to-digital converter with adjustable resolution as claimed in claim 1, characterized in that: The positive phase high capacitance array, the positive phase low capacitance array, the negative phase high capacitance array and the negative phase low capacitance array each include N-3 capacitance units arranged in sequence, wherein N is the number of bits of the analog-to-digital converter.

3. The partitioned dormant capacitor array analog-to-digital converter with adjustable resolution as claimed in claim 1, characterized in that: The analog-to-digital converter further includes two power supply modules, the state switching module includes a plurality of state switching units, and the power supply modules are correspondingly connected to the capacitor units via the state switching units.

4. The partitioned dormant capacitor array analog-to-digital converter with adjustable resolution as claimed in claim 3, characterized in that: The state switching unit includes a plurality of switching switches, and the switching switches are correspondingly connected to the capacitors in the capacitor unit.

5. The partitioned dormant capacitor array analog-to-digital converter with adjustable resolution as claimed in claim 3, characterized in that: The power supply module includes a ground terminal gnd, a reference voltage terminal V ref and common mode voltage terminal V cm .

6. A partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution, based on the partitioned dormant capacitor array analog-to-digital converter with adjustable resolution as claimed in any one of claims 1 to 5, characterized in that: The method comprises the following steps: Using the sampling module to perform initial sampling on the input signal; The circuit connection states of all the capacitor units are adjusted for the first time, so that the first capacitor unit is connected to the comparator, and the comparator performs a first comparison on the input signal and outputs the bit data D0; Based on D0, the circuit connection state of the capacitor unit is adjusted for the second time, the voltage state of the first capacitor unit is changed, and after the adjustment, the comparator performs a second comparison and outputs the bit data D1; Based on D1, the voltage states of the capacitor units in the positive phase low capacitance array and the negative phase low capacitance array are adjusted for the third time, and after the adjustment, the comparator performs a third comparison and outputs the bit data D2; The circuit connection states of all the capacitor units are adjusted for the fourth time based on D0, D1 and D2, and after the adjustment, the comparator performs the fourth comparison and outputs the bit data D3; The circuit connection states of all the capacitor units are adjusted for the fifth time based on D2 and D3, and after the adjustment, the comparator performs the fifth comparison and outputs the bit data D4; Based on D2 and D n-2 The circuit connection state of all capacitor units is adjusted for the nth time, and after the adjustment, the comparator performs the nth comparison and outputs the bit data D n-1 , until the bit data D is obtained N-1 , where N is the number of bits of the analog-to-digital converter.

7. The partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution as claimed in claim 6, characterized in that: When the sampling module is used to perform initial sampling on the input signal, the voltage state of all the capacitor units in the positive phase high capacitor array and the negative phase high capacitor array is adjusted to Vref, and the voltage state of all the capacitor units in the positive phase low capacitor array and the negative phase low capacitor array is adjusted to gnd.

8. The partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution as claimed in claim 6, characterized in that: The method for first adjusting the circuit connection status of all the capacitor units includes: Among the plurality of capacitor units, the state switching module is used to switch the connection states of all capacitor units except the first capacitor unit to disconnected.

9. The partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution as claimed in claim 8, characterized in that: The specific method of performing a second adjustment on the circuit connection state of the capacitor unit based on D0 includes: If D0=1, the state switching module is used to switch the connection state of the first capacitor unit in the positive phase low capacitor array and the negative phase high capacitor array to disconnection; if D0=0, the connection state of the first capacitor unit in the positive phase high capacitor array and the negative phase low capacitor array is switched to disconnection; The connection state is maintained as the voltage state of the first capacitor unit connected is adjusted to V cm 9.

10. The partitioned dormant capacitor array analog-to-digital conversion method with adjustable resolution as claimed in claim 6, characterized in that: Each time a bit of data is generated, the bit of data is sequentially stored in the shift register.

Images