A method and device for controlling clock phase synchronization

Abstract

The present invention discloses a method and device for controlling clock phase synchronization. This application receives a 12.288 MHz first clock signal from a DSP host and sends it to a clock generation chip to generate MCLK, BCLK, and LRCK clock signals. By controlling the clock generation chip, this application adjusts the phase difference between these clock signals until it falls within a preset error range, ensuring signal synchronization and addressing the difficulty of clock phase synchronization in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of clock phase synchronization control, and in particular to a clock phase synchronization control method and device. Background Art

[0002] In modern audio processing systems, such as audio processors and conference hosts, the I2S (Inter-IC Sound) bus is widely used to transmit multi-channel audio data. I2S provides a simple and efficient way to transmit audio signals, especially between digital audio devices. However, existing I2S transmission systems have some inherent limitations, particularly regarding processing timing alignment.

[0003] First, the I2S bus was not originally designed to include a complex timing calibration scheme. This means that when using I2S for audio transmission, the system relies primarily on the hardware's own clock signal to synchronize the data stream. While this purely hardware-based approach is simple, its limitations begin to become apparent when used in complex environments. The I2S standard bus itself does not support calibration of the clock signal's phase offset. Ideally, data and clock signals should be perfectly synchronized to ensure accurate data transmission and reception. However, in real-world applications, the clock signal's phase may shift due to various factors, such as performance variations in electronic components, temperature fluctuations, and power supply fluctuations.

[0004] Furthermore, the problem is exacerbated when the system is overloaded or when audio data needs to be transmitted over long traces. This is because as trace length increases, signal transmission delay also increases, which can further deteriorate the synchronization between data and clock. In extreme cases, this asynchrony can cause data errors or even produce noise in the audio output. In other words, clock phase synchronization is difficult in existing technologies. Summary of the Invention

[0005] The present invention provides a method and device for controlling clock phase synchronization, so as to solve the problem in the prior art that clock phase synchronization is difficult.

[0006] In a first aspect, the present application provides a method for controlling clock phase synchronization, comprising:

[0007] Receive a first clock signal from a DSP host;

[0008] Sending the first clock signal to a clock production chip, so that the clock production chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal;

[0009] The clock production chip is controlled so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal until the phase difference is within a preset error range, and the adjustment is stopped to obtain the first phase, the second phase and the third phase.

[0010] The present application ensures the initial synchronization of the clock signal by receiving the first clock signal provided by the DSP host and sending the signal to the clock production chip. Subsequently, the MCLK clock signal, BCLK clock signal and LRCK clock signal generated by the clock production chip correspond to different audio transmission channels respectively. The phase difference of these signals is adjusted until it reaches a preset error range. This process is achieved by controlling the phase relationship of each clock signal. This adjustment ensures that the clock signals of all channels can be synchronized with the original first clock signal, thereby reducing audio distortion and noise caused by phase deviation. When the adjustment stops and the first phase, second phase and third phase are obtained, the present application has achieved a highly synchronized clock signal. The method of the present application significantly improves the accuracy and reliability of audio data transmission, optimizes the overall performance of the audio processing system, and solves the problem of difficult clock phase synchronization in the prior art.

[0011] As a preferred embodiment of the first aspect, the clock production chip is controlled so that the clock production chip adjusts the phase difference between the MCLK clock signal, the BCLK clock signal, and the LRCK clock signal until the phase difference is within a preset error range, specifically:

[0012] According to the time domain waveform diagram, the clock production chip is controlled so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal until the phase difference is within a preset error range.

[0013] The clock production chip is controlled according to the time domain waveform diagram so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal, specifically:

[0014] The time domain waveform is displayed on an oscilloscope;

[0015] The clock production chip is connected to an oscilloscope;

[0016] The first input interface of the oscilloscope is connected to the pin of the MCLK clock signal, the second input interface of the oscilloscope is connected to the pin of the BCLK clock signal, and the third input interface of the oscilloscope is connected to the pin of the LRCK clock signal.

[0017] In this preferred embodiment, the present application connects the clock production chip to an oscilloscope, and respectively connects the input interface of the oscilloscope to the MCLK clock signal, the BCLK clock signal, and the LRCK clock signal, and uses the oscilloscope to accurately measure and display the time domain waveforms of these clock signals. By visually comparing the phase difference of these clock signals on the oscilloscope, the present application can observe and manually or automatically adjust these signals in real time until their phase difference reaches a preset error range. This phase adjustment process ensures that the clock signals of different channels can be synchronized, thereby reducing audio data transmission errors and distortion caused by clock asynchrony. Ultimately, this not only improves the transmission quality of the audio signal, but also enhances the stability and reliability of the system, providing users with clearer and more accurate audio output.

[0018] As a preferred embodiment of the first aspect, sending the first clock signal to a clock production chip so that the clock production chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal is specifically as follows:

[0019] The MCLK clock signal is a first clock signal with a doubled frequency, the BCLK clock signal is a first clock signal with a singled frequency, and the LRCK clock signal is a first clock signal with a divided frequency of 256.

[0020] In this preferred embodiment, the present application sends a first clock signal to a clock production chip, and specifically generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal, wherein the MCLK clock signal is twice the frequency of the first clock signal, the BCLK clock signal is once the frequency of the first clock signal, and the LRCK clock signal is 256 times the frequency of the first clock signal. This method can provide clock signals of different frequencies for the audio processing system to meet the needs of different components and transmission channels. The generation of such multi-frequency clock signals ensures the flexibility and adaptability of the system when processing different sampling rates and data streams. Since the frequency of the clock signal is directly related to the processing and transmission of audio data, this precise frequency control helps to improve the accuracy of data synchronization and reduce clock deviations and data transmission errors caused by frequency mismatch. Ultimately, this will improve the transmission quality of the audio signal, reduce distortion and noise, and enhance the overall performance of the system and the user's listening experience.

[0021] As a preferred embodiment of the first aspect, sending the first clock signal to a clock production chip so that the clock production chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal further includes:

[0022] The MCLK clock signal, the BCLK clock signal and the LRCK clock signal are connected to the first slave, the second slave, the third slave and the fourth slave respectively;

[0023] The MCLK clock signal, the BCLK clock signal and the LRCK clock signal directly drive the first slave, the second slave, the third slave and the fourth slave respectively.

[0024] In this preferred embodiment, the present application provides a first clock signal to a clock production chip and generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal. These signals are respectively connected to the first slave, the second slave, the third slave, and the fourth slave, and directly drive these slaves. The present application realizes precise clock synchronization of multiple slave devices in the audio transmission system. This direct connection and driving method ensures that the slave device can receive a stable and synchronous clock signal, thereby maintaining data consistency and synchronization during multi-channel audio transmission. Since the clock signal is the key to ensuring data integrity and accuracy in digital audio transmission, the present application reduces the audio distortion and noise caused by clock asynchrony by reducing the clock deviation during the transmission process. In addition, directly driving the slave device also improves the response speed and processing efficiency of the system, thereby optimizing the overall performance of the audio processing system and providing users with clearer and more synchronized audio output.

[0025] In a second aspect, the present application provides a clock phase synchronization control device. The clock phase synchronization control device includes a receiving module, a sending module, and an adjusting module;

[0026] The receiving module is used to receive the first clock signal of the DSP host;

[0027] The sending module is used to send the first clock signal to the clock production chip, so that the clock production chip generates an MCLK clock signal, a BCLK clock signal and an LRCK clock signal;

[0028] The adjustment module controls the clock production chip so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal until the phase difference is within a preset error range, stops adjusting, and obtains the first phase, the second phase and the third phase.

[0029] This device uses three modules to divide the work and coordinate work to better achieve the synchronization of clock phases. This application ensures the initial synchronization of the clock signal by receiving the first clock signal provided by the DSP host and sending the signal to the clock production chip. Subsequently, the MCLK clock signal, BCLK clock signal and LRCK clock signal generated by the clock production chip correspond to different audio transmission channels. The phase difference of these signals is adjusted until it reaches the preset error range. This process is achieved by controlling the phase relationship of each clock signal. This adjustment ensures that the clock signals of all channels can be synchronized with the original first clock signal, thereby reducing audio distortion and noise caused by phase deviation. When the adjustment stops and the first phase, second phase and third phase are obtained, the application has achieved a highly synchronized clock signal. The method of the application significantly improves the accuracy and reliability of audio data transmission, optimizes the overall performance of the audio processing system, and solves the problem of difficult clock phase synchronization in the prior art.

[0030] As a preferred embodiment of the second aspect, the clock production chip is controlled so that the clock production chip adjusts the phase difference between the MCLK clock signal, the BCLK clock signal, and the LRCK clock signal until the phase difference is within a preset error range, specifically:

[0031] According to the time domain waveform diagram, the clock production chip is controlled so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal until the phase difference is within a preset error range.

[0032] The clock production chip is controlled according to the time domain waveform diagram so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal, specifically:

[0033] The time domain waveform is displayed on an oscilloscope;

[0034] The clock production chip is connected to an oscilloscope;

[0035] The first input interface of the oscilloscope is connected to the pin of the MCLK clock signal, the second input interface of the oscilloscope is connected to the pin of the BCLK clock signal, and the third input interface of the oscilloscope is connected to the pin of the LRCK clock signal.

[0036] In this preferred embodiment, the present application connects the clock production chip to an oscilloscope, and respectively connects the input interface of the oscilloscope to the MCLK clock signal, the BCLK clock signal, and the LRCK clock signal, and uses the oscilloscope to accurately measure and display the time domain waveforms of these clock signals. By visually comparing the phase difference of these clock signals on the oscilloscope, the present application can observe and manually or automatically adjust these signals in real time until their phase difference reaches a preset error range. This phase adjustment process ensures that the clock signals of different channels can be synchronized, thereby reducing audio data transmission errors and distortion caused by clock asynchrony. Ultimately, this not only improves the transmission quality of the audio signal, but also enhances the stability and reliability of the system, providing users with clearer and more accurate audio output.

[0037] As a preferred embodiment of the second aspect, sending the first clock signal to a clock production chip so that the clock production chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal is specifically as follows:

[0038] The MCLK clock signal is a first clock signal with a doubled frequency, the BCLK clock signal is a first clock signal with a singled frequency, and the LRCK clock signal is a first clock signal with a divided frequency of 256.

[0039] In this preferred embodiment, the present application sends a first clock signal to a clock production chip, and specifically generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal, wherein the MCLK clock signal is twice the frequency of the first clock signal, the BCLK clock signal is once the frequency of the first clock signal, and the LRCK clock signal is 256 times the frequency of the first clock signal. This method can provide clock signals of different frequencies for the audio processing system to meet the needs of different components and transmission channels. The generation of such multi-frequency clock signals ensures the flexibility and adaptability of the system when processing different sampling rates and data streams. Since the frequency of the clock signal is directly related to the processing and transmission of audio data, this precise frequency control helps to improve the accuracy of data synchronization and reduce clock deviations and data transmission errors caused by frequency mismatch. Ultimately, this will improve the transmission quality of the audio signal, reduce distortion and noise, and enhance the overall performance of the system and the user's listening experience.

[0040] As a preferred embodiment of the second aspect, sending the first clock signal to a clock production chip so that the clock production chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal further includes:

[0041] The MCLK clock signal, the BCLK clock signal and the LRCK clock signal are connected to the first slave, the second slave, the third slave and the fourth slave respectively;

[0042] The MCLK clock signal, the BCLK clock signal and the LRCK clock signal directly drive the first slave, the second slave, the third slave and the fourth slave respectively.

[0043] In this preferred embodiment, the present application provides a first clock signal to a clock production chip and generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal. These signals are respectively connected to the first slave, the second slave, the third slave, and the fourth slave, and directly drive these slaves. The present application realizes precise clock synchronization of multiple slave devices in the audio transmission system. This direct connection and driving method ensures that the slave device can receive a stable and synchronous clock signal, thereby maintaining data consistency and synchronization during multi-channel audio transmission. Since the clock signal is the key to ensuring data integrity and accuracy in digital audio transmission, the present application reduces the audio distortion and noise caused by clock asynchrony by reducing the clock deviation during the transmission process. In addition, directly driving the slave device also improves the response speed and processing efficiency of the system, thereby optimizing the overall performance of the audio processing system and providing users with clearer and more synchronized audio output. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 : A flowchart of an embodiment of a clock phase synchronization control method provided by the present application;

[0045] Figure 2 : A structural diagram of an embodiment of a hardware structural connection for clock phase synchronization provided by the present application;

[0046] Figure 3 : A structural diagram of an embodiment of a clock phase synchronization control device provided in this application. DETAILED DESCRIPTION

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0048] Example 1

[0049] Please refer to Figure 1 , which is a clock phase synchronization control method provided by an embodiment of the present invention.

[0050] In this embodiment, the process of the clock phase synchronization control method in this application is described in detail through steps S01-S03.

[0051] like Figure 2 As shown, Figure 2 This is a schematic diagram of the connection structure of the hardware used in this application. The hardware used in this application includes a DSP (I 2S host), an oscillator crystal source, a clock generation chip, a main control chip, an I 2S slave 1 (ADC1), an I 2S slave 2 (ADC2), an I 2S slave 3 (DAC1), an I 2S slave 4 (DAC2), an analog audio input interface 1, an analog audio input interface 2, an analog audio output interface 1, and an analog audio output interface 2.

[0052] The signal flow in the hardware connection structure diagram is: analog audio input interface 1, analog audio input interface 2 ---> ADC1, ADC2 --> DSP --> DAC1, DAC2 --> analog output interface 1, analog output interface 2.

[0053] S01: Receive the first clock signal from the DSP host.

[0054] As a preferred embodiment of the first embodiment, the first clock signal of the DSP host is received as follows:

[0055] The main control chip receives the first clock signal from the DSP host, a process that is a key step in ensuring the synchronization of the entire audio system. This first clock signal has a frequency of 12.288MHz. This specific frequency was selected to meet the specific clock frequency requirements of the audio processing system. Specifically, this clock signal is generated by dividing the 24MHz clock provided by an external active crystal oscillator through the internal allocation register of the DSP (acting as the I2S host). This frequency division process not only ensures the stability and accuracy of the clock signal, but also allows the system to flexibly adjust the clock frequency according to different audio processing requirements.

[0056] The DSP host provides the divided 12.288MHz clock signal to the main control chip, which then controls the clock generation chip to further distribute and manage this clock signal. In this way, the main control chip can effectively control the clock synchronization of the entire audio system, ensuring the accuracy and reliability of audio data transmission. In addition, the main control chip's ability to control the clock generation chip enables the system to flexibly adapt to different operating conditions and load changes, further improving system stability and audio transmission quality.

[0057] Through this precise clock signal management and distribution mechanism, the audio processing system can achieve efficient data synchronization, reduce audio distortion and noise caused by clock deviation, and thus provide users with high-quality audio output. The application of this mechanism significantly improves the overall performance of the audio processing system and ensures that the clarity and accuracy of the audio signal can be maintained in various complex environments.

[0058] S02: Send the first clock signal to a clock generation chip, so that the clock generation chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal.

[0059] As a preferred embodiment of the first embodiment, the sending of the first clock signal to the clock production chip so that the clock production chip generates the MCLK clock signal, the BCLK clock signal and the LRCK clock signal is specifically as follows:

[0060] The clock generation chip is responsible for generating three key clock signals: MCLK (master clock), BCLK (bit clock), and LRCK (frame clock). These signals are essential for audio data synchronization in the I2S communication protocol. These three newly generated clock signals directly drive ADC1 and ADC2 (as I2S slaves 1 and 2) for analog-to-digital conversion, and DAC1 and DAC2 (as I2S slaves 3 and 4) for digital-to-analog conversion. This direct drive method ensures the timing accuracy and synchronization of audio signals during the conversion process, thereby improving the quality and reliability of audio data transmission.

[0061] The clock generation chip is capable of finely adjusting the phase difference between the three clock signals it generates, enabling the system to adapt to a variety of complex audio transmission environments and conditions. Specifically, the clock generation chip can adjust 128 different steps, each with an accuracy of 333 picoseconds (ps), providing the system with extremely high flexibility in clock synchronization. In practical applications, this fine adjustment capability allows the system to be optimized for specific transmission requirements and environmental changes, thereby ensuring stable audio signal transmission.

[0062] When the system detects output noise or distortion, the main control chip intervenes and adjusts the phase difference between the three clock signals, MCLK, BCLK, and LRCK, generated by the clock generation chip. By precisely adjusting the phase of these clock signals, the main control chip eliminates audio distortion and noise caused by phase deviation, restoring audio clarity and accuracy. This adjustment process can be automatic or manual, depending on the system design and user needs.

[0063] Through this clock phase adjustment mechanism, the present application not only provides high-quality audio output, but also maintains stable performance in the face of various challenges and interference. The application of this mechanism significantly improves the overall performance of the audio processing system and the user's listening experience, ensuring that the clarity and accuracy of the audio signal can be maintained in various complex environments.

[0064] S03: Controlling the clock production chip so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal, and the LRCK clock signal until the phase difference is within a preset error range, stopping the adjustment, and obtaining a first phase, a second phase, and a third phase.

[0065] As a preferred embodiment of the first embodiment, the clock production chip is controlled so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal, and the LRCK clock signal until the phase difference is within a preset error range, and then stops adjusting to obtain the first phase, the second phase, and the third phase, specifically:

[0066] In audio processing systems, ensuring precise clock signal synchronization is crucial for maintaining high-quality audio transmission. To achieve this, the system uses an oscilloscope to monitor and analyze the time domain waveforms of the three key clock signals: MCLK, BCLK, and LRCK, generated by the clock generation chip.

[0067] The oscilloscope's analog input 1 is connected to the MCLK pin of the clock generation chip to detect and display the time domain waveform of the MCLK clock signal. As the master clock signal, MCLK is typically used to synchronize audio sampling, and its stability has a crucial impact on the synchronization of the entire system.

[0068] Analog input interface 2 is connected to the BCLK pin and is used to detect and display the time domain waveform of the BCLK clock signal. As the bit clock, BCLK controls the bit rate of data transmission, and its accuracy directly affects the accuracy of data transmission.

[0069] Analog input interface 3 is connected to the LRCK pin to detect and display the time domain waveform of the LRCK clock signal. LRCK, as the frame clock, distinguishes left and right channel sampling and is crucial for maintaining stereo audio consistency.

[0070] An oscilloscope monitor allows for intuitive comparison of the phases of these three clock signals in the time domain. If the phase difference exceeds a preset tolerance, the master control chip intervenes and adjusts the clock generation chip to fine-tune the phase difference between MCLK, BCLK, and LRCK. This adjustment can be accomplished through an automatic control algorithm or manual adjustment, depending on the system design and operational convenience.

[0071] By precisely adjusting the phase differences between these three clock signals until they are within the error range, the system ensures the synchronization of audio data during transmission, thereby reducing or eliminating the noise and distortion caused by clock asynchrony. This precise clock phase control mechanism significantly improves the overall performance of the audio processing system, ensuring high-quality audio output and providing users with a clear and pure listening experience.

[0072] The present application ensures the initial synchronization of the clock signal by receiving the first clock signal provided by the DSP host and sending the signal to the clock production chip. Subsequently, the MCLK clock signal, BCLK clock signal and LRCK clock signal generated by the clock production chip correspond to different audio transmission channels respectively. The phase difference of these signals is adjusted until it reaches a preset error range. This process is achieved by controlling the phase relationship of each clock signal. This adjustment ensures that the clock signals of all channels can be synchronized with the original first clock signal, thereby reducing audio distortion and noise caused by phase deviation. When the adjustment stops and the first phase, second phase and third phase are obtained, the present application has achieved a highly synchronized clock signal. The method of the present application significantly improves the accuracy and reliability of audio data transmission, optimizes the overall performance of the audio processing system, and solves the problem of difficult clock phase synchronization in the prior art.

[0073] Example 2

[0074] Please refer to Figure 3 , is a clock phase synchronization control device provided in an embodiment of the present application.

[0075] In this embodiment, the control device for clock phase synchronization includes a receiving module 10 , a sending module 20 and an adjusting module 30 .

[0076] like Figure 2 As shown, Figure 2 This is a schematic diagram of the connection structure of the hardware used in this application. The hardware used in this application includes a DSP (I 2S host), an oscillator crystal source, a clock generation chip, a main control chip, an I 2S slave 1 (ADC1), an I 2S slave 2 (ADC2), an I 2S slave 3 (DAC1), an I 2S slave 4 (DAC2), an analog audio input interface 1, an analog audio input interface 2, an analog audio output interface 1, and an analog audio output interface 2.

[0077] The signal flow in the hardware connection structure diagram is: analog audio input interface 1, analog audio input interface 2 ---> ADC1, ADC2 --> DSP --> DAC1, DAC2 --> analog output interface 1, analog output interface 2.

[0078] The receiving module 10 is used to receive a first clock signal from the DSP host.

[0079] As a preferred embodiment of the first embodiment, the first clock signal of the DSP host is received as follows:

[0080] The main control chip receives the first clock signal from the DSP host, a process that is a key step in ensuring the synchronization of the entire audio system. This first clock signal has a frequency of 12.288MHz. This specific frequency was selected to meet the specific clock frequency requirements of the audio processing system. Specifically, this clock signal is generated by dividing the 24MHz clock provided by an external active crystal oscillator through the internal allocation register of the DSP (acting as the I2S host). This frequency division process not only ensures the stability and accuracy of the clock signal, but also allows the system to flexibly adjust the clock frequency according to different audio processing requirements.

[0081] The DSP host provides the divided 12.288MHz clock signal to the main control chip, which then controls the clock generation chip to further distribute and manage this clock signal. In this way, the main control chip can effectively control the clock synchronization of the entire audio system, ensuring the accuracy and reliability of audio data transmission. In addition, the main control chip's ability to control the clock generation chip enables the system to flexibly adapt to different operating conditions and load changes, further improving system stability and audio transmission quality.

[0082] Through this precise clock signal management and distribution mechanism, the audio processing system can achieve efficient data synchronization, reduce audio distortion and noise caused by clock deviation, and thus provide users with high-quality audio output. The application of this mechanism significantly improves the overall performance of the audio processing system and ensures that the clarity and accuracy of the audio signal can be maintained in various complex environments.

[0083] The sending module 20 is configured to send the first clock signal to a clock generation chip, so that the clock generation chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal.

[0084] As a preferred embodiment of the first embodiment, the sending of the first clock signal to the clock production chip so that the clock production chip generates the MCLK clock signal, the BCLK clock signal and the LRCK clock signal is specifically as follows:

[0085] The clock generation chip is responsible for generating three key clock signals: MCLK (master clock), BCLK (bit clock), and LRCK (frame clock). These signals are essential for audio data synchronization in the I2S communication protocol. These three newly generated clock signals directly drive ADC1 and ADC2 (as I2S slaves 1 and 2) for analog-to-digital conversion, and DAC1 and DAC2 (as I2S slaves 3 and 4) for digital-to-analog conversion. This direct drive method ensures the timing accuracy and synchronization of audio signals during the conversion process, thereby improving the quality and reliability of audio data transmission.

[0086] The clock generation chip is capable of finely adjusting the phase difference between the three clock signals it generates, enabling the system to adapt to a variety of complex audio transmission environments and conditions. Specifically, the clock generation chip can adjust 128 different steps, each with an accuracy of 333 picoseconds (ps), providing the system with extremely high flexibility in clock synchronization. In practical applications, this fine adjustment capability allows the system to be optimized for specific transmission requirements and environmental changes, thereby ensuring stable audio signal transmission.

[0087] When the system detects output noise or distortion, the main control chip intervenes and adjusts the phase difference between the three clock signals, MCLK, BCLK, and LRCK, generated by the clock generation chip. By precisely adjusting the phase of these clock signals, the main control chip eliminates audio distortion and noise caused by phase deviation, restoring audio clarity and accuracy. This adjustment process can be automatic or manual, depending on the system design and user needs.

[0088] Through this clock phase adjustment mechanism, the present application not only provides high-quality audio output, but also maintains stable performance in the face of various challenges and interference. The application of this mechanism significantly improves the overall performance of the audio processing system and the user's listening experience, ensuring that the clarity and accuracy of the audio signal can be maintained in various complex environments.

[0089] The adjustment module 30 is used to control the clock production chip so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal until the phase difference is within a preset error range, stops adjusting, and obtains the first phase, the second phase and the third phase.

[0090] As a preferred embodiment of the first embodiment, the clock production chip is controlled so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal, and the LRCK clock signal until the phase difference is within a preset error range, and then stops adjusting to obtain the first phase, the second phase, and the third phase, specifically:

[0091] In audio processing systems, ensuring precise clock signal synchronization is crucial for maintaining high-quality audio transmission. To achieve this, the system uses an oscilloscope to monitor and analyze the time domain waveforms of the three key clock signals: MCLK, BCLK, and LRCK, generated by the clock generation chip.

[0092] The oscilloscope's analog input 1 is connected to the MCLK pin of the clock generation chip to detect and display the time domain waveform of the MCLK clock signal. As the master clock signal, MCLK is typically used to synchronize audio sampling, and its stability has a crucial impact on the synchronization of the entire system.

[0093] Analog input interface 2 is connected to the BCLK pin and is used to detect and display the time domain waveform of the BCLK clock signal. As the bit clock, BCLK controls the bit rate of data transmission, and its accuracy directly affects the accuracy of data transmission.

[0094] Analog input interface 3 is connected to the LRCK pin to detect and display the time domain waveform of the LRCK clock signal. LRCK, as the frame clock, distinguishes left and right channel sampling and is crucial for maintaining stereo audio consistency.

[0095] An oscilloscope monitor allows for intuitive comparison of the phases of these three clock signals in the time domain. If the phase difference exceeds a preset tolerance, the master control chip intervenes and adjusts the clock generation chip to fine-tune the phase difference between MCLK, BCLK, and LRCK. This adjustment can be accomplished through an automatic control algorithm or manual adjustment, depending on the system design and operational convenience.

[0096] By precisely adjusting the phase differences between these three clock signals until they are within the error range, the system ensures the synchronization of audio data during transmission, thereby reducing or eliminating the noise and distortion caused by clock asynchrony. This precise clock phase control mechanism significantly improves the overall performance of the audio processing system, ensuring high-quality audio output and providing users with a clear and pure listening experience.

[0097] This device uses three modules to divide the work and coordinate work to better achieve the synchronization of clock phases. This application ensures the initial synchronization of the clock signal by receiving the first clock signal provided by the DSP host and sending the signal to the clock production chip. Subsequently, the MCLK clock signal, BCLK clock signal and LRCK clock signal generated by the clock production chip correspond to different audio transmission channels. The phase difference of these signals is adjusted until it reaches the preset error range. This process is achieved by controlling the phase relationship of each clock signal. This adjustment ensures that the clock signals of all channels can be synchronized with the original first clock signal, thereby reducing audio distortion and noise caused by phase deviation. When the adjustment stops and the first phase, second phase and third phase are obtained, the application has achieved a highly synchronized clock signal. The method of the application significantly improves the accuracy and reliability of audio data transmission, optimizes the overall performance of the audio processing system, and solves the problem of difficult clock phase synchronization in the prior art.

[0098] The specific embodiments described above further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A method for controlling clock phase synchronization, characterized in that: include: Receive a first clock signal from a DSP host; Sending the first clock signal to a clock production chip, so that the clock production chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal; The clock production chip is controlled so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal until the phase difference is within a preset error range, and the adjustment is stopped to obtain the first phase, the second phase and the third phase.

2. The clock phase synchronization control method according to claim 1, wherein: The clock production chip is controlled so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal, and the LRCK clock signal until the phase difference is within a preset error range, specifically: According to the time domain waveform diagram, the clock production chip is controlled so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal until the phase difference is within a preset error range.

3. The clock phase synchronization control method according to claim 2, wherein: The clock production chip is controlled according to the time domain waveform diagram so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal, specifically: The time domain waveform is displayed on an oscilloscope; The clock production chip is connected to an oscilloscope; The first input interface of the oscilloscope is connected to the pin of the MCLK clock signal, the second input interface of the oscilloscope is connected to the pin of the BCLK clock signal, and the third input interface of the oscilloscope is connected to the pin of the LRCK clock signal.

4. The clock phase synchronization control method according to claim 1, wherein: The sending of the first clock signal to a clock production chip so that the clock production chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal is specifically as follows: The MCLK clock signal is a first clock signal with a doubled frequency, the BCLK clock signal is a first clock signal with a singled frequency, and the LRCK clock signal is a first clock signal with a divided frequency of 256.

5. The clock phase synchronization control method according to claim 1, wherein: The step of sending the first clock signal to a clock production chip so that the clock production chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal further includes: The MCLK clock signal, the BCLK clock signal and the LRCK clock signal are connected to the first slave, the second slave, the third slave and the fourth slave respectively; The MCLK clock signal, the BCLK clock signal and the LRCK clock signal directly drive the first slave, the second slave, the third slave and the fourth slave respectively.

6. A clock phase synchronization control device, characterized in that: It includes a receiving module, a sending module and an adjusting module; The receiving module is used to receive the first clock signal of the DSP host; The sending module is used to send the first clock signal to the clock production chip, so that the clock production chip generates an MCLK clock signal, a BCLK clock signal and an LRCK clock signal; The adjustment module controls the clock production chip so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal until the phase difference is within a preset error range, stops adjusting, and obtains the first phase, the second phase and the third phase.

7. The clock phase synchronization control device according to claim 6, characterized in that: The clock production chip is controlled so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal, and the LRCK clock signal until the phase difference is within a preset error range, specifically: According to the time domain waveform diagram, the clock production chip is controlled so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal until the phase difference is within a preset error range.

8. The clock phase synchronization control device according to claim 7, characterized in that: The clock production chip is controlled according to the time domain waveform diagram so that the clock production chip adjusts the phase difference of the MCLK clock signal, the BCLK clock signal and the LRCK clock signal, specifically: The time domain waveform is displayed on an oscilloscope; The clock production chip is connected to an oscilloscope; The first input interface of the oscilloscope is connected to the pin of the MCLK clock signal, the second input interface of the oscilloscope is connected to the pin of the BCLK clock signal, and the third input interface of the oscilloscope is connected to the pin of the LRCK clock signal.

9. The clock phase synchronization control device according to claim 6, characterized in that: The sending of the first clock signal to a clock production chip so that the clock production chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal is specifically as follows: The MCLK clock signal is a first clock signal with a doubled frequency, the BCLK clock signal is a first clock signal with a singled frequency, and the LRCK clock signal is a first clock signal with a divided frequency of 256.

10. The clock phase synchronization control device according to claim 6, characterized in that: The step of sending the first clock signal to a clock production chip so that the clock production chip generates an MCLK clock signal, a BCLK clock signal, and an LRCK clock signal further includes: The MCLK clock signal, the BCLK clock signal and the LRCK clock signal are connected to the first slave, the second slave, the third slave and the fourth slave respectively; The MCLK clock signal, the BCLK clock signal and the LRCK clock signal directly drive the first slave, the second slave, the third slave and the fourth slave respectively.

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