Clock phase adjustment method, ethernet data transmission method and related devices

Abstract

The application relates to the technical field of chip signals, and discloses a clock phase adjusting method, an Ethernet data transmission method and related equipment. The clock phase adjusting method comprises the following steps: obtaining the link state and the working transmission rate of a counterpart chip (a PHY chip or a MAC chip), then setting an initial value of a counter and a count rollover condition, and when the value of the counter reaches the count rollover condition, generating a first clock signal and a second clock signal with a phase deviation, which are used for the output of a data signal and a clock signal of the PHY chip or the MAC chip. The application enables the RGMII interface to adapt to various MAC chip and PHY chip interconnection scenes, improves the compatibility of the network card chip, and solves the problem of RGMII interface data sampling errors.

Description

Technical Field

[0001] This invention relates to the field of chip signal technology, and in particular to a clock phase adjustment method, an Ethernet data transmission method, and related equipment. Background Technology

[0002] The RGMII (Reduced Gigabit Media Independent Interface) is a simplified version of the Gigabit Media Independent Interface, primarily used for communication between the Ethernet MAC (Media Access Control) and PHY (Physical Layer). The RGMII interface uses a 4-bit data interface and supports three communication rates: 10 / 100 / 1000 Mbps, meeting the needs of different network environments. At 1000 Mbps, the clock frequency is 125 MHz; at 100 Mbps, it is 25 MHz; and at 10 Mbps, it is 2.5 MHz. In 1000 Mbps mode, the RGMII interface transmits data simultaneously on both the rising and falling edges of the clock, achieving high-speed data transmission.

[0003] like Figure 1 As shown, the RGMII interface mainly includes the following signal lines:

[0004] TXCLK (Transmit Clock): Provided by the MAC to the PHY;

[0005] TX_CTRL (Send Control): Sends control signals;

[0006] TXDATA[3:0] (Transmit Data): 4-bit parallel transmit data signal;

[0007] RXCLK (Receive Clock): Extracted by the PHY from the received data, and is independent of the transmit clock.

[0008] RX_CTRL (Receive Control): Receive control signal.

[0009] RXDATA[3:0] (Received Data): 4-bit parallel received data signal.

[0010] In practical applications, both MAC (Machine Interface) data transmission and PHY (Physical Hyper-Hydraulic Interface) data reception require interconnection via PCB traces. For example, in data transmission, the MAC's data signal TXDATA and clock signal TXCLK are interconnected with the PHY chip via PCB traces. Due to inconsistencies in data and clock trace delays caused by PCB layout, and manufacturing errors in the PHY chip, significant data and clock deviations can occur, preventing the PHY chip from sampling the correct data using TXCLK. Similar problems exist in data reception. To address these issues in MAC-PHY interconnection, current technologies typically employ a fixed phase deviation of 90°. However, this fixed phase adjustment mode cannot adapt to compatibility scenarios involving various PHY chips and PCB designs from different manufacturers. For instance, if the data trace delay is greater than 90° phase, a fixed 90° clock phase adjustment will lead to data sampling errors. Summary of the Invention

[0011] The main objective of this invention is to provide a clock phase adjustment method, an Ethernet data transmission method, and related equipment, aiming to solve the technical problem of data sampling errors caused by the low compatibility of existing RGMII interfaces with PHY chips and PCB board designs from different manufacturers.

[0012] The first aspect of this invention provides a clock phase adjustment method applied to an RGMII interface, the clock phase adjustment method comprising:

[0013] Obtain the link status and operating transmission rate of the peer chip;

[0014] If the link status indicates that the link has been successfully created, then the working clock frequency of the RGMII interface is determined based on the working transmission rate.

[0015] Based on the chip clock frequency provided by the system chip and the working clock frequency of the RGMII interface, set the initial value of the counter and the count toggling condition;

[0016] The counter starts counting down from its initial value;

[0017] When the value of the counter reaches the count flip condition, a first clock signal and a second clock signal with phase deviation are generated.

[0018] Optionally, in a first implementation of the first aspect of the present invention, the clock phase adjustment method further includes:

[0019] When the value of the counter decreases to 0, the latest operating transmission rate of the peer chip is retrieved again, and the latest operating clock frequency of the RGMII interface is determined based on the latest operating transmission rate of the peer chip.

[0020] If the latest working transmission rate changes, the new initial value of the counter and the new count toggling condition are reset based on the chip clock frequency provided by the system chip and the latest working clock frequency of the RGMII interface.

[0021] The counter starts counting down from the new initial value;

[0022] When the value of the new counter reaches the new counting flip condition, a third clock signal and a fourth clock signal with phase deviation are generated.

[0023] Optionally, in a second implementation of the first aspect of the present invention, the clock phase adjustment method further includes:

[0024] If the latest working transmission rate has not changed, the counter will continue to decrement from the last set initial value.

[0025] When the value of the counter reaches the previously set count flip condition, the first clock signal and the second clock signal with phase deviation are generated.

[0026] Optionally, in a third implementation of the first aspect of the present invention, the first clock signal is in phase with the chip clock frequency and is used to drive the transmission or reception of data signals; the second clock signal is in frequency with the first clock signal and is used for the peer chip to perform data sampling.

[0027] Optionally, in a fourth implementation of the first aspect of the present invention, the formula for calculating the initial value of the counter is as follows:

[0028] C0 = (F1 / F2) - 1;

[0029] Where C0 represents the initial value of the counter, F1 represents the chip clock frequency provided by the system chip, and F2 represents the working clock frequency of the RGMII interface.

[0030] Optionally, in a fifth implementation of the first aspect of the present invention, the counter flipping condition is that the value of the counter is divided by a flipping threshold, and the formula for calculating the flipping threshold is as follows:

[0031] N = (C0 + 1) / 2;

[0032] Where N represents the flip threshold and C0 represents the initial value of the counter.

[0033] A second aspect of the present invention provides an Ethernet data transmission method applied to an RGMII interface, the Ethernet data transmission method comprising:

[0034] Using any of the clock phase adjustment methods described above, a first clock signal and a second clock signal with phase deviation are generated;

[0035] Ethernet data transmission is performed through the RGMII interface based on the first clock signal and the second clock signal.

[0036] A third aspect of the present invention provides a clock phase adjustment device for use in an RGMII interface, the clock phase adjustment device comprising:

[0037] The acquisition module is used to acquire the link status and operating transmission rate of the peer chip;

[0038] The determination module is used to determine the working clock frequency of the RGMII interface based on the working transmission rate if the link status is "link creation successful".

[0039] The counting module is used to set the initial value of the counter and the counting flip condition based on the chip clock frequency provided by the system chip and the working clock frequency of the RGMII interface, and to count down from the initial value of the counter.

[0040] The generation module is used to generate a first clock signal and a second clock signal with phase deviation when the value of the counter reaches the counting flip condition.

[0041] Optionally, in a first implementation of the third aspect of the present invention, the acquisition module is further configured to: when the value of the counter is decremented to 0, reacquire the latest operating transmission rate of the peer chip;

[0042] The determining module is also used to: determine the latest operating clock frequency of the RGMII interface based on the latest operating transmission rate of the peer chip;

[0043] The counting module is also used to: if the current latest working transmission rate changes, reset a new initial value of the counter and a new counting flip condition based on the chip clock frequency provided by the system chip and the latest working clock frequency of the RGMII interface, and start counting down from the new initial value of the counter;

[0044] The generation module is also used to generate a third clock signal and a fourth clock signal with phase deviation when the value of the new counter reaches the new counting flip condition.

[0045] Optionally, in a second implementation of the third aspect of the present invention, the counting module is further configured to: if the current latest working transmission rate has not changed, continue to count down from the previously set initial value of the counter;

[0046] The generation module is also used to: generate the first clock signal and the second clock signal with phase deviation when the value of the counter reaches the previously set counting flip condition.

[0047] Optionally, in a third implementation of the third aspect of the present invention, the first clock signal is in phase with the clock frequency of the chip and is used to drive the transmission or reception of data signals; the second clock signal is in frequency with the first clock signal and is used for the peer chip to perform data sampling.

[0048] Optionally, in a fourth implementation of the third aspect of the present invention, the formula for calculating the initial value of the counter is as follows:

[0049] C0 = (F1 / F2) - 1;

[0050] Where C0 represents the initial value of the counter, F1 represents the chip clock frequency provided by the system chip, and F2 represents the working clock frequency of the RGMII interface.

[0051] Optionally, in a fifth implementation of the third aspect of the present invention, the counter flipping condition is that the value of the counter is divided by a flipping threshold, and the formula for calculating the flipping threshold is as follows:

[0052] N = (C0 + 1) / 2;

[0053] Where N represents the flip threshold and C0 represents the initial value of the counter.

[0054] A fourth aspect of the present invention provides a computer device, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor invokes the instructions in the memory to cause the computer device to perform the clock phase adjustment method and / or the Ethernet data transmission method described above.

[0055] A fourth aspect of the present invention provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the clock phase adjustment method and / or the Ethernet data transmission method described above.

[0056] This invention provides a method for flexibly adjusting the clock phase. By acquiring the link status and operating transmission rate of the peer chip (PHY chip or MAC chip), an initial value and a counting toggle condition are set for a counter. When the counter value reaches the counting toggle condition, a first clock signal and a second clock signal with phase deviation are generated for the data signal and clock signal output of the PHY chip or MAC chip, thereby solving the timing problem of the RGMII interface. This invention allows for customization of the initial value and counting toggle condition of the counter, thus enabling the RGMII interface to adapt to various interconnection scenarios of MAC chips and PHY chips, improving network card chip compatibility, and resolving the data sampling error problem of the RGMII interface. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of an embodiment of RGMII interface interconnection in the present invention;

[0058] Figure 2 This is a schematic diagram of one embodiment of the clock phase adjustment method in this invention;

[0059] Figure 3 This is a schematic diagram of another embodiment of the clock phase adjustment method in this invention;

[0060] Figure 4 This is a schematic diagram of one embodiment of the Ethernet data transmission method in this invention;

[0061] Figure 5 This is a schematic diagram of one embodiment of the clock phase adjustment device in this invention;

[0062] Figure 6 This is a schematic diagram of one embodiment of the computer device in this invention. Detailed Implementation

[0063] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” or “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0064] Please see Figure 1 , Figure 1 This diagram illustrates an embodiment of the RGMII interface interconnect. The RGMII interface is a physical layer interface standard for Gigabit Ethernet, used to connect the MAC and PHY ends within a chip, thereby enabling Gigabit Ethernet data transmission. The RGMII interface transmits data and control signals between the MAC chip and the physical layer chip (i.e., the PHY chip) through specific pins and signal lines. These signals include clock signals (TXC / RXC), data signals (TXD[3:0] / RXD[3:0]), and control signals (such as TX_EN / RX_DV). In practical applications, the implementation of the RGMII interface may rely on the connection between an external PHY chip and the MAC controller, or it may be implemented within a SoC (System-on-a-Chip) through the integrated connection between the MAC chip and the PHY chip. This invention specifically describes an embodiment for the latter scenario.

[0065] The MAC chip (Media Access Control chip) is a component of the Data Link Layer, primarily responsible for data frame encapsulation and decapsulation, error detection, and media access control. The MAC chip determines whether data can be sent. If the conditions are met, it adds control information (such as source address, destination address, frame type, etc.) to the data and sends it to the Physical Layer (PHY layer) according to the prescribed format. When receiving data, the MAC chip first checks for transmission errors. If no errors are found, it removes the control information and sends the data to a higher layer for processing.

[0066] The PHY chip (Physical Layer chip) is a component of the Physical Layer, primarily responsible for functions such as digital-to-analog signal conversion, signal modulation and demodulation, and clock synchronization. When transmitting data, the PHY chip converts the digital signals received from the MAC chip into analog signals and transmits them through a transmission medium (such as a network cable). When receiving data, the PHY chip converts the received analog signals back into digital signals and transmits them to the MAC chip for processing.

[0067] A network interface card (NIC) chip is one of the core components of a computer local area network (LAN). It integrates a MAC chip and a PHY chip (or one of them) along with related interface circuits, responsible for connecting the computer to the network and enabling data transmission and network communication. Through its integrated MAC and PHY chips, the NIC chip converts the computer's digital signals into analog signals suitable for network transmission and sends them to the network via transmission media such as network cables.

[0068] For ease of understanding, the specific process of the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 2 This invention provides an embodiment of a clock phase adjustment method applied to an RGMII interface. The clock phase adjustment method includes:

[0069] 201. Obtain the link status and operating transmission rate of the peer chip;

[0070] In this embodiment, the peer chip can be either a physical layer chip (for transmitting data) or a media access control chip (for receiving data). The media access control chip (i.e., the MAC chip) or the physical layer chip (i.e., the PHY chip) is typically connected to upper-layer devices (such as link layer chips or processors) via interfaces (such as MDIO, MDC, etc.). Therefore, query commands can be sent through these interfaces to directly read the status registers or status bits of the physical layer chip or the media access control chip, thereby obtaining link status information. This status information may include whether the link is established, whether it is active, and whether any errors have occurred.

[0071] In network environments such as Ethernet, physical layer chips or media access control chips typically support auto-negotiation, allowing them to automatically detect and match the transmission rate and duplex mode of the peer device. The current operating transmission rate can be obtained by querying the auto-negotiation result. Physical layer chips or media access control chips usually have configuration registers for setting and storing device configuration information, including the operating transmission rate. The currently set operating transmission rate can be obtained by reading these configuration registers. Similar to obtaining link status, query commands can also be sent via interfaces such as MDIO and MDC to directly read the transmission rate-related registers or status bits in the physical layer chip or media access control chip, thereby obtaining the current operating transmission rate.

[0072] 202. If the link status is "link creation successful", then determine the working clock frequency of the RGMII interface based on the working transmission rate;

[0073] In Ethernet communication, when the link status of the physical layer chip or media access controller chip indicates successful link creation, the operating clock frequency of the RGMII interface needs to be determined based on the operating transmission rate of the physical layer chip or media access controller chip. The operating clock frequency of the RGMII interface may vary depending on the operating transmission rate of the physical layer chip or media access controller chip. However, in standard RGMII implementations, the clock frequency is typically fixed (e.g., 125MHz), and data is transmitted on the rising or falling edge (or both) of the clock to achieve higher data transmission rates.

[0074] In this embodiment, once the link is successfully established and the working transmission rate is determined, the RGMII interface will use a fixed clock frequency (e.g., 125MHz) and adapt to different transmission rates by adjusting the data encoding and transmission scheme.

[0075] For example, if the physical layer chip or media access control chip has an operating transmission rate of 1000Mbps, the RGMII interface uses a working clock frequency of 125MHz; if the physical layer chip or media access control chip has an operating transmission rate of 100Mbps, the RGMII interface uses a working clock frequency of 25MHz; if the physical layer chip or media access control chip has an operating transmission rate of 10Mbps, the RGMII interface uses a working clock frequency of 2.5MHz.

[0076] 203. Based on the chip clock frequency provided by the system chip and the operating clock frequency of the RGMII interface, set the initial value of the counter and the counting toggle condition;

[0077] 204. The counter starts counting down from its initial value;

[0078] The counter is set based on the chip clock frequency provided by the System-on-a-Chip (SoC) and the operating clock frequency of the RGMII interface. Its main purpose is to generate the clock signal required by the RGMII interface through the counter. Since the RGMII interface usually operates at a fixed clock frequency (such as 125MHz for Gigabit Ethernet), while the SoC's chip clock frequency is much higher than the RGMII interface's operating clock frequency, a counter is needed to divide the high-frequency clock signal.

[0079] Frequency division refers to reducing the frequency of an input signal to a lower frequency. In digital circuits, frequency dividers are used to generate multiple low-frequency clock signals from a high-frequency reference clock signal to meet the needs of different circuit modules. The implementation principle of a frequency divider depends on the specific circuit design and application requirements. For digital frequency dividers, the basic principle is to use digital circuit elements such as counters and registers to count and logically process the input signal, thereby obtaining a lower frequency output signal.

[0080] In the case of decrementing, the counter can start counting from an initial value greater than, less than, or equal to the division ratio. For example, assuming the SoC's clock frequency is 500MHz and the RGMII interface requires a 125MHz clock, the division ratio between the SoC's clock frequency and the RGMII interface's operating clock frequency is 4 (500MHz / 125MHz = 4). Therefore, the counter can start counting from 3, 4, or 5.

[0081] Since this embodiment is based on the chip clock frequency provided by the system chip, the counter decrements within each SoC clock cycle. The counter toggle condition refers to when the counter should toggle (i.e., reset to the initial value or a new value) to generate the required clock signal.

[0082] In one embodiment, the initial value of the counter is calculated using the following formula:

[0083] C0=(F1 / F2)-1 (Formula 1)

[0084] Where C0 represents the initial value of the counter, F1 represents the chip clock frequency provided by the system chip, and F2 represents the working clock frequency of the RGMII interface.

[0085] For example, assuming the SoC chip provides a chip clock frequency of 500MHz, if the working transmission rate negotiated by the PHY chip or MAC chip is 1000Mbps, then based on the transmission protocol, the working clock frequency of the RGMII interface can be determined to be 125MHz. Then, the initial value of the counter can be calculated as 3 using the above formula 1, that is, the counter counts down from 3 each time.

[0086] In one embodiment, the counter flipping condition is that the counter value is divided by a flipping threshold, and the flipping threshold is calculated using the following formula:

[0087] N = (C0 + 1) / 2 (Formula 2)

[0088] Where N represents the flip threshold and C0 represents the initial value of the counter.

[0089] Taking the above example again, the initial value of the counter calculated by Formula 1 is 3, and the toggle threshold calculated by Formula 2 is 2. That is, when the value of the counter is divided by 2, a clock signal will be generated.

[0090] As can be seen from the above, the initial value of the counter is not only related to the chip clock frequency of the system chip and the working clock frequency of the RGMII interface, but also to the working transmission rate negotiated by the PHY chip or MAC chip. That is, this embodiment can dynamically adjust the initial value of the counter based on the negotiation rate of the PHY chip or MAC chip, thereby adjusting the counting flip condition, so as to realize the phase deviation control of the output clock signal, and thus solve the problem of data sampling error caused by clock data phase deviation in the RGMII interface.

[0091] 205. When the value of the counter reaches the counting flip condition, a first clock signal and a second clock signal with phase deviation are generated.

[0092] The clock signals (such as TXCLK and RXCLK) of the RGMII interface are not directly provided by the RGMII interface itself, but by the PHY or MAC chip connected to the RGMII interface. These clock signals are used to synchronize data transmission and reception. The PHY or MAC chip typically contains clock generation circuits that can generate the required clock signals based on an external reference clock (such as a crystal oscillator). Depending on the actual needs, the clock generation circuit can divide or multiply the external reference clock to generate clock signals that meet the requirements of the RGMII interface. In some cases, to maintain synchronization with the data signal or meet specific timing requirements, the clock signal may also need phase adjustment, which can be achieved by adjusting the clock signal's delay or phase offset.

[0093] In this embodiment, when the counter value does not reach the set flip condition, the current clock signal state is not generated or is maintained. When the counter value reaches the set flip condition, the clock signal generation logic is triggered. For example, assuming the initial value of the counter is 3, and the counter flip is adjusted to the counter value being divisible by 2, then when the counter value is 2, the flip condition is met, thereby triggering the generation of a first clock signal and a second clock signal with phase deviation.

[0094] In this embodiment, the clock source used to generate the clock signal is preferably the clock frequency of the SoC.

[0095] In one embodiment, the generated first clock signal is in phase with the chip clock frequency and is used to drive the transmission of data signals (e.g., Figure 1 The TXDATA and TX_CTRL signals shown (or received data signals, such as...) Figure 1 The generated second clock signal is at the same frequency as the first clock signal and is used by the peer chip to sample data (that is, the second clock signal is the TXCLK input of the PHY chip, and the PHY chip uses the second clock signal to sample TXDATA and TX_CTRL; or the second clock signal is the RXCLK input of the MAC chip, and the MAC chip uses the second clock signal to sample RXDATA and RX_CTRL).

[0096] In this embodiment, an adjustable phase deviation between the first clock signal and the second clock signal is achieved by delaying the first clock signal. The amount of delay determines the phase deviation between the two clock signals. The delay can be implemented in various ways, such as using a digital delay line (DDL), a FIFO buffer, or a D flip-flop chain. Specifically, the required delay time can be calculated based on the desired phase deviation and the frequency of the clock signal. For example, if the clock frequency is 125MHz (period 8ns) and a 1ns phase deviation is required, then the required delay is 1ns.

[0097] This embodiment implements a method to support flexible clock phase adjustment. By acquiring the link status and operating transmission rate of the peer chip (PHY chip or MAC chip), an initial value and a counting toggle condition are set for a counter. When the counter value reaches the counting toggle condition, a first clock signal and a second clock signal with phase deviation are generated for the data signal and clock signal output of the PHY chip or MAC chip, thereby solving the timing problem of the RGMII interface. This embodiment achieves customization of the phase deviation of the data signal and clock signal by customizing the initial value and counting toggle condition of the counter, thus enabling the RGMII interface to adapt to various interconnection scenarios of MAC chips and PHY chips, improving network card chip compatibility, and solving the problem of data sampling errors in the RGMII interface.

[0098] Please see Figure 3 , Figure 3 This is another embodiment of the clock phase adjustment method of the present invention. In this embodiment, the clock phase adjustment method includes:

[0099] 301. Obtain the link status and operating transmission rate of the peer chip;

[0100] 302. If the link status is "link creation successful", then determine the working clock frequency of the RGMII interface based on the working transmission rate;

[0101] 303. Based on the chip clock frequency provided by the system chip and the operating clock frequency of the RGMII interface, set the initial value of the counter and the counting toggle condition;

[0102] 304. The counter starts counting down from its initial value;

[0103] 305. When the value of the counter reaches the counting flip condition, a first clock signal and a second clock signal with phase deviation are generated;

[0104] In this embodiment, steps 301-305 are the same as steps 201-205 in the previous embodiment, so they will not be described again.

[0105] 306. When the value of the counter decreases to 0, the latest operating transmission rate of the peer chip is reacquired, and the latest operating clock frequency of the RGMII interface is determined based on the latest operating transmission rate of the peer chip.

[0106] In this embodiment, since the clock signal is generated based on a counter, when the counter value decrements to 0, a new initial counter value and a new counting toggle condition need to be reset. Typically, the previously used initial counter value and counting toggle condition are directly reused. This embodiment considers that the operating transmission rate of the peer chip may change, which could affect the subsequent RGMII interface timing. Therefore, it is necessary to re-obtain the latest operating transmission rate of the peer chip and determine the latest operating clock frequency of the RGMII interface.

[0107] 307. If the latest working transmission rate changes, then based on the chip clock frequency provided by the system chip and the latest working clock frequency of the RGMII interface, reset the new initial value of the counter and the new counter toggle condition.

[0108] 308. Start counting down from the new initial value of the counter;

[0109] 309. When the value of the new counter reaches the new counting flip condition, a third clock signal and a fourth clock signal with phase deviation are generated.

[0110] In this embodiment, if the current physical layer chip or media access control chip's operating transmission rate changes, a new initial value for the counter and a new counting flip condition are reset, and the counter starts counting down from the new initial value. When the value of the new counter reaches the new counting flip condition, a third clock signal and a fourth clock signal with phase deviation are generated.

[0111] For example, if the physical layer chip or media access control chip operates at a transmission rate of 1000Mbps in steps 301 and 302, and the RGMII interface operates at a clock frequency of 125MHz, then the initial value of the counter in step 303 needs to be set to 3, the counting flip condition is divisibility by 2, and the counter starts counting down from the initial value of 3. In step 305, when the value of the counter after decrementing reaches the counting flip condition (for example, the counter value is 2), a first clock signal and a second clock signal with phase deviation are generated.

[0112] In step 306, when the counter's decremented value becomes 0, the latest operating transmission rate of the peer physical layer chip or media access control chip is retrieved again. If the operating transmission rate changes, a new initial counter value of 19 is reset in step 307, with the new counting flip condition being divisible by 10, and the counter starts decrementing from the new initial value of 19. When the new counter's decremented value reaches the new counting flip condition (e.g., the counter value is 10), a third clock signal and a fourth clock signal with phase deviation are generated.

[0113] In one embodiment, if the latest operating transmission rate of the current physical layer chip or media access control chip has not changed, the counter continues to decrement from the previously set initial value; when the value of the counter reaches the previously set counting flip condition, the first clock signal and the second clock signal with phase deviation are generated.

[0114] In this embodiment, when the counter value decreases to 0, if the latest operating transmission rate of the current physical layer chip or media access control chip has not changed, the previously set initial counter value and counting flip condition are used. When the counter value reaches the set counting flip condition, a first clock signal and a second clock signal with phase deviation are generated.

[0115] This embodiment adjusts the initial value of the counter and the counting toggle condition accordingly based on the changes in the operating transmission rate of the physical layer chip or media access control chip. By customizing the initial value of the counter and the counting toggle condition, the phase deviation between the data signal and the clock signal can be customized, thereby enabling the RGMII interface to adapt to various interconnection scenarios of MAC chips and PHY chips, improving the compatibility of network card chips, and solving the problem of data sampling errors in the RGMII interface.

[0116] Please see Figure 4 , Figure 4 This is another embodiment of the Ethernet data transmission method of the present invention. This embodiment is applied to the RGMII interface, and the Ethernet data transmission includes:

[0117] 401. A clock phase adjustment method is used to generate a first clock signal and a second clock signal with phase deviation;

[0118] 402. Based on the first clock signal and the second clock signal, Ethernet data transmission is performed through the RGMII interface.

[0119] The MAC chip's data signal TXDATA and clock signal TXCLK are interconnected with the PHY chip via PCB traces, while the PHY chip's data signal RXDATA and clock signal RXCLK are interconnected with the MAC chip via PCB traces. Inconsistencies in data and clock trace delays caused by PCB layout, along with PHY chip specifications and manufacturing errors, can lead to significant data and clock deviations, preventing the PHY or MAC chip from sampling the correct data using TXCLK or RXCLK.

[0120] In this embodiment, to address the issue of data sampling errors caused by the low compatibility of existing RGMII interfaces with PHY chips and PCB designs from different manufacturers, the clock phase adjustment method described in the above embodiment is adopted to generate a first clock signal and a second clock signal with phase deviation. Based on the generated first clock signal and second clock signal with phase deviation, the RGMII interface can perform Ethernet data transmission normally, ensuring the accuracy of data transmission.

[0121] The clock phase adjustment method and Ethernet data transmission method in the embodiments of the present invention have been described above. The clock phase adjustment device in the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 5 One embodiment of the clock phase adjustment device in this invention includes:

[0122] The acquisition module 501 is used to acquire the link status and operating transmission rate of the peer chip;

[0123] The determination module 502 is used to determine the working clock frequency of the RGMII interface based on the working transmission rate if the link status is "link creation successful".

[0124] The counting module 503 is used to set the initial value of the counter and the counting flip condition based on the chip clock frequency provided by the system chip and the working clock frequency of the RGMII interface, and to count down from the initial value of the counter.

[0125] The generation module 504 is used to generate a first clock signal and a second clock signal with phase deviation when the value of the counter reaches the counting flip condition.

[0126] Optionally, in one embodiment, the acquisition module 501 is further configured to: when the value of the counter is decremented to 0, reacquire the latest operating transmission rate of the peer chip;

[0127] The determining module 502 is further configured to: determine the latest operating clock frequency of the RGMII interface based on the latest operating transmission rate of the peer chip;

[0128] The counting module 503 is also used to: if the current latest working transmission rate changes, reset a new initial value of the counter and a new counting flip condition based on the chip clock frequency provided by the system chip and the latest working clock frequency of the RGMII interface, and start counting down from the new initial value of the counter.

[0129] The generation module 504 is also used to generate a third clock signal and a fourth clock signal with phase deviation when the value of the new counter reaches the new counting flip condition.

[0130] Optionally, in one embodiment, the counting module 503 is further configured to: if the current latest working transmission rate has not changed, continue counting from the previously set initial value of the counter;

[0131] The generation module 504 is further configured to: generate the first clock signal and the second clock signal with phase deviation when the value of the counter reaches the previously set counting flip condition.

[0132] Optionally, in one embodiment, the first clock signal is in phase with the chip clock frequency and is used to drive the transmission or reception of data signals; the second clock signal is in the same frequency as the first clock signal and is used by the peer chip to perform data sampling.

[0133] Optionally, in a fourth implementation of the third aspect of the present invention, the formula for calculating the initial value of the counter is as follows:

[0134] C0 = (F1 / F2) - 1;

[0135] Where C0 represents the initial value of the counter, F1 represents the chip clock frequency provided by the system chip, and F2 represents the working clock frequency of the RGMII interface.

[0136] Optionally, in one embodiment, the counter flipping condition is that the value of the counter is divided by a flipping threshold, and the flipping threshold is calculated using the following formula:

[0137] N = (C0 + 1) / 2;

[0138] Where N represents the flip threshold and C0 represents the initial value of the counter.

[0139] Since the embodiments of the device part correspond to the embodiments of the above method, the description of the clock phase adjustment device provided by the present invention should refer to the above method embodiments. The present invention will not be described again here, but it has the same beneficial effects as the above clock phase adjustment method.

[0140] above Figure 5 The clock phase adjustment device in the embodiments of the present invention will be described in detail from the perspective of modular functional entities. The computer device in the embodiments of the present invention will be described in detail from the perspective of hardware processing.

[0141] Figure 6This is a schematic diagram of the structure of a computer device 600 provided in an embodiment of the present invention. The computer device 600 can vary significantly due to different configurations or performance characteristics. It may include one or more central processing units (CPUs) 610 (e.g., one or more processors) and a memory 620, and one or more storage media 630 (e.g., one or more mass storage devices) for storing application programs 633 or data 632. The memory 620 and storage media 630 can be temporary or persistent storage. The program stored in the storage media 630 may include one or more modules (not shown in the diagram), each module including a series of instruction operations on the computer device 600. Furthermore, the processor 610 may be configured to communicate with the storage media 630 and execute the series of instruction operations in the storage media 630 on the computer device 600.

[0142] Computer device 600 may also include one or more power supplies 640, one or more wired or wireless network interfaces 650, one or more input / output interfaces 660, and / or one or more operating systems 631, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. Those skilled in the art will understand that... Figure 6 The computer device structure shown does not constitute a limitation on the computer device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0143] The present invention also provides a computer device, the computer device including a memory and a processor, the memory storing computer-readable instructions, which, when executed by the processor, cause the processor to perform the steps of the clock phase adjustment method and / or Ethernet data transmission method described in the above embodiments.

[0144] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when the instructions are executed on a computer, cause the computer to perform the steps of the clock phase adjustment method and / or the Ethernet data transmission method.

[0145] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0146] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0147] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock phase adjustment method applied to an RGMII interface, characterized in that, The clock phase adjustment method includes: Obtain the link status and operating transmission rate of the peer chip; If the link status indicates that the link has been successfully created, then the working clock frequency of the RGMII interface is determined based on the working transmission rate. Based on the chip clock frequency provided by the system chip and the working clock frequency of the RGMII interface, set the initial value of the counter and the count toggling condition; The counter starts counting down from its initial value; When the value of the counter reaches the count flip condition, a first clock signal and a second clock signal with phase deviation are generated.

2. The clock phase adjustment method according to claim 1, characterized in that, The clock phase adjustment method further includes: When the value of the counter decreases to 0, the latest operating transmission rate of the peer chip is retrieved again, and the latest operating clock frequency of the RGMII interface is determined based on the latest operating transmission rate of the peer chip. If the latest working transmission rate changes, the new initial value of the counter and the new count toggling condition are reset based on the chip clock frequency provided by the system chip and the latest working clock frequency of the RGMII interface. The counter starts counting down from the new initial value; When the value of the new counter reaches the new counting flip condition, a third clock signal and a fourth clock signal with phase deviation are generated.

3. The clock phase adjustment method according to claim 2, characterized in that, The clock phase adjustment method further includes: If the latest working transmission rate has not changed, the counter will continue to decrement from the last set initial value. When the value of the counter reaches the previously set count flip condition, the first clock signal and the second clock signal with phase deviation are generated.

4. The clock phase adjustment method according to claim 1, characterized in that, The first clock signal is in phase with the chip clock frequency and is used to drive the transmission or reception of data signals; the second clock signal is in the same frequency as the first clock signal and is used by the peer chip to perform data sampling.

5. The clock phase adjustment method according to any one of claims 1-3, characterized in that, The formula for calculating the initial value of the counter is as follows: C0 = (F1 / F2) - 1; Where C0 represents the initial value of the counter, F1 represents the chip clock frequency provided by the system chip, and F2 represents the working clock frequency of the RGMII interface.

6. The clock phase adjustment method according to claim 5, characterized in that, The counter flip condition is that the counter value is divided by a flip threshold, and the flip threshold is calculated using the following formula: N = (C0 + 1) / 2; Where N represents the flip threshold and C0 represents the initial value of the counter.

7. An Ethernet data transmission method applied to an RGMII interface, characterized in that, The Ethernet data transmission method includes: Using the clock phase adjustment method according to any one of claims 1-6, a first clock signal and a second clock signal with phase deviation are generated; Ethernet data transmission is performed through the RGMII interface based on the first clock signal and the second clock signal.

8. A clock phase adjustment device, applied to an RGMII interface, characterized in that, The clock phase adjustment device includes: The acquisition module is used to acquire the link status and operating transmission rate of the peer chip; The determination module is used to determine the working clock frequency of the RGMII interface based on the working transmission rate if the link status is "link creation successful". The counting module is used to set the initial value of the counter and the counting toggle condition based on the chip clock frequency provided by the system chip and the working clock frequency of the RGMII interface, and to count down from the initial value of the counter. The generation module is used to generate a first clock signal and a second clock signal with phase deviation when the value of the counter reaches the counting flip condition.

9. A computer device, characterized in that, The computer device includes: a memory and at least one processor, wherein the memory stores instructions; The at least one processor invokes the instructions in the memory to cause the computer device to perform the clock phase adjustment method as described in any one of claims 1-6, and / or the Ethernet data transmission method as described in claim 7.

10. A computer-readable storage medium storing instructions thereon, characterized in that, When the instruction is executed by the processor, it implements the clock phase adjustment method as described in any one of claims 1-6, and / or the Ethernet data transmission method as described in claim 7.

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