Hdlc receiver with adaptive adjustment of the phase of the synchronization clock and method of operation

Abstract

The application provides an HDLC receiver with adaptive adjustment of synchronous clock phase function and an operation method, belongs to the technical field of data communication, and solves the problem that a traditional HDLC receiver cannot adaptively adjust clock phase to adapt to different working environments and signal changes, wherein the HDLC receiver comprises a synchronous clock input module, a serial data input module, a clock phase shifter module, a phase difference calculator module, a serial-parallel converter module, a zero removal controller module, a '7E' detector module, a received data coding module, an address judgment module, a CRC check module, a function setting register module, a received buffer area module and a state register module; the modules in the HDLC receiver designed by the application are independent of each other, but are connected with each other through clock and data signals, so that the flexibility and expansibility of the system are ensured, and in different application scenarios, the parameters of different modules can be adjusted according to needs to adapt to different communication environments.

Description

Technical Field

[0001] The invention relates to an HDLC receiver with a function of adaptively adjusting a synchronous clock phase and an operating method thereof, belonging to the technical field of data communication. Background Art

[0002] In HDLC communication systems, the receiver needs to use the received data frame and the synchronous clock to accurately sample and process the received data. However, in practical applications, the received data signal and the clock signal may experience a phase difference due to various factors during transmission, such as transmission delay, clock jitter, clock drift, and noise. If this phase difference cannot be effectively compensated and adjusted, it can lead to data sampling errors or data loss, thus affecting the reliability and accuracy of data transmission. Therefore, accurately adjusting the phase of the receiving clock to adapt to the phase changes of the input signal is crucial to improving receiver performance. Traditional HDLC receivers typically use a fixed clock phase and are unable to adaptively adjust the clock phase to accommodate varying operating environments and signal variations. Developing an HDLC receiver that can automatically detect and adjust the clock phase as needed has become an important research direction for improving the performance and robustness of communication systems. The adaptive adjustment of the synchronous clock phase proposed in this invention monitors the phase difference between the clock and data signals in real time and automatically adjusts the clock phase based on the magnitude of the phase difference, thereby ensuring stable data transmission and accurate reception. Summary of the Invention

[0003] The present invention aims to solve the problem that a traditional HDLC receiver cannot adaptively adjust the clock phase to adapt to different working environments and signal changes, and further proposes an HDLC receiver with the function of adaptively adjusting the synchronous clock phase and an operating method.

[0004] The technical solution adopted by the present invention to solve the above-mentioned problem is as follows: the HDLC receiver with the function of adaptively adjusting the synchronous clock phase proposed by the present invention comprises:

[0005] Synchronous clock input module, serial data input module, clock phase shifter module, phase difference calculator module, serial-to-parallel converter module, zero removal controller module, '7E' detector module, received data encoding module, address judgment module, CRC check module, function setting register module, receive buffer module and status register module;

[0006] The synchronous clock input module is used to receive the input synchronous clock;

[0007] The serial data input module is used to receive input serial data;

[0008] The phase difference calculator module is used to calculate the phase difference between the synchronous clock and the serial data and transmit it to the clock phase shifter module;

[0009] The clock phase shifter module performs phase shifting on the synchronous clock according to the phase difference, and inputs the phase-shifted synchronous clock and serial data into the '7E' detector module;

[0010] The '7E' detector module is used to detect valid frame headers of serial data;

[0011] The zero removal controller module is used to perform zero removal operation on serial data;

[0012] The serial-to-parallel converter module converts the serial data after the zero removal operation into parallel data and inputs the parallel data into the address judgment module;

[0013] The address judgment module is used to judge whether the serial data after the zero removal operation is a valid frame;

[0014] When it is a valid frame, the receiving data encoder receives the instruction of the function setting register module, reads the parallel data from the serial-to-parallel converter module, stores it in the receiving buffer module and updates the status register module;

[0015] The CRC checker is used to perform real-time judgment on the serial data after the zero removal operation, and sends the judgment result to the status register module through the receiving data encoder module at the end of the frame.

[0016] Preferably, the phase difference calculator module includes an exclusive OR operation submodule, a phase difference positive and negative judgment submodule, a duty cycle calculation submodule and a phase difference calculation submodule;

[0017] The XOR operation submodule is used to perform an XOR operation on the input synchronous clock and serial data to generate an XOR data signal;

[0018] The phase difference positive and negative judgment submodule is used to measure the xor data signal and make a positive and negative judgment of the phase difference based on the measurement results;

[0019] The duty cycle calculation submodule is used to calculate the duty cycle according to the positive and negative judgment results of the phase difference;

[0020] The phase difference calculation submodule is used to calculate the phase difference between the synchronous clock and the serial data according to the duty cycle calculation result.

[0021] Preferably, the clock phase shifter module includes a phase difference input submodule, a phase difference judgment submodule, a clock delay time calculation submodule, a synchronous clock phase shift submodule, an edge detection and sampling point calculation submodule, a sampling point judgment submodule and a synchronous clock output submodule;

[0022] The phase difference input submodule is used to receive the phase difference output by the phase difference calculator module;

[0023] The phase difference judgment submodule compares the phase difference with the pre-stored phase difference threshold. If the phase difference is greater than the threshold, it sends a trigger signal to the clock delay time calculation submodule. If the phase difference is not greater than the threshold, it sends a signal to the synchronous clock output submodule to output the current synchronous clock.

[0024] The clock delay time calculation submodule is used to calculate the clock delay time and transmit it to the synchronous clock phase shift submodule;

[0025] The synchronous clock phase shift submodule performs a phase shift operation on the synchronous clock according to the received delay time and transmits it to the edge detection and sampling point calculation submodule;

[0026] The edge detection and sampling point calculation submodule performs edge detection and calculates the position of the sampling point in the serial data bit according to the received phase-shifted synchronous clock, and transmits the calculation result to the sampling point judgment submodule;

[0027] The sampling point judgment submodule determines whether the sampling point is located at the bit center. If so, it sends a signal to the synchronous clock output submodule to output the current synchronous clock. If not, it sends a feedback signal to the phase difference calculator module to reacquire the phase difference data and calculate until the sampling point is located at the bit center.

[0028] The synchronous clock output submodule transmits the corresponding synchronous clock to the '7E' detector module according to the received signal.

[0029] An operating method of an HDLC receiver with a function of adaptively adjusting a synchronous clock phase comprises:

[0030] Step 1: Input the synchronous clock and serial data into the synchronous clock input module and serial data input module respectively;

[0031] Step 2: Use the phase difference calculator module to calculate the phase difference between the synchronous clock and the serial data;

[0032] Step 3: Input the phase difference into the clock phase shifter module to perform phase shifting on the synchronous clock, and input the phase-shifted synchronous clock and serial data into the '7E' detector module;

[0033] Step 4: The '7E' detector module detects the valid frame header of the serial data and uses the zero removal controller module to perform a zero removal operation on the serial data;

[0034] Step 5: Input the serial data after the zero removal operation into the serial-to-parallel converter module and the CRC checker module respectively;

[0035] Step 6: The serial-to-parallel converter module converts the serial data after the zero removal operation into parallel data, and inputs the parallel data into the address reader module to detect whether the current data is a valid frame. If it is a valid frame, the receiving data encoder module reads the parallel data from the serial-to-parallel converter module and stores it in the receiving buffer module, and updates the status register module;

[0036] Step 7: The CRC checker module reads the serial data after the zero removal operation in real time, and sends the reading result to the status register module through the receiving data encoder module at the end of the frame.

[0037] Preferably, step 2 specifically includes:

[0038] Step 2.1: Perform an XOR operation on the input synchronous clock and serial data through the XOR operation submodule to obtain the XOR data signal;

[0039] Step 2.2: Measure the XOR data signal after the XOR operation through the phase difference positive and negative judgment submodule to obtain the high-level duration T1 of the data rising edge, the high-level duration T2 of the data falling edge, and the high-level duration T3 of the clock cycle. If the synchronous clock corresponding to T1 and T2 is low, the phase difference is judged to be positive; if the synchronous clock corresponding to T1 and T2 is high, the phase difference is judged to be negative.

[0040] Step 2.3: Based on the phase difference positive and negative judgment result, the duty cycle is calculated using the duty cycle calculation submodule. If the phase difference positive and negative judgment result is positive, the duty cycle is calculated using the T1 time. If the phase difference positive and negative judgment result is negative, the duty cycle is calculated using the T2+T3 time. The duty cycle calculation formula is: Duty cycle = high level time / period;

[0041] Step 2.4: Input the duty cycle calculation result into the phase difference calculation submodule to calculate the phase difference θ between the synchronous clock and the serial data.

[0042] Preferably, step 3 specifically includes:

[0043] Step 3.1: Input the phase difference θ into the phase difference input submodule and transmit it to the phase difference judgment submodule;

[0044] Step 3.2: The phase difference judgment submodule compares the received phase difference θ with the pre-stored phase difference threshold. If the phase difference is greater than the threshold, it sends a trigger signal to the clock delay time calculation submodule. If the phase difference is not greater than the threshold, it sends a signal to the synchronous clock output submodule to output the current synchronous clock.

[0045] Step 3.3: After receiving the trigger signal, the clock delay time calculation submodule calculates the clock delay time based on the phase difference θ and the synchronous clock frequency f, where the calculation formula for the delay time is t = θ / (2πf);

[0046] Step 3.4: Input the delay time into the synchronous clock phase shift submodule, and adjust the phase by delaying the synchronous clock by the corresponding time on the time axis to ensure that the phase of the synchronous clock is consistent with the phase of the serial data;

[0047] Step 3.5: Input the phase-shifted synchronous clock into the edge detection and sampling point calculation submodule. When the rising / falling edge of the synchronous clock is detected, the position of the sampling point in the data bit is calculated based on the clock period and the serial data bit period.

[0048] Step 3.6: The sampling point determination submodule compares the sampling point position with the center position of the data bit. If the sampling point is located at the bit center, it sends a signal to the synchronization clock output submodule to output the current synchronization clock. If the sampling point is not located at the bit center, it sends a feedback signal to the phase difference calculator module to reacquire the phase difference data and calculate until the sampling point position is located at the bit center.

[0049] Step 3.7: The synchronous clock output submodule transmits the corresponding synchronous clock to the '7E' detector module according to the received signal.

[0050] The beneficial effects of the present invention are:

[0051] 1. The receiver of the present invention has adaptive adjustment capabilities and can automatically calculate and adjust the required clock phase according to the changing phase angle in real time, reducing the need for human intervention and fixed calibration, greatly improving the robustness and flexibility of the system. Due to the dynamic phase adjustment function, the receiver can process phase errors in the signal in real time, reducing transmission errors caused by phase differences, and ensuring the stability and reliability of data transmission.

[0052] 2. The HDLC receiver with adaptive clock phase adjustment of the present invention is widely applicable to data reception in high-speed communication systems, particularly in digital communications, data transmission, and wireless communications. In these fields, signal phase differences are often significant. The receiver of the present invention can dynamically adjust the clock phase to ensure correct data reception.

[0053] 3. The present invention is implemented using the hardware description language (Verilog), has high integration and scalability, and can be easily integrated into various digital communication systems.

[0054] 4. This invention uses an exclusive OR (XOR) operation to reflect the phase offset between the input data and the clock signal, combined with delay control logic to achieve phase adjustment of the clock signal. The adjusted clock signal is used as input, ensuring that the received data can maintain precise synchronization with the clock.

[0055] 5. The modules in the HDLC receiver designed in this invention are independent of each other but interconnected through signals such as clock and data, ensuring system flexibility and scalability. In different application scenarios, the parameters of different modules can be adjusted as needed to adapt to different communication environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A structural block diagram of an HDLC receiver with a function of adaptively adjusting the synchronous clock phase provided by the present invention;

[0057] Figure 2 A structural block diagram of the phase difference calculator module provided by the present invention;

[0058] Figure 3 A structural block diagram of the clock phase shifter module provided by the present invention;

[0059] Figure 4 A schematic flow chart of an operating method of an HDLC receiver with a function of adaptively adjusting a synchronous clock phase provided by the present invention;

[0060] Figure 5 A schematic diagram of the flow chart of the phase difference calculator module provided by the present invention;

[0061] Figure 6 A schematic diagram of the XOR processing of the synchronous clock and serial data provided by the present invention;

[0062] Figure 7 This is a flow chart of the clock phase shifter module provided by the present invention. DETAILED DESCRIPTION

[0063] Specific implementation method 1: Combination Figure 1-3 This embodiment is described as follows. Figure 1 As shown, the structure of the HDLC receiver with the function of adaptively adjusting the synchronous clock phase described in this embodiment includes:

[0064] Synchronous clock input module, serial data input module, clock phase shifter module, phase difference calculator module, serial-to-parallel converter module, zero removal controller module, '7E' detector module, received data encoding module, address judgment module, CRC check module, function setting register module, receive buffer module and status register module;

[0065] In this embodiment, each module is independent of each other, but is connected to each other through signals such as clock and data, ensuring the flexibility and scalability of the system. In different application scenarios, the parameters of different modules can be adjusted as needed to adapt to different communication environments.

[0066] like Figure 2 As shown, the phase difference calculator module includes an exclusive OR operation submodule, a phase difference positive and negative judgment submodule, a duty cycle calculation submodule and a phase difference calculation submodule;

[0067] like Figure 3 As shown, the clock phase shifter module includes a phase difference input submodule, a phase difference judgment submodule, a clock delay time calculation submodule, a synchronous clock phase shift submodule, an edge detection and sampling point calculation submodule, a sampling point judgment submodule and a synchronous clock output submodule.

[0068] Specific implementation method 2: Combination Figure 4-7 This embodiment is described as follows. Figure 4 As shown, the operating method of the HDLC receiver with the function of adaptively adjusting the synchronous clock phase according to this embodiment includes the following steps:

[0069] S1: Input the synchronous clock and serial data into the synchronous clock input module and serial data input module respectively;

[0070] S2: Use the phase difference calculator module to calculate the phase difference between the synchronous clock and the serial data;

[0071] like Figure 5 As shown in the figure, the workflow of the phase difference calculator module includes:

[0072] S201: The XOR submodule performs an XOR operation on the input synchronous clock and serial data. The resulting signal is recorded as xor data. As a basic logical operation, the XOR operation can perform preliminary processing on the characteristics of clock and data signals. This operation can highlight the phase difference between the clock and data signals, facilitating subsequent measurement and calculation of the phase difference.

[0073] S202: If Figure 6 As shown, the phase difference positive / negative judgment submodule measures the XOR data signal after the XOR operation to obtain the high-level duration T1 of the data rising edge, the high-level duration T2 of the data falling edge, and the high-level duration T3 of the clock cycle. Based on the measured signal parameters, the sign of the phase difference between the clock signal and the data signal is determined. If the clock signal corresponding to time T1 and T2 is low, the phase difference is positive; conversely, if the clock signal corresponding to time T1 and T2 is high, the phase difference is negative.

[0074] The present invention uses an exclusive OR (XOR) operation to reflect the phase offset between the input data and the clock signal, combined with delay control logic to achieve phase adjustment of the clock signal. The adjusted clock signal is used as input, ensuring that the received data can maintain precise synchronization with the clock.

[0075] S203: Based on the positive or negative judgment result of the phase difference, the duty cycle is calculated using the duty cycle calculation submodule. If the judgment result is that the phase difference is positive, the T1 time in the xor data signal is used to calculate the duty cycle. The duty cycle calculation submodule calculates the proportional relationship between the high level duration T1 and the entire cycle time, duty cycle = high level time / cycle, thereby obtaining the duty cycle value; if the judgment result is that the phase difference is negative, the T2+T3 time is used to calculate the duty cycle, and the corresponding duty cycle result is obtained according to the established calculation rules.

[0076] S204: Inputting the duty cycle calculation result into the phase difference calculation submodule to calculate the phase difference θ between the synchronous clock and the serial data, where the unit of the phase difference is radian.

[0077] S3: Input the phase difference into the clock phase shifter module to perform phase shift operation on the synchronous clock, and input the synchronous clock and serial data after phase shift processing into the '7E' detector module;

[0078] like Figure 7 As shown in the figure, the workflow of the clock phase shifter module includes:

[0079] S301: The phase difference input submodule obtains the phase difference data between the synchronous clock and the data from the phase difference calculator, and transmits it to the phase difference judgment submodule;

[0080] S302: The phase difference determination submodule compares the received phase difference data with a tolerable phase difference threshold pre-stored in a register. This threshold is determined based on system performance requirements. If the phase difference exceeds the threshold, a trigger signal is sent to the clock delay calculation submodule. If the phase difference is not greater than the threshold, a signal is directly sent to the synchronous clock output submodule, causing it to output the current synchronous clock.

[0081] S303: When the clock delay calculation submodule receives the trigger signal, it calculates the required clock delay time based on the input phase difference data and parameters such as the synchronous clock frequency. Assuming the synchronous clock frequency is f and the phase difference is θ, the delay time t = θ / (2πf). The calculation result is stored in an internal register and transmitted to the synchronous clock phase shift submodule;

[0082] S304: The synchronous clock phase shift submodule performs a phase shift on the synchronous clock signal based on the received delay time. By delaying the clock signal accordingly on the time axis, the phase of the synchronous clock signal is adjusted to precisely match the phase of the data signal. The phase-shifted synchronous clock signal is then transmitted to the edge detection and sampling point calculation submodule.

[0083] S305: The edge detection and sampling point calculation submodule performs edge detection on the received phase-shifted synchronous clock signal. When a rising or falling edge of the clock signal is detected, the sampling point's position within the data bit is calculated based on information such as the clock period and the data bit period, and the calculation result is transmitted to the sampling point determination submodule.

[0084] S306: The sampling point determination submodule compares the calculated sampling point position with the center position of the data bit to determine whether the sampling point is at the bit center. If the sampling point is at the bit center, a signal is sent to the synchronization clock output submodule to output the current synchronization clock. If the sampling point is not at the bit center, a feedback signal is sent to reacquire the phase difference data and enter a new round of adjustment process.

[0085] S307: The synchronous clock output submodule transmits the adjusted synchronous clock to the '7E' detector module according to the received signal for data sampling and processing.

[0086] S4: The '7E' detector module detects the valid frame header of the serial data and uses the zero removal controller module to perform a zero removal operation on the serial data;

[0087] S5: inputting the serial data after the zero removal operation into the serial-to-parallel converter module and the CRC checker module respectively;

[0088] S6: The serial-to-parallel converter module converts the serial data after the zero removal operation into parallel data, and inputs the parallel data into the address reader module to detect whether the current data is a valid frame. If it is a valid frame, the receiving data encoder module reads the parallel data from the serial-to-parallel converter module and stores it in the receiving buffer module, and updates the status register module;

[0089] S7: The CRC checker module reads the serial data after the zero removal operation in real time, and sends the reading result to the status register module through the receiving data encoder module at the end of the frame.

[0090] In summary, the receiver of the present invention has adaptive adjustment capabilities and can automatically calculate and adjust the required clock phase according to the changing phase angle in real time, reducing the need for human intervention and fixed calibration, greatly improving the robustness and flexibility of the system. Due to the dynamic phase adjustment function, the receiver can process the phase error in the signal in real time, reducing transmission errors caused by phase difference, and ensuring the stability and reliability of data transmission.

[0091] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. An HDLC receiver with a function of adaptively adjusting the synchronous clock phase, characterized in that: The structure of the HDLC receiver with the function of adaptively adjusting the synchronous clock phase includes: Synchronous clock input module, serial data input module, clock phase shifter module, phase difference calculator module, serial-to-parallel converter module, zero removal controller module, '7E' detector module, received data encoding module, address judgment module, CRC check module, function setting register module, receive buffer module and status register module; The synchronous clock input module is used to receive an input synchronous clock; The serial data input module is used to receive input serial data; The phase difference calculator module is used to calculate the phase difference between the synchronous clock and the serial data and transmit the phase difference to the clock phase shifter module; The clock phase shifter module performs phase shifting on the synchronous clock according to the phase difference, and inputs the synchronous clock and serial data after the phase shifting into the '7E' detector module; The clock phase shifter module includes a phase difference input submodule, a phase difference judgment submodule, a clock delay time calculation submodule, a synchronous clock phase shift submodule, an edge detection and sampling point calculation submodule, a sampling point judgment submodule and a synchronous clock output submodule; The phase difference input submodule is used to receive the phase difference output by the phase difference calculator module; The phase difference judgment submodule compares the phase difference with a pre-stored phase difference threshold. If the phase difference is greater than the threshold, a trigger signal is sent to the clock delay time calculation submodule. If the phase difference is not greater than the threshold, a signal is sent to the synchronous clock output submodule to output the current synchronous clock. The clock delay time calculation submodule is used to calculate the clock delay time and transmit it to the synchronous clock phase shift submodule; The synchronous clock phase shift submodule performs a phase shift operation on the synchronous clock according to the received delay time and transmits the phase shift operation to the edge detection and sampling point calculation submodule; The edge detection and sampling point calculation submodule performs edge detection and calculates the position of the sampling point in the serial data bit according to the received phase-shifted synchronous clock, and transmits the calculation result to the sampling point judgment submodule; The sampling point judgment submodule judges whether the sampling point position is located at the bit center. If it is located at the bit center, it sends a signal to the synchronous clock output submodule to output the current synchronous clock. If it is not located at the bit center, it sends a feedback signal to the phase difference calculator module to reacquire the phase difference data and calculate until the sampling point position is located at the bit center. The synchronous clock output submodule transmits the corresponding synchronous clock to the '7E' detector module according to the received signal; The '7E' detector module is used to detect a valid frame header of serial data; The zero removal controller module is used to perform a zero removal operation on the serial data; The serial-to-parallel converter module converts the serial data after the zero removal operation into parallel data and inputs the parallel data into the address judgment module; The address judgment module is used to judge whether the serial data after the zero removal operation is a valid frame; When it is a valid frame, the receiving data encoder receives the instruction of the function setting register module, reads the parallel data from the serial-to-parallel converter module, stores it in the receiving buffer module and updates the status register module; The CRC check module is used to perform real-time judgment on the serial data after the zero removal operation, and send the judgment result to the status register module through the receiving data encoder module at the end of the frame.

2. The HDLC receiver with the function of adaptively adjusting the synchronous clock phase according to claim 1, characterized in that: The phase difference calculator module includes an exclusive OR operation submodule, a phase difference positive and negative judgment submodule, a duty cycle calculation submodule and a phase difference calculation submodule; The XOR operation submodule is used to perform an XOR operation on the input synchronous clock and serial data to generate an XOR data signal; The phase difference positive and negative judgment submodule is used to measure the xor data signal and judge the phase difference positive and negative according to the measurement result; The duty cycle calculation submodule is used to calculate the duty cycle according to the phase difference positive and negative judgment result; The phase difference calculation submodule is used to calculate the phase difference between the synchronous clock and the serial data according to the duty cycle calculation result.

3. An operating method of an HDLC receiver with a function of adaptively adjusting a synchronous clock phase, applied to the HDLC receiver with a function of adaptively adjusting a synchronous clock phase according to any one of claims 1 to 2, characterized in that: include: Step 1: Input the synchronous clock and serial data into the synchronous clock input module and serial data input module respectively; Step 2: Use the phase difference calculator module to calculate the phase difference between the synchronous clock and the serial data; Step 3: Input the phase difference into the clock phase shifter module to perform phase shifting on the synchronous clock, and input the phase-shifted synchronous clock and serial data into the '7E' detector module; Step 4: The '7E' detector module detects the valid frame header of the serial data and uses the zero removal controller module to perform a zero removal operation on the serial data; Step 5: Input the serial data after the zero removal operation into the serial-to-parallel converter module and the CRC check module respectively; Step 6: The serial-to-parallel converter module converts the serial data after the zero removal operation into parallel data, and inputs the parallel data into the address reader module to detect whether the current data is a valid frame. If it is a valid frame, the receiving data encoder module reads the parallel data from the serial-to-parallel converter module and stores it in the receiving buffer module, and updates the status register module; Step 7: The CRC check module reads the serial data after the zero removal operation in real time, and sends the reading result to the status register module through the receiving data encoder module at the end of the frame.

4. The operating method of the HDLC receiver with the function of adaptively adjusting the synchronous clock phase according to claim 3, characterized in that: Step 2 specifically includes: Step 2.1: Perform an XOR operation on the input synchronous clock and serial data through the XOR operation submodule to obtain the xordata signal; Step 2.2: Measure the XOR data signal after the XOR operation through the phase difference positive and negative judgment submodule to obtain the high-level duration T1 of the data rising edge, the high-level duration T2 of the data falling edge, and the high-level duration T3 of the clock cycle. If the synchronous clock corresponding to T1 and T2 is low, the phase difference is judged to be positive; if the synchronous clock corresponding to T1 and T2 is high, the phase difference is judged to be negative. Step 2.3: Based on the phase difference positive and negative judgment result, the duty cycle is calculated using the duty cycle calculation submodule. If the phase difference positive and negative judgment result is positive, the duty cycle is calculated using the T1 time. If the phase difference positive and negative judgment result is negative, the duty cycle is calculated using the T2+T3 time. The duty cycle calculation formula is: Duty cycle = high level time / period; Step 2.4: Input the duty cycle calculation result into the phase difference calculation submodule to calculate the phase difference between the synchronous clock and the serial data. θ .

5. The operating method of the HDLC receiver with the function of adaptively adjusting the synchronous clock phase according to claim 3, characterized in that: Step 3 specifically includes: Step 3.1: Phase Difference θ Input the phase difference input submodule and transmit it to the phase difference judgment submodule; Step 3.2: The phase difference judgment submodule will receive the phase difference θ Compare the phase difference with the pre-stored phase difference threshold. If the phase difference is greater than the threshold, a trigger signal is sent to the clock delay time calculation submodule. If the phase difference is not greater than the threshold, a signal is sent to the synchronous clock output submodule to output the current synchronous clock. Step 3.3: After the clock delay time calculation submodule receives the trigger signal, it calculates the time delay time based on the phase difference. θ and synchronized clock frequency f Calculate the delay time of the clock, where the calculation formula of the delay time is t=θ / (2πf); Step 3.4: Input the delay time into the synchronous clock phase shift submodule, and adjust the phase by delaying the synchronous clock by the corresponding time on the time axis to ensure that the phase of the synchronous clock is consistent with the phase of the serial data; Step 3.5: Input the phase-shifted synchronous clock into the edge detection and sampling point calculation submodule. When the rising / falling edge of the synchronous clock is detected, the position of the sampling point in the data bit is calculated based on the clock period and the serial data bit period. Step 3.6: The sampling point determination submodule compares the sampling point position with the center position of the data bit. If the sampling point is located at the bit center, it sends a signal to the synchronization clock output submodule to output the current synchronization clock. If the sampling point is not located at the bit center, it sends a feedback signal to the phase difference calculator module to reacquire the phase difference data and calculate until the sampling point position is located at the bit center. Step 3.7: The synchronous clock output submodule transmits the corresponding synchronous clock to the '7E' detector module according to the received signal.

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