Precision time protocol (PTP) high-precision network time synchronization implementation method

Abstract

The invention discloses a method for realizing PTP (Precision Time Protocol) high-precision network time synchronization, which relates to the technical field of network time synchronization, and comprises the following steps: S1, an MAC (Media Access Control) layer analyzes an Ethernet message and identifies a PTP message and a type, if the PTP message is the PTP message, a DMA descriptor is filled with a timestamp for receiving the message when the MAC uploads the DMA, and the timestamp is internally maintained by an MAC controller; s2, the MAC controller is provided with a register, and the CPU is allowed to set or update the current system time; the method has a relatively simple processing flow, relatively good cross-system portability and relatively high system security; comprising the following two key points: 1, maintaining an internal high-precision timestamp through an MAC (Media Access Control) controller, and recording the sending or receiving timestamp of a sent and received PTP (Precision Time Protocol) message by the MAC controller; and secondly, after the network driving software obtains the PTP timing message and the timestamp through the DMA, the time deviation and the clock frequency difference between the time of the local system and the time of the timing equipment are calculated, and the internal clock of the MAC controller is calibrated after the calculation of the software is completed.

Description

Technical Field

[0001] The present invention relates to the technical field of network time synchronization, and in particular to a method for implementing PTP high-precision network time synchronization. Background Art

[0002] Network timing is a high-tech product for calibrating computers, control devices, etc. in automation systems. Network timing equipment obtains standard time signals from GPS satellites and transmits this information to devices that require time information in the automation system through various interface types, so that the time synchronization of the entire system can be achieved.

[0003] Usually, network time synchronization is implemented through software or PHY chip. Software implementation has low accuracy (time synchronization accuracy is at ms level) because the program is affected by CPU main frequency, system interruption, DMA transmission delay, task scheduling, etc., while time synchronization through PHY chip with time synchronization function will lead to complex circuit design or untimely system time update or only support link layer synchronization messages (not supporting IPV4 and IPV6). Summary of the invention

[0004] The purpose of the present invention is to provide a method for implementing PTP high-precision network time synchronization to solve the problems raised in the above background technology.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: a method for implementing PTP high-precision network timing, The method comprises the following steps: S1. The MAC layer parses the Ethernet message and identifies the PTP message and type. If it is a PTP message, the MAC will fill the timestamp of receiving the message in the DMA descriptor when uploading the DMA. The timestamp is maintained internally by the MAC controller. S2. The MAC controller has registers that allow the CPU to set or update the current system time. S3, every second, the MAC controller outputs a pulse signal; S4. The CPU outputs the clock to the MAC controller for maintaining the system time. The MAC controller assumes that the clock rate is 50 MHz. The CPU updates the register of the tick counter according to the actual clock rate to dynamically adjust the clock rate.

[0006] Furthermore, in step S1, the MAC controller screens and identifies the PTP message, thereby simplifying the processing logic of the Ethernet driver.

[0007] Furthermore, in step S1, the receiving timestamp of the PTP message is maintained by the MAC controller, and the time is accurate to the ns level, thereby improving the accuracy of time synchronization.

[0008] Furthermore, the circuit design is simple and can provide clocks of different rates. In step S4, the CPU can adjust the clock rate through the register, which can reduce the problem of clock instability caused by environmental problems of the crystal oscillator and improve the accuracy of timing.

[0009] Compared with the prior art, the beneficial effects achieved by the present invention are: a relatively simple processing flow, good cross-system portability and high system security; including two key points: one is that the internal high-precision timestamp is maintained by the MAC controller, and the MAC controller records the sending or receiving timestamp of the sent and received PTP messages; the second is that after the network driver software obtains the PTP synchronization message and timestamp through DMA, it calculates the time deviation and clock frequency difference between the local system time and the time of the timing device, and the software calibrates the internal clock of the MAC controller after the calculation is completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings: Figure 1 It is a flow chart of the method of the present invention.

[0011] Figure 2 The working principle diagram of the present invention is shown.

[0012] Figure 3 A workflow diagram of the present invention is shown. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] See also Figure 1-3 The present invention provides a technical solution: a method for implementing PTP high-precision network timing. The present invention is applied to the test equipment to communicate with the timing equipment through PTP network timing to maintain clock synchronization. During specific implementation, the network ports of the test equipment and the timing equipment need to be directly connected or connected to an Ethernet switch with PTP timing function to verify the PTP high-precision network timing.

[0015] The method comprises the following steps: S1. The MAC layer parses the Ethernet message and identifies the PTP message and type. If it is a PTP message, the MAC will fill the timestamp of receiving the message in the DMA descriptor when uploading the DMA. The timestamp is maintained internally by the MAC controller. S2. The MAC controller has registers that allow the CPU to set or update the current system time. S3, every second, the MAC controller outputs a pulse signal; S4. The CPU outputs the clock to the MAC controller for maintaining the system time. The MAC controller assumes that the clock rate is 50 MHz. The CPU updates the register of the tick counter according to the actual clock rate to dynamically adjust the clock rate.

[0016] Among them, in step S1, the MAC controller screens and identifies the PTP message to simplify the processing logic of the Ethernet driver.

[0017] Among them, in step S1, the receiving timestamp of the PTP message is maintained by the MAC controller, and the time is accurate to the ns level, thereby improving the accuracy of time synchronization.

[0018] The circuit design is simple and can provide clocks of different rates. In step S4, the CPU can adjust the clock rate through the register, which can reduce the problem of clock instability caused by environmental problems of the crystal oscillator and improve the accuracy of timing.

[0019] Initialize the Ethernet driver to apply for two DMA buffers. The uplink DMA is used to receive Ethernet data packets uploaded by the MAC controller, and the downlink DMA is used to send Ethernet data packets to the MAC controller. PTP messages are transmitted through the uplink DMA and downlink DMA; the network driver software processes the PTP message and calibrates the local clock offset and clock frequency. See below Figure 3 The implementation process of PTP network time synchronization is described in detail: S201, the Ethernet MAC controller receives the Ethernet data packet, puts it into the uplink DMA buffer and triggers an interrupt signal; S202, the network driver software enters the Ethernet interrupt processing program, takes out the Ethernet data packet from the uplink DMA buffer, and parses the uplink DMA descriptor; S203, the network driver software parses the uplink DMA descriptor information, and if the received Ethernet data packet is not a PTP synchronization message, it enters the S204 process, and if it is an Ethernet synchronization message, it enters the S205 process; S204, receiving Ethernet data packets and non-PTP synchronization messages, directly reporting to the Ethernet protocol stack, which is processed by the operating system and reported to the application; S205, receiving an Ethernet data packet as a PTP synchronization message, first determine whether the received PTP message is a SYNC synchronization message, if so, enter the process S206, if not, enter the process S209; S206, receiving an Ethernet data packet as a SYNC time synchronization message, which contains the system timestamp information of the timing device, parsing the timing device timestamp and comparing it with the local system timestamp (the timestamp is maintained internally by the MAC controller), if the local time and the timing device time deviation exceed 1ms, then enter the process S207, if the local time and the timing device time deviation is less than 1ms, then enter the process S208; S207: If the deviation between the local system time and the timing device time exceeds 1ms, it means that the local time calibration has not been performed or the system time has deviated. The timing device time is used as the local system time, and is set to the MAC controller, and the timing device is not replied.

[0020] S208. If the time deviation between the local system time and the timing device is less than 1ms, it means that the local time has been calibrated, and the system timestamp of the timing device and the local timestamp of the SYNC message received locally are saved. If the timestamp information of the previous SYNC message is already cached, the time difference of the timing device and the local device time difference between two consecutive SYNC messages are calculated, and the clock frequency difference between the local device and the timing device is calculated based on the time difference information, and the local clock frequency is calibrated. The network driver software fills the DELAY REQ message, and fills the content of the message into the downlink DMA buffer. After filling, the flag is written in the downlink DMA descriptor. The flag can ensure that the MAC controller fills the time of sending the message into the downlink DMA descriptor after sending the packet data.

[0021] S209. The received PTP message is a DELAY RESP message, which is a reply from the timing device to the DELAY REQ message sent locally in the S208 process.

[0022] S210, the network driver software parses the data packet and obtains the system time of the timing device in the DELAY RESP message when the timing device receives the DELAYREQ message. The network driver software parses the downlink DMA descriptor and obtains the local system time when the MAC controller sends the DELAY REQ message. Combined with the timestamp information of the SYNC message stored in process S206, the timestamp offset between the local device and the timing device is calculated and the local system time is calibrated.

[0023] S211, the uplink DMA data message processing is completed and the process execution ends.

[0024] The high-precision PTP network timing method of the present invention is described in detail above. It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention can be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program codes.

[0025] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0026] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0027] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The present invention is a block or a plurality of blocks. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for implementing PTP high-precision network timing, characterized in that: The method comprises the following steps: S1. The MAC layer parses the Ethernet message and identifies the PTP message and type. If it is a PTP message, the MAC will fill the timestamp of receiving the message in the DMA descriptor when uploading the DMA. The timestamp is maintained internally by the MAC controller. S2. The MAC controller has registers that allow the CPU to set or update the current system time. S3, every second, the MAC controller outputs a pulse signal; S4. The CPU outputs the clock to the MAC controller for maintaining the system time. The MAC controller assumes that the clock rate is 50 MHz. The CPU updates the register of the tick counter according to the actual clock rate to dynamically adjust the clock rate.

2. The method for implementing PTP high-precision network timing according to claim 1, characterized in that: In step S1, the MAC controller screens and identifies the PTP message, thereby simplifying the processing logic of the Ethernet driver.

3. The method for implementing PTP high-precision network timing according to claim 2, characterized in that: In step S1, the receiving timestamp of the PTP message is maintained by the MAC controller, and the time is accurate to the ns level.

4. The method for implementing PTP high-precision network timing according to claim 2, characterized in that: In step S4, the CPU can adjust the clock rate through the register.

Images