Rate matching method and apparatus, electronic device, chip, and storage medium

Abstract

The present disclosure provides a rate matching method and device, electronic equipment, chip and storage medium, wherein the method comprises: in response to the encoded data of PUSCH transmission satisfying a set condition, performing bit padding on the encoded data based on first padding bits to obtain padded encoded data, and storing the padded encoded data in a single-port random memory; performing a set number of rate matching processes on the padded encoded data in the single-port random memory; wherein the first padding bits are not included in the to-be-rate-matched data of any rate matching process, thereby reducing memory fragmentation and storage overhead, improving memory utilization efficiency and saving storage area, and improving rate matching throughput and accuracy.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of communication, and particularly relates to a rate matching method and device, electronic equipment, chip and storage medium. BACKGROUND

[0002] With the rapid development and wide application of communication technology, the channel transmission environment and service demand are increasingly complex and changeable. In order to cope with different channel conditions and quality of service requirements, ensure the efficiency and reliability of data transmission, and match the actual transmission capacity of the channel between the sender and the receiver, rate matching is required for the transmission data. Therefore, how to realize rate matching of the transmission data is very important. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems in the related art to some extent.

[0004] To this end, the present disclosure provides a rate matching method and device, electronic equipment, chip and storage medium, which, when the encoded data meets a set condition, uses first padding bits to pad the encoded data to obtain padded encoded data, so that the padded encoded data is an integer multiple of a storage unit, and then stores the padded encoded data in a single-port random access memory (RAM), thereby reducing memory fragmentation and storage overhead, improving memory utilization efficiency and saving storage area. Finally, multiple rate matching processes are performed on the stored padded encoded data, wherein the first padding bits are not included in the rate matching data of any rate matching process, effectively avoiding the problem of reduced rate matching throughput caused by a large proportion of the first padding bits in the rate matching data, thereby improving the rate matching throughput and accuracy.

[0005] An embodiment of the present disclosure provides a rate matching method, including: obtaining encoded data of a physical uplink shared channel (PUSCH) transmission; in response to the encoded data meeting a set condition, padding the encoded data with first padding bits to obtain padded encoded data; storing the padded encoded data in a single-port random access memory (RAM); and performing a set number of rate matching processes on the padded encoded data in the single-port RAM, wherein the first padding bits are not included in the rate matching data of any rate matching process.

[0006] Another aspect of the present disclosure provides a rate matching apparatus, comprising: an obtaining module configured to obtain encoded data of a physical uplink shared channel (PUSCH) transmission; a first padding module configured to perform bit padding on the encoded data based on first padding bits to obtain padded encoded data, in response to the encoded data satisfying a set condition; a storing module configured to store the padded encoded data into a single-port random access memory; and a processing module configured to perform a set number of rate matching processes on the padded encoded data in the single-port random access memory, wherein the data to be rate matched in any rate matching process does not include the first padding bits.

[0007] Another aspect of the present disclosure provides an electronic device, comprising: a processor, and a memory connected to the processor; the memory stores computer-executable instructions; and the processor executes the computer-executable instructions stored in the memory to implement the rate matching method according to any one of the preceding aspects.

[0008] Another aspect of the present disclosure provides a chip, comprising a processing circuit configured to perform the rate matching method according to any one of the preceding aspects.

[0009] Another aspect of the present disclosure provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are executed by a processor to implement the rate matching method according to any one of the preceding aspects.

[0010] Another aspect of the present disclosure provides a computer program product, which stores a computer program, and the computer program is executed by a processor to implement the rate matching method according to any one of the preceding aspects.

[0011] The rate matching method provided by the present disclosure comprises the following steps: obtaining encoded data of a physical uplink shared channel (PUSCH); in response to the encoded data satisfying a set condition, performing bit padding on the encoded data based on first padding bits to obtain padded encoded data; storing the padded encoded data into a single-port random memory; and performing a set number of rate matching processes on the padded encoded data in the single-port random memory; wherein the data to be rate matched in any rate matching process does not include the first padding bits. In this way, when the encoded data satisfies the set condition, the first padding bits are used to perform bit padding to obtain the padded encoded data, which is an integer multiple of the storage unit, thereby reducing memory fragmentation and storage overhead, improving memory utilization efficiency and saving storage area. Finally, the stored padded encoded data is subjected to multiple rate matching processes, wherein the data to be rate matched in any rate matching process does not include the first padding bits, effectively avoiding the problem of a decrease in the rate matching throughput caused by a large proportion of the first padding bits in the data to be rate matched, thereby improving the rate matching throughput and accuracy.

[0012] Additional aspects and advantages of the present disclosure will be made apparent from the following description, which, taken together with the accompanying drawings, describes or illustrates such aspects and advantages by way of example as described below. BRIEF DESCRIPTION OF DRAWINGS

[0013] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily appreciated from the following description, taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 A flowchart of a rate matching method provided by an embodiment of the present disclosure;

[0015] Figure 2 A flowchart of another rate matching method provided by an embodiment of the present disclosure;

[0016] Figure 3 A column transformation sequence provided by an embodiment of the present disclosure;

[0017] Figure 4 A column transformation sequence and a corresponding padding indication sequence provided by an embodiment of the present disclosure;

[0018] Figure 5 A flowchart of another rate matching method provided by an embodiment of the present disclosure;

[0019] Figure 6 A flowchart of another rate matching method provided by an embodiment of the present disclosure;

[0020] Figure 7A flowchart of another rate matching method provided by an embodiment of the present disclosure;

[0021] Figure 8 A diagram of a first target row in a first target storage address provided by an embodiment of the present disclosure;

[0022] Figure 9 A diagram of a first target row in a first target storage address provided by an embodiment of the present disclosure;

[0023] Figure 10 A flowchart of another rate matching method provided by an embodiment of the present disclosure;

[0024] Figure 11 A diagram of column transform sequence reading provided by an embodiment of the present disclosure;

[0025] Figure 12 A flowchart of another rate matching method provided by an embodiment of the present disclosure;

[0026] Figure 13 A flowchart of another rate matching method provided by an embodiment of the present disclosure;

[0027] Figure 14 A diagram of a storage structure of encoded data in a single-port RAM provided by an embodiment of the present disclosure;

[0028] Figure 15 A diagram of a structure of a rate matching apparatus provided by an embodiment of the present disclosure;

[0029] Figure 16 A block diagram of an electronic device provided by an embodiment of the present disclosure;

[0030] Figure 17 A diagram of a structure of a chip provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Embodiments of the present disclosure are described in detail below with reference to the attached drawings, which are shown by way of example, and wherein the same or similar components have the same or similar designations. The embodiments described below are examples intended to explain the present disclosure, and should not be understood as limiting the present disclosure.

[0032] In the related art, the following two schemes are mainly used to realize rate matching of transmission data. One is to not consider padding bits when taking the encoded data, and to remove the padding bits when outputting the rate matching, and to splice and output the data after removing the padding bits. Although this processing method is simple, when the proportion of padding bits in the overall data is large, the throughput of rate matching will be greatly reduced, and in the worst case, the throughput of 8 parallel rate matching is only 64% of the original. If the number of bit retransmissions is large, the processing delay will be greatly increased.

[0033] The other is to first interleave and de-pad the encoded multi-parallel bit data, and then read the rate matching. Due to the rule of "row by column" of rate matching, the order of writing and reading is different, which also means that the encoded multi-bit data needs to be stored in different addresses, so this processing method cannot be implemented using a single-port RAM. Rate matching includes one data stream and two check streams, and the maximum number of bits is 6144*3=18432 bits. Whether a single RAM is changed into a register group or a single RAM is split into multiple RAMs will bring a huge area increase.

[0034] To solve the above problems, the present disclosure provides a rate matching method, device, electronic equipment, chip and storage medium.

[0035] The rate matching method, device, electronic equipment, chip and storage medium of the embodiments of the present disclosure are described below with reference to the drawings.

[0036] Figure 1 A flowchart of a rate matching method provided by an embodiment of the present disclosure.

[0037] The present embodiment takes the rate matching method configured in the rate matching device as an example, and the rate matching device can be arranged in an electronic equipment, for example, in a terminal. It should be noted that the execution subject of the embodiments of the present disclosure can be, for example, a central processing unit (CPU) of an electronic equipment in hardware, and a related background service of an electronic equipment in software, and is not limited to this.

[0038] As shown in Figure 1 The rate matching method can include the following steps:

[0039] Step 101, obtaining encoded data of physical uplink shared channel (PUSCH) transmission.

[0040] As an example, a transport block (TB) in uplink shared channel (UL_SCH) data transmitted on a physical uplink shared channel (PUSCH) is acquired, and then cyclic redundancy check (CRC), code block segmentation and encoding are performed on the TB to obtain code block encoded data, and the code block encoded data is taken as the encoded data; wherein the code block encoded data includes a system bit stream, a first check bit stream and a second check bit stream.

[0041] As another example, a channel quality indicator (CQI) is encoded to obtain code block encoded data, and the code block encoded data is taken as the encoded data.

[0042] At step 102, in response to the encoded data satisfying a set condition, bit padding is performed on the encoded data based on first padding bits to obtain padded encoded data.

[0043] To reduce memory fragmentation and storage overhead, as a possible implementation, when the encoded data satisfies a set condition, the first padding bits are used to perform bit padding on the encoded data to obtain padded encoded data.

[0044] As a possible implementation, in response to the length of the system bit stream being a non-integer multiple of a standard storage length of a storage unit in a single-port random access memory, the first padding bits are used to pad the system bit stream to obtain a padded system bit stream; wherein the length of the padded system bit stream is an integer multiple of the standard storage length.

[0045] As another possible implementation, in response to the length of the first check bit stream being a non-integer multiple of the standard storage length, the first padding bits are used to pad the first check bit stream to obtain a padded first check bit stream; wherein the length of the padded first check bit stream is an integer multiple of the standard storage length.

[0046] As yet another possible implementation, in response to the length of the second check bit stream being a non-integer multiple of the standard storage length, the first padding bits are used to pad the second check bit stream to obtain a padded second check bit stream; wherein the length of the padded second check bit stream is an integer multiple of the standard storage length.

[0047] It should be noted that the above three possible implementations can be satisfied simultaneously, or only one or two of them can be satisfied, and the present disclosure does not make specific limitations.

[0048] In addition, it should be noted that the length of the system bit stream, the first check bit stream or the second check bit stream is equal to K+4 (where K is the length of the corresponding code block and 4 is the tail bit added by encoding), and taking the standard storage length of the storage unit as 32 bits for example, since K is an integer multiple of 8 in the communication protocol, the first padding bit is used to pad the system bit stream, the first check bit stream or the second check bit stream to obtain a padded bit stream, and the length of the padded bit stream is an integer multiple of the standard storage length, i.e., K+4+the first padding bit = an integer multiple of 32, and the length of the first padding bit is one of 4, 12, 20 and 28.

[0049] In step 103, the padded encoded data is stored in the single-port random access memory.

[0050] In order to improve the memory utilization efficiency and save the storage area, as an example, the padded encoded data is stored in a single-port RAM, where the single-port RAM allows data to be read and written through a unique port, and only one of reading or writing can be performed at a time.

[0051] In order to avoid the write conflict of the single-port random access memory, as a possible implementation, the system bit stream, the first check bit stream and the second check bit stream are written into the single-port RAM in staggered manner.

[0052] As an example, the padded system bit stream, the padded first check bit stream and the padded second check bit stream are included in the padded encoded data, and the padded system bit stream, the padded first check bit stream and the padded second check bit stream are written into the single-port RAM in sequence.

[0053] For example, the system bit stream can be stored in the single-port RAM after the CRC, and the first check bit stream and the second check bit stream are stored in the single-port RAM after the Turbo encoding, and finally the tail bit after the encoding of the system bit stream is written, and the three can be staggered in the writing time to prevent the write conflict of the single-port RAM.

[0054] In step 104, a rate matching process is performed on the padded encoded data in the single-port random access memory for a set number of times, and the data to be rate matched in any rate matching process does not include the first padding bit.

[0055] To avoid the problem of throughput rate reduction of rate matching caused by the large proportion of the first padding bits in the data to be rate matched, as an example, the stored padding encoded data is subjected to multiple rate matching processes, wherein the data to be rate matched in any rate matching process does not include the first padding bits, that is, when reading the padding encoded data from the single-port random access memory, the first padding bits are skipped, and the data to be rate matched excluding the first padding bits is subjected to rate matching.

[0056] To sum up, when the encoded data meets the set condition, the first padding bits are used for bit padding to obtain padding encoded data, which realizes that the padding encoded data is an integer multiple of the standard storage length of the storage unit, and then the padding encoded data is stored in the single-port RAM, which reduces memory fragmentation and storage overhead, improves memory utilization efficiency and saves storage area. Finally, the stored padding encoded data is subjected to multiple rate matching processes, wherein the data to be rate matched in any rate matching process does not include the first padding bits, which effectively avoids the problem of throughput rate reduction of rate matching caused by the large proportion of the first padding bits in the data to be rate matched, thereby improving the rate matching throughput rate and accuracy.

[0057] To clearly illustrate how the data to be rate matched in any rate matching process is read from the single-port random access memory in the above-mentioned embodiments, the disclosure proposes another rate matching method.

[0058] Figure 2 A flowchart of another rate matching method provided by the embodiments of the disclosure is shown.

[0059] As Figure 2 shown, reading the data to be rate matched in any rate matching process from the single-port random access memory includes the following steps:

[0060] Step 201, obtaining an interleaving matrix corresponding to the padding encoded data, and obtaining a column transformation sequence associated with the interleaving matrix.

[0061] Wherein, the elements in the column transformation sequence are used to indicate the reading position of each row in any rate matching process.

[0062] As an example, the padding encoded data is written into the interleaving matrix row by row, wherein the number of columns of the interleaving matrix can be 32, and the row and column permutation is performed on the interleaving matrix to obtain the column transformation sequence associated with the interleaving matrix. It should be noted that the column transformation sequence corresponding to the system bit stream and the first check bit stream can be the same or different, and the column transformation sequence corresponding to the first check bit stream and the column transformation sequence corresponding to the second check bit stream can be the same or different.

[0063] For example, as Figure 3 shown,Figure 3 The interleaving matrix corresponding to the column transform sequence of the first check bit stream is different from the interleaving matrix corresponding to the column transform sequence of the second check bit stream. Figure 3 In the embodiment, only the column transform sequence of the system bit stream and the column transform sequence of the first check bit stream are the same, and the column transform sequence of the first check bit stream and the column transform sequence of the second check bit stream are different. In practice, the column transform sequence of the system bit stream and the column transform sequence of the first check bit stream can also be different, and the column transform sequence of the first check bit stream and the column transform sequence of the second check bit stream can also be the same.

[0064] In step 202, the padding indication sequence matching the column transform sequence is determined according to the number of the first padding bits.

[0065] The padding indication sequence is used to indicate whether the padding encoded data at each read position is the first padding bit.

[0066] It should be noted that, taking the standard storage length of the storage unit as 32 bits as an example, the length of the first padding bit is one of 4, 12, 20, and 28, as shown in FIG. 2A. According to any value of the first padding bit, it can be determined whether the padding encoded data at each read position in the column transform sequence is the first padding bit. Figure 4 Figure 4 In the embodiment, only the padding information of the value positions of the first to eighth elements in the column transform sequence is described as an example. The padding information of the value positions of the ninth to sixteenth elements, the padding information of the value positions of the seventeenth to twenty-fourth elements, and the padding information of the value positions of the twenty-fifth to thirty-second elements are the same as the padding information of the value positions of the first to eighth elements.

[0067] In step 203, the to-be-rate-matched data of any rate matching process is obtained from the padding encoded data according to the column transform sequence and the padding indication sequence.

[0068] In order to avoid the problem of throughput rate reduction of rate matching caused by a large proportion of the first padding bit in the to-be-rate-matched data, as an example, the valid bits except the first padding bit are read from the single-port random access memory according to the column transform sequence and the padding indication sequence, and the read valid bits are taken as the to-be-rate-matched data.

[0069] ​In summary, by obtaining the interleaving matrix corresponding to the padding coded data, and obtaining the column transformation sequence associated with the interleaving matrix, wherein the elements in the column transformation sequence are used to indicate the reading position of each row in any rate matching process; according to the number of first padding bits, determining the padding indication sequence matched with the column transformation sequence; wherein the padding indication sequence is used to indicate whether the padding coded data of each reading position is the first padding bit; according to the column transformation sequence and the padding indication sequence, obtaining the to-be-rate-matched data of any rate matching process from the padding coded data, thereby, the column transformation sequence provides flexible reading position indication for the rate matching process, and the padding indication sequence realizes accurate distinction between the valid bits and the first padding bits of each reading position, and further, by combining the column transformation sequence and the padding indication sequence, the to-be-rate-matched data of the current rate matching process which does not include the first padding bit can be accurately extracted from the padding coded data.

[0070] In order to clearly illustrate how the to-be-rate-matched data of any rate matching process is obtained from the padding coded data according to the column transformation sequence and the padding indication sequence in the above-mentioned embodiments, the present disclosure proposes another rate matching method.

[0071] Figure 5 A flowchart of another rate matching method provided by the embodiments of the present disclosure.

[0072] As Figure 5 shown, obtaining the to-be-rate-matched data of any rate matching process from the padding coded data according to the column transformation sequence and the padding indication sequence includes the following steps:

[0073] Step 501, determining the first target storage address to be read of any rate matching process from the plurality of storage addresses of the single-port random access memory.

[0074] It should be noted that the storage mode of the system bit stream in the single-port RAM is different from the storage mode of the first check bit stream and the second check bit stream in the single-port RAM, and therefore, the way of obtaining the first target storage address of the system bit stream to be read and obtaining the first target storage address of the first check bit stream and the second check bit stream to be read from the plurality of storage addresses of the single-port RAM is different, which will be described in detail in subsequent embodiments.

[0075] Step 502, determining the first target row to be read and the reading position in the first target row from the first target storage address according to the column transformation sequence and the padding indication sequence.

[0076] It should be noted that, since the elements in the column transformation sequence indicate the reading position of each row in any rate matching process, and the padding indication sequence indicates whether the padding coded data of each reading position is the first padding bit, according to the column transformation sequence and the padding indication sequence, the first target row to be read in any rate matching process and the reading position in the first target row, in which the padding coded data is not the first padding bit, can be accurately located from the first target storage address.

[0077] Step 503, reading the to-be-rate-matched data of any rate matching process from the first target row according to the reading position in the first target row.

[0078] Further, based on the reading position in the first target row, the to-be-rate-matched data of any rate matching process can be accurately read from the first target row.

[0079] In summary, by determining the first target storage address to be read in any rate matching process from the plurality of storage addresses of the single-port random memory, determining the first target row to be read and the reading position in the first target row from the first target storage address according to the column transformation sequence and the padding indication sequence, and reading the to-be-rate-matched data of any rate matching process from the first target row according to the reading position in the first target row, the reading position to be read in any rate matching process can be accurately determined from the first target storage address by combining the column transformation sequence and the padding indication sequence, and the to-be-rate-matched data of any rate matching process without the first padding bit can be accurately obtained according to the reading position.

[0080] In order to clearly illustrate how the first target storage address of the system bit stream to be read in any rate matching process is determined from the plurality of storage addresses of the single-port random memory in the above-mentioned embodiments, the present disclosure proposes another rate matching method.

[0081] Figure 6 A flowchart of another rate matching method provided by the embodiments of the present disclosure.

[0082] As Figure 6 indicated, determining the first target storage address of the system bit stream to be read in any rate matching process from the plurality of storage addresses of the single-port random memory includes the following steps:

[0083] Step 601, determining the first candidate storage address to be read in any rate matching process from the plurality of storage addresses.

[0084] As an example, in response to the any rate matching process being the first rate matching process, a redundancy version number associated with the first rate matching process is acquired; according to the redundancy version number associated with the first rate matching process, a first candidate storage address to be read by the first rate matching process is determined; in response to the any rate matching process being a non-first rate matching process, according to the storage addresses where the rows read by the last rate matching process are located, a first candidate storage address to be read by the current rate matching process is determined.

[0085] That is, for the first rate matching process, the starting position of rate matching can be determined according to the redundancy version number, that is, according to the redundancy version number, the starting storage position to be read by the matching process, i.e., the first candidate storage address, can be determined; for the non-first rate matching process, according to the storage addresses where the rows read by the last rate matching process are located, the first candidate storage address to be read by the current rate matching process is determined; for example, if the storage address where the rows read by the last rate matching process are located is address 2, and there are unread rows in address 2, the first candidate storage address to be read by the current rate matching process is address 2; if there are no unread rows in address 2, the first candidate storage address to be read by the current rate matching process is address 3, address 3 is the next storage address of address 2, and address 3 and address 2 are of the same type of stored bitstream data.

[0086] Step 602, in response to the total number of rows in the first candidate storage address being less than the parallelism of any rate matching process, if there is a second candidate storage address in the plurality of storage addresses, the sum of the total number of rows in the first candidate storage address and the second candidate storage address is acquired.

[0087] Wherein, the second candidate storage address is the next storage address of the first candidate storage address, and the first candidate storage address and the second candidate storage address are used to store system bitstream.

[0088] It should be noted that the parallelism of any rate matching process is the number of data bits processed in parallel, for example, the parallelism is 8, that is, the number of data bits processed in parallel in the any rate matching process is 8, that is, 8 valid bits need to be acquired in the any rate matching process.

[0089] As an example, it is determined whether the total number of rows in the first candidate storage address (for example, a single cell of a single-port RAM can represent a row of 32-bit data) is less than the corresponding parallelism, if yes, it is determined whether there is a next storage address of the first candidate storage in the plurality of storage addresses, that is, whether the first candidate storage address is the last storage address of the stored system bitstream; wherein, the first candidate storage address and the second candidate storage address are both used to store system bitstream.

[0090] It should be understood that if the second candidate storage address is the last storage address of the storage system bit stream, the total number of rows in each row of the second candidate storage address can be less than or equal to the parallelism (for example, 8), in the case that the total number of rows in each row of the second candidate storage address is equal to the parallelism, the sum of the total number of rows in each row of the first candidate storage address that has not been read and the total number of rows in each row of the second candidate storage address is greater than the parallelism, and in the case that the total number of rows in each row of the second candidate storage address is less than the parallelism, the sum of the total number of rows in each row of the first candidate storage address that has not been read and the total number of rows in each row of the second candidate storage address can also be less than the parallelism, therefore, it is necessary to determine whether the sum of the total number of rows in each row of the first candidate storage address that has not been read and the total number of rows in each row of the second candidate storage address is greater than or equal to the parallelism.

[0091] Step 603, in the case that the sum of the total number of rows in the first candidate storage address and the second candidate storage address that has not been read is greater than or equal to the parallelism, the first candidate storage address and the second candidate storage address are taken as the first target storage address to be read by any rate matching process.

[0092] As a possible implementation, in the case that the sum of the total number of rows in the first candidate storage address and the second storage address that has not been read is greater than or equal to the parallelism, the first candidate storage address and the second candidate storage address are taken as the first target storage address to be read by any rate matching process.

[0093] As another possible implementation, in response to the sum of the total number of rows in the first candidate storage address and the second storage address that has not been read being less than the parallelism, and the any rate matching process being a non-final rate matching process, a third candidate storage address to be read by the any rate matching process is obtained; wherein the third candidate storage address is the first storage address of the storage system bit stream; the first candidate storage address, the second candidate storage address and the third candidate storage address are taken as the first target storage address to be read by the any rate matching process.

[0094] That is, in the case that the total number of rows in each row of the second candidate storage address is less than the parallelism, the sum of the total number of rows in each row of the first candidate storage address that has not been read and the total number of rows in each row of the second candidate storage address is also less than the parallelism, it is indicated that the second candidate storage address is the last storage address of the storage system bit stream, therefore, in the case that the any rate matching process is a non-final rate matching process, the first storage address of the storage system bit stream is obtained from the plurality of storage addresses, and the first candidate storage address, the second candidate storage address and the third candidate storage address are taken as the first target storage address to be read by the any rate matching process.

[0095] As a further possible implementation, in response to the sum of the total number of rows not read in the first candidate storage address and the second storage address being less than the parallelism degree, and any rate matching procedure being the last rate matching procedure, the first candidate storage address and the second candidate storage address are taken as the first target storage addresses to be read by any rate matching procedure.

[0096] That is, in the case that the total number of rows in the second candidate storage address is less than the parallelism degree, the sum of the total number of rows not read in the first candidate storage address and the total number of rows in the second candidate storage address is also less than the parallelism degree, which indicates that the second candidate storage address is the last storage address of the storage system bitstream. Since in the case that any rate matching procedure is the last rate matching procedure, only the corresponding rate matching data is obtained from the rows not read in the first candidate storage address and the second candidate storage address, the first candidate storage address and the second candidate storage address are taken as the first target storage addresses to be read by any rate matching procedure.

[0097] As a further possible implementation, in response to the total number of rows not read in the first candidate storage address being less than the parallelism degree, and the second candidate storage address not existing in the plurality of storage addresses, the first candidate storage address and the third candidate storage address are taken as the first target storage addresses to be read by any rate matching procedure in the case that any rate matching procedure is a non-last rate matching procedure.

[0098] That is, in the case that the first candidate storage address is the last storage address of the storage system bitstream, but the total number of rows not read in the first candidate storage address is less than the parallelism degree and any rate matching procedure is a non-last rate matching procedure, the first candidate storage address and the first storage address of the storage system bitstream are taken as the first target storage addresses to be read by the rate matching procedure.

[0099] As a further possible implementation, in response to the total number of rows not read in the first candidate storage address being less than the parallelism degree, and the second candidate storage address not existing in the plurality of storage addresses, the first candidate storage address is taken as the first target storage address to be read by any rate matching procedure in the case that any rate matching procedure is a last rate matching procedure.

[0100] That is, in the case that the first candidate storage address is the last storage address of the storage system bitstream, but the total number of rows not read in the first candidate storage address is less than the parallelism degree and any rate matching procedure is a last rate matching procedure, the first candidate storage address is taken as the first target storage address to be read by any rate matching procedure.

[0101] It should be noted that the above possible implementations are parallel implementations, and in actual execution, one of them is executed.

[0102] In summary, by determining a first candidate storage address to be read by any rate matching process from a plurality of storage addresses; in response to a total number of rows not read in the first candidate storage address being less than a parallelism of any rate matching process, in a case where there is a second candidate storage address in the plurality of storage addresses, obtaining a sum of a total number of rows not read in the first candidate storage address and the second candidate storage address; in a case where the sum of the total number of rows not read in the first candidate storage address and the second candidate storage address is greater than or equal to the parallelism, taking the first candidate storage address and the second candidate storage address as a first target storage address to be read by any rate matching process, thereby the first target storage address to be read by any rate matching process can be accurately determined from the plurality of storage addresses.

[0103] In order to clearly illustrate how the first target row to be read is determined from the first target storage address of the storage system bitstream according to the column transformation sequence and the padding indication sequence in the above-mentioned embodiments, the disclosure proposes another rate matching method.

[0104] Figure 7 A flowchart of another rate matching method provided by the embodiments of the disclosure.

[0105] As Figure 7 shown, determining the first target row to be read from the first target storage address of the storage system bitstream according to the column transformation sequence and the padding indication sequence includes the following steps:

[0106] Step 701, in response to a total number of rows not read in the first target storage address being greater than the parallelism, determining a second target row matching the parallelism from the rows not read in the first target storage address.

[0107] As an example, the total number of rows not read in the first target storage address is greater than the parallelism, which indicates that there are multiple first target storage addresses. According to the order of the first target storage addresses and the order of the storage units from front to back, the second target row matching the parallelism is determined from the rows not read in the first target storage addresses. For example, the first target storage addresses include address 1 and address 2, address 2 is the next storage address of address 1, address 1 includes 5 rows not read, and address 2 includes 8 rows not read. The 5 rows not read in address 1 and the first 3 rows not read in address 2 are taken as the second target row.

[0108] Step 702, determining whether there is a third target row in the second target row according to the column transformation sequence and the padding indication sequence.

[0109] The third target row is a row whose reading is the first padding bit in this rate matching process.

[0110] Furthermore, based on the column transformation sequence and the padding indicator sequence, it is determined whether the first padding bit exists in each number taken in the second target row during this rate matching process. If the first padding bit exists in each number taken in the second target row during this rate matching process, it is determined that the second target row contains a third target row; if the first padding bit does not exist in each number taken in the second target row during this rate matching process, it is determined that the second target row does not contain a third target row. The third target row is the row in which the number taken in this rate matching process is the first padding bit.

[0111] Step 703: If a third target line exists in the second target line, the next line of the second target line and the other lines in the second target line excluding the third target line are taken as the first target line to be read in this rate matching process.

[0112] As an example, when a third target line exists in the second target line, that is, when the first padding bit exists in each number taken in the second target line during this rate matching process, the next line of the second target line and the other lines in the second target line excluding the third target line are taken as the first target line to be read in this rate matching process.

[0113] For example, such as Figure 8 As shown, the first target storage address includes the last storage address of the storage system bitstream, the storage address of the second-to-last storage system bitstream, and the storage address of the first storage system bitstream. Since the first storage cell of the storage address of the first storage system bitstream contains the first padding bit in this rate matching process, meaning that the first padding bit exists in each of the data taken from the second target row in this rate matching process, the next row of the second target row (i.e., ...) is determined from the rows not read from the storage address of the first storage system bitstream. Figure 8 The row containing the number 7 in the figure is then used as the first target row to be read in this rate matching process. That is, the rows containing the numbers 0 to 7 in the figure are the first target rows to be read in this rate matching process.

[0114] As an example, in response to the total number of unread rows in the first target memory address being less than or equal to the parallelism, the unread rows in the first target memory address are taken as the first target rows to be read in any rate matching process.

[0115] For example, for the last rate matching process of the system bit stream, the first target storage address includes the last storage address of the system bit stream and the second last storage address of the system bit stream, in the case that the total number of rows of the rows not read in the first target storage address is less than or equal to the parallelism, the rows not read in the first target storage address are directly taken as the first target rows to be read in any rate matching process.

[0116] For example, for the first rate matching process of the system bit stream, the first target storage address is the first storage address of the system bit stream, in the case that the total number of rows of the rows not read in the first target storage address is equal to the parallelism, the rows not read in the first target storage address are directly taken as the first target rows to be read in any rate matching process. For example, the first storage address of the system bit stream includes 8 rows, the 8 rows in the first storage address are taken as the first target rows to be read in the rate matching process. It should be noted that when the first storage unit in the first storage address of the system bit stream includes the first padding bit, the valid bit data in the first storage unit can be obtained by traversing the corresponding column transformation sequence.

[0117] In the case that the third target row does not exist in the second target row, the second target row is taken as the first target row to be read in any rate matching process.

[0118] As another example, when the third target row does not exist in the second target row, i.e., when the first padding bit does not exist in the rows in the second target row in the rate matching process, the second target row is directly taken as the first target row to be read in any rate matching process.

[0119] For example, as shown in FIG. 7, the rows in which the numbers 0 to 7 exist do not include the third target row, and the rows in which the numbers 0 to 7 exist are directly taken as the first target rows to be read in any rate matching process. Figure 9

[0120] In summary, in response to the total number of rows of the rows not read in the first target storage address being greater than the parallelism, the second target row matching the parallelism is determined from the rows not read in the first target storage address; whether the third target row exists in the second target row is determined according to the column transformation sequence and the padding indication sequence; in the case that the third target row exists in the second target row, the next row of the second target row and the other rows in the second target row except the third target row are taken as the first target rows to be read in the rate matching process; in the case that the third target row does not exist in the second target row, the second target row is taken as the first target row to be read in any rate matching process, so that the first target row to be read in any rate matching process can be accurately and flexibly determined from the first target storage address. ​

[0121] To clearly illustrate how the first target storage address of the first and second check bit streams to be read by any rate matching process is determined from the plurality of storage addresses of the single-port random memory in the above-mentioned embodiments, the present disclosure proposes another rate matching method.

[0122] Figure 10 A flowchart of another rate matching method provided by the embodiments of the present disclosure.

[0123] As Figure 10 shown, determining the first target storage address of the first and second check bit streams to be read by any rate matching process from the plurality of storage addresses of the single-port random memory includes the following steps:

[0124] Step 1001, determining the fourth candidate storage address to be read by any rate matching process from the plurality of storage addresses.

[0125] Among the fourth candidate storage address, there are a first candidate sub-storage address and a second candidate sub-storage address, the first candidate sub-storage address is used to store the first check bit stream, and the second candidate sub-storage address is used to store the second check bit stream.

[0126] As an example, in response to the rate matching process being a first rate matching process, a redundancy version number associated with the first rate matching process is obtained; the first candidate storage address to be read by the first rate matching process is determined according to the redundancy version number associated with the first rate matching process; in response to the rate matching process being a non-first rate matching process, the first candidate storage address to be read by the rate matching process is determined according to the storage addresses where the rows read by the last rate matching process are located.

[0127] That is, for the first rate matching process, the starting position of rate matching can be determined according to the redundancy version number, that is, the starting storage position of the data to be read by the rate matching process, i.e., the fourth candidate storage address, can be determined according to the redundancy version number; for the non-first rate matching process, the fourth candidate storage address to be read by the rate matching process is determined according to the storage addresses where the rows read by the last rate matching process are located.

[0128] It should be understood that, when the first check bit stream and the second check bit stream are stored in the single-port RAM, the first check bit stream and the second check bit stream are simultaneously stored in the same storage address, for example, the bit width of the single-port RAM is 8, the 0th to 3rd storage units are used to store the first check bit stream, and the 4th to 7th storage units are used to store the second check bit stream. Therefore, the fourth candidate storage address includes the first candidate sub-storage address and the second candidate sub-storage address, the first candidate sub-storage address is used to store the first check bit stream, and the second candidate sub-storage address is used to store the second check bit stream.

[0129] To improve the rate matching efficiency, as a possible implementation manner, it is judged whether the sum of the total number of rows of each row not read in the first candidate sub-storage address and the total number of rows of each row not read in the second candidate sub-storage address is equal to the parallelism degree.

[0130] Step 1002, in response to the sum of the total number of rows of each row not read in the first candidate sub-storage address and the total number of rows of each row not read in the second candidate sub-storage address being equal to the parallelism degree, and the read position of the same row of the first candidate sub-storage address and the second candidate sub-storage address not existing at the same time, the fourth candidate storage address is taken as the first target storage address to be read in any rate matching process.

[0131] To improve the rate matching efficiency, as a possible implementation manner, it is judged whether the sum of the total number of rows of each row not read in the first candidate sub-storage address and the total number of rows of each row not read in the second candidate sub-storage address is equal to the parallelism degree.

[0132] As an example, in the case where the sum of the number of rows not read in the first candidate sub-storage address and the second candidate sub-storage address is equal to the parallelism degree, the padding indication sequence, the column transformation sequence corresponding to the first check bit stream, and the column transformation sequence corresponding to the second check bit stream are obtained, and then, in order to align the reading order of the first check bit stream and the second check bit stream, it is judged whether the first padding bit exists at the same time at the read position of the same row of the first candidate sub-storage address and the second candidate sub-storage address according to the column transformation sequence corresponding to the first check bit stream, the column transformation sequence corresponding to the second check bit stream, and the padding indication sequence.

[0133] For example, as Figure 11As shown, based on the column transformation sequence corresponding to the first check bit stream, when the 3rd column of the first check bit stream is read (the value of the first padding bit is 4), based on the column transformation sequence corresponding to the second check bit stream, when the 4th column of the second check bit is read, at this time, the case that the column of the first check bit exists the first padding bit, and the column of the second check bit does not exist the first padding bit will occur; when the first check bit reads the 31st column, the second check bit needs to read the 0th column, at this time, the case that the column of the second check bit exists the first padding bit, and the column of the first check bit does not exist the first padding bit will occur; when the first check bit reads the 1st column, the second check bit needs to read the 2nd column, at this time, the case that the column of the first check bit exists the first padding bit, and the column of the second check bit also exists the first padding bit will occur.

[0134] In order to align the reading order of the first check bit stream and the second check bit stream, as a possible implementation manner, when the first padding bit does not exist at the same row of the first candidate sub-storage address and the second candidate sub-storage address, without deleting the first padding bit read in any rate matching process in the fourth candidate storage address, the fourth candidate storage address can be taken as the first target storage address.

[0135] As another possible implementation manner, in response to the first padding bit existing at the same row of the first candidate sub-storage address and the second candidate sub-storage address, when the fifth candidate storage address exists in the plurality of storage addresses, the total number of rows of the first check bit stream not read in the fourth candidate storage address and the fifth candidate storage address is obtained; in the case that the total number of rows of the first check bit stream not read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and any rate matching process is a non-last rate matching process, the sixth candidate storage address is obtained; wherein the sixth candidate storage address is the first storage address for storing the first check bit stream and the second check bit stream; the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are taken as the first target storage address to be read in any rate matching process.

[0136] That is, according to the column transformation sequence corresponding to the first check bit stream, the column transformation sequence corresponding to the second check bit stream and the padding bit sequence, it is determined that the first padding bit exists at the same row of the first candidate sub-storage address and the second candidate sub-storage address in the read position in any rate matching process, for example, the first padding bit exists at the 0th row and the 0th column of the first candidate sub-storage address, and the first padding bit exists at the 0th row and the 1st column of the second candidate sub-storage address. Since the first padding bit exists at the same row of the first candidate sub-storage address and the second candidate sub-storage address in the read position, when reading, the first padding bit needs to be skipped, so the number of effective bits is less than the parallelism, and therefore it can be determined whether the fourth candidate storage address is the last storage address of the first check bit stream and the second check bit stream.

[0137] If not, the next storage address of the fourth candidate storage address, that is, the fifth candidate storage address, is obtained, and then it is determined whether the total number of rows of the first check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism. If not, it indicates that the total number of rows of the first check bit stream that has not been read in the fifth candidate storage address is less than half of the parallelism. When the fifth candidate storage address is the last storage address of the first check bit stream and the second check bit stream in the single-port RAM, and the rate matching process is not the last rate matching process, the first storage address of the first check bit stream and the second check bit stream, that is, the sixth candidate storage address, is obtained, and then the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are taken as the first target storage address to be read in any rate matching process.

[0138] As another possible implementation, in response to the first padding bit existing at the same row of the first candidate sub-storage address and the second candidate sub-storage address in the read position, when the fifth candidate storage address exists in the plurality of storage addresses, the total number of rows of the second check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address is obtained. When the total number of rows of the second check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and the rate matching process is not the last rate matching process, the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are taken as the first target storage address to be read in any rate matching process.

[0139] That is, the first padding bit exists at the same time in the read position of the same row of the first candidate sub-storage address and the second candidate sub-storage address, in the case that the fifth candidate storage address exists in the plurality of storage addresses, it is judged whether the total number of rows of the second check bit stream not read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, the total number of rows of the second check bit stream not read in the fifth candidate storage address is less than half of the parallelism, the fifth candidate storage address is the last storage address in which the first check bit stream and the second check bit stream are stored in the single-port RAM, and in the case that any rate matching process is a non-final rate matching process, the first storage address in which the first check bit stream and the second check bit stream are stored, i.e., the sixth candidate storage address, can be obtained, and then the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are taken as the first target storage address to be read in any rate matching process.

[0140] As another possible implementation, in the case that the total number of rows of the first check bit stream not read in the fourth candidate storage address and the fifth candidate storage address is less than half of the parallelism, and any rate matching process is a final rate matching process, the fourth candidate storage address and the fifth candidate storage address are taken as the first target storage address to be read in any rate matching process.

[0141] As another possible implementation, in the case that the total number of rows of the second check bit stream not read in the fourth candidate storage address and the fifth candidate storage address is less than half of the parallelism, and any rate matching process is a final rate matching process, the fourth candidate storage address and the fifth candidate storage address are taken as the first target storage address to be read in any rate matching process.

[0142] As another possible implementation, in the case that the total number of rows of the second check bit stream not read is less than half of the parallelism, and any rate matching process is a final rate matching process, the fourth candidate storage address and the fifth candidate storage address are taken as the first target storage address to be read in any rate matching process.

[0143] As another possible implementation, in the case that the total number of rows of the first check bit stream not read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and the total number of rows of the second check bit stream not read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, the fourth candidate storage address and the fifth candidate storage address are taken as the first target storage address to be read in any rate matching process.

[0144] As another possible implementation, in response to the fifth candidate storage address not existing in the plurality of storage addresses, and in the case that the any rate matching process is the last rate matching process, the fourth candidate storage address is taken as the first target storage address to be read by the any rate matching process.

[0145] That is, in the case that the fifth candidate storage address does not exist in the plurality of storage addresses, that is, the fourth candidate storage address is the last storage address in the single-port RAM to store the first and second check bit streams, in the case that the any rate matching process is the last rate matching process, the fourth candidate storage address is taken as the first target storage address to be read by the any rate matching process; in the case that the fifth candidate storage address does not exist in the plurality of storage addresses, in the case that the any rate matching process is not the last rate matching process, the fourth candidate storage address and the first storage address to store the first and second check bit streams (the sixth candidate storage address) are taken as the first target storage addresses to be read by the any rate matching process.

[0146] It should be noted that the above possible implementation is a parallel implementation, and in actual execution, one of them is executed.

[0147] In summary, by determining the fourth candidate storage address to be read by the any rate matching process from the plurality of storage addresses; in response to the sum of the total number of rows of the rows not read in the first and second candidate sub-storage addresses being equal to the parallelism, and the taking position of the same row of the first and second candidate sub-storage addresses being different, the fourth candidate storage address is taken as the first target storage address to be read by the any rate matching process, thereby, in the case of ensuring that the read order of the first and second check bit streams read in the any rate matching process is aligned, the first target storage address to be read by the any rate matching process is flexibly and accurately determined.

[0148] In order to clearly illustrate how the first target row to be read is determined from the first target storage address storing the first and second check bit streams according to the column transformation sequence and the padding indication sequence in the above embodiment, the present disclosure proposes another rate matching method.

[0149] Figure 12 A flowchart of another rate matching method provided by the embodiment of the present disclosure.

[0150] As Figure 12 shown, determining the first target row to be read from the first target storage address storing the first and second check bit streams according to the column transformation sequence and the padding indication sequence includes the following steps:

[0151] Step 1201, according to the column transformation sequence corresponding to the first check bit stream, the column transformation sequence corresponding to the second check bit stream and the padding indication sequence, determine whether the first padding bit exists at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address.

[0152] Wherein, the first target sub-storage address is used to store the first check bit stream, and the second target sub-storage address is used to store the second check bit stream.

[0153] In order to obtain the effective bits matching the parallel degree, as an example, by traversing the column transformation sequence corresponding to the first check bit stream, the column transformation sequence corresponding to the second check bit stream, and querying the padding indication sequence, it is determined whether the first padding bit exists at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address. For example, the first target storage address includes address 1 and address 2, and it is determined whether the first padding bit exists at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address in address 1.

[0154] Step 1202, in the case that the first padding bit exists at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, according to the fourth target row in the first target sub-storage address and the second target sub-storage address, and each row of the subsequent first target storage address of the same first target storage address, determine the first target row.

[0155] Wherein, the fourth target row is the row which is not the first padding bit in this rate matching process.

[0156] Continue to take the first target storage address including address 1 and address 2 as an example, the first padding bit exists at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address in address 1, and the row which does not include the first padding bit in the first target sub-storage address and the second target sub-storage address in address 1, and each row in address 2, as the first target row.

[0157] Step 1203, in the case that the first padding bit does not exist at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, each row of the first target storage address to be read in any rate matching process is taken as the first target row to be read in any rate matching process.

[0158] As an example, if the first padding bits do not exist at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, each row of the first target storage address to be read by any rate matching process is directly read as the first target row to be read by any rate matching process.

[0159] In order to avoid the problem of throughput rate of rate matching being reduced due to the proportion of the first padding bits in the data to be rate matched being large, as an example, if the first padding bits do not exist at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address, the intermediate data of any rate matching process is read from the first target row to be read by any rate matching process according to the read position in the first target row to be read by any rate matching process, and the first padding bits are deleted from the intermediate data to obtain the data to be rate matched of any rate matching process.

[0160] That is, when reading the first check bit stream and the second check bit stream from the single-port RAM, if the first padding bits do not exist at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address, the first padding bits are not skipped when reading, and thus the data of any rate matching process read may include the first padding bits, and therefore, when rate matching, the first padding bits are deleted from the data read by any rate matching process to obtain the data to be rate matched of any rate matching process. That is, the intermediate data of any rate matching process is read from the first target row to be read by any rate matching process, and the first padding bits are deleted to obtain the data to be rate matched of any rate matching process. In addition, the first padding bits read in any rate matching process can also be deleted when rate matching output, which is not specifically limited in the present disclosure.

[0161] In summary, by the column transformation sequence corresponding to the first check bit stream, the column transformation sequence corresponding to the second check bit stream and the padding indication sequence, it is determined whether the first padding bit exists at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address; in the case that the first padding bit exists at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, according to the fourth target row in the first target sub-storage address and the second target sub-storage address and each row of the subsequent first target storage address of the same first target storage address, the first target row is determined; in the case that the first padding bit does not exist at the same time at the read position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, each row of the first target storage address to be read in any rate matching process is taken as the first target row to be read in any rate matching process, thereby, in the case of ensuring that the read order of the first check bit stream and the second check bit stream is aligned, the first target row to be read in any rate matching process is accurately and flexibly determined from the first target storage address to be read in any rate matching process.

[0162] In order to clearly illustrate how the above-mentioned embodiment obtains the encoded data of the physical uplink shared channel (PUSCH) transmission, the present disclosure proposes another rate matching method.

[0163] Figure 13 A flowchart of another rate matching method provided by the embodiment of the present disclosure is shown in the figure.

[0164] As shown in the figure, the rate matching method includes the following steps: Figure 13

[0165] Step 1301: obtaining the TB of the PUSCH transmission, and performing cyclic redundancy check (CRC) on the TB to obtain a system bit stream containing CRC code.

[0166] In order to improve the accuracy of data transmission, as an example, the TB in the UL_SCH data of the PUSCH transmission is obtained, and CRC is performed on the TB, so that a system bit stream containing CRC code can be obtained.

[0167] Step 1302: in response to the length of the system bit stream containing CRC code being a non-integer multiple of the code block length, performing bit padding on the system bit stream containing CRC code by using the second padding bit to obtain a padded system bit stream.

[0168] ​In order to make the system bit stream containing the CRC code complete code block segmentation, as an example, when the length of the system bit stream containing the CRC code is not an integer multiple of the code block length, then the second padding bit (also known as FILL_TB) is used to pad the system bit stream containing the CRC code to obtain the padded system bit stream.

[0169] Step 1303, the padded system bit stream is code block segmented to obtain a plurality of code blocks.

[0170] Further, the padded system bit stream is code block segmented to obtain a plurality of code blocks.

[0171] Step 1304, any code block is encoded to obtain a first check bit stream and a second check bit stream corresponding to any code block.

[0172] In order to improve the reliability and anti-interference ability of data transmission, as an example, any code block is Turbo encoded to obtain a first check bit stream and a second check bit stream corresponding to any code block.

[0173] Step 1305, the system bit stream, the first check bit stream and the second check bit stream corresponding to any code block are taken as encoding data.

[0174] In order to improve the reliability of data transmission, as an example, the system bit stream, the first check bit stream and the second check bit stream corresponding to any code block are taken as encoding data.

[0175] Step 1306, in response to the encoding data satisfying a set condition, the encoding data is bit padded based on the first padding bit to obtain padded encoding data.

[0176] Step 1307, the padded encoding data is stored in a single-port random memory.

[0177] Step 1308, a set number of rate matching processes are performed on the padded encoding data in the single-port random memory; wherein the first padding bit is not included in the rate matching data to be rate matched in any rate matching process.

[0178] As a possible implementation, taking the encoding data as an example, since in the process of obtaining the code block encoding data, when the system bit stream containing the CRC code is code block segmented, the second padding bit may need to be padded to make the padded system bit stream complete code block segmentation, therefore, in order to rate match the output effective bit data, when the second padding bit is included in any code block encoding data, the rate matching data to be rate matched is rate matched to obtain an initial encoding bit sequence of the rate matching output; the second padding bit is deleted from the initial encoding bit sequence to obtain a target encoding bit sequence.

[0179] In summary, by obtaining a TB of a PUSCH transmission, and performing a cyclic redundancy check (CRC) on the TB to obtain a system bit stream containing a CRC code; in response to a length of the system bit stream containing the CRC code being a non-integer multiple of a code block length, performing bit padding on the system bit stream containing the CRC code using second padding bits to obtain a padded system bit stream; performing code block segmentation on the padded system bit stream to obtain a plurality of code blocks; and encoding any code block to obtain a first check bit stream and a second check bit stream corresponding to the any code block, the encoding data is obtained by the CRC, the code block segmentation and the encoding on the TB.

[0180] In any embodiment of the present disclosure, the rate matching method of the present embodiment can also be implemented based on the following steps:

[0181] 1. The Turbo encoded data is stored in a single-port RAM (also referred to as a single-port RAM), and the storage manner is as shown in FIG. 1, wherein one cell represents one row of 32-bit data; the bit width of the RAM is 256, and the depth is 74, wherein the system bits are stored in the RAM addresses 0-24, the first check bit stream or the second check bit stream is stored in the RAM addresses 25-73, the first check bit stream occupies 0-127 bits of each storage address, and the second check bit stream occupies 128-255 bits of each storage address. Figure 14

[0182] It should be noted that the bit width of the single-port RAM is determined based on the parallelism of the rate matching, and the rate matching of the present technical solution is 8 parallelism. Since the rate matching follows the read-write rule listed in the row, that is, 8 rows of 1-bit data (8 rows of system bits, or a combination of 4 rows of first check bits and 4 rows of second check bits) need to be read at a time. Therefore, the bit width of the single-port RAM is selected as 32*8=256 bits. As for the depth of the RAM, the number of rows of the system bit stream, the first check bit stream or the second check bit stream is at most 193, so the address depth required for storing the system bit stream is ceil(193*32 / 256)=25, the address depth required for storing the first check bit stream or the second check bit stream is ceil(2*193*32 / 256)=49, and the total address depth required is 25+49=74.

[0183] In addition, it should be noted that the system bit stream can be stored in the RAM after the CRC, and the check bit stream can be stored in the RAM after the Turbo encoding, and finally the tail bits after the encoding of the system bit stream are written. The three can be written at different times to prevent write conflicts of the RAM.​

[0184] 2. Store the RAM address 0 and address 25 (corresponding to the 0 address of the system bit stream and the 0 address of the first second check bit stream) into two registers (ram_rdat_first) in advance;

[0185] 3. Calculate the row and column positions (row0-7, column0-7) of the 8 bits to be taken out in this rate matching, and select the row and column positions of the 8 bits without skipping the padding bits (FILL_32B) added in the rate matching, but without skipping the padding bits (FILL_TB) added in the CB segmentation;

[0186] As an example, if the 8 bits are located in the same column, the row positions of the 8 bits can be easily obtained (rowN=row0+N). If the 8-parallel rate matching can span multiple columns, the number of the spanned columns is related to the difference N between bitN and bit0 (bitN=bit0+N) and the effective number of rows in each column. If there is a padding bit FILL_32B (the first padding bit) in a column, the effective number of rows in the column is the total number of rows minus 1. Because the padding bits are related to the effective number of rows in each column, it is necessary to know whether there is a padding bit FILL_32B in the spanned columns.

[0187] It should be noted that when generating the row and column positions of the first check bit stream and the second check bit stream, the even bits (0, 2, 4, 6) are fixed to select the first check bits, and the odd bits (bit1, 3, 5, 7) are fixed to select the second check bits. The bit reading also needs to skip FILL_32B.

[0188] 4. Take the address of row0 plus 1 as the read address of the RAM, read the RAM data (ram_rdat) corresponding to the address, and take a beat of the ram_rdat to obtain ram_rdat_d1; that is, ram_rdat_d1 is the value of ram_rdat after a clock cycle delay, that is, data register of ram_rdat to obtain ram_rdat_d1;

[0189] How to select the read address of the RAM:

[0190] Generally, 8 bits are distributed in two different addresses, and only when 8 bits have data stored in the first address, 8 bits are distributed in three different addresses, so in the first step of rate matching, the data in the 0 address of the system bit stream, the first check bit stream and the second check bit stream need to be pre-stored (ram_rdat_first). The address of row0 is added 1 as the read address of the RAM, and the corresponding address of the RAM data (ram_rdat) is read, and ram_rdat is tapped to obtain ram_rdat_d1; the 8-bit data to be read must be located in ram_rdat_first, ram_rdat and ram_rdat_d1, and the corresponding row and column number of the bit is selected for reading.

[0191] The bit reading of the first and second check bits is similar to that of the system bits, which will not be described here.

[0192] 5. According to the row and column position of the 8 bits, the corresponding bits are taken out from ram_rdat_first / ram_rdat / ram_rdat_d1;

[0193] It should be noted that at the junction of the system bit stream and the check bit stream, there may be a scenario where the read system bits are less than 8 bits. In this case, the 8-bit data read in the same cycle (i.e. a rate matching process) does not cross the boundary of the system bit stream and the check bit stream, and only valid system bit data or check bit data is read. For example, if there are only 3 bits left in the system bit stream, only 3 bits are read this time, and the remaining 5 bits are considered invalid bits and are discarded after reading and then spliced with the check bits. The reason why the system bit stream and the check bit stream are not required to be read in the same cycle is that the reading rules of the two are different (the first check bit stream and the second check bit stream are output alternately, and the system bit stream is directly output), and the other reason is that the frequency of the system bit stream and the check bit stream across is low, and the influence on the overall delay is not obvious;

[0194] In addition, it should be noted that the column transformation rule of the second check bit is different from that of the first check bit, and some special processing is required in the specific implementation. The column transformation rules of the two are as shown in Figure 4

[0195] ​It can be found that when the first check bit stream reads 3 / 19 / 11 / 27, the column read by the second check bit stream is 4 / 20 / 12 / 28, at this time, the column of the first check bit stream exists a padding bit (the first padding bit), while the column of the second check bit stream does not exist a padding bit (the first padding bit). When the first check bit stream reads the 31st column, the second check bit stream needs to read the 0th column, at this time, the column of the second check bit stream exists a padding bit, while the column of the first check bit stream does not exist a padding bit, these two scenarios will disturb the reading order of the first and second check bits.

[0196] In order to prevent the disturbance of the order, for the above two scenarios, the padding bit is not skipped when reading, so that the reading order of the first check bit stream and the second check bit stream is aligned, and the first check bit stream exists a padding bit is taken as an example to illustrate:

[0197] The first check bit stream does not skip the padding bit when reading the FILL_32B-1 column, so that the reading order of the second check bit is aligned, the read bit is regarded as an invalid bit, and is removed when rate matching output.

[0198] 6. Determine whether the 8 extracted bits are valid bits, and remove the invalid bits including the FILL_TB;

[0199] After 8-bit data is read from the RAM, the validity of the 8-bit data needs to be determined, and the invalid bits are removed. The invalid bits can be summarized as the following three kinds:

[0200] (1) The read bit is a padding bit FILL_TB;

[0201] (2) The read bit is located at the invalid position of the junction of the system bit and the check bit;

[0202] (3) The read bit is the bit that needs to be removed when the first and second check bits are read specially;

[0203] 7. The valid bits are spliced to output 8-bit valid data as the output of rate matching.

[0204] As an example, after adding 24-bit CRC to the transmission data, the length is 57, 7-bit FILL_TB needs to be added to form a 64-bit CB block, and then 4-bit tail bits need to be added, and 28-bit padding bits FILL_32B need to be additionally added for rate matching to form 96 bits, and the data throughput rate is (57+4) / 96=63.5%;

[0205] As another example, after adding a 24-bit CRC to the transmitted data, the length is 41. It is necessary to add 7 bits of FILL_TB to form a CB block of length 48. After adding 4 bits of tail bits, an additional 12 bits of padding bits FILL_32B are needed for rate matching (this padding bit will be skipped when reading). Its data throughput is (41+4) / (41+4+7)=86.5%.

[0206] To visually demonstrate the throughput comparison between the comparative schemes in related technologies and this scheme, Table 1 shows the throughput comparison results of the comparative schemes and this scheme when the TB+CRC length ranges from 40 to 100.

[0207] Table 1 compares the throughput of the proposed and alternative schemes when the TB+CRC length ranges from 40 to 100.

[0208]

[0209]

[0210] The beneficial effects of this solution include: compared with direct data retrieval, this solution significantly improves the throughput of rate matching, increasing the throughput from 63.5% to 86.5% in extreme scenarios; compared with the solution of first removing padding bits to store data and then reading it, this solution only requires a single-port RAM, which greatly optimizes the storage area.

[0211] To achieve the above embodiments, this disclosure also proposes a rate matching device.

[0212] Figure 15 This is a schematic diagram of a rate matching device provided in an embodiment of the present disclosure.

[0213] like Figure 15 As shown, the rate matching device 1500 includes: an acquisition module 1510, a first filling module 1520, a storage module 1530, and a processing module 1540.

[0214] The system includes: an acquisition module 1510 for acquiring encoded data transmitted via the Physical Uplink Shared Channel (PUSCH); a first padding module 1520 for padding the encoded data based on a first padding bit in response to the encoded data meeting a set condition, to obtain padded encoded data; a storage module 1530 for storing the padded encoded data in a single-port random access memory (SRAM); and a processing module 1540 for performing a set number of rate matching processes on the padded encoded data in the SRAM; wherein the first padding bit is not included in the data to be rate matched in any rate matching process.

[0215] As a possible implementation manner of the embodiment of the present disclosure, any rate matching process comprises: reading data to be rate matched in any rate matching process from the single-port random memory; wherein the data to be rate matched does not include the first padding bit; and performing rate matching on the data to be rate matched to obtain a target coded bit sequence obtained by any rate matching process.

[0216] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to obtain an interleaving matrix corresponding to the padding coded data, and obtain a column transformation sequence associated with the interleaving matrix; wherein an element in the column transformation sequence is used to indicate a reading position of each row in any rate matching process; determine a padding indication sequence matched with the column transformation sequence according to the number of the first padding bits; wherein the padding indication sequence is used to indicate whether the padding coded data in each reading position is the first padding bit; and obtain the data to be rate matched in any rate matching process from the padding coded data according to the column transformation sequence and the padding indication sequence.

[0217] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to determine a first target storage address to be read in any rate matching process from a plurality of storage addresses of the single-port random memory; determine a first target row to be read and a reading position in the first target row in the first target storage address according to the column transformation sequence and the padding indication sequence; and read the data to be rate matched in any rate matching process from the first target row according to the reading position in the first target row.

[0218] As a possible implementation manner of the embodiment of the present disclosure, the coded data comprises a plurality of code block coded data, and any code block coded data comprises a system bit stream; the processing module 1540 is configured to determine a first candidate storage address to be read in any rate matching process from a plurality of storage addresses; in response to a total number of rows in each row not read in the first candidate storage address being less than a parallelism degree of any rate matching process, in a case that there is a second candidate storage address in the plurality of storage addresses, obtain a sum of the total number of rows in each row not read in the first candidate storage address and the second candidate storage address; wherein the second candidate storage address is a next storage address of the first candidate storage address, and the first candidate storage address and the second candidate storage address are used to store the system bit stream; and in a case that the sum of the total number of rows in each row not read in the first candidate storage address and the second candidate storage address is greater than or equal to the parallelism degree, take the first candidate storage address and the second candidate storage address as a first target storage address to be read in any rate matching process.

[0219] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to any rate matching process being a first rate matching process, acquire a redundancy version number associated with the first rate matching process; and determine a first candidate storage address to be read by the first rate matching process according to the redundancy version number associated with the first rate matching process.

[0220] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to any rate matching process being a non-first rate matching process, determine a first candidate storage address to be read by the non-first rate matching process according to storage addresses where rows read by a previous rate matching process are located.

[0221] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to a sum of total rows not read in the first candidate storage address and the second storage address being less than the parallelism degree, and any rate matching process being a non-last rate matching process, acquire a third candidate storage address to be read by any rate matching process; the third candidate storage address is a storage address of a first storage system bit stream; and the first candidate storage address, the second candidate storage address, and the third candidate storage address are taken as the first target storage address to be read by any rate matching process.

[0222] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to a sum of total rows not read in the first candidate storage address and total rows not read in the second storage address being less than the parallelism degree, and any rate matching process being a last rate matching process, take the first candidate storage address and the second candidate storage address as the first target storage address to be read by any rate matching process.

[0223] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to total rows not read in the first candidate storage address being less than the parallelism degree, and the second candidate storage address not existing in the plurality of storage addresses, in a case where any rate matching process is a non-last rate matching process, take the first candidate storage address and a third candidate storage address as the first target storage address to be read by any rate matching process.

[0224] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to total rows not read in the first candidate storage address being less than the parallelism degree, and the second candidate storage address not existing in the plurality of storage addresses, in a case where any rate matching process is a last rate matching process, take the first candidate storage address as the first target storage address to be read by any rate matching process.

[0225] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to the total number of the unread rows in the first target storage address being greater than the parallelism, determine a second target row matching the parallelism from the unread rows in the first target storage address; determine whether a third target row exists in the second target row according to the column transformation sequence and the padding indication sequence, wherein the third target row is a row from which the first padding bit is read in the current rate matching process; and in the case that the third target row exists in the second target row, take the next row of the second target row and the other rows of the second target row except the third target row as the first target rows to be read in the current rate matching process.

[0226] As a possible implementation manner of the embodiment of the present disclosure, in the case that the third target row does not exist in the second target row, take the second target row as the first target row to be read in any rate matching process.

[0227] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to the total number of the unread rows in the first target storage address being less than or equal to the parallelism, take the unread rows in the first target storage address as the first target rows to be read in any rate matching process.

[0228] As a possible implementation manner of the embodiment of the present disclosure, any code block coded data includes a first check bit stream and a second check bit stream, and the processing module 1540 is configured to determine a fourth candidate storage address to be read in any rate matching process from a plurality of storage addresses; wherein the fourth candidate storage address includes a first candidate sub-storage address and a second candidate sub-storage address, the first candidate sub-storage address is used to store the first check bit stream, and the second candidate sub-storage address is used to store the second check bit stream; in response to the total number of the unread rows in the first candidate sub-storage address and the second candidate sub-storage address being equal to the parallelism, and the first padding bit not existing at the same row of the first candidate sub-storage address and the second candidate sub-storage address at different read positions, take the fourth candidate storage address as the first target storage address to be read in any rate matching process.

[0229] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to the first padding bit existing at the same read position of the same row of the first candidate sub-storage address and the second candidate sub-storage address, and in the case that the fifth candidate storage address exists in the plurality of storage addresses, acquire the total number of rows of the first check bit stream that is not read in the fourth candidate storage address and the fifth candidate storage address; the fifth candidate storage address is a next storage address of the fourth candidate storage address, and the fifth candidate storage address is used to store the first check bit stream and the second check bit stream; in the case that the total number of rows of the first check bit stream that is not read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and any rate matching process is a non-last rate matching process, acquire the sixth candidate storage address; the sixth candidate storage address is the first storage address in which the first check bit stream and the second check bit stream are stored; and the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are used as the first target storage address to be read in any rate matching process.

[0230] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to the first padding bit existing at the same read position of the same row of the first candidate sub-storage address and the second candidate sub-storage address, and in the case that the fifth candidate storage address exists in the plurality of storage addresses, acquire the total number of rows of the second check bit stream that is not read in the fourth candidate storage address and the fifth candidate storage address; and in the case that the total number of rows of the second check bit stream that is not read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and any rate matching process is a non-last rate matching process, the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are used as the first target storage address to be read in any rate matching process.

[0231] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in the case that any of the following conditions is met, the fourth candidate storage address and the fifth candidate storage address are used as the first target storage address to be read in any rate matching process: the total number of rows of the first check bit stream that is not read is less than half of the parallelism, and any rate matching process is a last rate matching process; the total number of rows of the second check bit stream that is not read is less than half of the parallelism, and any rate matching process is a last rate matching process; the total number of rows of the first check bit stream that is not read is greater than or equal to half of the parallelism, and the total number of rows of the second check bit stream that is not read is greater than or equal to half of the parallelism.

[0232] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to the fifth candidate storage address not existing in the plurality of storage addresses, and in the case that the last rate matching process is any rate matching process, take the fourth candidate storage address as the first target storage address to be read in any rate matching process.

[0233] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to determine, according to the column transformation sequence corresponding to the first check bit stream, the column transformation sequence corresponding to the second check bit stream, and the padding indication sequence, whether the first padding bit exists at the same read position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address; wherein the first target sub-storage address is used to store the first check bit stream, and the second target sub-storage address is used to store the second check bit stream; in the case that the first padding bit exists at the same read position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, determine the first target row according to the fourth target row in the first target sub-storage address and the second target sub-storage address, and each row of the subsequent first target storage address of the same first target storage address; wherein the fourth target row is a row whose read value is not the first padding bit in the current rate matching process.

[0234] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to take each row of the first target storage address to be read in any rate matching process as the first target row to be read in any rate matching process.

[0235] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to the first padding bit not existing at the same read position of the same row of the first target sub-storage address and the second target sub-storage address, read the intermediate data of any rate matching process from the first target row to be read in any rate matching process according to the read position in the first target row to be read in any rate matching process; and delete the first padding bit from the intermediate data to obtain the rate matching data to be rate matched in any rate matching process.

[0236] As a possible implementation manner of the embodiment of the present disclosure, the acquisition module 1510 is configured to acquire a TB of a PUSCH transmission, and performs cyclic redundancy check (CRC) on the TB to obtain a system bit stream containing a CRC code; in response to a length of the system bit stream containing the CRC code being a non-integer multiple of a code block length, performs bit padding on the system bit stream containing the CRC code by using second padding bits to obtain a padded system bit stream; performs code block segmentation on the padded system bit stream to obtain a plurality of code blocks; encodes any code block to obtain a first check bit stream and a second check bit stream corresponding to the code block; and takes the system bit stream, the first check bit stream and the second check bit stream corresponding to any code block as the encoded data.

[0237] As a possible implementation manner of the embodiment of the present disclosure, the first padding module 1520 is configured to, in response to a length of the system bit stream being a non-integer multiple of a standard storage length of a storage unit in the single-port random access memory, pad the system bit stream by using the first padding bits to obtain a padded system bit stream; wherein the length of the padded system bit stream is an integer multiple of the standard storage length; and / or, in response to a length of the first check bit stream being a non-integer multiple of the standard storage length, pad the first check bit stream by using the first padding bits to obtain a padded first check bit stream; wherein the length of the padded first check bit stream is an integer multiple of the standard storage length; and / or, in response to a length of the second check bit stream being a non-integer multiple of the standard storage length, pad the second check bit stream by using the first padding bits to obtain a padded second check bit stream; wherein the length of the padded second check bit stream is an integer multiple of the standard storage length.

[0238] As a possible implementation manner of the embodiment of the present disclosure, the storage module 1530 is configured to sequentially write the padded system bit stream, the padded first check bit stream and the padded second check bit stream into the single-port random access memory.

[0239] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is configured to, in response to the second padding bits being included in the encoded data, perform rate matching on the to-be-rate-matched data to obtain an initial encoded bit sequence of rate matching output; and delete the second padding bits from the initial encoded bit sequence to obtain a target encoded bit sequence.

[0240] The rate matching device provided by the embodiment of the present disclosure, by using the first padding bits to perform bit padding when the encoded data meets the set condition, obtaining padded encoded data, realizes that the padded encoded data is an integer multiple of the storage unit, and then stores the padded encoded data into the single-port RAM, reduces the memory fragmentation and storage overhead, improves the memory utilization efficiency and saves the storage area, and finally, performs multiple rate matching processes on the stored padded encoded data, wherein the to-be-rate-matched data of any rate matching process does not include the first padding bits, effectively avoiding the problem that the throughput rate of rate matching may be reduced when the proportion of the first padding bits in the to-be-rate-matched data is large, thereby improving the rate matching throughput rate and accuracy.

[0241] To achieve the above-mentioned embodiments, the present disclosure further provides an electronic device, comprising a processor, and a memory connected with the processor in communication; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement the rate matching method as described in the foregoing method embodiments.

[0242] To achieve the above-mentioned embodiments, the present disclosure further provides a chip, comprising a processing circuit, the processing circuit is configured to execute the rate matching method as described in the foregoing method embodiments.

[0243] To achieve the above-mentioned embodiments, the present disclosure further provides a computer readable storage medium, the computer readable storage medium stores computer execution instructions, the computer execution instructions are executed by the processor to implement the rate matching method as described in the foregoing method embodiments.

[0244] To achieve the above-mentioned embodiments, the present disclosure further provides a computer program product, the computer program is stored on the computer program product, the computer program is executed by the processor to implement the rate matching method as described in the foregoing method embodiments.

[0245] Figure 16 A block diagram of an electronic device provided by an embodiment of the present disclosure is provided. For example, the electronic device 1600 can be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0246] Reference Figure 16 The electronic device 1600 can include one or more of the following components: a processing component 1602, a memory 1604, a power component 1606, a multimedia component 1608, an audio component 1610, an input / output (I / O) interface 1612, a sensor component 1614, and a communication component 1616.

[0247] The processing component 1602 generally controls the overall operation of the electronic device 1600, such as the operation associated with displaying, making phone calls, transmitting and receiving data, camera operations, and recording operations. The processing component 1602 can include one or more processors 1620 to execute instructions and to complete the steps of the methods described above in whole or in part. Further, the processing component 1602 can include one or more modules to facilitate interaction between the processing component 1602 and other components. For example, the processing component 1602 can include a multimedia module to facilitate the interaction between the multimedia component 1608 and the processing component 1602.

[0248] The memory 1604 is configured to store various types of data to support the operations of the electronic device 1600. Examples of these data include instructions for any application or method operating on the electronic device 1600, contact data, phonebook data, messages, pictures, videos, and the like. The memory 1604 can be implemented by any type of volatile or nonvolatile memory, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0249] The power component 1606 provides power to the various components of the electronic device 1600. The power component 1606 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 1600.

[0250] The multimedia component 1608 includes a screen providing an output interface between the electronic device 1600 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes the touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide, and a gesture on the touch panel. The touch sensors can not only sense a boundary of a touching or sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 1608 includes a front camera and / or a rear camera. The front camera and / or the rear camera can receive external multimedia data when the electronic device 1600 is in an operation mode, such as a shooting mode or a video mode. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0251] The audio component 1610 is configured to output and / or input audio signals. For example, the audio component 1610 includes a microphone (MIC) that is configured to receive an external audio signal when the electronic device 1600 is in a particular mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 1604 or transmitted via the communication component 1616. In some embodiments, the audio component 1610 also includes a speaker for outputting audio signals.

[0252] The I / O interface 1612 provides an interface between the processing component 1602 and peripheral interface modules, which can include a keypad, a click wheel, buttons, and so on. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0253] The sensor component 1614 includes one or more sensors for providing status assessments of various aspects of the electronic device 1600. For example, the sensor component 1614 can detect an open / closed position of the electronic device 1600, relative positioning of components, such as a display and a keypad of the electronic device 1600, a change of location of the electronic device 1600 or a component of the electronic device 1600, the presence or absence of user contact with the electronic device 1600, the orientation or acceleration / deceleration of the electronic device 1600, and a temperature change of the electronic device 1600. The sensor component 1614 can include an orientation sensor, an acceleration sensor, a proximity sensor, a gesture sensor, a biometric sensor, a temperature / humidity sensor, an illumination sensor, and / or an interaction sensor.

[0254] The communication component 1616 is configured to facilitate wired or wireless communication between the electronic device 1600 and external devices. The electronic device 1600 can access a wireless network based on a corresponding communication standard, such as WiFi, 4G, or 5G, or a combination thereof. In an example embodiment, the communication component 1616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the communication component 1616 further includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) techniques, infrared data association (IrDA) techniques, ultra-wideband (UWB) techniques, Bluetooth (BT) techniques, and other techniques.

[0255] In exemplary embodiments, the electronic device 1600 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic elements for performing the above-described methods.

[0256] In exemplary embodiments, a non-transitory computer-readable storage medium including instructions, such as the memory 1604 including instructions, is also provided, which can be executed by the processor 1620 of the electronic device 1600 to complete the above-described methods. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0257] Figure 17 is a structural schematic diagram of a chip proposed by embodiments of the present disclosure. Referring to Figure 17 , a structural schematic diagram of the chip 1700 is shown, but is not limited thereto.

[0258] The chip 1700 includes a processing circuit 1701 configured to perform any of the above methods.

[0259] In some embodiments, the chip 1700 further includes one or more interface circuits 1702. Optionally, the interface circuit 1702 is connected with the memory 1703, and the interface circuit 1702 can be used to receive signals from the memory 1703 or other devices, and the interface circuit 1702 can be used to send signals to the memory 1703 or other devices. For example, the interface circuit 1702 can read instructions stored in the memory 1703 and send the instructions to the processing circuit 1701.

[0260] In some embodiments, the interface circuit 1702 performs at least one of the communication steps such as sending and / or receiving in the above-described methods, and the processing circuit 1701 performs other steps.

[0261] In some embodiments, the terms of interface circuit, interface, transceiver pin, transceiver, etc. can be replaced with each other.

[0262] In some embodiments, the chip 1700 further includes one or more memories 1703 for storing instructions. Optionally, all or part of the memory 1703 can be outside the chip 1700.

[0263] In the description of the disclosure, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the disclosure. In the description of the disclosure, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, a person skilled in the art can combine and combine different embodiments or examples described in the specification and the features of different embodiments or examples without contradiction.

[0264] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the disclosure, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified.

[0265] Any process or method descriptions in flow charts or otherwise described herein represent embodiments that can be understood as a module, segment, or portion of code that includes one or more executable instructions for implementing the specified logical function or process. The scope of the preferred embodiments of the disclosure includes additional implementation in which the functions described in the illustrated or discussed order are performed in a different order, including substantially simultaneously, or in reverse order, according to the functions involved, which should be understood by those skilled in the art to which the embodiments of the disclosure belong.

[0266] The logic and / or steps represented in flow diagrams or otherwise described herein, for example, can be considered as a sequence of instructions to implement logic functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device, such as a computer-based system, processor- containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this specification, a "computer-readable medium" can be any means that can contain, store, communicate, propagate or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be a machine-readable storage device (e.g., magnetic, optical or other) a machine-readable storage diskette (e.g., floppy disk, optical disk, CD- ROM, etc.), a machine- readable storage card (e.g., PCMCIA card, etc.), a machine-readable storage tape (e.g., magnetic tape, optical tape, etc.), a machine-readable storage medium (e.g., RAM, ROM, etc.), a machine-readable signal (e.g., electrical, optical, etc.), a machine-readable medium (e.g., carrier wave, etc.) or any other suitable medium or means of embodying the program. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a RAM, a ROM, an EPROM, a FLASH memory card, an optical fiber, and a portable compact disc read-only memory (CD-ROM). Additionally, the computer-readable medium can be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example, via optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and stored in a computer memory.

[0267] It should be understood that various aspects of the disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. As such, if desired, the various steps or methods can be implemented in hardware (e.g., as opposed to software) and / or in a different manner than is described. For example, any of the following can be used to implement the various techniques and / or methods, including, but not limited to: discrete logic circuitry having logic gates for implementing logic functions upon data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), and / or the like.

[0268] Those skilled in the art can understand that all or part of the steps carried out by the above-mentioned embodiment methods can be completed by programs instructing related hardware, and the programs can be stored in a computer-readable storage medium. When the programs are executed, one or a combination of the steps of the method embodiments is included.

[0269] In addition, each functional unit in each embodiment of the present disclosure can be integrated in one processing module, or each unit can exist physically separately, or two or more units can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module. When the integrated module is realized in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer readable storage medium.

[0270] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A rate matching method, characterized by, The method comprises: obtaining encoded data of a physical uplink shared channel (PUSCH) transmission; in response to the encoded data satisfying a set condition, performing bit padding on the encoded data based on first padding bits to obtain padded encoded data; storing the padded encoded data into a single-port random memory; performing a set number of rate matching processes on the padded encoded data in the single-port random memory; wherein the data to be rate matched in any rate matching process does not include the first padding bits.

2. The method of claim 1, wherein, The any rate matching process comprises: reading the data to be rate matched in the any rate matching process from the single-port random memory; wherein the data to be rate matched does not include the first padding bits; performing rate matching on the data to be rate matched to obtain a target encoded bit sequence obtained by the any rate matching process.

3. The method of claim 2, wherein, The reading the data to be rate matched in the any rate matching process from the single-port random memory comprises: obtaining an interleaving matrix corresponding to the padded encoded data, and obtaining a column transformation sequence associated with the interleaving matrix; wherein elements in the column transformation sequence are used to indicate the reading position of each row in the any rate matching process; determining a padding indication sequence matched with the column transformation sequence according to the number of the first padding bits; wherein the padding indication sequence is used to indicate whether the padded encoded data at each reading position is a first padding bit; obtaining the data to be rate matched in the any rate matching process from the padded encoded data according to the column transformation sequence and the padding indication sequence.

4. The method of claim 3, wherein, The obtaining the data to be rate matched in the any rate matching process from the padded encoded data according to the column transformation sequence and the padding indication sequence comprises: determining a first target storage address to be read in the any rate matching process from a plurality of storage addresses of the single-port random memory; determining a first target row to be read and a reading position in the first target row from the first target storage address according to the column transformation sequence and the padding indication sequence; reading the data to be rate matched in the any rate matching process from the first target row according to the reading position in the first target row.

5. The method of claim 4, wherein, The encoded data comprises a plurality of code block encoded data, and any code block encoded data comprises a system bit stream. The determining the first target storage address to be read in the any rate matching process from the plurality of storage addresses of the single-port random memory comprises: determining a first candidate storage address to be read in the any rate matching process from the plurality of storage addresses; in response to the total number of rows in each row not read in the first candidate storage address being less than the parallelism degree of the any rate matching process, in a case that there is a second candidate storage address in the plurality of storage addresses, obtaining the sum of the total number of rows in each row not read in the first candidate storage address and the second candidate storage address; wherein the second candidate storage address is a next storage address of the first candidate storage address, and the first candidate storage address and the second candidate storage address are used to store the system bit stream. if the sum of the total number of rows in each row not read in the first candidate storage address and the second candidate storage address is greater than or equal to the parallelism degree, the first candidate storage address and the second candidate storage address are taken as the first target storage address to be read by the any rate matching process.

6. The method of claim 5, wherein, The method further comprises: in response to the any rate matching process being a first rate matching process, obtaining a redundancy version number associated with the first rate matching process; determining the first candidate storage address to be read by the first rate matching process according to the redundancy version number associated with the first rate matching process.

7. The method of claim 5, wherein, The method further comprises: in response to the any rate matching process being a non-first rate matching process, determining the first candidate storage address to be read by the non-first rate matching process according to the storage address where each row read by a previous rate matching process is located.

8. The method of claim 5, wherein, The method further comprises: in response to the sum of the total number of rows in each row not read in the first candidate storage address and the second candidate storage address being less than the parallelism degree, and the any rate matching process being a non-last rate matching process, obtaining a third candidate storage address to be read by the any rate matching process; wherein the third candidate storage address is a first storage address where the system bit stream is stored; the first candidate storage address, the second candidate storage address and the third candidate storage address are taken as the first target storage address to be read by the any rate matching process.

9. The method of claim 5, wherein, The method further comprises: in response to the sum of the total number of rows in each row not read in the first candidate storage address and the second candidate storage address being less than the parallelism degree, and the any rate matching process being a last rate matching process, the first candidate storage address and the second candidate storage address are taken as the first target storage address to be read by the any rate matching process.

10. The method of claim 8, wherein, The method further comprises: in response to the total number of rows in each row not read in the first candidate storage address being less than the parallelism degree, and the second candidate storage address not existing in the plurality of storage addresses, the first candidate storage address and the third candidate storage address are taken as the first target storage address to be read by the any rate matching process in a case where the any rate matching process is a non-last rate matching process.

11. The method of claim 8, wherein, The method further comprises: in response to the total number of rows in each row not read in the first candidate storage address being less than the parallelism degree, and the second candidate storage address not existing in the plurality of storage addresses, the first candidate storage address is taken as the first target storage address to be read by the any rate matching process in a case where the any rate matching process is a last rate matching process.

12. The method of claim 4, wherein, The method further comprises: determining the first target row to be read from the first target storage address according to the column transform sequence and the padding indication sequence; determining, from the unread rows in the first target storage address, a second target row matching the parallelism in response to a total number of the unread rows in the first target storage address being greater than the parallelism; determining, according to the column transformation sequence and the padding indication sequence, whether a third target row exists in the second target row; the third target row is a row from which a first padding bit is read in the current rate matching process; in a case where the third target row exists in the second target row, taking a next row of the second target row and other rows in the second target row except the third target row as first target rows to be read in the current rate matching process.

13. The method of claim 12, wherein, The method further comprises: in a case where the third target row does not exist in the second target row, taking the second target row as the first target row to be read in the current rate matching process.

14. The method of claim 4, wherein, The determining, according to the column transformation sequence and the padding indication sequence, the first target row to be read from the first target storage address comprises: in response to a total number of the unread rows in the first target storage address being less than or equal to the parallelism, taking the unread rows in the first target storage address as the first target row to be read in the current rate matching process.

15. The method of claim 5, wherein, The any code block encoded data comprises: a first check bit stream and a second check bit stream, The determining, from the multiple storage addresses of the single-port random access memory, the first target storage address to be read in the current rate matching process comprises: determining, from the multiple storage addresses, a fourth candidate storage address to be read in the current rate matching process; the fourth candidate storage address comprises a first candidate sub-storage address and a second candidate sub-storage address; the first candidate sub-storage address is used to store the first check bit stream; and the second candidate sub-storage address is used to store the second check bit stream; in response to a sum of a total number of unread rows in the first candidate sub-storage address and the second candidate sub-storage address being equal to the parallelism, and the first padding bit existing at different read positions of a same row of the first candidate sub-storage address and the second candidate sub-storage address, taking the fourth candidate storage address as the first target storage address to be read in the current rate matching process.

16. The method of claim 15, wherein, The method further comprises: in response to the first padding bit existing at the same read position of the same row of the first candidate sub-storage address and the second candidate sub-storage address, and a fifth candidate storage address existing in the multiple storage addresses, obtaining a total number of unread first check bit streams in the fourth candidate storage address and the fifth candidate storage address; the fifth candidate storage address is a next storage address of the fourth candidate storage address; the fifth candidate storage address is used to store the first check bit stream and the second check bit stream; and In a case where the total number of the first parity bit streams not read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and the any rate matching process is a non-last rate matching process, a sixth candidate storage address is obtained; wherein the sixth candidate storage address is a first storage address in which the first parity bit stream and the second parity bit stream are stored. The fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are taken as the first target storage addresses to be read in the any rate matching process.

17. The method of claim 16, wherein, The method further comprises: In a case where the first padding bit exists at the same row of the first candidate sub-storage address and the second candidate sub-storage address, and the fifth candidate storage address exists in the plurality of storage addresses, a total number of the second parity bit streams not read in the fourth candidate storage address and the fifth candidate storage address is obtained. In a case where the total number of the second parity bit streams not read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and the any rate matching process is a non-last rate matching process, the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are taken as the first target storage addresses to be read in the any rate matching process.

18. The method of claim 16, wherein, The method further comprises: In a case where any one of the following conditions is met, the fourth candidate storage address and the fifth candidate storage address are taken as the first target storage addresses to be read in the any rate matching process: The total number of the first parity bit streams not read is less than half of the parallelism, and the any rate matching process is a last rate matching process; The total number of the second parity bit streams not read is less than half of the parallelism, and the any rate matching process is a last rate matching process; The total number of the first parity bit streams not read is greater than or equal to half of the parallelism, and the total number of the second parity bit streams not read is greater than or equal to half of the parallelism.

19. The method of claim 16, wherein, The method further comprises: In a case where the any rate matching process is a last rate matching process, the fourth candidate storage address is taken as the first target storage address to be read in the any rate matching process, in response to the fifth candidate storage address not existing in the plurality of storage addresses.

20. The method of claim 15, wherein, The determining, according to the column transformation sequence and the padding indication sequence, of the first target row to be read from the first target storage address comprises: Determining, according to the column transformation sequence corresponding to the first parity bit stream, the column transformation sequence corresponding to the second parity bit stream and the padding indication sequence, whether the first padding bit exists at the same row of a read position of a first target sub-storage address and a second target sub-storage address in the same first target storage address; wherein the first target sub-storage address is used to store the first parity bit stream, and the second target sub-storage address is used to store the second parity bit stream. In the case that the first padding bits exist simultaneously at the read positions of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, the first target row is determined according to a fourth target row of the first target sub-storage address and the second target sub-storage address, and each row of a subsequent first target storage address of the same first target storage address; wherein the fourth target row is a row in which no first padding bit is read in the current rate matching process.

21. The method of claim 20, wherein, The method further comprises: In the case that the first padding bits do not exist simultaneously at the read positions of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, each row of the first target storage address to be read in the any rate matching process is taken as the first target row to be read in the any rate matching process.

22. The method of claim 20, wherein, The method further comprises: In response to the first padding bits not existing simultaneously at the read positions of the same row of the first target sub-storage address and the second target sub-storage address, intermediate data of the any rate matching process is read from the first target row to be read in the any rate matching process according to the read positions in the first target row to be read in the any rate matching process; The first padding bits are deleted from the intermediate data to obtain the rate matching data of the any rate matching process.

23. The method of claim 1, wherein, The method further comprises: The method further comprises: In response to the length of the system bit stream containing the CRC code being a non-integer multiple of the code block length, the second padding bits are used to perform bit padding on the system bit stream containing the CRC code to obtain a padded system bit stream; The padded system bit stream is subjected to code block segmentation to obtain a plurality of code blocks; Any code block is encoded to obtain a first check bit stream and a second check bit stream corresponding to the any code block; The system bit stream, the first check bit stream and the second check bit stream corresponding to the any code block are taken as the encoding data.

24. The method of claim 23, wherein, The method further comprises: In response to the length of the system bit stream being a non-integer multiple of the standard storage length of the storage unit in the single-port random storage, the first padding bits are used to pad the system bit stream to obtain a padded system bit stream; wherein the length of the padded system bit stream is an integer multiple of the standard storage length; and / or, In response to the length of the first check bit stream being a non-integer multiple of the standard storage length, the first padding bit is used to pad the first check bit stream to obtain a padded first check bit stream; wherein the length of the padded first check bit stream is an integer multiple of the standard storage length; and / or, In response to the length of the second check bit stream being a non-integer multiple of the standard storage length, the first padding bit is used to pad the second check bit stream to obtain a padded second check bit stream; wherein the length of the padded second check bit stream is an integer multiple of the standard storage length.

25. The method of claim 24, wherein, The storing of the padded encoding data into the single-port random access memory comprises: The padded system bit stream, the padded first check bit stream and the padded second check bit stream are sequentially written into the single-port random access memory.

26. The method of claim 2, wherein, The rate matching of the to-be-rate-matched data to obtain the target encoding bit sequence obtained by any rate matching process comprises: In response to the encoding data including a second padding bit, the to-be-rate-matched data is rate matched to obtain an initial encoding bit sequence output by the rate matching; wherein the second padding bit is a bit padded when the length of the system bit stream of the CRC code included in the encoding data satisfies a preset condition; The second padding bit is deleted from the initial encoding bit sequence to obtain the target encoding bit sequence.

27. A rate matching apparatus, characterized by, Comprise: An obtaining module is configured to obtain encoding data of physical uplink shared channel (PUSCH) transmission; A first padding module is configured to, in response to the encoding data satisfying a set condition, perform bit padding on the encoding data based on a first padding bit to obtain padded encoding data; A storage module is configured to store the padded encoding data into a single-port random access memory; A processing module is configured to perform a set number of rate matching processes on the padded encoding data in the single-port random access memory; wherein the to-be-rate-matched data in any rate matching process does not include the first padding bit.

28. An electronic device, comprising: Comprise: A processor and a memory connected with the processor in communication; The memory stores computer execution instructions; The processor executes the computer execution instructions stored in the memory to implement the method in any one of claims 1-26.

29. A chip, characterized by The chip comprises processing circuitry, and the processing circuitry is configured to execute the method in any one of claims 1-26.

30. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the processor to implement the method in any one of claims 1-26.

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