High-speed equalizer and serializer / deserializer receiver using the same

Abstract

The embodiment of the present disclosure provides a high-speed equalizer and a serializer / deserializer receiver using the equalizer. The high-speed equalizer includes at least two-stage equalization circuits, the first-stage equalization circuit outputs a first differential voltage output signal, the first-stage equalization circuit includes a first transistor and a second transistor, one end of the first transistor is connected to the first peaking circuit, and one end of the second transistor is connected to the second peaking circuit; the second-stage equalization circuit in the at least two-stage equalization circuit outputs a second differential voltage output signal, the second-stage equalization circuit includes a third transistor and a fourth transistor, one end of the third transistor is connected to the third peaking circuit, one end of the fourth transistor is connected to the fourth peaking circuit, the first peaking circuit is coupled with the inductance in the third peaking circuit, and the second peaking circuit is coupled with the inductance in the fourth peaking circuit. The high-speed equalizer disclosed in the present disclosure can increase the circuit gain without reducing the circuit bandwidth.

Description

Technical Field

[0001] The present disclosure relates to the field of communications, and in particular to a high-speed equalizer and a serializer / deserializer receiver using the same. Background Art

[0002] The equalizer currently used in serializer / deserializer (SERDES) usually adopts the form of equalization circuits connected in series, that is, the output of the first-stage equalization circuit is connected to the input of the second-stage equalization circuit, and so on. The disadvantage of this structure is that it is difficult to further increase the bandwidth of the circuit, because the multi-stage equalization circuits are connected in series, and each additional stage of the equalization circuit will reduce the overall bandwidth. If a single-stage equalization circuit is used, the overall gain is not enough. Therefore, there is a trade-off between gain and bandwidth. Summary of the invention

[0003] In order to increase the bandwidth of the equalizer while increasing the gain of the equalizer, the present disclosure provides a high-speed equalizer.

[0004] According to one aspect, an embodiment of the present disclosure provides a high-speed equalizer, which includes at least two-stage equalizing circuits, wherein a first-stage equalizing circuit in the at least two-stage equalizing circuits receives a first differential voltage input signal and outputs a first differential voltage output signal, wherein the first-stage equalizing circuit includes a first transistor and a second transistor, wherein one end of the first transistor is connected to a first peaking circuit, one end of the second transistor is connected to a second peaking circuit, and the other ends of the first transistor and the second transistor are respectively connected to a first and a second current source; wherein a second-stage equalizing circuit in the at least two-stage equalizing circuits receives a first differential voltage output signal and outputs a second differential voltage output signal, wherein the second-stage equalizing circuit includes a third transistor and a fourth transistor, wherein one end of the third transistor is connected to a third peaking circuit, one end of the fourth transistor is connected to a fourth peaking circuit, the other ends of the third transistor and the fourth transistor are respectively connected to a third and a fourth current source, and the first peaking circuit is coupled to an inductor in the third peaking circuit, and the second peaking circuit is coupled to an inductor in the fourth peaking circuit.

[0005] The above method adds a fast feedforward path between the equalizing circuits through coupling between inductors, thereby increasing the speed of the equalizer and thus increasing the bandwidth of the circuit.

[0006] Optionally, according to an embodiment of one aspect of the present disclosure, the high-speed equalizer further includes a third-stage equalization circuit, which receives the second differential voltage output signal and outputs a third differential voltage output signal, the third-stage equalization circuit includes a fifth transistor and a sixth transistor, one end of the fifth transistor is connected to the fifth peaking circuit, one end of the sixth transistor is connected to the sixth peaking circuit, the other ends of the fifth transistor and the sixth transistor are respectively connected to the fifth and sixth current sources, and the inductive coupling in the first peaking circuit, the third peaking circuit and the fifth peaking circuit, and the inductive coupling in the second peaking circuit, the fourth peaking circuit and the sixth peaking circuit. The high-speed equalizer can increase the number of stages as needed. After increasing the number of circuit stages, since the maximum operating speed of the circuit is determined by the speed of the fastest path, establishing a fast signal path through inductive coupling will not reduce the speed of the circuit.

[0007] Optionally, according to an embodiment of one aspect of the present disclosure, the inductance of the first peaking circuit and the inductance of the third peaking circuit are wound together and the inductance of the second peaking circuit and the inductance of the fourth peaking circuit are wound together, or the inductance of the first peaking circuit and the inductance of the third peaking circuit are arranged close to each other on different layers of a circuit board and the inductance of the second peaking circuit and the inductance of the fourth peaking circuit are arranged close to each other on different layers of the circuit board.

[0008] Optionally, according to an embodiment of one aspect of the present disclosure, the inductance of the first peaking circuit, the inductance of the third peaking circuit and the inductance of the fifth peaking circuit are wound together and the inductance of the second peaking circuit, the inductance of the fourth peaking circuit and the inductance of the sixth peaking circuit are wound together, or the inductance of the first peaking circuit, the inductance of the third peaking circuit and the inductance of the fifth peaking circuit are arranged close to each other on different layers of a circuit board and the inductance of the second peaking circuit, the inductance of the fourth peaking circuit and the inductance of the sixth peaking circuit are arranged close to each other on different layers of the circuit board.

[0009] Optionally, according to an embodiment of one aspect of the present disclosure, a first differential voltage input signal is input to the control ends of the first and second transistors, and the nodes between the first peaking circuit and the first transistor and between the second peaking circuit and the second transistor serve as output nodes of the first-stage balancing circuit to output the first differential voltage output signal, and the first differential voltage output signal is input to the control ends of the third and fourth transistors, and the nodes between the third peaking circuit and the third transistor and between the fourth peaking circuit and the fourth transistor serve as output nodes of the second-stage balancing circuit to output the second differential voltage output signal.

[0010] Optionally, according to an embodiment of one aspect of the present disclosure, the high-speed equalizer includes at least two voltage output paths, the first voltage output path is from the control ends of the first and second transistors, via the output node of the first-stage equalizing circuit, the control ends of the third and fourth transistors, to the output node of the second-stage equalizing circuit; the second voltage output path is from the control ends of the first and second transistors, via the inductive coupling path in the first peaking circuit and the third peaking circuit and the inductive coupling path in the second peaking circuit and the fourth peaking circuit, to the output node of the second-stage equalizing circuit, without passing through the third and fourth transistors of the second-stage equalizing circuit, and the second differential voltage output signal is the sum of the differential voltage outputs of the first voltage output path and the second voltage output path.

[0011] Since a fast output path is added, the output of the second-stage equalization circuit is the sum of the output signals of the two output paths. Overall, the bandwidth (ie, speed) of the circuit is significantly improved.

[0012] Optionally, according to an embodiment of one aspect of the present disclosure, a first differential voltage input signal is input to the control ends of the first and second transistors, the nodes between the first peaking circuit and the first transistor and between the second peaking circuit and the second transistor serve as output nodes of the first-stage balancing circuit to output the first differential voltage output signal, the first differential voltage output signal is input to the control ends of the third and fourth transistors, the nodes between the third peaking circuit and the third transistor and between the fourth peaking circuit and the fourth transistor serve as output nodes of the second-stage balancing circuit to output the second differential voltage output signal, the second differential voltage output signal is input to the control ends of the fifth and sixth transistors, the nodes between the fifth peaking circuit and the fifth transistor and between the sixth peaking circuit and the sixth transistor serve as output nodes of the third-stage balancing circuit to output the third differential voltage output signal.

[0013] Optionally, according to an embodiment of one aspect of the present disclosure, the high-speed equalizer includes at least three voltage output paths, the first voltage output path is from the control ends of the first and second transistors, sequentially through the output node of the first-stage equalizing circuit, the control ends of the third and fourth transistors, the output node of the second-stage equalizing circuit, the control ends of the fifth and sixth transistors, to the output node of the third-stage equalizing circuit; the second voltage output path is from the control ends of the first and second transistors, sequentially through the output node of the first-stage equalizing circuit, the inductive coupling path of the first peaking circuit and the third peaking circuit, the fifth peaking circuit, and the inductive coupling path of the second peaking circuit, the fourth peaking circuit, and the sixth peaking circuit to the output node of the third-stage equalizing circuit, without passing through the third and fourth transistors of the second-stage equalizing circuit and the fifth and sixth transistors of the third-stage equalizing circuit; the third voltage output path includes from the control ends of the first and second transistors, The third differential voltage output signal is the sum of the differential voltage outputs of the first voltage output path, the second voltage output path, and the third voltage output path. As the number of equalization circuit stages increases, the high-speed equalizer can further include more voltage output paths, wherein the output path through each inductive coupling of each stage is the fastest output path.

[0014] Optionally, according to an embodiment of one aspect of the present disclosure, the first peaking circuit, the second peaking circuit, the third peaking circuit and the fourth peaking circuit respectively include a resistor and an inductor, and the nodes between the first peaking circuit and the first transistor, the second peaking circuit and the second transistor, the third peaking circuit and the third transistor, and the fourth peaking circuit and the fourth transistor are respectively grounded through load capacitors. For high-speed equalizers with more stages, other stages of equalization circuits can adopt the same or similar structure.

[0015] Optionally, according to an embodiment of one aspect of the present disclosure, a first RLC network is provided between a node between the first transistor and the first current source and a node between the second transistor and the second current source, and a second RLC network is provided between a node between the third transistor and the third current source and a node between the fourth transistor and the fourth current source. For high-speed equalizers with more stages, other stages of equalization circuits may adopt the same or similar structure.

[0016] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a serializer / deserializer receiver, which includes a terminal for matching the impedance of a transmission line, a continuous time linear equalizer including the high-speed equalizer as described above, a variable gain amplifier, an analog-to-digital converter for converting a received equalized signal into a digital signal, and a digital signal processor.

[0017] It is not necessary to achieve all the advantages described above at the same time for any device or method to implement the present disclosure. Other features and advantages of the present disclosure will be described in the subsequent description embodiments, and partly become apparent from the description embodiments, or be understood by implementing the present disclosure. The purposes and advantages of the embodiments of the present disclosure can be realized and obtained by the structures indicated in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0019] Figure 1 is a structural schematic diagram of a high-speed equalizer including a two-stage equalization circuit according to an embodiment of the present disclosure;

[0020] Figure 2 is a schematic diagram of an equivalent form of a single-sided circuit of a two-stage equalization circuit according to an embodiment of the present disclosure;

[0021] Figure 3 is a structural schematic diagram of a high-speed equalizer including a three-stage equalization circuit according to another embodiment of the present disclosure;

[0022] Figure 4 is a schematic diagram of an equivalent form of a single-sided circuit of a three-stage equalization circuit according to another embodiment of the present disclosure;

[0023] Figure 5 It is a structural schematic diagram of coupling the inductors of a three-stage equalization circuit with each other according to an embodiment of the present disclosure;

[0024] Figure 6 A serializer / deserializer receiver including a continuous-time linear equalizer according to an embodiment of the present disclosure is disclosed. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The various different embodiments can be combined with each other to form other embodiments not shown in the following description. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0026] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not necessarily indicate a quantity restriction. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0027] The transistor described below may refer to a triode, a MOS tube, etc. In the present disclosure, the control end of the transistor may refer to the base of the triode and the gate of the MOS tube, the input end of the transistor may refer to the emitter of the triode and the source of the MOS tube, and the output end of the transistor may refer to the collector of the triode and the drain of the MOS tube.

[0028] Figure 1 1 is a schematic diagram of a high-speed equalizer structure including a two-stage equalization circuit according to an embodiment of the present disclosure. The first-stage equalization circuit 10 and the second-stage equalization circuit 20 may use a common source amplifier. The structure of the first-stage equalization circuit may be the same or similar to that of the second-stage equalization circuit. The first-stage equalization circuit 10 converts the first differential signal Vip / Vin into a first output signal V1p / V1n, and the second-stage equalization circuit 20 uses the first output signal V1p / V1n as its input signal and converts the first output signal into a second output signal Von / Vop.

[0029] The first-stage equalization circuit 10 includes a first and a second transistor M1, M2, for example, the first and the second transistors may be metal oxide semiconductor field effect transistors (hereinafter referred to as MOS transistors) or triodes. The first differential signal Vip / Vin is connected to the control terminals of the first and the second transistors. The first and the second resistors R1, R2 are load resistors of the first-stage equalization circuit 10, the first and the second capacitors C1, C2 are load capacitors of the first-stage equalization circuit 10, the first end of the first resistor and the first end of the first capacitor are connected to the output terminal of the first transistor, the first end of the second resistor and the first end of the second capacitor are connected to the output terminal of the second transistor, and the other ends of the first and the second capacitors are grounded. The first resistor and the second resistor are respectively connected in series with the first and the second inductors L1, L2 as a peaking circuit to realize the function of series peaking, which helps to expand the bandwidth of the first-stage equalization circuit. In one embodiment, the second end of the first resistor R1 and the second end of the second resistor R2 are respectively connected to the first end of the first inductor L1 and the first end of the second inductor L2, and the second ends of the first and the second inductors L1 and L2 are connected to the working voltage Vdd of the chip. The peaking circuit is a circuit that uses the resonance effect to improve the high-frequency response of the equalization circuit, which can form resonance at a specific frequency to improve the circuit gain near the frequency.

[0030] In one embodiment, a first RLC network 11 may be connected between the input terminals of the first and second transistors. The first RLC network 11 may be a complex network composed of resistors, capacitors, and inductors, and may also be implemented using wires and / or resistors as needed. Thus, the embodiment of the present disclosure may implement the function of a continuous time linear equalizer (CTLE).

[0031] The nodes between the first and second transistors M1 and M2 and the first and second resistors R1 and R2 and the first and second capacitors C1 and C2 serve as output nodes of the first-stage equalizer circuit 10 to output the first output signal V1p / V1n.

[0032] Similarly, the second-stage equalization circuit 20 includes a third and a fourth transistor M3, M4, for example, the third and the fourth transistor can be a MOS tube or a triode. The first output signal V1p / V1n is input to the control end of the third and the fourth transistor as the input of the second-stage equalization circuit 20. The third and the fourth resistors R3, R4 are the load resistors of the second-stage equalization circuit 20, the third and the fourth capacitors C3, C4 are the load capacitors of the second-stage equalization circuit 20, the first end of the third resistor and the first end of the third capacitor are connected to the output end of the third transistor, and the first end of the fourth resistor and the first end of the fourth capacitor are connected to the output end of the fourth transistor. The third resistor and the fourth resistor are respectively connected in series with the third and the fourth inductors L3, L4 as peaking circuits to realize the function of series peaking, thereby expanding the bandwidth of the second-stage equalization circuit. In one embodiment, the second end of the third resistor R3 and the second end of the fourth resistor R4 are respectively connected to the first end of the third inductor L3 and the first end of the fourth inductor L4, and the second ends of the third and the fourth inductors L3 and L4 are connected to the working voltage Vdd of the chip.

[0033] In one embodiment, a second RLC network 21 may be connected between the input terminals of the third and fourth transistors. The second RLC network 21 may be a complex network composed of resistors, capacitors, and inductors, and may also be implemented using wires and / or resistors as needed to achieve the function of a continuous time linear equalizer (CTLE).

[0034] The connection point between the third and fourth transistors, the third and fourth resistors R1 and R2, and the third and fourth capacitors C1 and C2 serves as an output node of the second-stage equalizing circuit 20, and outputs a second output signal Von / Vop.

[0035] In one embodiment, the first and second stage equalization circuits use open loop amplifier circuits, thereby achieving a higher bandwidth. In one embodiment, the first and second stage equalization circuits can use the same configuration.

[0036] In one embodiment, the input terminals of each transistor of the first-stage equalization circuit 10 and the second-stage equalization circuit 20 can be grounded (for example, the source of the MOS tube) via the same or different current sources. For example, the first and second transistors of the first-stage equalization circuit 10 are connected to the first and second current sources, respectively, and the third and fourth transistors of the second-stage equalization circuit 20 are connected to the third and fourth current sources, respectively. The first and second current sources can be one current source or two different current sources, and the third and fourth transistors can be one current source or two different current sources. The current source provides a bias current, which can prevent the output common-mode voltage from changing with the input common-mode voltage, thereby ensuring the stability of the output common-mode voltage. At this time, the output common-mode voltage is related to the current of the current source and the above-mentioned resistor. Figure 1As shown in , if the first and second current sources are the same, the current is Ib, the load resistance R1=R2=R, and the power supply voltage is Vdd, the output common-mode voltage can be calculated to be Vdd-I b *R.

[0037] Further, in one embodiment, the first inductor L1 and the second inductor L2 are coupled to the third inductor L3 and the fourth inductor L4, respectively. The coupling method may include arranging the first inductor L1 and the third inductor L3 close to each other and arranging the second inductor L2 and the fourth inductor L4 close to each other (for example, they may be arranged on different layers of the circuit board), or winding the first inductor L1 and the third inductor L3 together and winding the second inductor L2 and the fourth inductor L4 together (for example, they may be arranged on the same layer of the circuit board). With such an arrangement, only the layout of the circuit board diagram needs to be modified without increasing the area of ​​the board diagram.

[0038] The two-stage balancing circuit adds a fast path through the coupling between the inductors. For clarity, Figure 2 Figure 2 shows the equivalent form of a unilateral circuit. Figure 1 The output of the two-stage equalizing circuit shown is the sum of the outputs of path A1 and path B1. In path A1, the first-stage equalizing circuit 10 outputs the first differential signal to the second-stage equalizing circuit 20 through the control end of its transistor and the output node of the first-stage equalizing circuit, and the second-stage equalizing circuit 20 outputs the first output signal to the output node of the second-stage equalizing circuit 20 through the control end of its transistor. Path A1 is a normal signal path. In path B1, the first-stage equalizing circuit 10 converts the first differential signal into a first output signal, and the first output signal is directly loaded to the output node of the second-stage equalizing circuit 20 through a feedforward path formed by inductive coupling between the first and second inductors of the first-stage equalizing circuit 10 and the third and fourth inductors of the second-stage equalizing circuit 20, without passing through the transistor of the second-stage equalizing circuit. Path B1 is an inductively coupled signal fast path. The second output signal is the sum of the output of path A1 and the output of path B1. As a result, the bandwidth (i.e., speed) of the two-stage equalizing circuit is improved.

[0039] In each level of the balancing circuit, the transistor first converts the input voltage into current, which is then converted into voltage through the series resistor and inductor, and then outputs the voltage to the next level or outward. Figure 1 The inductor and resistor in each level of the equalization circuit shown in FIG are connected in series to achieve series peaking, which can compensate for the influence of the capacitor and expand the bandwidth. On the other hand, compared with the circuit before coupling, the bandwidth can be further improved by coupling the inductors in each level of the equalization circuit.

[0040] The high-speed equalizer of the present invention is not limited to Figure 1The two-stage equalization circuit shown in the figure can be designed as a plurality of equalization circuits connected in series in another embodiment. The connection method between each equalization circuit is the same as or similar to that of the two-stage equalization circuit, which can improve the gain while ensuring that the required bandwidth meets the requirements. Figure 3 A schematic diagram of a three-stage equalization circuit structure according to the present disclosure is shown.

[0041] Figure 3 The three-stage equalization circuit shown is in Figure 1 On the basis of the two-stage equalization circuit, a third-stage equalization circuit is added, which includes a first-stage equalization circuit 10, a second-stage equalization circuit 20, and a third-stage equalization circuit 30, wherein the structures of the first-stage equalization circuit and the second-stage equalization circuit can refer to the above description. The structure of the third-stage equalization circuit is similar to that of the first-stage and second-stage equalization circuits.

[0042] The third-stage equalization circuit 30 includes a fifth and a sixth transistor M5, M6, for example, the fifth and the sixth transistors can be MOS tubes or triodes. The second output signal V2p / V2n is input to the control end of the fifth and the sixth transistors as the input of the third-stage equalization circuit 30. R5 and R6 are load resistors of the third-stage equalization circuit 30, and C5 and C6 are load capacitors of the third-stage equalization circuit 30. The first end of R5 and the first end of C5 are connected to the output end of M5, and the first end of R6 and the first end of C6 are connected to the output end of M6. R5 and R6 are connected in series with the fifth and the sixth inductors L5 and L6, respectively, to realize the function of series peaking, thereby expanding the bandwidth of the third-stage equalization circuit. In one embodiment, the second end of R5 and the second end of R6 are connected to the first end of L5 and the first end of L6, respectively, and the second ends of L5 and L6 are connected to the working voltage Vdd of the chip.

[0043] In one embodiment, a third RLC network 31 may be connected between the input terminals of M5 and M6. The third RLC network 31 may be a complex network composed of resistors, capacitors, and inductors, and may also be implemented using wires and / or resistors as needed. Thus, the embodiment of the present disclosure may implement the function of a continuous time linear equalizer (CTLE).

[0044] The connection point of M5, R5 and C5 and the connection point of M6, R6 and C6 serve as output nodes of the third-stage equalizing circuit 30, outputting the third output signal Von3 / Vop3.

[0045] In one embodiment, the third-stage equalization circuit may adopt an open-loop amplifier circuit, thereby achieving a higher bandwidth. In one embodiment, the first, second and third-stage equalization circuits may adopt the same configuration.

[0046] In one embodiment, the input terminals of each transistor of the third-stage equalization circuit 30 (e.g., the source of the MOS tube) are grounded via the same or different current sources. For example, the fifth and sixth transistors are connected to the fifth and sixth current sources, respectively. The current source is the same or similar to the current source of the first and second stages. According to actual needs, the current sources used in the first, second, and third-stage equalization circuits can be the same or different in size.

[0047] In one embodiment, L5 can be coupled with L1 and L3, and L6 can be coupled with L2 and L4. The coupling method can include arranging L1, L3, and L5 close to each other and arranging L2, L4, and L6 close to each other (for example, they can be arranged on different layers of the circuit board), or L1, L3, and L5 can be wound together, and L2, L4, and L6 can be wound together (for example, they can be arranged on the same layer of the circuit board). With such an arrangement, only the layout of the circuit board diagram needs to be modified without increasing the area of ​​the board diagram. Figure 5 The schematic diagram of the structure of the inductors L1, L3, and L5 of the three-stage balancing circuit coupled to each other is shown. The inductors can be arranged on the same layer of the circuit board or on different layers of the circuit board according to the position relationship shown in the schematic diagram.

[0048] Figure 4 yes Figure 3The equivalent form of the single-side circuit of the three-stage equalizing circuit shown in FIG. 1 is a schematic diagram. In path A2, the first-stage equalizing circuit 10 outputs the first differential signal to the input end of the second-stage equalizing circuit 20 (i.e., the control end of the transistor of the second-stage equalizing circuit) through the control end of its transistor and the output node of the first-stage equalizing circuit, the second-stage equalizing circuit 20 outputs the first output signal to the third-stage equalizing circuit through the control end of its transistor and the output node of the second-stage equalizing circuit, and the third-stage equalizing circuit 30 outputs the second output signal to the output node of the third-stage equalizing circuit 30 through its transistor. Path A2 is a normal signal path. In path B2, the first-stage equalizing circuit 10 converts the first differential signal into a first output signal, and the first output signal directly reaches the output node of the third-stage equalizing circuit 30 through the feedforward path formed by the inductive coupling between the inductance of the first-stage equalizing circuit 10 and the inductance of the second-stage equalizing circuit 20 and the inductance of the third-stage equalizing circuit 30, without passing through the transistors of the second-stage and third-stage equalizing circuits. Path B2 is an inductively coupled signal fast path. In path C, the input first differential signal is converted into a first output signal via the first-stage equalizing circuit 10 and output to the input end of the second-stage equalizing circuit 20. The second-stage equalizing circuit 20 converts the first output signal into a second output signal. The second output signal reaches the output node of the third-stage equalizing circuit 30 via the inductive coupling path of the second-stage and third-stage equalizing circuits, which does not pass through the transistor of the third-stage equalizing circuit and the inductive coupling path from the first-stage equalizing circuit to the second-stage equalizing circuit. In addition, path C also includes the first output signal reaching the output node of the second-stage equalizing circuit via the inductive coupling path of the first-stage and second-stage equalizing circuits, and outputting the third output signal via the control end of the transistor of the third-stage equalizing circuit to the output node of the third-stage equalizing circuit, which does not pass through the transistor of the second-stage equalizing circuit and the inductive coupling path between the second-stage equalizing circuit and the third-stage equalizing circuit (not shown). Path C is a signal sub-fast path, and its signal transmission speed is between paths A2 and B2.

[0049] The third output signal is the sum of the outputs of path A2, path B2, and path C. Since the highest operating speed of the circuit is determined by the speed of the fastest path, that is, the speed of path B2, the establishment of a fast signal path through inductive coupling can avoid the reduction of the speed of the three-stage equalization circuit, thereby improving the bandwidth of the three-stage equalization circuit.

[0050] The high-speed equalizer disclosed in the present invention can be increased to any number of stages as needed. After increasing the number of circuit stages, since the highest operating speed of the circuit is determined by the speed of the fastest path, establishing a fast signal path through inductive coupling will not reduce the speed of the circuit.

[0051] In addition, after increasing the number of stages of the circuit, a very high low-frequency gain can be obtained, so that the circuit is very sensitive to low-frequency errors, which is conducive to extracting low-frequency error signals from the output of the multi-stage equalization circuit and calibrating these errors through some calibration circuits. Such low-frequency errors can be DC offset, flicker noise, etc. Furthermore, after increasing the number of circuit stages, by changing the parameters of components in the circuit, the circuit can achieve very complex transfer functions to adapt to different applications.

[0052] Figure 6 A serializer / deserializer receiver including a continuous time linear equalizer according to an embodiment of the present disclosure is shown. The receiver includes a terminal 61, a continuous time linear equalizer 62, a variable gain amplifier (VGA) 63, an analog-to-digital converter (ADC) 64, and a digital signal processor (DSP) 65. The terminal 61 is used to match the transmission line impedance so that the terminal load impedance matches the transmission line impedance, thereby avoiding or reducing signal reflection and ensuring signal integrity. The terminal can use a differential terminal resistor, for example.

[0053] The continuous time linear equalizer 62 uses the same Figure 1-5 The high-speed equalizer can be used Figure 1 or Figure 3 The structure shown enhances high-frequency signal components by selectively amplifying the frequency, thereby reducing signal distortion.

[0054] The variable gain amplifier 63 can dynamically adjust the gain of the signal, can adjust the gain according to the signal strength, and can variably enhance the signal amplitude so that the input signal reaches an appropriate level range in the subsequent analog-to-digital converter. The variable gain amplifier 63 can be implemented using an existing variable gain amplifier or the high-speed equalizer described in the above embodiment.

[0055] The analog-to-digital converter 64 converts the received equalized signal into a digital signal for subsequent digital signal processing. The digital signal processor serves as a digital backend (DBE), which may include but is not limited to a feedforward equalizer (FFE), a decision feedback equalizer (DFE), a clock data recovery module (CDR), and an adaptive equalizer to implement equalization, filtering, symbol recovery, and other functions. Here, the serializer / deserializer receiver may use an existing digital signal processor as a digital backend.

[0056] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A high-speed equalizer, comprising at least two-stage equalizing circuits, wherein a first-stage equalizing circuit in the at least two-stage equalizing circuits receives a first differential voltage input signal and outputs a first differential voltage output signal, wherein the first-stage equalizing circuit comprises a first transistor and a second transistor, wherein one end of the first transistor is connected to a first peaking circuit, one end of the second transistor is connected to a second peaking circuit, and the other ends of the first transistor and the second transistor are respectively connected to a first and a second current source; wherein a second-stage equalizing circuit in the at least two-stage equalizing circuits receives the first differential voltage output signal and outputs a second differential voltage output signal, wherein the second-stage equalizing circuit comprises a third transistor and a fourth transistor, wherein one end of the third transistor is connected to a third peaking circuit, one end of the fourth transistor is connected to a fourth peaking circuit, the other ends of the third transistor and the fourth transistor are respectively connected to a third and a fourth current source, and the first peaking circuit is coupled to an inductor in the third peaking circuit, and the second peaking circuit is coupled to an inductor in the fourth peaking circuit.

2. The high-speed equalizer according to claim 1, characterized in that It also includes a third-stage balancing circuit, which receives the second differential voltage output signal and outputs a third differential voltage output signal. The third-stage balancing circuit includes a fifth transistor and a sixth transistor. One end of the fifth transistor is connected to the fifth peaking circuit, one end of the sixth transistor is connected to the sixth peaking circuit, the other ends of the fifth transistor and the sixth transistor are connected to the fifth and sixth current sources respectively, and the inductances in the first peaking circuit, the third peaking circuit and the fifth peaking circuit are coupled, and the inductances in the second peaking circuit, the fourth peaking circuit and the sixth peaking circuit are coupled.

3. The high-speed equalizer according to claim 1, characterized in that The inductance of the first peaking circuit and the inductance of the third peaking circuit are wound together, and the inductance of the second peaking circuit and the inductance of the fourth peaking circuit are wound together, or the inductance of the first peaking circuit and the inductance of the third peaking circuit are arranged close to each other on different layers of the circuit board, and the inductance of the second peaking circuit and the inductance of the fourth peaking circuit are arranged close to each other on different layers of the circuit board.

4. The high-speed equalizer according to claim 2, characterized in that The inductance of the first peaking circuit, the inductance of the third peaking circuit and the inductance of the fifth peaking circuit are wound together, and the inductance of the second peaking circuit, the inductance of the fourth peaking circuit and the inductance of the sixth peaking circuit are wound together, or the inductance of the first peaking circuit, the inductance of the third peaking circuit and the inductance of the fifth peaking circuit are arranged close to each other on different layers of the circuit board, and the inductance of the second peaking circuit, the inductance of the fourth peaking circuit and the inductance of the sixth peaking circuit are arranged close to each other on different layers of the circuit board.

5. The high-speed equalizer according to claim 1, characterized in that The first differential voltage input signal is input to the control ends of the first and second transistors, and the nodes between the first peaking circuit and the first transistor and between the second peaking circuit and the second transistor serve as output nodes of the first-stage balancing circuit to output the first differential voltage output signal. The first differential voltage output signal is input to the control ends of the third and fourth transistors, and the nodes between the third peaking circuit and the third transistor and between the fourth peaking circuit and the fourth transistor serve as output nodes of the second-stage balancing circuit to output the second differential voltage output signal.

6. The high-speed equalizer according to claim 5, characterized in that It includes at least two voltage output paths, the first voltage output path is from the control ends of the first and second transistors, through the output node of the first-stage equalizing circuit, the control ends of the third and fourth transistors, to the output node of the second-stage equalizing circuit; the second voltage output path is from the control ends of the first and second transistors, through the inductive coupling path in the first peaking circuit and the third peaking circuit and the inductive coupling path in the second peaking circuit and the fourth peaking circuit, to the output node of the second-stage equalizing circuit, without passing through the third and fourth transistors of the second-stage equalizing circuit, and the second differential voltage output signal is the sum of the differential voltage outputs of the first voltage output path and the second voltage output path.

7. The high-speed equalizer according to claim 2, characterized in that The first differential voltage input signal is input to the control ends of the first and second transistors, the nodes between the first peaking circuit and the first transistor and between the second peaking circuit and the second transistor serve as output nodes of the first-stage balancing circuit to output the first differential voltage output signal, the first differential voltage output signal is input to the control ends of the third and fourth transistors, the nodes between the third peaking circuit and the third transistor and between the fourth peaking circuit and the fourth transistor serve as output nodes of the second-stage balancing circuit to output the second differential voltage output signal, the second differential voltage output signal is input to the control ends of the fifth and sixth transistors, the nodes between the fifth peaking circuit and the fifth transistor and between the sixth peaking circuit and the sixth transistor serve as output nodes of the third-stage balancing circuit to output the third differential voltage output signal.

8. The high-speed equalizer according to claim 7, characterized in that It includes at least three voltage output paths, the first voltage output path is from the control ends of the first and second transistors, sequentially through the output node of the first-stage equalizing circuit, the control ends of the third and fourth transistors, the output node of the second-stage equalizing circuit, the control ends of the fifth and sixth transistors, to the output node of the third-stage equalizing circuit; the second voltage output path is from the control ends of the first and second transistors, sequentially through the output node of the first-stage equalizing circuit, the inductive coupling path of the first peaking circuit and the third peaking circuit, the fifth peaking circuit, and the inductive coupling path of the second peaking circuit, the fourth peaking circuit, and the sixth peaking circuit to the output node of the third-stage equalizing circuit, without passing through the third and fourth transistors of the second-stage equalizing circuit and the fifth and sixth transistors of the third-stage equalizing circuit; the third voltage output path includes from the control ends of the first and second transistors, sequentially through the output node of the first-stage equalizing circuit, the inductive coupling path of the first peaking circuit and the third peaking circuit, the fifth peaking circuit, and the inductive coupling path of the second peaking circuit, the fourth peaking circuit, and the sixth peaking circuit to the output node of the third-stage equalizing circuit. The output node, the control terminals of the third and fourth transistors, the output node of the second-stage balancing circuit, the inductive coupling path between the third peaking circuit and the fifth peaking circuit and the inductive coupling path between the fourth peaking circuit and the sixth peaking circuit to the output node of the third-stage balancing circuit without passing through the fifth and sixth transistors of the third-stage balancing circuit, and from the control terminals of the first and second transistors, sequentially through the output node of the first-stage balancing circuit, the inductive coupling path between the first peaking circuit and the third peaking circuit and the inductive coupling path between the second peaking circuit and the fourth peaking circuit, the output node of the second-stage balancing circuit, the control terminals of the fifth and sixth transistors, to the output node of the third-stage balancing circuit without passing through the third and fourth transistors of the second-stage balancing circuit, the third differential voltage output signal is the sum of the differential voltage outputs of the first voltage output path, the second voltage output path and the third voltage output path.

9. The high-speed equalizer according to claim 1, characterized in that The first peaking circuit, the second peaking circuit, the third peaking circuit and the fourth peaking circuit respectively include resistors and inductors, and nodes between the first peaking circuit and the first transistor, the second peaking circuit and the second transistor, the third peaking circuit and the third transistor, and the fourth peaking circuit and the fourth transistor are each grounded through a load capacitor.

10. The high-speed equalizer according to claim 1, characterized in that An RLC network is connected between the output ends of the first transistor and the second transistor of the first-stage equalizing circuit, and an RLC network is connected between the output ends of the third transistor and the fourth transistor of the second-stage equalizing circuit.

11. The high-speed equalizer according to claim 1 or 2, characterized in that Each level of equalization circuit is a common source amplifier.

12. The high-speed equalizer according to claim 1 or 2, characterized in that The structure of each level of equalization circuit is the same.

13. A serializer / deserializer receiver comprising a terminal for matching the impedance of a transmission line, using a high-speed equalizer as described in any one of claims 1 to 12 as a continuous-time linear equalizer, a variable gain amplifier, an analog-to-digital converter for converting a received equalized signal into a digital signal, and a digital signal processor.

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