Projection data processing method, system, equipment and medium

Abstract

The invention discloses a projection data processing method, system and device and a medium. The method comprises the steps of obtaining projection data through a first thread; under the condition that the projection data belong to the interlaced scanning data and / or the CVBS data, performing de-interlacing processing on the projection data through a second thread to obtain de-interlacing data; performing anti-interlacing processing on the de-interlaced data through a third thread to obtain display data, wherein the first thread, the second thread and the third thread are synchronously performed; and displaying the display data, wherein the display data is displayed frame by frame by taking one frame of display data as a display period. The first thread, the second thread and the third thread are synchronously performed, so that the display data are displayed frame by frame by taking one frame of display data as a display period, the processing time of each frame of image of a projector is reduced, the display frame rate is improved, and the method can be widely applied to the technical field of data processing.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a projection data processing method, system, device and medium. Background Art

[0002] Existing Android smart TV or projector devices need to be connected according to the Android TIF (TV Input Framework) framework. The native Android system provides a method to display the collected data of HDMI (High-Definition Multimedia Interface) and CVBS (Composite Video Baseband Signal) signals on the screen.

[0003] However, the native Android system takes a long time to process each frame of the projector, resulting in a decrease in the display frame rate. Summary of the invention

[0004] In view of this, an object of the embodiments of the present invention is to provide a projection data processing method, system, device and medium, which can reduce the processing time of each frame of the projector and improve the display frame rate.

[0005] In a first aspect, an embodiment of the present invention provides a projection data processing method, comprising:

[0006] Acquire projection data through a first thread, where the projection data includes HDMI data and / or CVBS data;

[0007] In the case where the projection data is interlaced scan data and / or CVBS data, deinterlacing the projection data through a second thread to obtain deinterlaced data, wherein the interlaced scan data represents HDMI data using interlaced scan;

[0008] Performing deinterlacing processing on the deinterlaced data through a third thread to obtain display data, wherein the first thread, the second thread and the third thread are performed synchronously, the third thread processes the deinterlaced data of a previous frame of the second thread, and the second thread processes the projection data of a previous frame of the first thread;

[0009] The display data is displayed, and the display data is displayed frame by frame with one frame of the display data as a display period.

[0010] In some optional embodiments, the first thread, the second thread, and the third thread perform data synchronization through a mutex lock, including:

[0011] Establishing a structure, the structure comprising a buffer pointer, a mutex lock, a video frame sequence and a next status flag, the next status flag comprising an acquisition status flag, a deinterlacing status flag, a deinterlacing status flag and a completion status flag;

[0012] The first thread locks the first buffer area through the mutex lock, sets the next state flag of the first buffer area to a de-interlacing state flag, sets the second buffer area to a collection state flag, and collects the projection data of the second buffer area through the buffer area pointer and the mutex lock;

[0013] The second thread performs deinterlacing processing on the first buffer area after identifying the deinterlacing state flag to obtain deinterlaced data, and sets the next state flag of the first buffer area to a deinterlacing state flag;

[0014] After identifying the de-interlacing state flag, the third thread performs de-interlacing processing on the first buffer area to obtain display data, and sets the next state flag of the first buffer area to a completion state flag.

[0015] In some optional embodiments, after setting the next status flag of the first buffer area to a completion status flag, the method further comprises:

[0016] Obtaining the video frame sequence of the first buffer area;

[0017] The first data of the first buffer area of ​​the completion status mark is displayed frame by frame according to the video frame sequence, and the first data represents the display data.

[0018] In some optional embodiments, acquiring projection data through the first thread includes:

[0019] In the case where the projection data belongs to interlaced scanning data, the projection data is obtained by judging by an internal high-speed receiver, and the projection data is allocated to a continuous buffer area by a core allocation module, and one frame of the projection data occupies one buffer area;

[0020] In the case where the projection data is CVBS data, the projection data is obtained through a digital-to-analog conversion module, and the projection data is allocated to continuous buffer areas through a kernel allocation module, and one frame of the projection data occupies one buffer area.

[0021] In some optional embodiments, the method further includes:

[0022] Mapping the cache area to a user space through a memory mapping function, wherein the user space represents a memory space accessible to the first thread, the second thread, and the third thread;

[0023] Obtaining the first address and storage information of the cache area from the interface of the user space through the middleware;

[0024] The first address and storage information are sent to the first thread, the second thread and the third thread through the middleware.

[0025] In some optional embodiments, performing deinterlacing processing on the projection data by a second thread to obtain deinterlaced data includes:

[0026] Splitting the projection data and storing them in odd field space and even field space respectively;

[0027] Allocating display storage space, wherein the display storage space matches the resolution of the display screen;

[0028] A line of odd field data in the odd field space and a line of even field data in the even field space are read alternately in a loop, and the line of odd field data and the line of even field data are alternately filled into the display storage space, and the display storage space stores the de-interlaced data.

[0029] In some optional embodiments, performing deinterlacing on the deinterlaced data by a third thread to obtain display data includes:

[0030] Reading the deinterlaced data in the display storage space line by line, and performing pixel comparison on two adjacent lines of the deinterlaced data to obtain a comparison result;

[0031] When the comparison result indicates that pixels of two adjacent rows of the deinterlaced data have an overlap ratio within a preset range, pixels of another row of the deinterlaced data that overlaps one of the two adjacent rows are removed, and the removed pixels are added to the other row of the deinterlaced data.

[0032] In a second aspect, an embodiment of the present invention provides a projection data processing system, including:

[0033] A first module is used to obtain projection data through a first thread, where the projection data includes HDMI data and / or CVBS data;

[0034] A second module is used for, when the projection data is interlaced scanning data and / or CVBS data, performing deinterlacing processing on the projection data through a second thread to obtain deinterlaced data, wherein the interlaced scanning data represents HDMI data using interlaced scanning;

[0035] A third module is used to perform deinterlacing processing on the deinterlaced data through a third thread to obtain display data, wherein the first thread, the second thread and the third thread are performed synchronously, the third thread processes the deinterlaced data of a previous frame of the second thread, and the second thread processes the projection data of a previous frame of the first thread;

[0036] The fourth module is used to display the display data, and the display data is displayed frame by frame with one frame of the display data as a display period.

[0037] In a third aspect, an embodiment of the present invention provides a computer device, comprising a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein the steps of the above method are implemented when the computer program is executed by the processor.

[0038] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to perform the method as described above.

[0039] The implementation of the embodiment of the present invention includes the following beneficial effects: The embodiment of the present invention provides a projection data processing method, including: obtaining projection data through a first thread, the projection data including HDMI data and / or CVBS data; when the projection data belongs to interlaced scanning data and / or CVBS data, deinterlacing the projection data through a second thread to obtain deinterlaced data, the interlaced scanning data represents HDMI data using interlaced scanning; deinterlacing the deinterlaced data through a third thread to obtain display data, the first thread, the second thread and the third thread are performed synchronously, the third thread processes the deinterlaced data of the previous frame of the second thread, and the second thread processes the projection data of the previous frame of the first thread; displaying the display data, the display data is displayed frame by frame with one frame of the display data as the display cycle. The first thread, the second thread and the third thread are performed synchronously, so that the display data is displayed frame by frame with one frame of the display data as the display cycle, thereby reducing the processing time of each frame of the projector image and improving the display frame rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a flowchart of the steps of a projection data processing method provided by an embodiment of the present invention;

[0041] Figure 2 is a flowchart of projection data processing provided by an embodiment of the present invention;

[0042] Figure 3is a schematic diagram of multi-threaded processing of projection data processing provided by an embodiment of the present invention;

[0043] Figure 4 is a structural block diagram of a projection data processing system provided by an embodiment of the present invention;

[0044] Figure 5 It is a schematic block diagram of the structure of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0046] In the description of the present invention, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0047] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0048] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0049] The embodiment of the present invention provides a projection data processing method, system, device and medium, wherein a projection data processing method includes: obtaining projection data through a first thread, the projection data including HDMI data and / or CVBS data; when the projection data belongs to interlaced scanning data and / or CVBS data, deinterlacing the projection data through a second thread to obtain deinterlaced data, the interlaced scanning data represents HDMI data using interlaced scanning; deinterlacing the deinterlaced data through a third thread to obtain display data, the first thread, the second thread and the third thread are performed synchronously, the third thread processes the deinterlaced data of the previous frame of the second thread, and the second thread processes the projection data of the previous frame of the first thread; and displaying the display data, the display data is displayed frame by frame with one frame of the display data as a display cycle. The first thread, the second thread and the third thread are performed synchronously, so that the display data is displayed frame by frame with one frame of the display data as a display cycle, thereby reducing the processing time of each frame of the projector image and improving the display frame rate.

[0050] The allocation method of the embodiment of the present invention is further described below.

[0051] Reference Figure 1 , Figure 1 A flowchart of a projection data processing method provided by an embodiment of the present invention, the projection data processing method includes but is not limited to the following steps:

[0052] S101, acquiring projection data through a first thread, where the projection data includes HDMI data and / or CVBS data;

[0053] S102, when the projection data is interlaced scanning data and / or CVBS data, performing deinterlacing processing on the projection data through a second thread to obtain deinterlaced data, wherein the interlaced scanning data represents HDMI data using interlaced scanning;

[0054] S103, performing deinterlacing processing on the deinterlaced data by a third thread to obtain display data, wherein the first thread, the second thread and the third thread are performed synchronously, the third thread processes the deinterlaced data of a previous frame of the second thread, and the second thread processes the projection data of a previous frame of the first thread;

[0055] S104, displaying the display data, wherein the display data is displayed frame by frame with one frame of the display data as a display period.

[0056] It should be noted that the first thread of the present application is the acquisition thread, the second thread is the deinterlacing processing thread, and the third thread is the deinterlacing processing thread. The first thread, the second thread and the third thread are pipelined at the same time, and the efficiency is improved through multi-threaded parallelism, so that the display frame rate of the display data is improved compared with the native. That is, the processing time of a frame of projection image is reduced to one cycle, and one cycle represents the time for the third thread to process a frame of deinterlacing data to generate a frame of display data, that is, multiple frames of display data are seamlessly connected for display, which greatly improves the frame rate.

[0057] In some optional embodiments, the first thread, the second thread and the third thread perform data synchronization through a mutex lock, including: establishing a structure, the structure including a buffer pointer, a mutex lock, a video frame sequence and a next status flag, the next status flag including an acquisition status flag, a deinterlacing status flag, a deinterlacing status flag and a completion status flag; the first thread locks the first buffer through the mutex lock, and sets the next status flag of the first buffer to the deinterlacing status flag, sets the second buffer to the acquisition status flag, and acquires the projection data of the second buffer through the buffer pointer and the mutex lock; the second thread deinterlaces the first buffer after identifying the deinterlacing status flag to obtain deinterlaced data, and sets the next status flag of the first buffer to the deinterlacing status flag; the third thread deinterlaces the first buffer after identifying the deinterlacing status flag to obtain display data, and sets the next status flag of the first buffer to the completion status flag.

[0058] Specifically, a mutex lock is used to ensure data synchronization in the buffer. Specifically, a structure is defined, which includes a buffer pointer, a mutex lock, an index frame order (i.e., video frame order), and a next_state (indicating the next state to be entered in the state transition logic) state flag. Next_state has four states: CAP (capture), COMB (combined deinterlacing), DEINTR (deinterlacing), and FINISH (finish). The mutex lock is added to the first buffer (buffer1), that is, the mutex lock is set when the first buffer (buffer1) is captured to avoid other thread operations, and the next_state of the first buffer (buffer1) is set to COMB after the capture is completed. The capture thread continues to capture buffer2 (the second buffer)...bufferN (the Nth buffer) according to the buffer pointer, and buffer1 can only be deinterlaced by the second thread, following next_state, and transferred to the second thread for processing. After the deinterlacing thread (second thread) gets a structure, it first reads next_state, determines that buffer1 is what it wants to process, and then deinterlaces the data in buffer1. After the processing is completed, the next_state of buffer1 is set to DEINTR. Similarly, after the third thread gets a structure, it first reads next_state, determines that buffer1 is what it wants to process, and then deinterlaces the data in buffer1. After the processing is completed, the next_state of buffer1 is set to FINISH, and finally the data in buffer1 is displayed as an image according to the index frame order. The three steps of acquisition, deinterlacing, and deinterlacing are turned into three threads running simultaneously. The data synchronization of the cache interval is guaranteed by mutex locks and conditional judgments. The data processing pipeline is carried out. After running for a period of time, the pipeline becomes stable (that is, the three threads are stable). At this time, the processing time is reduced to one cycle, which greatly improves the frame rate.

[0059] In some optional embodiments, after setting the next status flag of the first cache area to the completion status flag, it includes: obtaining the video frame sequence of the first cache area; displaying the first data of the first cache area of ​​the completion status flag frame by frame according to the video frame sequence, the first data representing the display data.

[0060] Specifically, after the third thread completes the deinterlacing process on the data in buffer1, it sets the next_state of buffer1 to FINISH, and finally displays the data in buffer1 according to the index frame order. The index frame order indicates the display order of the data (first data) in buffer1, so the data in buffer1 is displayed according to the display order.

[0061] In some optional embodiments, acquiring projection data through the first thread includes: when the projection data is interlaced scanning data, the projection data is obtained by judgment through an internal high-speed receiver, and the projection data is allocated to a continuous cache area through a kernel allocation module, and one frame of the projection data occupies one cache area; when the projection data is CVBS data, the projection data is obtained through a digital-to-analog conversion module, and the projection data is allocated to a continuous cache area through a kernel allocation module, and one frame of the projection data occupies one cache area.

[0062] Specifically, the signal acquisition process is performed by the TVCAP (TV acquisition) module inside the TV chip. The TVCAP module processes HDMI and CVBS separately. HDMI is a TMDS (Transition Minimized Differential Signaling) differential signal. The projection data is obtained through the internal high-speed receiver, while the CVBS signal is converted into the required projection data through the ADC (digital-to-analog conversion module). The projection data is processed by configuring the corresponding registers. The TVCAP module can automatically store HDMI data or CVBS data in the continuous buffer area allocated by the kernel (that is, buffer1...bufferN). One frame of projection data occupies one buffer area, that is, each buffer in buffer1...bufferN stores one frame of projection data.

[0063] In some optional embodiments, the method further includes: mapping the cache area to a user space through a memory mapping function, wherein the user space represents a memory space accessible to the first thread, the second thread, and the third thread; obtaining the first address and storage information of the cache area from an interface of the user space through middleware; and sending the first address and storage information to the first thread, the second thread, and the third thread through the middleware.

[0064] Specifically, the cache area is mapped to the user space through the mmap (memory mapping function) of the Linux system. The software driver provides an interface for the middleware to obtain the first address and information of the cache area. Due to the fast frame rate, one frame of projection data occupies one buffer, so the buffer address collected each time is different.

[0065] In some optional embodiments, the mmap mapping process includes: calling to open the file descriptor corresponding to the device; using the mmap system call file descriptor to map the file or other object to the address space of the process (i.e., the user space). The software driver implements an interface for the middleware to call to obtain the first address and related information of the mapped memory area (buffer). Due to the high frame rate, each frame of data may be stored in a different buffer, which means that the middleware needs to be able to handle dynamically changing buffer addresses. A synchronization mechanism is established between the driver and the middleware to ensure that the middleware can obtain the latest buffer address and data in a timely manner. The driver needs to manage multiple buffers to achieve circular use or automatic expansion of the buffer area. Ensure that access to the buffer does not cause competition conditions in a multi-threaded environment. Due to the high frame rate, the data transmission path needs to be optimized to reduce delays. Use system calls such as msync to synchronize the buffer in the user space and the buffer in the kernel space to ensure data consistency. The middleware needs to be able to handle errors that may occur during the mmap and driver interface calls, and use the munmap system call to release the mapped memory when mapping is not required. The driver needs to work closely with the middleware to ensure timely delivery and processing of data. If multiple processes need to access the same data, shared memory mapping can be used. To improve performance, a memory pool can be used to manage the allocation and release of buffers.

[0066] In some optional embodiments, the deinterlacing processing of the projection data by the second thread to obtain deinterlaced data includes: splitting the projection data and storing them in an odd field space and an even field space respectively; allocating a display storage space, wherein the display storage space matches the resolution of the display screen; cyclically and alternately reading a line of odd field data in the odd field space and a line of even field data in the even field space, and alternately filling the line of odd field data and the line of even field data into the display storage space, wherein the display storage space stores the deinterlaced data.

[0067] Specifically, the collected projection data is split into a first part and a second part, the first part is stored in the odd field space, and the second part is stored in the even field space. The de-interlacing algorithm allocates a display storage space equivalent to the resolution of the display screen, that is, the display data stored in the display storage space can display the entire display screen. First, a line of odd field data is read to fill a line of the display storage space, and then a line of even field data is read to fill the next line of the display storage space, and the filling is alternated in this way.

[0068] In some optional embodiments, the deinterlacing of the deinterlaced data by a third thread to obtain display data includes: reading the deinterlaced data in the display storage space row by row, and performing pixel comparison on two adjacent rows of the deinterlaced data to obtain a comparison result; when the comparison result indicates that the pixels of the deinterlaced data of two adjacent rows have an overlapping rate within a preset range, removing another row of pixels of one of the two adjacent rows where the deinterlaced data overlaps, and adding the removed pixels to the other row of the deinterlaced data.

[0069] Specifically, two adjacent rows of the display storage space are one row of odd field data and one row of even field data. The de-interlaced data of two adjacent rows (i.e., one row of odd field data and one row of even field data) are compared pixel by pixel, so as to compare the pixel difference between the two rows of de-interlaced data. When there is interlacing between the two rows of de-interlaced data, that is, there is pixel overlap between the two rows of de-interlaced data, the overlapped part is separated, so as to complete the de-interlacing. Specifically, by detecting the overlap rate between two lines of de-interlaced data, when the overlap rate is within a preset range, it indicates that the two lines of de-interlaced data at this time will have a aliasing effect or a blurred state when displayed, and therefore de-interlacing processing is required; the pixel overlapping part of the two lines of de-interlaced data is extracted, that is, the first pixel of the first line of de-interlaced data belonging to the second line of de-interlaced data is eliminated, and the eliminated first pixel is added to the second line of de-interlaced data, the eliminated first pixel is calculated according to the first position in the first line of de-interlaced data, and the second position in the second line of de-interlaced data is calculated accordingly, and the first pixel is added to the second position, so as to enhance the pixels of the second line of de-interlaced data; similarly, the second pixel of the second line of de-interlaced data belonging to the first line of de-interlaced data is eliminated, and the eliminated second pixel is added to the first line of de-interlaced data, the eliminated second pixel is calculated according to the third position in the second line of de-interlaced data, and the second pixel is added to the fourth position, so as to enhance the pixels of the first line of de-interlaced data.

[0070] In some optional embodiments, referring to Figure 2 ,The process of projection data processing specifically includes:

[0071] Step 1, SetSurface;

[0072] Step 2: Get the Native Window.

[0073] Step 3. Set the number of buffers.

[0074] Step 4: Determine whether to exit, if yes, then end, otherwise go to step 5;

[0075] Step 5, set dequeueBuffer to store the projection data to be collected;

[0076] Step 6: Collect projection data;

[0077] Step 7, de-interlacing the projection data;

[0078] Step 8, deinterlacing the projection data;

[0079] Step 9. Store the display data in queueBuffer and jump to step 4.

[0080] Reference Figure 3 The three steps of acquisition, deinterlacing and deinterlacing are turned into three threads running simultaneously, and the data processing is carried out in a pipeline. The time for processing one frame of projection data is one cycle, which greatly improves the frame rate.

[0081] The implementation of the embodiment of the present invention includes the following beneficial effects: The embodiment of the present invention provides a projection data processing method, including: obtaining projection data through a first thread, the projection data including HDMI data and / or CVBS data; when the projection data belongs to interlaced scanning data and / or CVBS data, deinterlacing the projection data through a second thread to obtain deinterlaced data, the interlaced scanning data represents HDMI data using interlaced scanning; deinterlacing the deinterlaced data through a third thread to obtain display data, the first thread, the second thread and the third thread are performed synchronously, the third thread processes the deinterlaced data of the previous frame of the second thread, and the second thread processes the projection data of the previous frame of the first thread; displaying the display data, the display data is displayed frame by frame with one frame of the display data as the display cycle. The first thread, the second thread and the third thread are performed synchronously, so that the display data is displayed frame by frame with one frame of the display data as the display cycle, thereby reducing the processing time of each frame of the projector image and improving the display frame rate.

[0082] like Figure 4 As shown, in a second aspect, an embodiment of the present invention provides a projection data processing system, comprising:

[0083] A first module is used to obtain projection data through a first thread, where the projection data includes HDMI data and / or CVBS data;

[0084] A second module is used for, when the projection data is interlaced scanning data and / or CVBS data, performing deinterlacing processing on the projection data through a second thread to obtain deinterlaced data, wherein the interlaced scanning data represents HDMI data using interlaced scanning;

[0085] A third module is used to perform deinterlacing processing on the deinterlaced data through a third thread to obtain display data, wherein the first thread, the second thread and the third thread are performed synchronously, the third thread processes the deinterlaced data of a previous frame of the second thread, and the second thread processes the projection data of a previous frame of the first thread;

[0086] The fourth module is used to display the display data, and the display data is displayed frame by frame with one frame of the display data as a display period.

[0087] It can be seen that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0088] like Figure 5 As shown, in the third aspect, an embodiment of the present invention further provides a computer device, which can be a terminal. The computer device includes a processor, a memory, and a network interface connected via a system bus, wherein the memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium can store an operating system and a computer program. The computer program includes program instructions, which, when executed, enable the processor to execute any one of the methods for visualizing management of industrial equipment. The processor is used to provide computing and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium, which, when executed by the processor, enables the processor to execute any one of the methods for visualizing management of industrial equipment. The network interface is used for network communications, such as sending assigned tasks, etc. Those skilled in the art will appreciate that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present disclosure, and does not constitute a limitation on the computer device to which the solution of the present disclosure is applied. The specific computer device may include Figure 5More or less components shown in, or some components are combined, or there are different component arrangements. It should be understood that the processor can be a central processing unit (CPU), and the processor can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. In one embodiment, the processor is used to run a computer program stored in a memory to implement the following steps: obtaining projection data through a first thread, the projection data including HDMI data and / or CVBS data; when the projection data is interlaced scan data and / or CVBS data, deinterlacing the projection data through a second thread to obtain deinterlaced data, the interlaced scan data representing HDMI data using interlaced scan; deinterlacing the deinterlaced data through a third thread to obtain display data, the first thread, the second thread and the third thread are performed synchronously, the third thread processes the deinterlaced data of a previous frame of the second thread, and the second thread processes the projection data of a previous frame of the first thread; and displaying the display data, the display data is displayed frame by frame with one frame of the display data as a display period.

[0089] It can be seen that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0090] In addition, the embodiment of the present application also discloses a computer program product or a computer program, and the computer program product or the computer program is stored in a computer-readable storage medium. The processor of the computer device can read the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device performs the above method. Similarly, the contents in the above method embodiment are all applicable to the storage medium embodiment, and the functions specifically implemented by the storage medium embodiment are the same as those in the above method embodiment, and the beneficial effects achieved are also the same as those achieved by the above method embodiment.

[0091] It is understood that all or some steps and systems in the disclosed method above can be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components can be implemented as processors, such as software executed by a central processing unit, a digital information processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, and the computer-readable medium can include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other data processing technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, magnetic tape, disk storage or other magnetic storage device, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media generally contain computer readable instructions, data structures, program modules, or other data in modulated data information such as carrier waves or other transport mechanisms, and may include any information delivery media.

[0092] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the technical field without departing from the purpose of the present invention.

Claims

1. A projection data processing method, characterized in that: include: Acquire projection data through a first thread, where the projection data includes HDMI data and / or CVBS data; In the case where the projection data is interlaced scan data and / or CVBS data, deinterlacing the projection data through a second thread to obtain deinterlaced data, wherein the interlaced scan data represents HDMI data using interlaced scan; Performing deinterlacing processing on the deinterlaced data through a third thread to obtain display data, wherein the first thread, the second thread and the third thread are performed synchronously, the third thread processes the deinterlaced data of a previous frame of the second thread, and the second thread processes the projection data of a previous frame of the first thread; The display data is displayed, and the display data is displayed frame by frame with one frame of the display data as a display period.

2. The method according to claim 1, characterized in that: The first thread, the second thread and the third thread perform data synchronization through a mutex lock, including: Establishing a structure, the structure comprising a buffer pointer, a mutex lock, a video frame sequence and a next status flag, the next status flag comprising an acquisition status flag, a de-interlacing status flag, a de-interlacing status flag and a completion status flag; The first thread locks the first buffer area through the mutex lock, sets the next state flag of the first buffer area to a de-interlacing state flag, sets the second buffer area to a collection state flag, and collects the projection data of the second buffer area through the buffer area pointer and the mutex lock; The second thread performs deinterlacing processing on the first buffer area after identifying the deinterlacing state flag to obtain deinterlaced data, and sets the next state flag of the first buffer area to a deinterlacing state flag; After identifying the de-interlacing state flag, the third thread performs de-interlacing processing on the first buffer area to obtain display data, and sets the next state flag of the first buffer area to a completion state flag.

3. The method according to claim 2, characterized in that After setting the next status flag of the first buffer area to a completion status flag, the method further comprises: Obtaining the video frame sequence of the first buffer area; The first data of the first buffer area of ​​the completion status mark is displayed frame by frame according to the video frame sequence, and the first data represents the display data.

4. The method according to claim 1, characterized in that: The obtaining of projection data through the first thread includes: In the case where the projection data belongs to interlaced scanning data, the projection data is obtained by judging by an internal high-speed receiver, and the projection data is allocated to a continuous buffer area by a core allocation module, and one frame of the projection data occupies one buffer area; In the case where the projection data is CVBS data, the projection data is obtained through a digital-to-analog conversion module, and the projection data is allocated to continuous buffer areas through a kernel allocation module, and one frame of the projection data occupies one buffer area.

5. The method according to claim 4, characterized in that The method further comprises: Mapping the cache area to a user space through a memory mapping function, wherein the user space represents a memory space accessible to the first thread, the second thread, and the third thread; Obtaining the first address and storage information of the cache area from the interface of the user space through the middleware; The first address and the storage information are sent to the first thread, the second thread and the third thread through the middleware.

6. The method according to claim 1, characterized in that The step of performing deinterlacing processing on the projection data by a second thread to obtain deinterlaced data includes: Splitting the projection data and storing them in odd field space and even field space respectively; Allocating display storage space, wherein the display storage space matches the resolution of the display screen; A line of odd field data in the odd field space and a line of even field data in the even field space are read alternately in a loop, and the line of odd field data and the line of even field data are alternately filled into the display storage space, and the display storage space stores the de-interlaced data.

7. The method according to claim 6, characterized in that The step of performing de-interlacing processing on the de-interlaced data by a third thread to obtain display data includes: Reading the deinterlaced data in the display storage space line by line, and performing pixel comparison on two adjacent lines of the deinterlaced data to obtain a comparison result; When the comparison result indicates that pixels of two adjacent rows of the deinterlaced data have an overlap ratio within a preset range, pixels of another row of the deinterlaced data that overlaps one of the two adjacent rows are removed, and the removed pixels are added to the other row of the deinterlaced data.

8. A projection data processing system, characterized in that: include: A first module is used to obtain projection data through a first thread, where the projection data includes HDMI data and / or CVBS data; A second module is used for, when the projection data is interlaced scanning data and / or CVBS data, performing deinterlacing processing on the projection data through a second thread to obtain deinterlaced data, wherein the interlaced scanning data represents HDMI data using interlaced scanning; A third module is used to perform deinterlacing processing on the deinterlaced data through a third thread to obtain display data, wherein the first thread, the second thread and the third thread are performed synchronously, the third thread processes the deinterlaced data of a previous frame of the second thread, and the second thread processes the projection data of a previous frame of the first thread; The fourth module is used to display the display data, and the display data is displayed frame by frame with one frame of the display data as a display period.

9. A computer device, wherein: The computer device comprises a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to perform the method according to any one of claims 1 to 7 when executed by the processor.

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