Printed circuit board

Abstract

The present disclosure relates to a printed circuit board including: an insulating layer; and a plurality of wiring layers disposed in the insulating layer, in which the plurality of wiring layers includes a first wiring layer, a second wiring layer disposed over the first wiring layer, and a third wiring layer disposed over the second wiring layer, the second wiring layer being thicker than each of the first wiring layer and the third wiring layer, and the second wiring layer includes a microcircuit pattern, and the microcircuit pattern has an aspect ratio of 2.4 to 3.6, which is a ratio of a height to a line width of the microcircuit pattern.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0085811 filed on July 3, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] As the market has recently changed from the existing business for portable devices to high-capacity servers, the amount of data is growing rapidly, and the amount of servers, networks, and storage is also growing rapidly. Therefore, multi-layer new structure substrates including microcircuits are expanding. For example, fan-out multi-chip modules (FOMCM), fan-out embedded bridges (FOEB), and embedded multi-chip interconnect bridges (EMIB) are being developed. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board that can ensure excellent signal characteristics without substantially increasing the overall thickness.

[0005] One of the various technical solutions proposed by the present disclosure is to reduce signal loss by increasing the thickness of a wiring layer including a microcircuit pattern (eg, by increasing the aspect ratio of the microcircuit pattern to a certain level) while controlling the overall thickness.

[0006] For example, according to one aspect of the present disclosure, a printed circuit board may include: an insulating layer; and a plurality of wiring layers arranged in the insulating layer, wherein the plurality of wiring layers may include a first wiring layer, a second wiring layer arranged above the first wiring layer, and a third wiring layer arranged above the second wiring layer, the second wiring layer may be thicker than each of the first wiring layer and the third wiring layer, and the second wiring layer may include a microcircuit pattern, and the microcircuit pattern may have an aspect ratio of 2.4 to 3.6, wherein the aspect ratio is a ratio of a height of the microcircuit pattern to a line width.

[0007] Another technical solution among various technical solutions proposed by the present disclosure is to reduce signal loss by increasing the thickness of the wiring layer including the microcircuit pattern to a certain level compared with the insulation distance between the microcircuit pattern and other wiring layers while controlling the overall thickness.

[0008] For example, according to one aspect of the present disclosure, a printed circuit board may include: an insulating layer; and multiple wiring layers arranged in the insulating layer, wherein the multiple wiring layers may include a first wiring layer, a second wiring layer arranged above the first wiring layer, and a third wiring layer arranged above the second wiring layer, the second wiring layer may be thicker than each of the first wiring layer and the third wiring layer, the thickness of the second wiring layer may be greater than each of the insulation distance between the first wiring layer and the second wiring layer and the insulation distance between the second wiring layer and the third wiring layer, and when the thickness of the second wiring layer is defined as t2, the insulation distance between the first wiring layer and the second wiring layer is defined as d1, and the insulation distance between the second wiring layer and the third wiring layer is defined as d2, t2, d1 and d2 may satisfy (1.4×d1)≤t2≤(2.6×d1) and (1.4×d2)≤t2≤(2.6×d2).

[0009] One of the effects of the present disclosure is to provide a printed circuit board that can ensure excellent signal characteristics without substantially increasing the overall thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram schematically illustrating an example of an electronic device system;

[0012] Figure 2 is a perspective view schematically showing an example of an electronic device;

[0013] Figure 3 is a schematic cross-sectional view of an example of a printed circuit board;

[0014] Figure 4 is a cross-sectional view schematically showing another example of a printed circuit board;

[0015] Figure 5 is a schematic cross-sectional view of another example of a printed circuit board; and

[0016] Figure 6 is a cross-sectional view schematically showing an image of a wiring layer including a microcircuit pattern. DETAILED DESCRIPTION

[0017] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer description.

[0018] Electronic Devices

[0019] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0020] Reference Figure 1 , a main board 1010 is housed in the electronic device 1000. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also coupled to other electronic components to be described below through various signal lines 1090.

[0021] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM, flash memory), etc.; application processor chips, such as central processing units (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may have the form of a package including the above-mentioned chips and / or electronic components.

[0022] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the IEEE 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G) Protocol, Fourth Generation Mobile Communication Technology (4G) Protocol and Fifth Generation Mobile Communication Technology (5G) Protocol, and any other wireless standards or protocols and wired standards or protocols specified hereafter. However, the network-related component 1030 is not limited thereto, and may also include components compatible with or operating according to any of a variety of other wireless standards or protocols and wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020.

[0023] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components are not limited thereto, and may also include passive components in the form of chip components for various other purposes. In addition, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0024] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto, but may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition to this, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0025] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, or an automotive component. However, the electronic device 1000 is not limited thereto, and may be any other electronic device capable of processing data in addition to the above-mentioned electronic devices.

[0026] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0027] Reference Figure 2, the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may have the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface-mounted. Alternatively, the component package 1121 may have the form of a printed circuit board in which an electronic component (active component and / or a passive component) is embedded. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0028] Printed Circuit Board

[0029] Figure 3 is a schematic cross-sectional view of an example of a printed circuit board.

[0030] Reference Figure 3 , a printed circuit board 100A according to an example embodiment includes an insulating layer 110 and a plurality of wiring layers 120, 130, and 140 disposed in the insulating layer 110. The plurality of wiring layers 120, 130, and 140 include a first wiring layer 120, a second wiring layer 130 disposed above the first wiring layer 120, and a third wiring layer 140 disposed above the second wiring layer 130. The second wiring layer 130 may include a microcircuit pattern 131 (e.g., a signal pattern 131), and the first wiring layer 120 and the third wiring layer 140 may include one or more ground patterns 121 and one or more ground patterns 141, respectively. For example, the first wiring layer 120 and the third wiring layer 140 may also include signal patterns, respectively, to achieve signal transmission; and / or the second wiring layer 130 may achieve signal transmission through other wiring layers (not shown) or circuit patterns (not shown).

[0031] In addition, the second wiring layer 130 may include one or more microcircuit patterns 131, and the microcircuit pattern 131 may have an aspect ratio of 2.4 to 3.6, where the aspect ratio is the ratio of the height of the microcircuit pattern 131 to the line width. For example, the microcircuit pattern 131 may have a line width w of approximately 1 μm, a spacing s between patterns of approximately 1 μm, and a height h of approximately 3 μm, but the present disclosure is not limited thereto. In this case, the signal loss may be reduced by increasing the cross-sectional area while the signal pattern is maintained as a microcircuit pattern, thereby improving the signal characteristics. When the aspect ratio of the microcircuit pattern 131 is less than 2.4, this may not be sufficient to reduce the signal loss, and when the aspect ratio of the microcircuit pattern 131 is greater than 3.6, the yield may be reduced due to process defects, etc., and the thickness of the second wiring layer 130 may be too thick, which may make it difficult to control the overall thickness.

[0032] For example, as shown in Table 1 below, it can be seen that in Invention Examples 3 to 7 where the aspect ratio of the microcircuit pattern 131 is greater than or equal to 2.4, the signal loss is low (approximately less than -0.10 db at 3.2 GHz, and further, less than or equal to -0.08 db), but in Invention Examples 1 and 2 where the aspect ratio is less than 2.4, the signal loss is significant (approximately greater than or equal to -0.10 db at 3.2 GHz). In addition, in the case of Invention Examples 1 to 6 where the aspect ratio is less than or equal to 3.6, the expected yield is excellent at about 0.70 to 0.90 (for example, 0.75 to 0.90), but in the case of Invention Example 7 where the aspect ratio exceeds 3.6, the expected yield deteriorates to about 0.30. In addition, based on the polished cross section or the cut cross section of the printed circuit board, the line width, spacing and height of the microcircuit pattern are measured using a scanning microscope, an electron microscope and / or an optical microscope. When the line width, spacing and height of the microcircuit pattern are not constant, the corresponding values ​​are measured using the average value of the values ​​measured at any five points. Furthermore, copper (Cu) is used as a material of a microcircuit pattern.

[0033]

[0034]

[0035] In addition, the thickness of the second wiring layer 130 may be greater than the thickness of each of the first wiring layer 120 and the third wiring layer 140. For example, when the thickness of the first wiring layer 120 is defined as t1 and the thickness of the second wiring layer 130 is defined as t2 (t2 may be equal to the height h of the microcircuit pattern 131), considering the process deviation percentage of ±30%, t1 and t2 may satisfy (2.1×t1)≤t2≤(3.9×t1). In addition, when the thickness of the third wiring layer 140 is defined as t3, considering the process deviation percentage of ±30%, t2 and t3 may satisfy (2.1×t3)≤t2≤(3.9×t3). In this case, by increasing the thickness of the wiring layer including the microcircuit pattern (e.g., the second wiring layer 130 including the microcircuit pattern 131), the overall thickness can be easily controlled while reducing signal loss. When t2 is less than 2.1 times t1 and / or less than 2.1 times t3, the thickness of the wiring layer including the microcircuit pattern may not be sufficient to improve the signal characteristics, and when t2 is greater than 3.9 times t1 and / or greater than 3.9 times t3, yield problems may occur due to process defects, etc., and it may be difficult to control the overall thickness.

[0036] For example, as shown in Table 2 below, compared with Invention Example 8 which does not meet the above conditions, Invention Example 9 which meets the above conditions has an excellent effect of reducing signal loss. In addition, in the case of Invention Example 10, it can be seen that the expected yield is reduced. In addition, based on the polished cross section or cut cross section of the printed circuit board, the thickness of the wiring layer is measured using a scanning microscope, an electron microscope and / or an optical microscope. When the thickness of the wiring layer is not constant, the average value of the values ​​measured at any five points is used to measure the thickness value of the corresponding wiring layer. In addition, copper (Cu) is used as the material of the pattern of each wiring layer.

[0037]

[0038] Invention Example t1 t2 t3 Signal loss [at 3.2GHz] Expected yield (Y) 8 1.0μm 2.0μm 1.0μm -0.10dB 0.85 9 1.0μm 3.0μm 1.0μm -0.07dB 0.75 10 1.0μm 4.0μm 1.0μm -0.06dB 0.30

[0039] In addition, the thickness of the second wiring layer 130 may be greater than the insulation distance between the first wiring layer 120 and the second wiring layer 130 and greater than the insulation distance between the second wiring layer 130 and the third wiring layer 140. For example, when the thickness of the second wiring layer 130 is defined as t2 and the insulation distance between the first wiring layer 120 and the second wiring layer 130 is defined as d1, considering the process deviation percentage of ±30%, t2 and d1 may satisfy (1.4×d1)≤t2≤(2.6×d1). In addition, when the insulation distance between the second wiring layer 130 and the third wiring layer 140 is defined as d2, considering the process deviation percentage of ±30%, t2 and d2 may satisfy (1.4×d2)≤t2≤(2.6×d2). In this case, by increasing the thickness of the wiring layer including the microcircuit pattern, the overall thickness can be easily controlled while reducing signal loss. When t2 is less than 1.4 times d1 and / or less than 1.4 times d2, this may not be sufficient to improve signal characteristics, and when t2 is greater than 2.6 times d1 and / or greater than 2.6 times d2, yield issues may occur due to process defects, etc., and it may be difficult to control the overall thickness.

[0040] For example, as shown in Table 3 below, it can be seen that, compared with Invention Example 11 and Invention Example 13 which do not meet the above conditions, Invention Example 12 which meets the above conditions has an excellent effect of reducing signal loss. In addition, in the case of Invention Example 13, it can be seen that the expected yield is reduced. In addition, based on the polished cross section or cut cross section of the printed circuit board, the thickness of the wiring layer and the insulation distance between the wiring layers are measured using a scanning microscope, an electron microscope and / or an optical microscope. When the thickness of the wiring layer and the insulation distance between the wiring layers are not constant, the average value of the values ​​measured at any five points is used to measure the thickness of the corresponding wiring layer and the insulation distance value between the wiring layers.

[0041] In one embodiment, the insulation distance between the first wiring layer 120 and the second wiring layer 130 and the insulation distance between the second wiring layer 130 and the third wiring layer 140 may be substantially the same as each other. It will be understood by those skilled in the art that the expression "substantially the same" includes the case of being completely identical as well as the case of process errors, position deviations and / or measurement errors that may occur in the manufacturing process, and the range of the errors and deviations may be widely accepted in the art (e.g., ±5%, but not limited thereto).

[0042]

[0043] Invention Example t2 d1 d2 Signal loss [at 3.2GHz] Expected yield (Y) 11 3.0μm 3.0μm 3.0μm -0.12dB 0.85 12 3.0μm 1.5μm 1.5μm -0.07dB 0.75 13 3.0μm 0.5μm 0.5μm -0.12dB 0.20

[0044] In addition, the printed circuit board 100A according to example embodiments may be used independently, or may be attached to or embedded in another substrate.

[0045] Hereinafter, components of a printed circuit board 100A according to example embodiments will be described in more detail with reference to the accompanying drawings.

[0046] The insulating layer 110 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler and / or glass fiber (for example, glass fabric using glass cloth as an example) and a thermosetting resin and / or a thermoplastic resin. For example, the insulating material may be a non-photosensitive insulating material such as an Ajinomoto Build-up Film (ABF) or a prepreg (PPG), but the present disclosure is not limited thereto, and in addition thereto, other polymer materials may be used as insulating materials. In addition, the insulating material may be a photosensitive insulating material such as a photosensitive dielectric (PID). The insulating layer 110 may have a multilayer structure, and the multilayer structure may have interlayer boundaries or may not have interlayer boundaries.

[0047] Each of the first wiring layer 120, the second wiring layer 130 and the third wiring layer 140 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first wiring layer 120, the second wiring layer 130 and the third wiring layer 140 may perform various functions according to the design. For example, each of the first wiring layer 120, the second wiring layer 130 and the third wiring layer 140 may include a signal pattern, a power pattern and a ground pattern. Each of these patterns may have various shapes (such as a line shape, a plane shape and a pad shape, etc.). Each of the first wiring layer 120, the second wiring layer 130 and the third wiring layer 140 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Optionally, each of the first wiring layer 120, the second wiring layer 130, and the third wiring layer 140 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Optionally, each of the first wiring layer 120, the second wiring layer 130, and the third wiring layer 140 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). If necessary, each of the first wiring layer 120, the second wiring layer 130, and the third wiring layer 140 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), or may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer). If necessary, the first wiring layer 120, the second wiring layer 130, and the third wiring layer 140 may be electrically connected to each other through one or more connection vias that penetrate at least a portion of the insulating layer 110, respectively.

[0048] Figure 4is a cross-sectional view schematically showing another example of a printed circuit board.

[0049] Reference Figure 4 A printed circuit board 100B according to another example embodiment may further include, in the printed circuit board 100A according to the aforementioned example embodiment, a fourth wiring layer 150 disposed above the third wiring layer 140 and a fifth wiring layer 160 disposed above the fourth wiring layer 150. The fourth wiring layer 150 may include a microcircuit pattern 151 (e.g., a signal pattern), and the third wiring layer 140 and the fifth wiring layer 160 may include a ground pattern 141 and a ground pattern 161, respectively.

[0050] In addition, the second wiring layer 130 and the fourth wiring layer 150 may include one or more microcircuit patterns 131 and one or more microcircuit patterns 151, respectively, and each of the microcircuit patterns 131 and 151 may have an aspect ratio of 2.4 to 3.6, which is a ratio of the height of the corresponding microcircuit pattern to the line width. For example, the microcircuit patterns 131 and 151 may have line widths w1 and w2 of approximately 1 μm, intervals s1 and s2 between patterns of approximately 1 μm, and heights h1 and h2 of approximately 3 μm, respectively, but the present disclosure is not limited thereto. In this case, the signal characteristics can be improved by reducing the signal loss by increasing the cross-sectional area while maintaining the signal pattern as a microcircuit pattern, and the details thereof are as described above.

[0051] In addition, the thickness of the fourth wiring layer 150 may be greater than the thickness of each of the third wiring layer 140 and the fifth wiring layer 160. For example, when the thickness of the third wiring layer 140 is defined as t3 and the thickness of the fourth wiring layer 150 is defined as t4 (t4 may be equal to the height h2 of the microcircuit pattern 151), considering the process deviation percentage of ±30%, t3 and t4 may satisfy (2.1×t3)≤t4≤(3.9×t3). In addition, when the thickness of the fifth wiring layer 160 is defined as t5, considering the process deviation percentage of ±30%, t4 and t5 may satisfy (2.1×t5)≤t4≤(3.9×t5). In this case, by increasing the thickness of the wiring layer including the microcircuit pattern (for example, the fourth wiring layer 150 including the microcircuit pattern 151), the overall thickness can be easily controlled while reducing signal loss, and the details thereof are as described above.

[0052] In addition, the thickness of the fourth wiring layer 150 may be greater than the insulation distance between the third wiring layer 140 and the fourth wiring layer 150, and may be greater than the insulation distance between the fourth wiring layer 150 and the fifth wiring layer 160. For example, when the thickness of the fourth wiring layer 150 is defined as t4 and the insulation distance between the third wiring layer 140 and the fourth wiring layer 150 is defined as d3, considering the process deviation percentage of ±30%, t4 and d3 may satisfy (1.4×d3)≤t4≤(2.6×d3). In addition, when the insulation distance between the fourth wiring layer 150 and the fifth wiring layer 160 is defined as d4, considering the process deviation percentage of ±30%, t4 and d4 may satisfy (1.4×d4)≤t4≤(2.6×d4). In this case, by increasing the thickness of the wiring layer including the microcircuit pattern, the overall thickness can be easily controlled while reducing signal loss, and the details thereof are as described above.

[0053] Hereinafter, components of a printed circuit board 100B according to another example embodiment will be described in more detail with reference to the accompanying drawings.

[0054] Each of the fourth wiring layer 150 and the fifth wiring layer 160 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. Each of the fourth wiring layer 150 and the fifth wiring layer 160 may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the fourth wiring layer 150 and the fifth wiring layer 160 may perform various functions according to the design. For example, each of the fourth wiring layer 150 and the fifth wiring layer 160 may include a signal pattern, a power pattern and a ground pattern. Each of these patterns may have various shapes (such as a line shape, a plane shape and a pad shape, etc.). Each of the fourth wiring layer 150 and the fifth wiring layer 160 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Optionally, each of the fourth wiring layer 150 and the fifth wiring layer 160 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Optionally, each of the fourth wiring layer 150 and the fifth wiring layer 160 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). If necessary, each of the fourth wiring layer 150 and the fifth wiring layer 160 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), or may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer). If necessary, the first wiring layer 120, the second wiring layer 130, the third wiring layer 140, the fourth wiring layer 150 and the fifth wiring layer 160 may be electrically connected to each other through one or more connection vias that penetrate at least a portion of the insulating layer 110, respectively.

[0055] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described exemplary embodiment, and thus a repeated description thereof will be omitted.

[0056] Figure 5 is a schematic cross-sectional view of another example of a printed circuit board.

[0057] Reference Figure 5 According to another exemplary embodiment, a printed circuit board 200 may include: a core layer 211; a first core wiring layer 221a and a second core wiring layer 221b, which are respectively disposed on the upper surface and the lower surface of the core layer 211; a through-hole 231, which penetrates the core layer 211 and connects the first core wiring layer 221a and the second core wiring layer 221b to each other; a plurality of first buildup insulating layers 212, which are disposed on the upper surface of the core layer 211; a plurality of first buildup wiring layers 222a, 222b, 222c and 222d, which are respectively disposed on the plurality of first buildup insulating layers 212 or respectively disposed in the plurality of first buildup insulating layers 212; a plurality of first buildup via layers 232, each of which has a plurality of first buildup via layers 232. At least one of the plurality of first stacked insulating layers 212 is penetrated and each first stacked via layer 232 is connected to at least one of the plurality of first stacked wiring layers 222a, 222b, 222c and 222d; a plurality of second stacked insulating layers 213 are disposed on the lower surface of the core layer 211; a plurality of second stacked wiring layers 223 are respectively disposed on the plurality of second stacked insulating layers 213 or respectively disposed in the plurality of second stacked insulating layers 213; and a plurality of second stacked via layers 233, each second stacked via layer 233 penetrates at least one of the plurality of second stacked insulating layers 213, and each second stacked via layer 233 is connected to at least one of the plurality of second stacked wiring layers 223. If necessary, the printed circuit board 200 may further include a first resist layer 241 disposed above the plurality of first stacked insulating layers 212 and / or a second resist layer 242 disposed below the plurality of second stacked insulating layers 213.

[0058] In addition, the plurality of first buildup insulating layers 212 may include: the insulating layer 110 of the printed circuit board 100A according to the above-described example embodiment or the insulating layer 110 of the printed circuit board 100B according to the above-described another example embodiment. In addition, the plurality of first buildup wiring layers 222a, 222b, 222c, and 222d may include the plurality of wiring layers 120, 130, and 140 of the printed circuit board 100A according to the above-described example embodiment or the plurality of wiring layers 120, 130, 140, 150, and 160 of the printed circuit board 100B according to the above-described another example. For example, the printed circuit board 200 according to another example embodiment may have a first region R1 and / or a second region R2, and the printed circuit board 100A according to the above-described example embodiment or the printed circuit board 100B according to another example embodiment may be applied to the first region R1 and / or the second region R2. For example, the printed circuit board 200 according to another example embodiment may be a package substrate, and may have a wiring layer including the above-described microcircuit pattern in the first region R1 and / or the second region R2. However, the structure of the printed circuit board 200 is not limited thereto, and for example, the structure located above the core layer 211 in the printed circuit board 200 may be interchanged with the structure located below the core layer 211. For example, the first buildup wiring layers 222a and 222c may further include signal patterns to implement signal transmission, respectively; and / or the first buildup wiring layer 222b may implement signal transmission through other wiring layers (not shown) or circuit patterns (not shown).

[0059] On the other hand, if necessary, the printed circuit board 100A according to the above example embodiment or the printed circuit board 100B according to the above another example embodiment may be embedded in the printed circuit board 200 according to another example embodiment in the form of a separate micro circuit board in the first region R1 and / or the second region R2. For example, after forming a cavity in the plurality of first buildup insulating layers 212 of the printed circuit board 200 according to another example embodiment, the printed circuit board 100A according to the above example embodiment or the printed circuit board 100B according to the above another example embodiment may be inserted into the cavity and embedded in the cavity. For example, the printed circuit board 100A according to the above example embodiment or the printed circuit board 100B according to the above another example embodiment may be used as an organic bridge for interconnection.

[0060] Hereinafter, components of a printed circuit board 200 according to another example embodiment will be described in more detail with reference to the accompanying drawings.

[0061] The core layer 211 may include an insulating material. A thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material in which a thermosetting resin and / or a thermoplastic resin is mixed with an inorganic filler (such as silica), or a material prepared by impregnating a core material such as glass fiber (for example, glass fabric exemplified by glass cloth) and an inorganic filler in a resin (for example, a copper clad laminate (CCL)) may be used as an insulating material, but the present disclosure is not limited thereto. The thickness of the core layer 211 may be greater than the thickness of each of the plurality of first stacked insulating layers 212 and the plurality of second stacked insulating layers 213, but the present disclosure is not limited thereto.

[0062] Each of the plurality of first stacked insulating layers 212 and the plurality of second stacked insulating layers 213 may include an insulating material. A thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material in which a thermosetting resin and / or a thermoplastic resin is mixed with an inorganic filler such as silica, or a material prepared by impregnating a core material such as glass fiber and an inorganic filler in a resin (e.g., Ajinomoto stacked film (ABF), prepreg, resin coated copper (RCC), and photosensitive dielectric (PID)) may be used as the insulating material, but the present disclosure is not limited thereto. The number of layers of the plurality of first stacked insulating layers 212 and the number of layers of the plurality of second stacked insulating layers 213 may be the same, but the present disclosure is not limited thereto.

[0063] Each of the first core wiring layer 221a and the second core wiring layer 221b may include a metal material. Copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys may be used as the metal material, and the metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. The first core wiring layer 221a and the second core wiring layer 221b may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), respectively, but the present disclosure is not limited thereto. Each of the first core wiring layer 221a and the second core wiring layer 221b may include a sputtering layer instead of an electroless plating layer, or may include both a sputtering layer and an electroless plating layer. In addition, each of the first core wiring layer 221a and the second core wiring layer 221b may also include a copper foil. Each of the first core wiring layer 221a and the second core wiring layer 221b may perform various functions according to the design of the corresponding layer. For example, each of the first core wiring layer 221a and the second core wiring layer 221b may include a ground pattern, a power pattern, and a signal pattern. Each of these patterns may include a line pattern, a plane pattern, and / or a pad pattern.

[0064] Each of the plurality of first buildup wiring layers 222a, 222b, 222c, 222d and the plurality of second buildup wiring layers 223 may include a metal material. Copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof may be used as the metal material, and the metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the plurality of first buildup wiring layers 222a, 222b, 222c, 222d and the plurality of second buildup wiring layers 223 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. Each of the plurality of first buildup wiring layers 222a, 222b, 222c, 222d and the plurality of second buildup wiring layers 223 may include a sputtering layer instead of an electroless plating layer, or may include both a sputtering layer and an electroless plating layer. In addition, each of the plurality of first buildup wiring layers 222a, 222b, 222c, 222d and the plurality of second buildup wiring layers 223 may further include copper foil. Each of the plurality of first buildup wiring layers 222a, 222b, 222c, 222d and the plurality of second buildup wiring layers 223 may perform various functions according to the design of the corresponding layer. For example, each of the plurality of first buildup wiring layers 222a, 222b, 222c, 222d and the plurality of second buildup wiring layers 223 may include a ground pattern, a power pattern and a signal pattern. Each of these patterns may include a line pattern, a plane pattern and / or a pad pattern.

[0065] The through-hole 231 may include a metal layer formed on the wall surface of the through-hole and a plug portion filled with the metal layer. The metal layer may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys, and the metal layer may preferably include copper (Cu), but the present disclosure is not limited thereto. The plug portion may include an insulating material (e.g., ink). The metal layer may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. The metal layer may include a sputtering layer instead of an electroless plating layer, or may include both a sputtering layer and an electroless plating layer. The through-hole 231 may perform various functions according to the design. For example, the through-hole 231 may include a ground via, a power via, and a signal via.

[0066] Each of the plurality of first stacked via layers 232 and the plurality of second stacked via layers 233 may include a micro via. The micro via may be a filled via that fills the via hole or a conformal via arranged along the wall surface of the via hole. The micro via may be arranged in a stacked type and / or a staggered type. Each of the plurality of first stacked via layers 232 and the plurality of second stacked via layers 233 may include a metal material, and the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys, and may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the plurality of first stacked via layers 232 and the plurality of second stacked via layers 233 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. Each of the plurality of first stacked via layers 232 and the plurality of second stacked via layers 233 may include a sputtering layer instead of an electroless plating layer, or may include both a sputtering layer and an electroless plating layer. The plurality of first stacked via layers 232 and the plurality of second stacked via layers 233 may perform various functions according to the design of the corresponding layers. For example, the plurality of first stacked via layers 232 and the plurality of second stacked via layers 233 may include ground vias, power vias, and signal vias.

[0067] The first resist layer 241 and the second resist layer 242 may include a liquid solder resist or a film solder resist, but the present disclosure is not limited thereto, and other types of insulating materials may be used. The first resist layer 241 may have an opening that exposes at least a portion of the first buildup wiring layer 222d on the uppermost side. The second resist layer 242 may have an opening that exposes at least a portion of the second buildup wiring layer 223 on the lowermost side.

[0068] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described example embodiment and the printed circuit board 100B according to the above-described other example embodiment, and thus a repeated description thereof will be omitted.

[0069] Figure 6 is a cross-sectional view schematically showing an image of a wiring layer including a microcircuit pattern.

[0070] Reference Figure 6 , the microcircuit pattern according to the present disclosure may have a line width of about 1 μm and a spacing of about 1 μm, and may have a thickness or height of about 3 μm. For example, the aspect ratio may be about 3. In this case, since the microcircuit pattern can increase the cross-sectional area, excellent signal characteristics can be obtained by reducing signal loss. In addition, a cross-sectional image of the wiring layer can be obtained using a known scanning microscope, electron microscope, and / or optical microscope.

[0071] In the present disclosure, "substantially / approximately" may be determined by including process errors or positional deviations occurring in the manufacturing process, errors in measurement. For example, the fact that "line width, spacing, thickness, and height have approximately specific values" may include not only having corresponding values, but also having values ​​similar thereto.

[0072] In the present disclosure, “the same insulating material” may refer not only to the case where the insulating materials are exactly the same, but also to the case where the types of the insulating materials are the same, for example, the compositions of the insulating materials may be substantially the same, but the specific composition ratios thereof may be slightly different.

[0073] In the present disclosure, the meaning of "cross section" may refer to the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when the object is viewed from a side perspective. In addition, the meaning of "plane" may refer to the cross-sectional shape when an object is cut horizontally, or the plane shape when the object is viewed from a top or bottom perspective.

[0074] In the present disclosure, "lower side", "lower part" and "lower surface" are used to refer to the downward direction relative to the cross section of the drawings, and "upper side", "upper part" and "upper surface" are used to refer to the opposite direction. However, these directions are defined for convenience of explanation, and the scope of the claims is not particularly limited by the description of such directions, and the concepts of "upper part" and "lower part" can be interchanged at any time.

[0075] In the present disclosure, the meaning of "connection" includes not only the concept of direct connection, but also the concept of indirect connection through an adhesive layer or the like. In addition, the meaning of "electrical connection" includes the concepts of physical connection and non-physical connection. In addition, expressions such as "first" and "second" are used to distinguish one component from another component and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component without departing from the scope of the claims.

[0076] The expression "example embodiments used in the present disclosure" does not mean the same embodiment, but is provided to illustrate different unique features. However, the example embodiments presented above do not exclude implementation in combination with features of other example embodiments. For example, even if the content described in a specific example embodiment is not described in other example embodiments, it can be understood as an interpretation related to the other example embodiments unless there is an interpretation contrary or contradictory to the content in other example embodiments.

[0077] The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, unless the context clearly indicates a different meaning, a singular expression includes a plural expression.

Claims

1. A printed circuit board, comprising: Insulation layer; as well as A plurality of wiring layers are provided in the insulating layer, The plurality of wiring layers include a first wiring layer, a second wiring layer disposed above the first wiring layer, and a third wiring layer disposed above the second wiring layer. The second wiring layer is thicker than each of the first wiring layer and the third wiring layer, and The second wiring layer includes a microcircuit pattern, and the microcircuit pattern has an aspect ratio of 2.4 to 3.6, the aspect ratio being a ratio of a height to a line width of the microcircuit pattern.

2. The printed circuit board according to claim 1, wherein: Each of the first wiring layer and the third wiring layer includes a ground pattern, and The microcircuit pattern of the second wiring layer is a signal pattern.

3. The printed circuit board according to claim 1, wherein: The microcircuit pattern of the second wiring layer has a line width of 1 μm and a height of 3 μm; and / or The second wiring layer includes a plurality of the microcircuit patterns, and an interval between adjacent microcircuit patterns in the plurality of the microcircuit patterns is 1 μm.

4. The printed circuit board according to claim 1, wherein: When the thickness of the first wiring layer is defined as t1 and the thickness of the second wiring layer is defined as t2, t1 and t2 satisfy (2.1×t1)≤t2≤(3.9×t1).

5. The printed circuit board according to claim 1, wherein When the thickness of the second wiring layer is defined as t2 and the thickness of the third wiring layer is defined as t3, t2 and t3 satisfy (2.1×t3)≤t2≤(3.9×t3).

6. The printed circuit board according to claim 1, wherein The thickness of the second wiring layer is larger than each of an insulation distance between the first wiring layer and the second wiring layer and an insulation distance between the second wiring layer and the third wiring layer.

7. The printed circuit board according to claim 6, wherein: When the thickness of the second wiring layer is defined as t2 and the insulation distance between the first wiring layer and the second wiring layer is defined as d1, t2 and d1 satisfy (1.4×d1)≤t2≤(2.6×d1).

8. The printed circuit board according to claim 6, wherein: When the thickness of the second wiring layer is defined as t2 and the insulation distance between the second wiring layer and the third wiring layer is defined as d2, t2 and d2 satisfy (1.4×d2)≤t2≤(2.6×d2).

9. The printed circuit board according to claim 8, wherein: An insulation distance between the first wiring layer and the second wiring layer and an insulation distance between the second wiring layer and the third wiring layer are the same as each other.

10. The printed circuit board according to claim 1, wherein The plurality of wiring layers further include a fourth wiring layer disposed above the third wiring layer and a fifth wiring layer disposed above the fourth wiring layer, and The fourth wiring layer is thicker than each of the third wiring layer and the fifth wiring layer.

11. The printed circuit board according to claim 10, wherein: The thickness of the fourth wiring layer is larger than each of an insulation distance between the third wiring layer and the fourth wiring layer and an insulation distance between the fourth wiring layer and the fifth wiring layer.

12. The printed circuit board according to claim 1, comprising a plurality of build-up insulation layers, a plurality of build-up wiring layers and a plurality of build-up via layers, The plurality of built-up insulating layers include the insulating layer, and The plurality of build-up wiring layers include the plurality of wiring layers.

13. The printed circuit board according to claim 12, further comprising: Core layer; A first core wiring layer and a second core wiring layer are respectively arranged on the upper surface and the lower surface of the core layer; The through via penetrates the core layer and connects the first core wiring layer and the second core wiring layer to each other.

14. The printed circuit board according to claim 13, wherein: The plurality of stacked insulating layers include: a plurality of first stacked insulating layers disposed on the upper surface of the core layer and including the insulating layer; and a plurality of second stacked insulating layers disposed on the lower surface of the core layer. The plurality of built-up wiring layers include: a plurality of first built-up wiring layers, which are respectively arranged on the plurality of first built-up insulating layers or respectively arranged in the plurality of first built-up insulating layers, and include the plurality of wiring layers; and a plurality of second built-up wiring layers, which are respectively arranged on the plurality of second built-up insulating layers or respectively arranged in the plurality of second built-up insulating layers, and The multiple stacked via layers include: multiple first stacked via layers, each first stacked via layer penetrates at least one of the multiple first stacked insulation layers, and each first stacked via layer is connected to at least one of the multiple first stacked wiring layers; and multiple second stacked via layers, each second stacked via layer penetrates at least one of the multiple second stacked insulation layers, and each second stacked via layer is connected to at least one of the multiple second stacked wiring layers.

15. A printed circuit board, comprising: Insulation layer; as well as A plurality of wiring layers are provided in the insulating layer, The plurality of wiring layers include a first wiring layer, a second wiring layer disposed above the first wiring layer, and a third wiring layer disposed above the second wiring layer. the second wiring layer is thicker than each of the first wiring layer and the third wiring layer, The thickness of the second wiring layer is larger than each of an insulation distance between the first wiring layer and the second wiring layer and an insulation distance between the second wiring layer and the third wiring layer, and When the thickness of the second wiring layer is defined as t2, the insulation distance between the first wiring layer and the second wiring layer is defined as d1, and the insulation distance between the second wiring layer and the third wiring layer is defined as d2, t2, d1 and d2 satisfy (1.4×d1)≤t2≤(2.6×d1) and (1.4×d2)≤t2≤(2.6×d2).

16. The printed circuit board according to claim 15, wherein When the thickness of the first wiring layer and the thickness of the third wiring layer are defined as t1 and t3, respectively, t1, t2, and t3 satisfy (2.1×t1)≤t2≤(3.9×t1) and (2.1×t3)≤t2≤(3.9×t3).

17. The printed circuit board according to claim 15, wherein: Each of the first wiring layer and the third wiring layer includes one or more ground patterns, and The second wiring layer includes a signal pattern.

18. The printed circuit board according to claim 17, wherein: The signal pattern has a line width of 1 μm and a height of 3 μm; and / or The second wiring layer includes a plurality of the signal patterns, and an interval between adjacent signal patterns in the plurality of the signal patterns is 1 μm.

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