Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of suppressing concentration of an electric field when a voltage is applied while suppressing a decrease in capacitance. A laminated body (10) having a plurality of dielectric layers (20) and a plurality of internal electrode layers (30), and first and second external electrodes (40A, 40B), the plurality of internal electrode layers (30) having a plurality of first and second internal electrode layers (31, 32) electrically connected to the first and second external electrodes (40A, 40B), respectively, a plurality of holes (H) having different area-equivalent diameters being present in the first and second internal electrode layers (31, 32), and the first and second internal electrode layers (31, 32) being electrically connected to the first and second external electrodes (40A, 40B). The thickness t of a dielectric layer (20) is 0.6 [mu] m or less and satisfies formula (1), # imgabs0 #, where the area-equivalent diameter having a cumulative value of 99% in the cumulative distribution of the area-equivalent diameters of a plurality of holes (H) is defined as the area-equivalent diameter (D99), and the thickness t of the dielectric layer (20) sandwiched between first and second internal electrode layers (31, 32) is defined as the thickness t.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] In the past, there are known laminated ceramic capacitors. Generally, laminated ceramic capacitors have a laminated body formed by alternately laminating a plurality of dielectric layers and internal electrode layers. In such laminated ceramic capacitors, further miniaturization, higher capacitance, and improved reliability are required. Therefore, attempts have been made to thin the dielectric layer, thin the internal electrode layer, and increase the number of layers stacked.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2000-133545 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] However, as the dielectric layer is thinned, the electric field strength applied to each layer becomes relatively high, and the reliability when the voltage is applied decreases. For example, the following content is shown in the above-mentioned patent document 1: When a thin dielectric layer is used for high voltage, insulation breakdown may occur due to the concentration of the electric field. In addition, the following content is also shown in patent document 1: By providing a plurality of auxiliary electrodes, a high withstand voltage of the stacked ceramic capacitor can be achieved. However, since the stacked ceramic capacitor of patent document 1 has a plurality of auxiliary electrodes, it is difficult to ensure the area of ​​the effective part of the capacitor that generates electrostatic capacitance. Therefore, it is difficult to suppress the decrease in electrostatic capacitance and suppress the concentration of the electric field.

[0008] An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing a decrease in electrostatic capacitance and electric field concentration when voltage is applied by forming a dielectric layer interposed between a plurality of internal electrode layers from a relatively thin layer.

[0009] Technical solutions to solve problems

[0010] The multilayer ceramic capacitor of the present invention comprises: a multilayer body having a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; and a first external electrode and a second external electrode, the plurality of internal electrode layers having a plurality of first internal electrode layers electrically connected to the first external electrode and a plurality of second internal electrode layers electrically connected to the second external electrode, a plurality of holes having different area equivalent diameters being present in the first internal electrode layer and the second internal electrode layer, an area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes becomes 99% being set as an area equivalent diameter D99, and when the thickness of the dielectric layer sandwiched between the first internal electrode layer and the second internal electrode layer is set as a thickness t, the thickness t of the dielectric layer is not more than 0.6 μm, and the following formula (1) is satisfied.

[0011] (Area equivalent diameter D99) < 0.1468 × exp (6.7622 × t) … (1)

[0012] Effects of the Invention

[0013] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of suppressing a decrease in electrostatic capacitance and electric field concentration when voltage is applied by forming a dielectric layer interposed between a plurality of internal electrode layers from a relatively thin layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment.

[0015] Figure 2 It is along Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line II-II shown in FIG.

[0016] Figure 3 It is along Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line III-III.

[0017] Figure 4A It is along Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line IVA-IVA shown in FIG.

[0018] Figure 4B It is along Figure 2 FIG. 1 is a cross-sectional view taken along line IVB-IVB of the multilayer ceramic capacitor shown.

[0019] Figure 5 yes Figure 4AAn enlarged view of the V portion of the multilayer ceramic capacitor 1 is shown.

[0020] Figure 6 This is a diagram showing area-equivalent diameter distribution data of a plurality of pores existing in the internal electrode layer.

[0021] Fig. 7A is a diagram showing a model of an internal electrode layer used for simulation.

[0022] Figure 7B 1 is a diagram showing the electric field intensity distribution near the hole of the internal electrode layer.

[0023] Figure 8 This is a graph in which the maximum electric field intensity in the model calculated in each simulation model with the value of the area-equivalent diameter D99 of the pores existing in the internal electrode layer being varied is plotted.

[0024] Fig. 9 This is a graph in which the maximum electric field intensity in the model calculated in each simulation model is plotted while changing the thickness of the dielectric layer and the value of the area-equivalent diameter D99 of the pores present in the internal electrode layer.

[0025] Fig.10 It is a graph for showing a region where electric field concentration can be suppressed when voltage is applied.

[0026] Fig.11 This is a diagram for explaining a method for measuring the thicknesses of the internal electrode layers and the dielectric layers, and is a diagram showing an example of an enlarged image of a cross section of an exposed effective layer portion in a multilayer ceramic capacitor observed by SEM.

[0027] Fig.12 is with Figure 3 The SEM image corresponding to the enlarged view of the portion XII of the multilayer ceramic capacitor shown is a diagram showing a burnout state of the multilayer body at the time of dielectric breakdown when an accelerated life test is performed. DETAILED DESCRIPTION

[0028] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described. Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the present embodiment. Figure 2 It is along Figure 1 A cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II. Figure 3 It is along Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III. Figure 4A It is along Figure 2 A cross-sectional view of the multilayer ceramic capacitor 1 taken along line IVA-IVA is shown. Figure 4B It is along Figure 21 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line IVB-IVB.

[0029] The multilayer ceramic capacitor 1 includes a multilayer body 10 and external electrodes 40 .

[0030] exist Figure 1 to Figure 4B The XYZ orthogonal coordinate system is shown in FIG. The length direction L of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the X direction. The width direction W of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Y direction. The height direction T of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Z direction. Here, Figure 2 The section shown is also referred to as the LT section. Figure 3 The section shown is also referred to as the WT section. Figure 4A and Figure 4B The section shown is also referred to as the LW section.

[0031] like Figure 1 to Figure 4B As shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction T, a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W orthogonal to the height direction T, and a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L orthogonal to the height direction T and the width direction W.

[0032] like Figure 1 As shown, the laminate 10 has a substantially rectangular parallelepiped shape. It should be noted that the dimension of the length direction L of the laminate 10 is not necessarily longer than the dimension of the width direction W. It is preferred that the corners and ridges of the laminate 10 are rounded. The corner is the portion where three faces of the laminate intersect, and the ridge is the portion where two faces of the laminate intersect. It should be noted that concavities and convexities may also be formed on a portion or all of the surface constituting the laminate 10.

[0033] The size of the laminate 10 is not particularly limited, but when the dimension in the length direction L of the laminate 10 is set to L dimension, the L dimension is preferably 0.2 mm or more and 6 mm or less. In addition, when the dimension in the height direction T of the laminate 10 is set to T dimension, the T dimension is preferably 0.05 mm or more and 5 mm or less. In addition, when the dimension in the width direction W of the laminate 10 is set to W dimension, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0034] like Figure 2 and Figure 3 As shown, the laminate 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged in the height direction T so as to sandwich the inner layer portion 11 .

[0035] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 side to the internal electrode layer 30 located closest to the second main surface TS2 side in the height direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite to each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and substantially functions as a capacitor.

[0036] The plurality of dielectric layers 20 are composed of dielectric materials. The dielectric material may be, for example, a dielectric ceramic including BaTiO3, CaTiO3, SrTiO3, or CaZrO3. In addition, the dielectric material may be a material obtained by adding a secondary component such as a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound to these main components. The dielectric material is preferably a material including BaTiO3 as a main component.

[0037] The thickness of the dielectric layer 20 is preferably 0.6 μm or less. The number of the laminated dielectric layers 20 is preferably 15 or more and 1200 or less. It should be noted that the number of the dielectric layers 20 is the total number of the dielectric layers of the inner layer portion 11 and the dielectric layers of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0038] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 are arranged on the plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on the plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the height direction T of the laminate 10 with the dielectric layers 20 interposed therebetween. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layer 20.

[0039] The first internal electrode layer 31 includes a first opposing portion 31A opposing the second internal electrode layer 32 and a first lead portion 31B led out from the first opposing portion 31A toward the first end surface LS1. The first lead portion 31B is exposed at the first end surface LS1.

[0040] The second internal electrode layer 32 includes a second opposing portion 32A opposing the first internal electrode layer 31 and a second lead portion 32B led out from the second opposing portion 32A toward the second end surface LS2. The second lead portion 32B is exposed at the second end surface LS2.

[0041] In the present embodiment, the first opposing portion 31A and the second opposing portion 32A are opposed to each other via the dielectric layer 20 to form a capacitor, thereby exhibiting the characteristics of a capacitor.

[0042] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely. The shapes of the first lead-out portion 31B and the second lead-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely.

[0043] The dimension of the first opposing portion 31A in the width direction W and the dimension of the first lead portion 31B in the width direction W may be formed to be the same dimension, or one of the dimensions may be formed to be smaller. The dimension of the second opposing portion 32A in the width direction W and the dimension of the second lead portion 32B in the width direction W may be formed to be the same dimension, or one of the dimensions may be formed to be narrower.

[0044] like Figure 4A As shown, the first internal electrode layer 31 has a first side WE1 on the first side surface WS1 and a second side WE2 on the second side surface WS2. Figure 4B As shown, the second internal electrode layer 32 has a third side WE3 on the first side surface WS1 side and a fourth side WE4 on the second side surface WS2 side.

[0045] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0046] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 15 or more and 1000 or less in total. It should be noted that the thickness of the first internal electrode layer 31 and the second internal electrode layer 32 may be thicker than the thickness of the dielectric layer 20.

[0047] The first main surface side outer layer portion 12 is located on the first main surface TS1 side of the stacked body 10. The first main surface side outer layer portion 12 is an aggregate of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layer 20 used in the first main surface side outer layer portion 12 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0048] The second main surface side outer layer portion 13 is located on the second main surface TS2 side of the stacked body 10. The second main surface side outer layer portion 13 is an aggregate of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layer 20 used in the second main surface side outer layer portion 13 may be the same as the dielectric layer 20 used in the inner layer portion 11.

[0049] Thus, the laminated body 10 includes a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20. That is, the laminated ceramic capacitor 1 includes the laminated body 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated.

[0050] The laminate 10 includes an opposing electrode portion 11E. The opposing electrode portion 11E is a portion where the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other. The opposing electrode portion 11E is configured as a part of the internal layer portion 11. Figure 4A and Figure 4B 1 and 2 show the range of the opposing electrode portion 11E in the width direction W and the length direction L. It should be noted that the opposing electrode portion 11E is also referred to as a capacitor effective portion.

[0051] It should be noted that the stack 10 has a side outer layer portion. The side outer layer portion has a first side outer layer portion WG1 and a second side outer layer portion WG2. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figure 3 , Figure 4A and Figure 4B The range of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2 in the width direction W is shown. It should be noted that the side surface outer layer portion is also referred to as a W gap or a side gap.

[0052] It should be noted that the stacked body 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first end surface LS1. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second end surface LS2. Figure 2 , Figure 4A and Figure 4B The range of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L is shown. It should be noted that the end surface side outer layer portion is also referred to as an L gap or an end gap.

[0053] The external electrode 40 includes a first external electrode 40A disposed on the first end surface LS1 side and a second external electrode 40B disposed on the second end surface LS2 side.

[0054] The first external electrode 40A is arranged on the first end surface LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In the present embodiment, the first external electrode 40A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0055] The second external electrode 40B is arranged on the second end surface LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In the present embodiment, the second external electrode 40B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0056] As described above, in the laminate 10, a capacitor is formed by the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 being opposed to each other via the dielectric layer 20. Therefore, the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32 exhibit capacitor characteristics.

[0057] The first external electrode 40A includes a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A.

[0058] The second external electrode 40B includes a second underlying electrode layer 50B and a second plating layer 60B disposed on the second underlying electrode layer 50B.

[0059] The first foundation electrode layer 50A is arranged on the first end surface LS1. The first foundation electrode layer 50A is connected to the first internal electrode layer 31. In the present embodiment, the first foundation electrode layer 50A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0060] The second foundation electrode layer 50B is arranged on the second end surface LS2. The second foundation electrode layer 50B is connected to the second internal electrode layer 32. In the present embodiment, the second foundation electrode layer 50B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0061] The first base electrode layer 50A and the second base electrode layer 50B of the present embodiment are sintered layers. The sintered layer preferably includes any one of a metal component and a glass component or a ceramic component, or includes both of them. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component can use the same type of ceramic material as the dielectric layer 20, or a ceramic material different from the dielectric layer 20. The ceramic component includes, for example, at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc.

[0062] The sintered layer is obtained by, for example, applying a conductive paste including glass and metal to a stacked body and sintering it. The sintered layer can be obtained by simultaneously sintering a stacked chip having an internal electrode and a dielectric layer and a conductive paste applied to the stacked chip, or can be obtained by applying a conductive paste to the stacked body and sintering it after the stacked chip having an internal electrode and a dielectric layer is sintered to obtain a stacked body. It should be noted that, when the stacked chip having an internal electrode and a dielectric layer and the conductive paste applied to the stacked chip are sintered simultaneously, the sintered layer is preferably formed by sintering a material to which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. The sintered layer can also be a multilayer.

[0063] The thickness in the longitudinal direction of the first foundation electrode layer 50A located at the first end surface LS1 is preferably about 3 μm or more and 200 μm or less in the central portion in the height direction T and the width direction W of the first foundation electrode layer 50A, for example.

[0064] The thickness in the longitudinal direction of the second foundation electrode layer 50B located at the second end surface LS2 is preferably about 3 μm or more and 200 μm or less in the central portion in the height direction T and the width direction W of the second foundation electrode layer 50B, for example.

[0065] When the first base electrode layer 50A is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the height direction of the first base electrode layer 50A provided on the portion is preferably greater than 3 μm and less than 25 μm in the central portion in the length direction L and the width direction W of the first base electrode layer 50A provided on the portion.

[0066] When the first base electrode layer 50A is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness in the width direction of the first base electrode layer 50A provided on the portion is preferably greater than 3 μm and less than 25 μm in the central portion of the length direction L and the height direction T of the first base electrode layer 50A provided on the portion.

[0067] When a second base electrode layer 50B is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the height direction of the second base electrode layer 50B provided on the portion is preferably greater than 3 μm and less than 25 μm in the central portion of the second base electrode layer 50B provided on the portion in the length direction L and the width direction W.

[0068] When a second base electrode layer 50B is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness in the width direction of the second base electrode layer 50B provided on the portion is preferably greater than 3 μm and less than 25 μm in the central portion of the length direction L and the height direction T of the second base electrode layer 50B provided on the portion.

[0069] It should be noted that the first base electrode layer 50A and the second base electrode layer 50B are not limited to sintered layers. The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a sintered layer, a conductive resin layer, a thin film layer, etc. For example, the first base electrode layer 50A and the second base electrode layer 50B may also be a thin film layer. The thin film layer is formed by a thin film forming method such as a sputtering method or an evaporation method. The thin film layer is a layer of less than 10 μm on which metal particles are deposited.

[0070] The first plating layer 60A is arranged to cover the first base electrode layer 50A.

[0071] The second plating layer 60B is arranged to cover the second base electrode layer 50B.

[0072] The first plating layer 60A and the second plating layer 60B may include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may also be formed of multiple layers. The first plating layer 60A and the second plating layer 60B are preferably a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0073] The first plating layer 60A is arranged to cover the first base electrode layer 50A. In the present embodiment, the first plating layer 60A includes a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0074] The second plating layer 60B is arranged to cover the second base electrode layer 50B. In the present embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0075] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being corroded by the solder when mounting the multilayer ceramic capacitor 1. In addition, the Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. Thus, the mounting of the multilayer ceramic capacitor 1 becomes easy. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 10 μm or less.

[0076] It should be noted that the first external electrode 40A and the second external electrode 40B of the present embodiment may also have, for example, a conductive resin layer including conductive particles and a thermosetting resin. When a conductive resin layer is provided as a base electrode layer (the first base electrode layer 50A, the second base electrode layer 50B), the conductive resin layer may be configured to cover the sintered layer, or may be directly provided on the laminate 10 without providing the sintered layer. When the conductive resin layer is configured to cover the sintered layer, the conductive resin layer is provided between the sintered layer and the plating layer (the first plating layer 60A, the second plating layer 60B). The conductive resin layer may completely cover the sintered layer, or may cover a portion of the sintered layer.

[0077] The conductive resin layer including a thermosetting resin is more flexible than a conductive layer including a plated film or a fired product of a conductive paste, for example. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the multilayer ceramic capacitor 1, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the generation of cracks in the multilayer ceramic capacitor 1.

[0078] The metal constituting the conductive particles may also be Ag, Cu, Ni, Sn, Bi or alloys thereof. The conductive particles preferably include Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals and is therefore suitable as an electrode material. In addition, since Ag is a noble metal, it is difficult to oxidize and has high weather resistance. Therefore, Ag metal powder is suitable as the conductive particles.

[0079] In addition, the conductive particles may be metal powders coated with Ag on the surface of the metal powders. When using metal powders coated with Ag on the surface of the metal powders, the metal powders are preferably Cu, Ni, Sn, Bi or alloy powders thereof. In order to keep the properties of Ag while making the metal of the base material cheap, it is preferred to use metal powders coated with Ag.

[0080] Furthermore, the conductive particles may be metal powders subjected to oxidation prevention treatment on Cu and Ni. In addition, the conductive particles may be metal powders coated with Sn, Ni, or Cu on the surface of the metal powders. When using metal powders coated with Sn, Ni, or Cu on the surface of the metal powders, the metal powders are preferably Ag, Cu, Ni, Sn, Bi, or alloy powders thereof.

[0081] The shape of the conductive particles is not particularly limited. As the conductive particles, spherical or flat metal powders can be used, but it is preferred to use a mixture of spherical metal powders and flat metal powders.

[0082] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the conductivity of the conductive resin layer. Specifically, a plurality of conductive particles are in contact with each other, thereby forming a conductive path inside the conductive resin layer.

[0083] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, polyurethane resin, silicone resin, polyimide resin, etc. Among them, epoxy resin having excellent heat resistance, moisture resistance, adhesion, etc. is one of the most suitable resins. In addition, the resin of the conductive resin layer preferably includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent of the epoxy resin may also be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, amide-imide, etc.

[0084] In addition, the conductive resin layer may be formed of a plurality of layers. The thickness of the thickest portion of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0085] It should be noted that the first base electrode layer 50A and the second base electrode layer 50B may be not provided, and the first plated layer 60A and the second plated layer 60B described later may be directly arranged on the laminate 10. That is, the laminated ceramic capacitor 1 may also have a structure including a plated layer that is directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, the plated layer may be formed after a catalyst is arranged on the surface of the laminate 10 as a pretreatment.

[0086] In this case, the plating layer is also preferably a multilayer. The lower plating layer and the upper plating layer are preferably respectively, for example, preferably include at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni with solder resistance. The upper plating layer is more preferably formed using Sn or Au with good solder wettability. It should be noted that, for example, when Ni is used to form the first internal electrode layer 31 and the second internal electrode layer 32, the lower plating layer is preferably formed using Cu with good bonding properties with Ni. It should be noted that the upper plating layer can be formed as needed, and the external electrode 40 can also be composed of only the lower plating layer. In addition, the plating layer can use the upper plating layer as the outermost layer, and other plating layers can also be further formed on the surface of the upper plating layer.

[0087] The thickness of each plating layer arranged without providing a base electrode layer is preferably 2 μm or more and 10 μm or less. It should be noted that the plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99 volume % or more.

[0088] It should be noted that, when the plated layer is directly formed on the laminate 10, the thickness of the base electrode layer can be reduced. Therefore, the dimension of the height direction T of the laminated ceramic capacitor 1 can be reduced by the amount of the reduced thickness of the base electrode layer, thereby achieving a lower height of the laminated ceramic capacitor 1. Alternatively, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 can be increased by the amount of the reduced thickness of the base electrode layer, thereby achieving an increase in the thickness of the body. In this way, by directly forming the plated layer on the laminate 10, the degree of freedom in designing the laminated ceramic capacitor can be increased.

[0089] It should be noted that, when the dimension in the length direction of the multilayer ceramic capacitor 1 including the stacked body 10 and the external electrode 40 is set to L dimension, the L dimension is preferably 0.2 mm or more and 6 mm or less. In addition, when the dimension in the height direction of the multilayer ceramic capacitor 1 is set to T dimension, the T dimension is preferably 0.05 mm or more and 5 mm or less. In addition, when the dimension in the width direction of the multilayer ceramic capacitor 1 is set to W dimension, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0090] Here, the inventor of the present application has obtained the following insight through research, experiments, and simulations: even when a dielectric layer sandwiched between a plurality of internal electrode layers is formed of a relatively thin layer, in order to suppress the decrease in reliability of a laminated ceramic capacitor, it is desirable to make the holes in the internal electrode layers in an appropriate state. This point is explained below.

[0091] In the past, various methods have been used to improve the reliability of multilayer ceramic capacitors. For example, Patent Document 1 discloses a multilayer ceramic capacitor having a plurality of dielectric layers and internal electrode layers alternately stacked and a plurality of auxiliary electrodes. In the multilayer ceramic capacitor of Patent Document 1, the reliability of the product can be improved by having a plurality of auxiliary electrodes. However, since the multilayer ceramic capacitor of Patent Document 1 has a plurality of auxiliary electrodes, it is difficult to ensure the area of ​​the effective part of the capacitor that generates electrostatic capacitance. Therefore, it is difficult to improve reliability while suppressing the decrease in electrostatic capacitance.

[0092] The inventors of the present application have considered the above contents and conducted in-depth research on the structure of the internal electrode layer that can suppress the decrease of electrostatic capacitance and improve reliability by forming the dielectric layer with a relatively thin layer. As a result, the inventors of the present application have obtained the following insights: if the structure of the present embodiment is provided, the decrease of electrostatic capacitance and the concentration of electric field can be suppressed by forming the dielectric layer with a relatively thin layer, thereby improving reliability when voltage is applied.

[0093] Specifically, the inventors of the present application have found that when insulation breakdown occurs in a laminated ceramic capacitor, burning occurs starting from the location where the holes in the internal electrode layer exist. Furthermore, the inventors of the present application have found that even when the dielectric layer is formed of a relatively thin layer, the size of the area equivalent diameter D99 described later of the plurality of holes in the internal electrode layer can be adjusted to suppress the decrease in electrostatic capacitance and the concentration of the electric field when the voltage is applied.

[0094] More specifically, the inventors of the present application have discovered that, when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes existing in the first internal electrode layer 31 and the second internal electrode layer 32 becomes 99% is set as the area equivalent diameter D99, and the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is set as the thickness t, by adopting a structure that satisfies the following formula (1), even in the case where the dielectric layer 20 sandwiched between the plurality of internal electrode layers 30 is formed by a relatively thin layer, electric field concentration when voltage is applied can be suppressed.

[0095] (Area equivalent diameter D99) < 0.1468 × exp (6.7622 × t) … (1)

[0096] Hereinafter, the dielectric layer 20 and the internal electrode layer 30 of the present embodiment will be described in detail.

[0097] Figure 5 yes Figure 4A The enlarged view of the V portion of the multilayer ceramic capacitor 1 shown in FIG. 1 is a view showing, by way of example, the state of the first internal electrode layer 31 as the internal electrode layer 30. More specifically, Figure 5 This is a diagram when the internal electrode layer 30 in the WT cross section of the multilayer ceramic capacitor 1 of the present embodiment is observed in the height direction T connecting the first main surface TS1 and the second main surface TS2, that is, it is a diagram when viewed from above. It should be noted that the covering state of the first internal electrode layer 31 with respect to the dielectric layer 20 and the covering state of the second internal electrode layer 32 with respect to the dielectric layer 20 when observed in the height direction T connecting the first main surface TS1 and the second main surface TS2 are basically the same. Therefore, in the following description, the first internal electrode layer 31 and the second internal electrode layer 32 are collectively described as the internal electrode layer 30 as needed.

[0098] Figure 5 1 is a diagram showing the internal electrode layer 30 in the vicinity of the first side WE1 which is a side of the internal electrode layer 30. Figure 5 As shown, there are a plurality of holes H having different area equivalent diameters in the internal electrode layer 30. It should be noted that Figure 5 The thickness of the internal electrode layer 30 shown is 0.6 μm, and the coverage of the internal electrode layer with respect to the dielectric layer 20 is 90%. It should be noted that the inside of the hole H of the internal electrode layer 30 may be a void, or a glass component such as a dielectric or silicon dioxide may exist. When the inside of the hole H of the internal electrode layer 30 is a void, the dielectric layer 20 can be observed through the hole H. It should be noted that the thickness of the dielectric layer 20 sandwiched between the two internal electrode layers 30 (the first internal electrode layer 31 and the second internal electrode layer 32) is 0.5 μm.

[0099] Figure 6 3 is a diagram showing area-equivalent diameter distribution data of a plurality of holes H existing in the internal electrode layer 30 . Figure 6 Cumulative % relative to area equivalent diameter is shown. Figure 6 The horizontal axis is the area equivalent diameter of hole H, Figure 6 The vertical axis of is the cumulative % of the value obtained by dividing the number of holes H with an area-equivalent diameter or less (the cumulative value of the number of holes H) by the total number (the number of holes H forming the total). That is, Figure 6 The area equivalent diameter distribution data shown are area equivalent diameter distribution data based on number. Figure 6 The data is the area equivalent diameter distribution data in the measurement target area near the edge of the internal electrode layer 30, which is the area equivalent diameter distribution data in the measurement target area near the edge of the internal electrode layer 30. Figure 5 The area shown is the data when the holes H in the wide area are taken as a whole.

[0100] In the multilayer ceramic capacitor 1 of the present embodiment, when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes H existing in the first internal electrode layer 31 and the second internal electrode layer 32 becomes 99% is set as the area equivalent diameter D99, and the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is set as the thickness t, the thickness t of the dielectric layer 20 is 0.6 μm or less, and satisfies the following formula (1). It should be noted that the unit of the area equivalent diameter D99 and the unit of the thickness t of the dielectric layer 20 are expressed uniformly, for example, in "μm".

[0101] (Area equivalent diameter D99) < 0.1468 × exp (6.7622 × t) … (1)

[0102] exist Figure 6 In the example of the area equivalent diameter distribution data shown, the area equivalent diameter D99 is 3.6 μm. This is smaller than the value of 4.3 μm when 0.5 μm is substituted into the thickness t on the right side of equation (1). That is, when the thickness t of the dielectric layer 20 is 0.5 μm and the area equivalent diameter distribution data of the internal electrode layer 30 is Figure 6 In the data example shown, the thickness t of the dielectric layer 20 is 0.6 μm or less and satisfies the formula (1). With such a structure, even when the dielectric layer 20 sandwiched between the plurality of internal electrode layers 30 is formed of a relatively thin layer, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0103] It should be noted that the area equivalent diameter refers to the value of the diameter of a perfect circle having an area equal to the area of ​​the hole H defined by the outline of the hole H. For example, when the area of ​​the hole H defined by the outline of the hole H is 50 μm 2 When , the area equivalent diameter becomes 8.0 μm.

[0104] It should be noted that, as described above, the area equivalent diameter D99 is the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of the plurality of holes H becomes 99%. That is, the value at which the ratio of holes H having area equivalent diameters below this value becomes 99% is referred to as the area equivalent diameter D99.

[0105] Next, a description will be given of a case where the above-mentioned effects are obtained using simulation.

[0106] Fig. 7A is a model of the internal electrode layer 30 used for simulation. In this model, the internal electrode layer 30 is provided on the dielectric layer 20. In addition, in this model, Fig. 7AAs shown, a plurality of holes H are randomly arranged. In addition, the area equivalent diameters of the plurality of holes H vary. It should be noted that in this model, an internal electrode layer 30 having a plurality of holes H randomly arranged is also provided on the back side of the dielectric layer 20 as on the front side.

[0107] For example, in portable electronic devices such as smartphones, high-capacitance and small-sized multilayer ceramic capacitors are required. In order to achieve high capacitance and small size, it is preferable to reduce the thickness of the dielectric layer 20 sandwiched between the two internal electrode layers 30 (the first internal electrode layer 31 and the second internal electrode layer 32). In this simulation, first, the thickness t of the dielectric layer 20 is set to 0.5 μm.

[0108] In addition, for example, in the case of laminated ceramic capacitors for portable electronic devices, laminated ceramic capacitors with relatively low rated voltages, such as laminated ceramic capacitors with a rated voltage of 6.3 V, are often used. Therefore, simulation was performed with an applied voltage of 6.3 V. It should be noted that in the simulation, a voltage was applied between the internal electrode layer 30 on the surface side and the internal electrode layer 30 on the back side sandwiching the dielectric layer 20.

[0109] In this simulation, the thickness of the internal electrode layer 30 is set to 0.6 μm, and the coverage of the internal electrode layer 30 with respect to the dielectric layer 20 is set to 88%. In this simulation, first, a plurality of holes H are set in the internal electrode layer 30 so that the area equivalent diameter D99 becomes 2.0 μm.

[0110] When simulation was performed under the present setting conditions, a tendency that the electric field tends to concentrate around the contour of the hole H was confirmed. Figure 7B is a diagram showing the electric field intensity distribution near the hole H. Figure 7B In the figure, the electric field strength is shown in grayscale, and the parts with higher electric field strength are shown in lighter colors. Figure 7B , it was confirmed that the electric field was concentrated around the outline of the hole H. In addition, it was confirmed that Figure 7B Compared with the contour of a relatively small hole H as shown on the right side of FIG. Figure 7B The trend around the contour of a relatively large hole H as shown on the left.

[0111] Next, the electric field strength generated in each model was calculated using a model in which the value of the area equivalent diameter D99 was changed. Specifically, a model in which the area equivalent diameter D99 was set to 1.5 μm and a model in which the area equivalent diameter D99 was set to 1.0 μm were additionally created, and the electric field strength generated in the model was calculated. It should be noted that the thickness of the internal electrode layer 30, the coverage of the internal electrode layer 30 relative to the dielectric layer 20, the thickness of the dielectric layer 20, and the applied voltage were set to fixed values ​​for simulation. Figure 8 This is a graph showing the results. Figure 8 The horizontal axis (x-axis) is the value of the area equivalent diameter D99 in the model. Figure 8 The vertical axis (y-axis) is the maximum electric field strength in the model. It should be noted that Figure 8 An approximate curve obtained by fitting the plotted points is shown.

[0112] according to Figure 8 It is confirmed that the smaller the area equivalent diameter D99 is, the more the electric field concentration is suppressed. Figure 8 The approximate curve of the dielectric layer 20 shows that when the thickness t of the dielectric layer 20 is 0.5 μm, when the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 is less than about 4 μm, the value of the maximum electric field intensity generated in the model is less than 72 MV / m, and the electric field concentration is suppressed. The value of the maximum electric field intensity is a value that can be allowed in terms of ensuring the reliability of the multilayer ceramic capacitor.

[0113] Next, a simulation was performed to calculate the electric field strength by changing the value of the thickness t of the dielectric layer 20. Specifically, the electric field strength in the model was calculated when the area equivalent diameter D99 was set to 2.0 μm, 1.5 μm, and 1.0 μm when the thickness t of the dielectric layer 20 was 0.4 μm and 0.6 μm, respectively. In addition, the electric field strength in the model was calculated when the area equivalent diameter D99 was set to 4.0 μm when the thickness t of the dielectric layer 20 was 0.4 μm. It should be noted that the thickness of the internal electrode layer 30, the coverage of the internal electrode layer 30 relative to the dielectric layer 20, the thickness of the dielectric layer 20, and the applied voltage were set to fixed values ​​for simulation.

[0114] Fig. 9 This is a graph showing the results. Fig. 9 The horizontal axis (x-axis) is the value of the area equivalent diameter D99 in the model. Fig. 9 The vertical axis (y-axis) is the maximum electric field strength in the model. It should be noted that Fig. 9 An approximate curve obtained by fitting the plotted points is shown.

[0115] like Fig. 9 As shown in FIG. 1 , it is confirmed that even when the thickness t of the dielectric layer 20 is 0.4 μm or 0.6 μm, the electric field concentration tends to be suppressed as the area equivalent diameter D99 value decreases, similarly to the case of 0.5 μm. Fig. 9The approximate curve of , confirms that when the thickness t of the dielectric layer 20 is 0.4 μm, when the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 is less than about 2 μm, the value of the maximum electric field intensity generated in the model is less than 72 MV / m, and the electric field concentration is suppressed. In addition, it is confirmed that when the thickness t of the dielectric layer 20 is 0.6 μm, when the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 is less than about 8.5 μm, the value of the maximum electric field intensity generated in the model is less than 72 MV / m, and the electric field concentration is suppressed.

[0116] Next, use Fig. 9 The approximate curves shown in FIG. 1 and FIG. 2 show that the value of the maximum electric field intensity generated in the model when the thickness t of the dielectric layer 20 is 0.4 μm, 0.5 μm, and 0.6 μm is 72 MV / m. Fig.10 Draw out in. Fig.10 The horizontal axis (x axis) is the thickness t of the dielectric layer 20, Fig.10 The vertical axis (y-axis) is the value of the area equivalent diameter D99. It should be noted that Fig.10 An approximate curve obtained by fitting the plotted points is shown.

[0117] In the laminated ceramic capacitor 1 in which the dielectric layer 20 sandwiched between the plurality of internal electrode layers 30 is formed of a relatively thin layer, the area equivalent diameter D99 of the plurality of holes H existing in the internal electrode layers 30 is Fig.10 The area below the approximate curve of can improve the reliability when voltage is applied. That is, when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes H existing in the first internal electrode layer 31 and the second internal electrode layer 32 becomes 99% is set as the area equivalent diameter D99, and the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is set as the thickness t, by adopting a structure in which the thickness t of the dielectric layer 20 is set to 0.6 μm or less and the following formula (1) is satisfied, it is possible to suppress the decrease in electrostatic capacitance by thinning the thickness t of the dielectric layer 20, and suppress the concentration of the electric field when voltage is applied.

[0118] (Area equivalent diameter D99) < 0.1468 × exp (6.7622 × t) … (1)

[0119] In addition, by adopting a structure in which the thickness t of the dielectric layer 20 is set to 0.5 μm or less and the above-mentioned formula (1) is satisfied, the thickness t of the dielectric layer 20 can be reduced to increase the electrostatic capacitance, and the electric field concentration when the voltage is applied can be suppressed. In addition, the thickness t of the dielectric layer 20 can be reduced to achieve miniaturization of the multilayer ceramic capacitor 1, and the electric field concentration when the voltage is applied can be suppressed.

[0120] Furthermore, by adopting a structure in which the thickness t of the dielectric layer 20 is set to 0.4 μm or less and the above formula (1) is satisfied, the thickness t of the dielectric layer 20 can be further reduced to increase the electrostatic capacitance and suppress the electric field concentration when a voltage is applied. In addition, the thickness t of the dielectric layer 20 can be reduced to achieve miniaturization of the multilayer ceramic capacitor 1 and suppress the electric field concentration when a voltage is applied.

[0121] The thickness t of the dielectric layer 20 may be 0.2 μm or more and may satisfy the above formula (1). In this case, the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 may be 0.57 μm or more. The thickness t of the dielectric layer 20 may be 0.3 μm or more. The thickness t of the dielectric layer 20 may be 0.2 μm or more and 0.6 μm or less. Alternatively, the thickness t of the dielectric layer 20 may be 0.2 μm or more and 0.5 μm or less. In addition, the thickness t of the dielectric layer 20 may be 0.2 μm or more and 0.4 μm or less.

[0122] It should be noted that, in the model of this simulation, even when the coverage of the internal electrode layer 30 relative to the dielectric layer 20 is changed, the value of the maximum electric field strength hardly changes. In order to ensure the electrostatic capacitance, it is preferred that the coverage is higher. For example, even when the coverage is 70% or more and 99% or less, by adopting the structure of the present embodiment, it is possible to suppress the decrease in electrostatic capacitance while suppressing the concentration of the electric field when the voltage is applied. In addition, even when the coverage is as high as 86% or more and 93% or less and the productivity is also good, by adopting the structure of the present embodiment, it is possible to suppress the decrease in electrostatic capacitance while suppressing the concentration of the electric field when the voltage is applied. That is, in the present embodiment, the coverage of the internal electrode layer 30 relative to the dielectric layer 20, that is, the coverage, can be 70% or more and 99% or less, or 86% or more and 93% or less.

[0123] It should be noted that in the model of this simulation, even when the thickness of the internal electrode layer 30 is changed, the value of the maximum electric field strength hardly changes. By reducing the thickness of the internal electrode layer 30, the number of stacked sheets can be increased even for the same size of the stacked body 10, so the electrostatic capacitance can be ensured. For example, when the thickness of the internal electrode layer 30 is greater than 0.2 μm and less than 2.0 μm, by adopting the structure of this embodiment, it is possible to suppress the decrease in electrostatic capacitance while suppressing the concentration of the electric field when the voltage is applied. In addition, when the thickness of the internal electrode layer 30 is greater than 0.2 μm and less than 0.6 μm, by adopting the structure of this embodiment, it is possible to suppress the decrease in electrostatic capacitance while suppressing the concentration of the electric field when the voltage is applied. In addition, when the thickness of the internal electrode layer 30 is greater than 0.2 μm and less than 0.4 μm, by adopting the structure of this embodiment, it is possible to suppress the decrease in electrostatic capacitance while suppressing the concentration of the electric field when the voltage is applied.

[0124] It should be noted that the thickness of the first internal electrode layer 31 and the second internal electrode layer 32 may be thicker than the thickness t of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32. As a result, it is easy to increase the coverage of the internal electrode layer 30 and reduce the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30. As a result, it is possible to improve the reliability of the product while suppressing the decrease in electrostatic capacitance.

[0125] It should be noted that, in the present simulation model, even when the area equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30 is fixed and the average diameter is changed, the value of the maximum electric field intensity hardly changes. Therefore, the average pore diameter has a low dependence on the maximum electric field intensity, and it can be said that the change in the state of the hole H having a larger area equivalent diameter is highly helpful in suppressing the maximum electric field intensity.

[0126] The structure of the present embodiment can be suitable for use in a laminated ceramic capacitor for a portable electronic terminal, such as a laminated ceramic capacitor used at a rated voltage of 6.3V or less. For example, in the laminated ceramic capacitor 1 of the present embodiment, the value of the maximum electric field strength when the rated voltage is applied between the first internal electrode layer 31 and the second internal electrode layer 32 sandwiching the dielectric layer 20 is preferably 72MV / m or less. The rated voltage is, for example, 6.3V. That is, in the laminated ceramic capacitor 1 of the present embodiment, the value of the maximum electric field strength when 6.3V is applied between the first internal electrode layer 31 and the second internal electrode layer 32 sandwiching the dielectric layer 20 is preferably 72MV / m or less. The laminated ceramic capacitor 1 of the present embodiment can also be practically used for laminated ceramic capacitors with a rated voltage of 10V or less. However, the use of laminated ceramic capacitors is not limited to this.

[0127] The following describes the measurement methods of various parameters. Various parameters can be confirmed by the following methods.

[0128] <Method for measuring thickness of internal electrode layer and dielectric layer>

[0129] A method for measuring the thicknesses of the dielectric layer 20 and the internal electrode layer 30 of the multilayer ceramic capacitor 1 will be described.

[0130] First, the outer layer of the side surface is removed by grinding from the first side surface WS1 or the second side surface WS2 to expose the internal electrode layer 30. Then, grinding is performed by about 10 μm toward the center side in the width direction W to expose the LT cross section where multiple internal electrode layers 30 are exposed. If necessary, the cross section where the observation position is exposed is etched to remove the internal electrode layer 30 stretched by grinding.

[0131] The exposed cross section was observed using a SEM (scanning electron microscope) at the center of the longitudinal direction L and at the upper, central, and lower portions in the stacking direction (height direction T). The observation was performed at a magnification that enables observation of the five dielectric layers 20 and the six internal electrode layers 30, and at a magnification that enables clear distinction between the dielectric layers 20 and the internal electrode layers 30. Fig.11 This is a diagram showing an example of an enlarged image of a cross section of the multilayer ceramic capacitor 1 observed by SEM.

[0132] When measuring the thickness of the internal electrode layer 30 of the multilayer ceramic capacitor 1, first, Fig.11 As shown, in the enlarged image of the cross section of the multilayer ceramic capacitor 1, five straight lines La to Le extending in the stacking direction of the stack 10 are drawn at equal intervals (pitch S). ​​The pitch S may be determined to be 5 to 10 times the thickness of the internal electrode layer 30 to be measured. For example, when measuring the internal electrode layer 30 having a thickness of about 0.5 μm, the pitch S = 2.5 μm. Next, the thickness of the internal electrode layer 30 is measured on each of the straight lines La to Le. However, on each of the straight lines La to Le, when the internal electrode layer 30 is missing and the dielectric layers 20 sandwiching the internal electrode layer 30 are connected to each other or when the enlarged image of the measurement position is unclear, a new straight line is drawn to measure the thickness of the internal electrode layer 30.

[0133] For example, when measuring the thickness of the internal electrode layer 30, Fig.11As shown, the thickness d1 on the straight line La, the thickness d2 on the straight line Lb, the thickness d3 on the straight line Lc, the thickness d4 on the straight line Ld, and the thickness d5 on the straight line Le are measured. Then, the thickness of each of the five internal electrode layers 30 is measured by the above-mentioned method at the upper part, the middle part, and the lower part of the cross section of the stacked body 10, and the average value thereof is set as the thickness of the internal electrode layer 30 of the present embodiment.

[0134] The thickness of the dielectric layer 20 is also measured by the same method as the internal electrode layer 30. When measuring the thickness of the dielectric layer 20, Fig.11 As shown in FIG. 1 , the thickness D1 on the straight line La, the thickness D2 on the straight line Lb, the thickness D3 on the straight line Lc, the thickness D4 on the straight line Ld, and the thickness D5 on the straight line Le are measured. Then, the thickness of each of the five dielectric layers 20 is measured at the upper part, the middle part, and the lower part of the cross section of the laminate 10 by the above-mentioned method, and the average value thereof is set as the thickness of the dielectric layer 20 of the present embodiment.

[0135] <Measurement area of ​​area equivalent diameter D99, etc.>

[0136] Next, the measurement target region when measuring parameters such as the area-equivalent diameter D99 will be described.

[0137] The inventors of the present application have accumulated the following insights through research, experiments, and simulations: In order to improve the reliability of a laminated ceramic capacitor, it is particularly desirable to make the holes in a specified area of ​​the internal electrode layer in an appropriate state. Specifically, the inventors of the present application have obtained the following insights through repeated analysis after accelerated life tests of laminated ceramic capacitors: The burnout position of the laminated body of the laminated ceramic capacitor during insulation breakdown is mostly near the outer layer portion on the side, and is a region slightly separated from the edge (end) of the internal electrode layer, and it is desirable to make the holes in this region in an appropriate state.

[0138] Fig.12 is with Figure 3 The SEM image corresponding to the enlarged view of the XII part of the WT cross section of the multilayer ceramic capacitor 1 shown is a diagram showing the burnout state of the multilayer body 10 during the insulation breakdown during the accelerated life test. Thus, in the multilayer ceramic capacitor 1, the burnout portion D of the multilayer body 10 is easily generated in the area near the side outer layer portion WG and slightly separated from the edge of the internal electrode layer 30.

[0139] Therefore, it is preferable to make the plurality of holes H of the internal electrode layer 30 in this region into an appropriate state. The above-mentioned measurement target region is preferably set in a region near the side outer layer portion WG and slightly separated from the side of the internal electrode layer 30 .

[0140] Specifically, the region from the position separated from the first side WE1 by 10 μm to the position separated from the first side WE1 by 50 μm is defined as the first region A1, the region from the position separated from the second side WE2 by 10 μm to the position separated from the second side WE2 by 50 μm is defined as the second region A2, the region from the position separated from the third side by 10 μm to the position separated from the third side by 50 μm is defined as the third region A3, and the region from the position separated from the fourth side by 10 μm to the position separated from the fourth side by 50 μm is defined as the fourth region A4. In this case, it is preferable that the first region A1, the second region A2, the third region A3, and the fourth region A4 are defined as the measurement target regions. It should be noted that, when the linearity of the first side WE1 to the fourth side WE4 is low, the first region A1 to the fourth region A4 are defined on the basis of defining each side as a straight line by linear fitting based on linear regression or the like.

[0141] Figure 4A A first area A1 and a second area A2 as measurement target areas are schematically shown. Figure 4B The third area A3 and the fourth area A4 as measurement target areas are schematically shown.

[0142] In the first area A1 , the second area A2 , the third area A3 , and the fourth area A4 as the measurement target areas, the measurement target range for actually measuring the parameters is set based on the SEM observation.

[0143] In SEM observation, the observation range in one observation field is set to about 40μm×40μm to 80μm×80μm. Moreover, the analysis target range is set to the range of 40μm×40μm therein. Moreover, based on the set of the analysis target ranges of 12 locations, parameters such as area equivalent diameter are measured.

[0144] Specifically, in each of the first area A1, the second area A2, the third area A3, and the fourth area A4, three analysis target ranges a are set. The three analysis target ranges a are set within the range of the opposing electrode portion 11E. The analysis target range a set on the side closest to the first end surface LS1 in the three analysis target ranges a is set at a position separated by 10 μm from the first end surface side outer layer portion LG1. The analysis target range a set on the side closest to the second end surface LS2 in the three analysis target ranges a is set at a position separated by 10 μm from the second end surface side outer layer portion LG2. The analysis target range a set at the middle position in the three analysis target ranges a is set at the central position in the length direction L of the stacked body 10. The three analysis target ranges a are set at positions that are equally spaced in the length direction L of the stacked ceramic capacitor. Figure 4A , the analysis target range a of three locations set in the second area A2 is shown as an example. Then, the measurement target range for measuring parameters such as the area equivalent diameter D99 is set by a set of analysis target ranges a of 12 locations in total, 4 regions×3 locations.

[0145] It should be noted that, when the chip size of the multilayer ceramic capacitor 1 is small, the first area A1 to the fourth area A4 can also be set at overlapping positions. In addition, each analysis target range a can also be set at an overlapping position. In this case, each area is overlapped and set at a different position, and each analysis target range is set to cover the internal electrode layer 30 as wide as possible.

[0146] <Measurement method of area equivalent diameter D99>

[0147] A method for measuring the area-equivalent diameter D99 of the pores present in the internal electrode layer 30 will be described.

[0148] First, the internal electrode layer 30 and the dielectric layer 20 located in the center of the stack 10 in the height direction are peeled off by electric field peeling, thereby exposing the internal electrode layer 30. Next, a portion of the first region A1 to the fourth region A4 of the internal electrode layer 30 as the measurement target region is set as the above-mentioned analysis target range a, and SEM observation is performed. It should be noted that when the first internal electrode layer 31 is exposed, first, a portion of the first region A1 and the second region A2 of the first internal electrode layer 31 are set as the above-mentioned analysis target range a, and SEM observation is performed. Thereafter, the second internal electrode layer 32 is exposed by FIB (focused ion beam) processing. Then, a portion of the third region A3 and the fourth region A4 of the second internal electrode layer 32 is set as the above-mentioned analysis target range a, and SEM observation is performed. It should be noted that the SEM observation of the first internal electrode layer 31 may also be performed after the SEM observation of the second internal electrode layer 32 is performed.

[0149] In the SEM observation, the SEM image is analyzed to identify the contour of each hole H formed in the internal electrode layer 30. Then, for each hole H formed in the internal electrode layer 30, the area equivalent diameter of the hole H is calculated based on the area of ​​the hole H specified by the contour of the hole H. It should be noted that the area equivalent diameter (area circle equivalent diameter) refers to the value of the diameter of a perfect circle having an area equal to the area of ​​the hole H specified by the contour of the hole H.

[0150] The area-equivalent diameter of each of the holes H described above is calculated for the analysis target range a of 12 locations constituting the measurement target range.

[0151] The population of the wells H is set as a collection of all wells H identified within the measurement target range, that is, the analysis target range of 12 locations.

[0152] The area equivalent diameter D99 is calculated based on the data of the area equivalent diameter of the entire holes H within the measurement target range. The area equivalent diameter D99 is calculated as the area equivalent diameter at which the cumulative value in the number-based cumulative distribution of the area equivalent diameters of the plurality of holes H existing in the measurement target region becomes 99%.

[0153] <Method for measuring coverage>

[0154] A method for measuring the coverage ratio, which is the coverage ratio of the internal electrode layer 30 with respect to the dielectric layer 20 , will be described.

[0155] First, the internal electrode layer 30 and the dielectric layer 20 located in the center of the stack 10 in the height direction are peeled off by electric field peeling, thereby exposing the internal electrode layer 30. Next, a portion of the first region A1 to the fourth region A4 of the internal electrode layer 30 as the measurement target region is set as the above-mentioned analysis target range a, and SEM observation is performed. It should be noted that when the first internal electrode layer 31 is exposed, first, a portion of the first region A1 and the second region A2 of the first internal electrode layer 31 is set as the above-mentioned analysis target range a, and SEM observation is performed. Thereafter, the second internal electrode layer 32 is exposed by FIB (focused ion beam) processing. Then, a portion of the third region A3 and the fourth region A4 of the second internal electrode layer 32 is set as the above-mentioned analysis target range a, and SEM observation is performed. It should be noted that the SEM observation of the first internal electrode layer 31 may also be performed after the SEM observation of the second internal electrode layer 32 is performed.

[0156] Then, the region of the internal electrode layer 30 within the analysis target range a is identified by analyzing the SEM image. Then, based on the area of ​​the analysis target range a and the area of ​​the region of the internal electrode layer 30, the coverage of the internal electrode layer 30 with respect to the dielectric layer 20 is calculated by the following formula (2).

[0157] Coverage rate (%) = (area of ​​internal electrode layer / area of ​​analysis target range) × 100 … (2)

[0158] The coverage of the internal electrode layer 30 with respect to the dielectric layer 20 is calculated for the 12 analysis target areas constituting the measurement target area. The average value is defined as the coverage of the internal electrode layer 30 with respect to the dielectric layer 20 in the present embodiment.

[0159] Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment will be described. It should be noted that the method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment is not limited as long as the above-mentioned requirements are satisfied.

[0160] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode include a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0161] Conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern by screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern of the first internal electrode layer 31 and a dielectric sheet having a pattern of the second internal electrode layer 32 are prepared.

[0162] By stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed, a portion of the first main surface TS1 side that becomes the first main surface side outer layer portion 12 is formed. On top of the dielectric sheets on which the pattern of the first internal electrode layer 31 is printed and the dielectric sheets on which the pattern of the second internal electrode layer 32 is printed are stacked in sequence, thereby forming a portion of the inner layer portion 11. On the portion that becomes the inner layer portion 11, a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed are stacked, thereby forming a portion of the second main surface side outer layer portion 13 on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0163] The laminated sheets are pressed in the height direction by isostatic pressing or the like, thereby producing a laminated block.

[0164] The stacked block is cut into a predetermined size to produce stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by roller grinding or the like.

[0165] The stacked small pieces are fired to produce the stacked body 10. The firing temperature is determined by the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0166] Here, the above-mentioned manufacturing conditions are adjusted so that the area-equivalent diameter D99 of the hole H present in the internal electrode layer 30 becomes equal to or less than a predetermined value and falls within a predetermined range.

[0167] Specifically, the area-equivalent diameter D99 of the hole H present in the internal electrode layer 30 is adjusted to a predetermined value or less by adjusting the pressure, temperature, and pressing time during lamination of the dielectric sheets on which the patterns of the internal electrode layers 30 are printed. For example, when the internal electrode layers 30 are relatively thin, the pressure during pressing of the laminated sheets is set to be high.

[0168] In order to make the area-equivalent diameter D99 of the holes H present in the internal electrode layer 30 equal to or less than a predetermined value, the material of the conductive paste for the internal electrode layer 30 may be adjusted. For example, when the main component of the internal electrode layer 30 is Ni, by using Ni particles with a large average particle size as the raw material of the conductive paste, the bonding start temperature of the Ni particles can be close to the sintering shrinkage start temperature of the ceramic. As a result, the sphericalization of the internal electrode layer 30 is suppressed, and the area-equivalent diameter D99 is adjusted to be equal to or less than a predetermined value. In addition, when the same ceramic powder as the ceramic powder contained in the dielectric layer 20 is added to the conductive paste for the internal electrode layer 30 as a common material, by using a common material with a large average particle size, the bonding start temperature of the Ni particles can be close to the sintering shrinkage start temperature of the ceramic. As a result, the sphericalization of the internal electrode layer 30 is suppressed, and the area-equivalent diameter D99 is adjusted to be equal to or less than a predetermined value. In addition, the dispersibility of the common material can be improved by controlling the affinity between the Ni particles, the common material, and the solvent of the conductive paste for the internal electrode layer 30. As a result, the sphericalization of the internal electrode layer 30 is suppressed, and the area-equivalent diameter D99 of the hole H is adjusted to be equal to or smaller than a predetermined value.

[0169] In addition, when the stacked small pieces are fired, the temperature uniformity within the small pieces during firing can be improved by arranging the stacked small pieces closely in advance. As a result, the sphericity of the internal electrode layer 30 is suppressed, and the area equivalent diameter D99 is adjusted to be less than the specified value. In addition, the temperature uniformity inside and outside the small pieces during firing can be improved by firing the stacked small pieces while being buried in the ceramic powder. As a result, the sphericity of the internal electrode layer 30 is suppressed, and the area equivalent diameter D99 is adjusted to be less than the specified value. It should be noted that during firing, the temperature of the portion of the stacked small pieces close to the first side surface and the second side surface, such as the edge on the first side surface WS1 side of the internal electrode layer 30 and the edge on the second side surface WS2 side of the internal electrode layer 30, is likely to rise. Therefore, the sphericity of the internal electrode layer 30 is likely to occur in this portion. However, by the above method, the sphericity of the first area A1 to the fourth area A4 of the internal electrode layer 30 can be suppressed, and the area equivalent diameter D99 of the hole H present in the internal electrode layer 30 is less than the specified value.

[0170] It should be noted that by forming the internal electrode layer 30 by printing in two stages, the internal electrode layer 30 can also be formed so that the area equivalent diameter D99 of the hole H existing at least in the portion close to the first side and the second side of the stacked small piece, such as the first area A1 to the fourth area A4, becomes less than a specified value. In this case, a conductive paste including Ni particles with a large average particle size and a common material with a large average particle size is printed at least in the first area A1 to the fourth area A4. In addition, a conductive paste including Ni particles with a relatively small average particle size and a common material with a relatively small average particle size is printed in other areas including the central area of ​​the internal electrode layer 30. As a result, for the hole H existing at least in the first area A1 to the fourth area A4, its area equivalent diameter D99 can be made less than a specified value.

[0171] It should be noted that the above-mentioned methods for making the area equivalent diameter D99 of the hole H present in the internal electrode layer 30 less than the specified value can be appropriately combined. Thus, the area equivalent diameter D99 of the hole H present in the internal electrode layer 30 can be adjusted to less than the specified value or within the specified range. Similarly, the area equivalent diameter D90 of the hole H present in the internal electrode layer 30 can be adjusted to less than the specified value or within the specified range by the above-mentioned method.

[0172] A conductive paste to be a base electrode layer (a first base electrode layer 50A and a second base electrode layer 50B) is applied to both end surfaces of the stack 10. In the present embodiment, the base electrode layer is a sintered layer. A conductive paste including a glass component and a metal is applied to the stack 10 by, for example, a dipping method. Thereafter, a sintering treatment is performed to form the base electrode layer. The temperature of the sintering treatment at this time is preferably 700° C. or higher and 900° C. or lower.

[0173] It should be noted that, when the stacked small pieces before firing and the conductive paste applied to the stacked small pieces are fired simultaneously, the sintered layer is preferably formed by firing a material to which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. In this case, the conductive paste is applied to the stacked small pieces before firing, and the stacked small pieces and the conductive paste applied to the stacked small pieces are fired simultaneously to form a stacked body 10 having a sintered layer formed thereon.

[0174] Afterwards, a plating layer is formed on the surface of the base electrode layer. In the present embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. In addition, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In the present embodiment, a Ni plating layer and a Sn plating layer are formed as plating layers. When performing the plating process, any one of electrolytic plating and electroless plating can also be used. However, in order to increase the plating deposition speed, electroless plating needs to be pre-treated with a catalyst, etc., and therefore, there is a disadvantage of complicating the process. Therefore, it is generally preferred to use electrolytic plating. For example, by roller plating, a Ni plating layer and a Sn plating layer are formed in sequence.

[0175] It should be noted that, when the base electrode layer is formed by a thin film layer, the thin film layer as the base electrode layer is formed at the portion where the external electrode is to be formed by masking, etc. The thin film layer is formed by a thin film forming method such as sputtering or evaporation. The thin film layer is a layer of 1.0 μm or less on which metal particles are deposited.

[0176] It should be noted that, when the conductive resin layer is set as the base electrode layer, the conductive resin layer can be configured to cover the sintered layer, or it can be directly configured on the laminate 10 without setting the sintered layer. When the conductive resin layer is set, a conductive resin paste including a thermosetting resin and a metal component is applied to the sintered layer or the laminate 10, and then heat-treated at a temperature of 250 to 550° C. or above. Thus, the thermosetting resin is heat-cured to form a conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably below 100 ppm.

[0177] It should be noted that the base electrode layer may not be provided, and the plating layer may be directly configured to the exposed portion of the internal electrode layer 30 of the stack 10. In this case, the first end face LS1 and the second end face LS2 of the stack 10 are plated to form a plating layer on the exposed portion of the internal electrode layer 30. When the plating process is performed, any one of electrolytic plating and electroless plating may be used. However, electroless plating needs to be pre-treated with a catalyst etc. in order to improve the plating precipitation speed, and therefore, there is a disadvantage that the process is complicated. Therefore, it is usually preferred to use electrolytic plating. As a plating process, drum plating is preferably used. In addition, as required, the upper plating layer formed on the surface of the lower plating layer may also be formed by the same process as the lower plating layer.

[0178] Through such manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0179] It should be noted that the multilayer ceramic capacitor 1 may be a two-terminal multilayer ceramic capacitor having two external electrodes, or may be a multi-terminal multilayer ceramic capacitor having a plurality of external electrodes.

[0180] According to the multilayer ceramic capacitor 1 of the present embodiment, the following effects are achieved.

[0181] (1) A multilayer ceramic capacitor 1 according to the present embodiment comprises: a multilayer body 10 having a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in a height direction, a first side surface WS1 and a second side surface WS2 opposite to each other in a width direction perpendicular to the height direction, and a first end surface LS1 and a second end surface LS2 opposite to each other in a length direction perpendicular to the height direction and the width direction; and a first external electrode 40A and a second external electrode 40B, wherein the plurality of internal electrode layers 30 have a first main surface TS1 and a second main surface TS2 opposite to each other in a height direction, a first side surface WS1 and a second side surface WS2 opposite to each other in a width direction perpendicular to the height direction, and a first end surface LS1 and a second end surface LS2 opposite to each other in a length direction perpendicular to the height direction and the width direction. The electrode 40A is electrically connected to a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32 are electrically connected to the second external electrode 40B, and a plurality of holes H having different area equivalent diameters exist in the first internal electrode layer 31 and the second internal electrode layer 32, and an area equivalent diameter at which a cumulative value of a cumulative distribution of the area equivalent diameters of the plurality of holes H becomes 99% is set as an area equivalent diameter D99, and when the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is set as a thickness t, the thickness t of the dielectric layer 20 is less than 0.6 μm and satisfies the following formula (1).

[0182] (Area equivalent diameter D99) < 0.1468 × exp (6.7622 × t) … (1)

[0183] Thus, it is possible to provide a multilayer ceramic capacitor capable of suppressing a decrease in electrostatic capacitance and suppressing electric field concentration when voltage is applied by forming the dielectric layer 20 sandwiched between the plurality of internal electrode layers 30 from a relatively thin layer.

[0184] (2) In the multilayer ceramic capacitor 1 of the present embodiment, the thickness t of the dielectric layer 20 is 0.5 μm or less. This can further suppress a decrease in electrostatic capacitance and suppress electric field concentration during voltage application.

[0185] (3) In the multilayer ceramic capacitor 1 of the present embodiment, the thickness t of the dielectric layer 20 is 0.4 μm or less. This can further suppress a decrease in electrostatic capacitance and suppress electric field concentration during voltage application.

[0186] (4) In the multilayer ceramic capacitor 1 of the present embodiment, the thickness t of the dielectric layer 20 interposed between the first internal electrode layer 31 and the second internal electrode layer 32 is 0.2 μm or more. This can suppress electric field concentration when voltage is applied while ensuring the thickness t of the dielectric layer 20 .

[0187] (5) In the multilayer ceramic capacitor 1 of the present embodiment, the thickness t of the dielectric layer 20 interposed between the first internal electrode layer 31 and the second internal electrode layer 32 is 0.3 μm or more. This can suppress electric field concentration when voltage is applied while ensuring the thickness t of the dielectric layer 20 .

[0188] (6) In the multilayer ceramic capacitor 1 of the present embodiment, the area-equivalent diameter D99 of the plurality of holes H present in the first internal electrode layer 31 and the second internal electrode layer 32 is 0.57 μm or more. The 0.57 μm in this case is a value obtained by substituting 0.2 μm as the thickness t of the dielectric layer 20 into the above equation (1).

[0189] (7) In the multilayer ceramic capacitor 1 of the present embodiment, the thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is thicker than the thickness t of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32. This makes it easy to increase the coverage of the internal electrode layer 30 and reduce the area-equivalent diameter D99 of the plurality of holes H present in the internal electrode layer 30. As a result, it is possible to improve the reliability of the product while suppressing a decrease in electrostatic capacitance.

[0190] (8) In the multilayer ceramic capacitor 1 of the present embodiment, the coverage of the internal electrode layer 30 with respect to the dielectric layer 20 is 70% to 99%. This can suppress a decrease in capacitance and reduce electric field concentration when voltage is applied.

[0191] (9) In the multilayer ceramic capacitor 1 of the present embodiment, the coverage of the internal electrode layer 30 with respect to the dielectric layer 20 is 86% or more and 93% or less. This can suppress a decrease in capacitance and also suppress electric field concentration when voltage is applied.

[0192] (10) The external electrode 40 of the multilayer ceramic capacitor 1 of the present embodiment includes a first external electrode 40A arranged on the first end surface LS1 side and a second external electrode 40B arranged on the second end surface LS2 side. The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 electrically connected to the first external electrode 40A and a plurality of second internal electrode layers 32 electrically connected to the second external electrode 40B. The first internal electrode layer 31 includes a first edge WE1 on the first side surface WS1 side and a second edge WE2 on the second side surface WS2 side. The second internal electrode layer 32 includes a third edge WE3 on the first side surface WS1 side and a fourth edge WE4 on the second side surface WS2 side. The region of the first internal electrode layer 31 from a position separated from the first edge WE1 by 10 μm to a position separated from the first edge WE1 by 50 μm is defined as a first region A. 1, the region from the position separated from the second side WE2 by 10 μm to the position separated from the second side WE2 by 50 μm in the first internal electrode layer 31 is set as the second region A2, the region from the position separated from the third side WE3 by 10 μm to the position separated from the third side WE3 by 50 μm in the second internal electrode layer 32 is set as the third region A3, the region from the position separated from the fourth side WE4 by 10 μm to the position separated from the fourth side WE4 by 50 μm in the second internal electrode layer 32 is set as the fourth region A4, and the set of holes H existing in the first region A1, the second region A2, the third region A3 and the fourth region A4 is set as the total number of holes H, in which case the area equivalent diameter D99 is the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of the holes H in the total number of holes H becomes 99%. Thus, a laminated ceramic capacitor with high reliability and suppressed electric field concentration can be provided.

[0193] (11) The multilayer ceramic capacitor 1 of the present embodiment comprises: a multilayer body 10 having a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction, a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction perpendicular to the height direction, and a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction perpendicular to the height direction and the width direction; and an external electrode 40 connected to the internal electrode layer 30, wherein the internal electrode layer 30 has a plurality of internal electrode layers 30 having different area equivalent diameters. The hole H, the external electrode 40 has a first external electrode 40A arranged on the first end surface LS1 side and a second external electrode 40B arranged on the second end surface LS2 side, the plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 electrically connected to the first external electrode 40A, and a plurality of second internal electrode layers 32 electrically connected to the second external electrode 40B, the first internal electrode layer 31 has a first side WE1 on the first side surface WS1 side and a second side WE2 on the second side surface WS2 side, the second internal electrode layer 32 has a third side WE3 on the first side surface WS1 side and a fourth side WE4 on the second side surface WS2 side The first internal electrode layer 31 includes a region from a position separated from the first side WE1 by 10 μm to a position separated from the first side WE1 by 50 μm as a first region A1, a region from a position separated from the second side WE2 by 10 μm to a position separated from the second side WE2 by 50 μm as a second region A2, a region from a position separated from the third side WE3 by 10 μm to a position separated from the third side WE3 by 50 μm as a third region A3, a region from a position separated from the fourth side WE4 by 10 μm to a position separated from the fourth side WE5 by 10 μm as a third region A4, and a region from a position separated from the fourth side WE5 by 10 μm to a position separated from the fourth side WE6 by 10 μm as a third region A5. The area from the position of 0 μm to the position separated from the fourth side WE4 by 50 μm is set as the fourth area A4, the set of holes H existing in the first area A1, the second area A2, the third area A3 and the fourth area A4 is set as the total number of holes H, the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the holes H in the total number of holes H becomes 99% is set as the area equivalent diameter D99, and the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is set as the thickness t. At this time, the thickness t of the dielectric layer 20 is less than 0.6 μm and satisfies the following formula (1).

[0194] (Area equivalent diameter D99) < 0.1468 × exp (6.7622 × t) … (1)

[0195] Thus, it is possible to provide a highly reliable multilayer ceramic capacitor that suppresses electric field concentration.

[0196] The present invention is not limited to the configuration of the above-described embodiment, and can be applied with appropriate changes within the scope of the present invention. It should be noted that a combination of two or more of the desired configurations described in the above-described embodiment also belongs to the present invention.

[0197] Description of Reference Numerals

[0198] 1. Multilayer ceramic capacitor;

[0199] 10 laminated bodies;

[0200] 20 dielectric layer;

[0201] 30 internal electrode layer;

[0202] 31 first internal electrode layer;

[0203] 32 second internal electrode layer;

[0204] 40 external electrodes;

[0205] 40A first external electrode;

[0206] 40B second external electrode;

[0207] H hole;

[0208] L length direction;

[0209] W width direction;

[0210] T height direction;

[0211] LS1 first end face;

[0212] LS2 second end face;

[0213] WS1 first side;

[0214] WS2 second side;

[0215] TS1 first main surface;

[0216] TS2 Second main surface.

Claims

1. A multilayer ceramic capacitor comprising: A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; and a first external electrode and a second external electrode, The plurality of internal electrode layers include a plurality of first internal electrode layers electrically connected to the first external electrode and a plurality of second internal electrode layers electrically connected to the second external electrode. The first internal electrode layer and the second internal electrode layer have a plurality of holes having different area equivalent diameters. When the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes becomes 99% is set as the area equivalent diameter D99, and the thickness of the dielectric layer sandwiched between the first internal electrode layer and the second internal electrode layer is set as the thickness t, the thickness t of the dielectric layer is 0.6 μm or less, and satisfies the following formula (1), 。 2. The multilayer ceramic capacitor according to claim 1, wherein The thickness t of the dielectric layer is less than 0.5 μm.

3. The multilayer ceramic capacitor according to claim 2, wherein: The thickness t of the dielectric layer is less than 0.4 μm.

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