Direct word line contact for 3D memory and method of manufacture

Abstract

Memory devices having an array region and an extension region adjacent to the array region are described. The array region includes at least two unit cells vertically stacked. The extension region includes a memory stack and a plurality of word line contacts. The memory stack includes alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. A plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts has a height different from a height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. More particularly, embodiments of the present disclosure provide a three-dimensional (3D) dynamic random access memory cell. Background Art

[0002] Electronic devices (such as personal computers, workstations, computer servers, mainframes, and other computer-related equipment such as printers, scanners, and hard disk drives) use memory devices that provide substantial data storage capabilities while incurring low power consumption. There are two main types of random access memory cells - dynamic and static - that are well suited for use in electronic devices. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than a very short period of time. Static random access memory (SRAM) is so named because they do not require periodic refreshing.

[0003] DRAM memory circuits are manufactured by replicating millions of identical circuit elements (called DRAM cells) on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit of data (a binary number). The most common form of a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.

[0004] Manufacturing a DRAM cell includes manufacturing a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is constant pressure to reduce the size of the individual cells and increase the density of memory cells to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 256 megabits. Limitations to cell size reduction include the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of array devices with non-array devices. Forming a low resistance contact between the active region and the bottom electrode of a 3D DRAM is critical to the performance of the device.

[0005] DRAM consists of hundreds of sub-blocks. For each sub-block, word lines (WL) and bit lines (BL) are connected to control circuits. Multiple cells are stacked in 3D DRAM. Each word line of each stack should have a contact to connect the word line to the control circuit in the sub-array. When nWL memory cells are stacked in 3D DRAM, nWL contacts are required in each row of WL. Reducing the WL contact area is critical to reducing chip area.

[0006] Thus, there is a need in the art for memory devices and methods of forming memory devices having reduced chip area. Summary of the invention

[0007] One or more embodiments of the present disclosure are directed to a memory device. In one or more embodiments, a memory device includes: an array region including at least two unit cells stacked vertically; and an extension region adjacent to the array region, the extension region including a memory stack and a plurality of word line contacts, the memory stack including alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer, the plurality of word line contacts extending through the memory stack to the at least one conductive layer, each of the plurality of word line contacts having a height different from a height of an adjacent word line contact, and each of the plurality of word line contacts having a metallization layer on a top surface.

[0008] Additional embodiments of the present disclosure relate to methods of forming a memory device. In one or more embodiments, a method of forming a memory device includes: forming a memory stack on a substrate, the memory stack including alternating layers of at least one sacrificial layer, an insulating layer, and a semiconductor layer; patterning the memory stack to form a plurality of openings extending through the memory stack, each of the plurality of openings having a depth different from that of adjacent openings; depositing an etch stop layer and a sacrificial fill layer in each of the plurality of openings; replacing at least one sacrificial layer of a unit cell with at least one conductive layer; removing the sacrificial fill layer in each of the plurality of openings to form a plurality of contact openings; removing a bottom portion of the etch stop layer; and depositing a conductive material in each of the plurality of contact openings to form a plurality of word line contacts, each of the plurality of word line contacts having a height different from that of adjacent word line contacts.

[0009] Further embodiments of the present disclosure relate to a non-transitory computer-readable medium comprising instructions which, when executed by a controller of a processing chamber, cause the processing chamber to perform the following operations: forming a memory stack on a substrate, the memory stack comprising alternating layers of at least one sacrificial layer, an insulating layer, and a semiconductor layer; patterning the memory stack to form a plurality of openings extending through the memory stack, each of the plurality of openings having a depth different from that of adjacent openings; depositing an etch stop layer and a sacrificial fill layer in each of the plurality of openings; replacing at least one sacrificial layer of a unit cell with at least one conductive layer; removing the sacrificial fill layer in each of the plurality of openings to form a plurality of contact openings; removing a bottom portion of the etch stop layer; and depositing a conductive material in each of the plurality of contact openings to form a plurality of word line contacts, each of the plurality of word line contacts having a height different from that of adjacent word line contacts. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are used, a more specific description of the present disclosure briefly summarized above may be obtained with reference to the embodiments, some of which are shown in the accompanying drawings. However, it will be noted that the drawings only show typical embodiments of the present disclosure and are not to be considered as limiting the scope of the present disclosure, as the present disclosure may admit of other equally effective embodiments. The embodiments as described herein are shown by way of example and not limitation in the figures of the accompanying drawings, in which the same reference numerals indicate similar elements.

[0011] Figure 1 A process flow diagram illustrating a method according to one or more embodiments;

[0012] Figure 2A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0013] Figure 2B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0014] Figure 2C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0015] Figure 3A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0016] Figure 3B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0017] Figure 3C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0018] Figure 4A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0019] Figure 4B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0020] Figure 4C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0021] Figure 5A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0022] Figure 5Bshows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0023] Figure 5C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0024] Fig. 6A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0025] Figure 6B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0026] Figure 6C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0027] Fig.6D shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0028] Fig. 7A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0029] Figure 7B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0030] Figure 7C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0031] Fig.7D shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0032] Fig. 8A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0033] Figure 8B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0034] Figure 8C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0035] Fig.8D shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0036] Fig. 9A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0037] Fig. 9B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0038] Fig. 9C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0039] Fig.9D shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0040] Fig. 10A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0041] Fig. 10B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0042] Fig. 10C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0043] Fig.11A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0044] Fig. 11B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0045] Fig. 11C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0046] Fig.11D shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0047] Fig. 12A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0048] Fig. 12B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0049] Fig. 12C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0050] Fig.12D shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0051] Fig.13Ashows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0052] Fig. 13B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0053] Fig. 13C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0054] Fig.14A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0055] Fig. 14B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0056] Fig.15 shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0057] Fig.16A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0058] Fig. 16B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0059] Fig. 16C shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0060] Fig.17 shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0061] Fig.18A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0062] Fig.18B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0063] Fig.19A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0064] Fig.19B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0065] Fig. 20A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0066] Fig. 20B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0067] Fig.21A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0068] Fig.21B shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0069] Fig.22A shows a cross-sectional view of a memory device according to one or more embodiments of the present disclosure;

[0070] Fig. 22B A cross-sectional view showing a memory device according to one or more embodiments of the present disclosure; and

[0071] Fig.23 A cluster tool is shown in accordance with one or more implementations. DETAILED DESCRIPTION

[0072] Before describing several exemplary embodiments of the present disclosure, it will be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0073] In the following description, several specific details (such as specific materials, chemicals, dimensions, etc. of components) are set forth in order to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to those skilled in the art that one or more embodiments of the present disclosure may be practiced without these specific details. In other cases, semiconductor manufacturing processes, techniques, materials, equipment, etc. are not described in more detail to avoid unnecessarily obscuring this description. With the included description, those skilled in the art will be able to implement the appropriate functions without excessive experimentation.

[0074] While certain exemplary embodiments of the present disclosure are described and illustrated in the drawings, it will be understood that such embodiments are merely illustrative and not restrictive of the disclosure, and that the disclosure is not limited to the specific construction and arrangements illustrated and described, as modifications may occur to those skilled in the art.

[0075] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species that can react with a substrate surface.

[0076] According to one or more embodiments, the term "on..." with respect to a film or film layer includes a film or layer directly on a surface (e.g., a substrate surface), and one or more underlayers (underlayers) between the film or layer and the surface (e.g., a substrate surface). Thus, in one or more embodiments, the phrase "on a substrate surface" is intended to include one or more underlayers. In other embodiments, the phrase "directly on..." refers to a layer or film in contact with a surface (e.g., a substrate surface) without an intermediate layer. Thus, the phrase "a layer directly on a substrate surface" refers to a layer in direct contact with a substrate surface without a layer in between.

[0077] As used herein, "atomic layer deposition" or "cyclic deposition" refers to sequentially exposing two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate, or a portion of the substrate, is separately exposed to two or more reactive compounds, which are introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere to the substrate surface and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are considered to be exposed to the substrate sequentially. In a spatial ALD process, different portions of the substrate surface or the material on the substrate surface are simultaneously exposed to two or more reactive compounds, so that any given point on the substrate is not substantially exposed to more than one reactive compound at the same time. As used in this specification and the appended claims, as will be understood by those skilled in the art, the term "substantially" used in this regard means that there is a possibility that a small portion of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, and this simultaneous exposure is unintentional.

[0078] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A, e.g., an aluminum precursor) is pulsed into a reaction zone, followed by a first time delay. Next, a second precursor or compound B (e.g., an oxidant) is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas (such as argon) is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either case, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is a cycle. The cycle may start with either compound A or compound B, and continue the corresponding order of the cycles until a film having a predetermined thickness is obtained.

[0079] In one embodiment of a spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen) are delivered to the reaction zone simultaneously, but separated by an inert gas curtain and / or a vacuum curtain. The substrate moves relative to the gas delivery apparatus so that any given point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0080] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to situations where there is overlap in the exposure of a large portion of the co-flow or precursors.

[0081] Plasma enhanced chemical vapor deposition (PECVD) is widely used to deposit thin films due to cost efficiency and versatility of film properties. In the PECVD process, for example, a hydrocarbon source (such as a vapor of a gas phase hydrocarbon or a liquid phase hydrocarbon that has been entrained in a carrier gas) is introduced into a PECVD chamber. A plasma-induced gas (usually helium) is also introduced into the chamber. The plasma is then ignited in the chamber to produce excited CH- radicals. The excited CH- radicals chemically bind to the surface of a substrate positioned in the chamber, thereby forming a desired film on the surface of the substrate. The embodiments described herein with reference to the PECVD process can be performed using any suitable thin film deposition system. Any device description described herein is illustrative and should not be understood or interpreted as limiting the scope of the embodiments described herein.

[0082] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores a bit of data by storing a charge packet (i.e., a binary one) on a capacitor, or not storing a charge packet (i.e., a binary zero). The charge is gated onto the capacitor via an access transistor, and is sensed by turning on the same transistor and looking at the voltage disturbance created by the accumulation of the charge packet on the interconnect line at the transistor output. Thus, a single DRAM cell is made of one transistor and one capacitor. A DRAM device is formed of an array of DRAM cells.

[0083] Traditionally, DRAM cells have a recessed high work function metal structure in a buried word line structure. In a DRAM device, the bit lines are formed in a metal level located above the substrate, while the word lines are formed at the polysilicon gate level at the substrate surface. In a buried word line (bWL), the word line is buried below the surface of the semiconductor substrate using metal as the gate electrode.

[0084] In current 3D DRAM devices, a staircase structure is generated, and word line contacts are formed on the stairs. However, in order to prevent short circuits between the stairs and the word line contacts, the contact holes must have a large critical dimension, which is problematic during manufacturing. In one or more embodiments, a memory device is provided that advantageously has word line contacts of varying heights, wherein the word line contacts connect the metallization layer to the conductive layer of the unit cell, thereby forming a reduced chip area and reducing the difficulty of processing. Therefore, the method of one or more embodiments does not require the formation of a staircase structure. In the word line contacts of one or more embodiments, only the short circuit between the contacts needs to be considered. In addition, the contact structure of one or more embodiments is advantageously used as a support to prevent mold collapse during the gate replacement process.

[0085] In one or more embodiments, metal deposition and other processes may be performed in an isolated environment (eg, a cluster processing tool). Accordingly, some embodiments of the present disclosure provide an integrated tool system having related processing modules to implement a method.

[0086] Figure 1 A process flow diagram of method 10 is shown that may include any or all of the processes shown. In addition, the order of the individual processes may be changed for some parts. Method 10 may begin with any of the listed processes without departing from the present disclosure. Figure 1 , at operation 12, a memory stack is formed. At operation 14, an opening is patterned into the memory stack. At operation 16, an etch stop layer is deposited through the opening. At operation 18, a sacrificial fill layer is deposited on the etch stop layer in the opening. At operation 20, the memory stack is slit patterned. At operation 22, the sacrificial layer of the memory stack is removed and replaced with a conductive layer. At operation 24, the sacrificial fill layer is removed to form a contact opening. At operation 26, the slit is filled with an insulating material. At operation 28, a bottom portion of the etch stop layer is removed. At operation 30, a conductive material is deposited in the contact opening to form a word line contact.

[0087] Figure 2A Until Fig. 22B A cross-sectional view of a memory device during processing is shown according to a method of one or more embodiments.

[0088] refer to FIG. 2A to FIG. 2C, the 3D DRAM device 100 includes an array region 101 and an extension region 103 adjacent to the array region 101. The extension region 103 connects the memory cell to a non-array node of the DRAM device. In one or more embodiments, the array region 101 includes at least two unit cells 105 stacked vertically. The unit cell 105 includes a transistor and a cell capacitor. In one or more embodiments, the extension region 103 includes a memory stack 111 and a plurality of word line contacts 136. In one or more embodiments, the memory stack 111 does not include a staircase structure, but has a plurality of word line contacts 136 each having a height different from that of an adjacent contact.

[0089] See also FIG. 3A to FIG. 3C , an initial or starting mold for forming the extended region 103 according to one or more embodiments of the present disclosure. Figure 3B It is along Figure 2C A view of line A, and Figure 3C It is along Figure 2C In some embodiments, Figure 3A The electronic device 103 shown in FIG. 1 is formed in layers on a bare substrate (not shown). In one or more embodiments, Figure 3A The electronic device is made of a substrate 102 and a unit stack 110. In one or more embodiments, the unit stack 110 includes an insulating layer 104, at least one sacrificial layer 106, and a semiconductor layer 108. In some embodiments, the unit stack 110 includes an insulating layer 104, a first sacrificial layer 106 on the insulating layer 104, a semiconductor layer 108 on the first sacrificial layer 106, and a second sacrificial layer 106b on the semiconductor layer 108. Repeated unit stacks 110 stacked vertically on top of each other form a memory stack 111 on the substrate. The memory stack 111 includes alternating layers of the insulating layer 104, the at least one sacrificial layer 106, and the semiconductor layer 108.

[0090] The substrate 102 may be any suitable material known to those skilled in the art. As used in this specification and the appended claims, the term "substrate" refers to a surface, or portion of a surface, on which a process acts. As will also be understood by those skilled in the art, unless the context clearly indicates otherwise, reference to a substrate may also refer to only a portion of a substrate. In addition, reference to deposition on a substrate may mean a bare substrate as well as a substrate having one or more films or features deposited or formed on the substrate.

[0091] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, depending on the application, the substrate surface (on which the treatment may be performed) includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to the film treatment directly on the surface of the substrate itself, in the present disclosure, as disclosed in more detail below, any of the disclosed film treatment steps may also be performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such an underlying layer as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0092] In one or more embodiments, the insulating layer 104 is on the top surface of the substrate 102. The insulating layer 104 can be formed by any suitable technique known to a skilled person and can be made of any suitable material. In one or more embodiments, the insulating layer 104 comprises silicon oxide (SiO x ).

[0093] In one or more embodiments, the first sacrificial layer 106 is on the insulating layer 104. The first sacrificial layer 106 may include any suitable material known to a skilled person. In one or more embodiments, the first sacrificial layer 106 includes silicon nitride (SiN).

[0094] In one or more embodiments, the semiconductor layer 108 may be formed on the first sacrificial layer 106. The semiconductor layer 108 may also be referred to as an active layer or a memory layer.

[0095] As used herein, the term "active" or "memory layer" refers to a material layer in which a channel, bit line, word line, or capacitor can be made. In one or more embodiments, the active layer, or semiconductor layer 108 includes one or more of silicon or doped silicon. In some embodiments, the semiconductor layer 108 may include a semiconductor material that is a doped material, such as n-doped silicon (n-Si), or p-doped silicon (p-Si). In some embodiments, the semiconductor layer 108 can be doped using any suitable process (such as an ion implantation process). As used herein, the term "n-type" refers to a semiconductor layer 108 produced by doping with an electron donor element during manufacturing. The term n-type comes from the negative charge of electrons. In an n-type semiconductor material layer, electrons are majority carriers and holes are minority carriers. As used herein, the term "p-type" refers to the positive charge of the well (or hole). In contrast to n-type semiconductor materials, p-type semiconductor materials have a larger hole concentration than the electron concentration. In p-type semiconductor materials, holes are majority carriers and electrons are minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof. In some embodiments, semiconductor layer 108 comprises several different conductive or semiconductor materials.

[0096] The first sacrificial layer 106 and the insulating layer 104 may be formed on the substrate 102 and may be made of any suitable material. In some embodiments, one or more of the first sacrificial layer 106 and the insulating layer 104 may be removed and replaced in a later process. In some embodiments, one or more of the first sacrificial layer 106 and the insulating layer 104 are not removed and remain within the memory device 100. In this case, the term "sacrificial" has an expanded meaning to include permanent layers and may be referred to as conductive layers. In one or more embodiments, one or more of the first sacrificial layer 106 and the insulating layer 104 include a material that can be selectively removed relative to adjacent layers of the memory stack.

[0097] The memory stack 111 in the illustrated embodiment includes a plurality of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108. Figure 3AThe memory stack 111 shown in FIG. 1 has four sets of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108, and those skilled in the art will recognize that this is for illustration purposes only. The memory stack 111 may have any number of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108. For example, in some embodiments, the memory stack 111 includes 192 pairs of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108. In other embodiments, the memory stack 111 includes more than 50 pairs of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108, or more than 100 pairs of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108, or more than 300 pairs of alternating sacrificial layers 106, insulating layers 104, and semiconductor layers 108.

[0098] In one or more embodiments, sequential deposition is used to form a plurality of active area regions. In one or more embodiments, alternating layers of films are deposited, for example, oxide-polysilicon, polysilicon-nitride, oxide-nitride, silicon-germanium silicon, oxide-nitride-silicon-nitride.

[0099] In one or more embodiments, the sacrificial layer 106 independently comprises an insulating material. In one or more embodiments, the sacrificial layer 106 comprises a nitride material, such as silicon nitride, and the insulating layer 104 comprises an oxide material, such as silicon oxide. The sacrificial layer 106 comprises a material that is etch selective relative to the insulating layer 104 and the semiconductor layer 108, so that the sacrificial layer 106 can be removed without substantially affecting the insulating layer 104 and the semiconductor layer 108. In one or more embodiments, the sacrificial layer 106 comprises silicon nitride (SiN). In one or more embodiments, the insulating layer 104 comprises silicon oxide (SiO x In one or more embodiments, the sacrificial layer 106, the insulating layer 104, and the semiconductor layer 108 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0100] The individual alternating layers may be formed to any suitable thickness. In some embodiments, the thickness of each sacrificial layer 106 is approximately equal. In one or more embodiments, each sacrificial layer 106 has a sacrificial layer thickness. In some embodiments, the thickness of each insulating layer 104 is approximately equal. As used in this context, approximately equal thicknesses are within + / - 5% of each other. In some embodiments, a semiconductor layer 108 (e.g., silicon) is formed between the first sacrificial layer 106 and the second sacrificial layer 106b of the unit stack 110. The thickness of the semiconductor layer 108 may be relatively thin compared to the thickness of the sacrificial layer 106 and the insulating layer 104.

[0101] In one or more embodiments, the insulating layer 104 has a thickness in a range from about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the insulating layer 104 has a thickness in a range from about 0.5 to about 40 nm. In one or more embodiments, the sacrificial layer 106 has a thickness in a range from about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the sacrificial layer 106 has a thickness in a range from about 0.5 to about 40 nm.

[0102] refer to FIG. 4A to FIG. 4C , patterning the device to form isolation openings 109 for cell-to-cell isolation.

[0103] See also FIG. 5A to FIG. 5C , the isolation opening 109 is filled with an insulating material 109i. The insulating material 109i can be any suitable insulating material known to the skilled person. In one or more embodiments, the insulating material 109i is a dielectric material. As used herein, the term "dielectric material" refers to a material layer of an electrical insulator that can be polarized in an electric field. In one or more embodiments, the insulating material 109i includes one or more of the following: oxide, carbon-doped oxide, silicon oxide (SiO), porous silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide / silicon nitride, carbide, carbon oxide, nitride, nitrogen oxide, nitrogen-carbon oxide, polymer, phosphosilicate glass, fluorosilicate (SiOF) glass, or organosilicate glass (SiOCH). In one or more embodiments, the insulating material 109i includes silicon oxide (SiO x ).

[0104] See also FIG. 6A to FIG. 6D , patterning the device 103 to form the opening 112. In some embodiments, patterning the opening 112 includes etching through the memory stack 111. In one or more embodiments, the semiconductor substrate 108 is used as an etch stop. See Fig. 6A The opening 112 has sidewalls extending through the memory stack 111 , thereby exposing surfaces of the sacrificial layer 106 , the insulating layer 104 , and the semiconductor layer 108 .

[0105] In one or more embodiments, each of the openings 112 has a depth different from the depth of the adjacent openings 112. In one or more embodiments, the openings 112 have a depth in the range of nLayer x tUnit in the range of 1.5um to 50um, wherein the stacking number nLayer is 50 to 500 layers, and tUnit (thickness of a unit mold) is in the range of 30nm to 100nm.

[0106] The sacrificial layer 106, the semiconductor layer 108, and the insulating layer 104 have surfaces exposed as sidewalls of the opening 112. The bottom of the opening 112 can be formed at any point within the thickness of the semiconductor layer 108. In some embodiments, the thickness of the opening 112 extending into the semiconductor layer is in a range from about 10% to about 90% of the thickness of the semiconductor layer 108, or in a range from about 20% to about 80%, or in a range from about 30% to about 70%, or in a range from about 40% to about 60%. In some embodiments, the distance that the opening 112 extends into the semiconductor layer 108 is greater than or equal to 10%, 20%, 30%, 40%, 50%, 60%, 70%, or 80% of the thickness of the semiconductor layer 108.

[0107] See also 7A to 7D , an insulating layer 114 is conformally deposited in each of the plurality of openings 112 of high aspect ratio. When used in this manner, the conformal film has a thickness near the top of the feature in the range of about 80-120% of the thickness at the bottom of the feature. The insulating layer 114 can be any suitable material known to a skilled person. In one or more embodiments, the insulating layer 114 (or liner) comprises silicon oxide (SiO x ) and one or more of silicon nitride (SiN). In some embodiments, the insulating layer 114 is used as an etch stop layer in a later processing step.

[0108] refer to FIG. 8A to FIG. 8D , a sacrificial layer 116 is deposited in the plurality of openings 112 adjacent to the insulating layer 114. The sacrificial layer 116 can be any suitable material known to a skilled person. In one or more embodiments, the sacrificial layer 116 comprises one or more of the following: tungsten (W), silicon germanium (SiGe), germanium (Ge), carbon (C), titanium nitride (TiN), and the like. In subsequent processing, after the replacement gate is formed, the sacrificial layer 116 will be replaced with a conductive material 134. In one or more embodiments, the plurality of openings 112 are filled in a bottom-up gap fill process, thereby filling the features from the bottom. In other embodiments, the plurality of openings 112 are filled using a conformal process, where the features are filled from the bottom and the sides.

[0109] 9A to 9DOperation 20 of method 10 is illustrated, in which the device is slit patterned to form a slit pattern opening 120 extending from a top surface of the memory stack 111 to the substrate 102 .

[0110] refer to FIG. 10A to FIG. 10C , the sacrificial layer 106 (ie, silicon nitride (SiN)) is selectively removed through the slit patterned opening 120 to form the open region 118. In one or more embodiments, the sacrificial layer 106 (eg, nitride layer) is removed through the slit patterned opening 120 using thermal phosphorus (HP).

[0111] See also FIG. 11A to FIG. 11D , a gate oxide layer 124 is deposited onto the insulating layer 104 through the opening 120. The gate oxide layer 124 may comprise any suitable material known to the skilled person. The gate oxide layer 124 may be deposited using one or more deposition techniques known to the skilled person. In one or more embodiments, the gate oxide layer 124 is deposited using one of the deposition techniques, such as but not limited to ALD, CVD, PVD, MBE, MOCVD, spin coating, or other deposition techniques known to the skilled person. The illustrated embodiment illustrates the gate oxide layer 124 as a conformal layer having a uniform shape. However, the skilled person will recognize that this is for illustrative purposes only, and that the gate oxide layer 124 may be formed in an isotropic manner, such that the gate oxide layer 124 has a rounded appearance. In some embodiments, the gate oxide layer 124 is selectively deposited as a conformal layer on the surface of the insulating layer 104. In some embodiments, the gate oxide layer 124 is formed by oxidizing the semiconductor surface.

[0112] In one or more embodiments, the gate oxide layer 124 comprises silicon oxide (SiO x ). Although the term "silicon oxide" may be used to describe the gate oxide layer 124, skilled artisans will recognize that the present disclosure is not limited to a particular stoichiometry. For example, the terms "silicon oxide" and "silicon dioxide" may each be used to describe a material having silicon and oxygen atoms in any suitable stoichiometric ratio. The same is true for other materials listed in the present disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, and the like.

[0113] In one or more embodiments, a word line is then formed in the opening 118. The word line includes one or more of a barrier layer 126 and a word line metal 122. The barrier layer 126 may include any suitable barrier layer known to a skilled person. In one or more embodiments, the barrier layer 126 includes one or more of the following: titanium nitride (TiN), tantalum nitride (TaN), or the like. In one or more embodiments, the word line metal 122 includes a bulk metal including one or more of the following: copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the word line metal 122 includes tungsten (W). In other embodiments, the word line metal 122 includes ruthenium (Ru).

[0114] See also FIG. 12A to FIG. 12D , the slit pattern opening 120 is filled with an insulating material 128. The insulating material 128 may include any suitable material known to a skilled person. In one or more embodiments, the insulating material 128 includes silicon oxide (SiO x In one or more embodiments, the insulating material 128 is a sacrificial material that is removed in subsequent processing.

[0115] refer to FIG. 13A to FIG. 13C , removing the sacrificial layer 116 to form a plurality of contact openings 130. The sacrificial layer 116 can be removed by any suitable technique known to a skilled person. In one or more embodiments, the sacrificial layer 116 is removed by one or more of wet etching or dry etching. Each of the plurality of contact openings 130 has a depth that is different from the depth of the contact openings adjacent to the contact opening. Each contact opening 130 extends from the top surface of the device 103 to the semiconductor layer 108. In one or more embodiments, the critical dimension (CD) of each of the contact openings 130 is in the range of from 100 nm to 2000 nm.

[0116] See also FIG. 14A to FIG. 14B , a portion of the insulating layer 114 at the bottom of each of the plurality of contact openings 130 is removed to form a portion 131 of the contact opening 130 without the insulating layer 114. Fig.15 In one or more embodiments, the semiconductor layer 108 , the gate oxide layer 124 , and the conductive layer 122 adjacent to the bottoms of the plurality of contact openings 130 are enlarged using a selective removal process (SRP).

[0117] refer to FIG. 16A to FIG. 16C , a barrier layer 133 is conformally deposited in each of the plurality of contact openings 130. The barrier layer 133 may include any suitable material known to a skilled person. In one or more embodiments, the barrier layer 133 includes titanium nitride (TiN).

[0118] See also Fig.17 , a conductive layer 134 is deposited in the plurality of contact openings 130 to form contacts. In one or more embodiments, the plurality of contact openings 130 are filled in a bottom-up gap fill process, thereby filling the features from the bottom. In other embodiments, the plurality of contact openings 130 are filled using a conformal process, where the features are filled from the bottom and the sides. The conductive layer 134 may include any suitable material known to a skilled person. In one or more embodiments, the conductive layer 134 includes tungsten (W).

[0119] refer to Fig.18A and Fig.18B , the insulating material 109i is removed to form an opening 160. The insulating material 109i may be removed by any suitable means known to a skilled person.

[0120] See also FIG. 19A to FIG. 19B , removing the semiconductor layer 108 and trimming the sacrificial layer 106 to form an opening 234. The opening 234 can be enlarged or trimmed to produce a widened opening 234. The opening 234 can be widened by any suitable technique known to a skilled person. The opening 234 of some embodiments is widened by a percentage of the thickness of the semiconductor layer 108. In some embodiments, the opening 234 is widened by an amount in the range of 10% to 80% of the thickness of the semiconductor layer 108. In some embodiments, the opening 234 is widened by an amount in the range of 20% to 75%, or in the range of 30% to 60%. In some embodiments, the opening 234 is widened using a dilute HF (~1% HF in water) wet etch.

[0121] See also FIG. 20A to FIG. 20B In one or more embodiments, the pads at the bottom of the contacts are removed.

[0122] refer to FIG. 21A to FIG. 21B , a bit line 238 is formed in the filled slit pattern opening. In one or more embodiments, the bit line 238 may include an optional bit line liner (also referred to as a bit line barrier layer) and a bit line metal.

[0123] The optional bit line liner can be made of any suitable material deposited by any suitable technique known to the skilled person. In one or more embodiments, the bit line liner is deposited on the source / drain region at the inner end of the active material. The bit line liner can be any suitable material, including but not limited to titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the optional bit line liner contains titanium nitride (TiN) or consists essentially of titanium nitride (TiN). As used in this manner, the term "consisting essentially of..." means that the composition of the film is greater than or equal to about 95%, 98%, 99% or 99.5% of the species. In some embodiments, the optional bit line liner contains tantalum nitride (TaN) or consists essentially of tantalum nitride (TaN). In some embodiments, the bit line liner is a conformal layer. In some embodiments, the bit line liner is deposited by atomic layer deposition.

[0124] In some embodiments, the bit line 238 includes a bit line metal. The bit line metal may include any suitable metal known to a skilled person. In one or more embodiments, the bit line metal includes or consists essentially of one or more of the following: tungsten silicide (WSi), tungsten nitride (WN), or tungsten (W). The bit line metal may be deposited by any suitable technique known to a skilled person and may be any suitable material. In one or more embodiments, forming the bit line 238 further includes forming a bit line metal seed layer (not shown) prior to depositing the bit line metal.

[0125] See also Fig.22A and Fig. 22B , the extension region 103 of the 3D DRAM device connects the memory cell to the non-array node of the DRAM device. In one or more embodiments, the extension region 103 includes a memory stack 111 and a plurality of word line contacts 136. In one or more embodiments, the memory stack 111 does not include a staircase structure, but has a plurality of word line contacts 136 each having a height different from that of adjacent contacts.

[0126] The memory stack 111 includes alternating layers of at least one conductive layer 122, semiconductor layers 108, and insulating layers 104. A plurality of word line contacts 136 extend through the memory stack 111 to the at least one conductive layer 122. Each of the plurality of word line contacts 136 has a height that is different from a height of an adjacent word line contact 136, and each of the plurality of word line contacts 136 has a metallization layer 138 on a top surface.

[0127] In one or more embodiments, each of the word line contacts 136 includes a first region a, a second region b, and a third region c. The second region b is located between the first region a and the third region c. In one or more embodiments, the third region c is larger than the second region b.

[0128] In one or more embodiments, the first region and the third region are connected to one or more of the metallization layer 138 and the at least one conductive layer 122. The second region b may be surrounded by the pad 114. In one or more embodiments, the pad 114 is adjacent to the at least one conductive layer 122, the insulating layer 104, and the semiconductor layer 108.

[0129] Additional embodiments of the present disclosure relate to the processing tool 900 described for forming memory devices and methods, such as Fig.23 The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are positioned within the central transfer station 921, 931 and are configured to move robot blades and wafers to each of the multiple sides.

[0130] The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to a central transfer station. Various processing chambers provide separate processing areas isolated from adjacent process stations. The processing chambers can be any suitable chamber, including but not limited to pre-cleaning chambers, buffer chambers, transfer spaces, wafer orienters / degassing chambers, cryogenic cooling chambers, deposition chambers, annealing chambers, etching chambers, selective etching chambers, and the like. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be considered to limit the scope of the present disclosure.

[0131] exist Fig.23 In the embodiment shown in FIG. 1 , a factory interface 950 is connected to the front of the cluster tool 900. On the front 951 of the factory interface 950, the factory interface 950 includes a loading chamber 954 and an unloading chamber 956. Although the loading chamber 954 is illustrated on the left side and the unloading chamber 956 is illustrated on the right side, those skilled in the art will appreciate that this represents only one possible configuration.

[0132] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary depending, for example, on the substrates being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette in which a plurality of wafers are positioned.

[0133] The robot 952 is within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 through the factory interface 950 to a load lock chamber 960. The robot 952 can also transfer wafers from a load lock chamber 962 through the factory interface 950 to a cassette in the unloading chamber 956. As will be appreciated by those skilled in the art, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0134] The cluster tool 900 shown has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 via load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921, which has at least one robot 925 positioned in the first transfer chamber 921. The robot 925 is also referred to as a robotic wafer transport mechanism. The first transfer chamber 921 is centrally positioned relative to the load lock chambers 960, 962, the process chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 of some embodiments is a multi-arm robot capable of independently moving more than one wafer at a time. In some embodiments, the first transfer chamber 921 includes more than one robotic wafer transfer mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are carried on a wafer transport blade that is located at a distal end of the first robotic mechanism.

[0135] After processing the wafer in the first section 920, the wafer can be transferred to the second section 930 via a pass-through chamber. For example, the chambers 922, 924 can be one-way or two-way pass-through chambers. The pass-through chambers 922, 924 can be used, for example, to cryogenically cool the wafer prior to processing in the second section 930 or to allow the wafer to cool or post-process before moving back to the first section 920.

[0136] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component that can control the processing chambers and the robots. For example, the system controller 990 may be a computer that includes a central processing unit (CPU), memory, suitable circuitry, and storage.

[0137] The process may be stored generally in the memory of the system controller 990 as a software routine that, when executed by the processor, causes the process chamber to perform the process of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown) that is remotely located from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. As such, the process may be implemented in software and executed in hardware using a computer system, as, for example, an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by the processor, the software routine converts a general purpose computer into a special purpose computer (controller) that controls the chamber operation so that the process is performed.

[0138] For ease of description, spatially relative terms (such as "below," "beneath," "lower," "above," "upper," and the like) may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, elements described as being "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary term "below" may include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0139] Unless otherwise indicated herein or explicitly denied by context, the use of the terms "a" and "an" and "the" and similar references in the context of describing the materials and methods discussed herein (particularly in the context of the appended claims) will be understood to cover both the singular and the plural. Unless otherwise indicated herein, the recording of the range of values ​​herein is intended only to be used as a shorthand method of independently referring to each individual value falling within the range, and each individual value is incorporated into the specification as if the individual value is independently recorded herein. Unless otherwise indicated herein or explicitly denied by context, all methods described herein can be performed in any suitable order. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods, and does not confer limitations on the scope unless otherwise claimed. The language in the specification should not be interpreted as indicating that any unclaimed element is essential to practicing the disclosed materials and methods.

[0140] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in certain embodiments," "in an embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0141] Although the disclosure herein has been described with reference to specific embodiments, it will be understood by those skilled in the art that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure may include modifications and variations within the scope of the appended claims and the equivalents of the claims.

Claims

1. A memory device, comprising: an array region comprising at least two unit cells stacked vertically; and an extension region adjacent to the array region, the extension region comprising a memory stack and a plurality of word line contacts, the memory stack comprising alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer, the plurality of word line contacts extending through the memory stack to the at least one conductive layer, each of the plurality of word line contacts having a height different from the height of an adjacent word line contact and each of the plurality of word line contacts having a metallization layer on a top surface.

2. The memory device of claim 1, wherein the plurality of word line contacts connect the metallization layer with the at least one conductive layer.

3. The memory device of claim 1, wherein each of the plurality of word line contacts comprises a first region, a second region, and a third region.

4. The memory device of claim 3, wherein the first region and the third region are connected to one or more of: the metallization layer and the at least one conductive layer.

5. The memory device of claim 3, wherein the second region is located between the first region and the third region. The memory device of claim 3 , wherein the second region is surrounded by a pad.

7. The memory device of claim 6, wherein the pad is adjacent to the at least one conductive layer, the insulating layer, and the semiconductor layer.

8. The memory device of claim 3, wherein the third area is larger than the second area.

9. The memory device of claim 1, wherein the memory device is a 3D DRAM device.

10. A method of manufacturing a memory device, the method comprising: forming a memory stack on a substrate, the memory stack comprising alternating layers of at least one sacrificial layer, an insulating layer, and a semiconductor layer; patterning the memory stack to form a plurality of openings extending through the memory stack, each of the plurality of openings having a different depth than an adjacent opening, depositing an etch stop layer and a sacrificial fill layer in each of the plurality of openings; replacing the at least one sacrificial layer of the unit cell with at least one conductive layer; removing the sacrificial filling layer in each of the plurality of openings to form a plurality of contact openings; removing a bottom portion of the etch stop layer; and A conductive material is deposited in each of the plurality of contact openings to form a plurality of word line contacts, each of the plurality of word line contacts having a height that is different from the height of an adjacent word line contact.

11. The method of claim 10, wherein the memory device is a 3D DRAM device.

12. The method of claim 10, wherein the at least one sacrificial layer comprises silicon nitride.

13. The method of claim 10, wherein the insulating layer comprises one or more of silicon oxide and silicon nitride.

14. The method of claim 10, wherein the conductive material of the plurality of word line contacts comprises one or more of titanium nitride (TiN) and tungsten (W).

15. The method of claim 10, further comprising: slit patterning the device to form at least one slit opening adjacent to the plurality of openings.

16. The method of claim 15, wherein the at least one sacrificial layer is removed and replaced through the at least one slit opening to form the at least one conductive layer.

17. The method of claim 16, wherein the at least one conductive layer comprises a gate oxide layer comprising a material selected from one or more of titanium nitride (TiN) and tungsten (W).

18. The method of claim 16, further comprising filling the slot opening with an insulating material.

19. The method of claim 10, wherein the method is performed in a processing tool without breaking vacuum.

20. A non-transitory computer readable medium comprising instructions which, when executed by a controller of a processing chamber, cause the processing chamber to: forming a memory stack on a substrate, the memory stack comprising alternating layers of at least one sacrificial layer, an insulating layer, and a semiconductor layer; patterning the memory stack to form a plurality of openings extending through the memory stack, each of the plurality of openings having a different depth than an adjacent opening, depositing an etch stop layer and a sacrificial fill layer in each of the plurality of openings; replacing the at least one sacrificial layer of the unit cell with at least one conductive layer; removing the sacrificial filling layer in each of the plurality of openings to form a plurality of contact openings; removing a bottom portion of the etch stop layer; and A conductive material is deposited in each of the plurality of contact openings to form a plurality of word line contacts, each of the plurality of word line contacts having a height that is different from the height of an adjacent word line contact.

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