Method and system for electro-acoustic transducer

Abstract

Various methods and systems are provided for an electro-acoustic module (EAM) for a probe. In one example, the EAM may be formed from a microelectromechanical system (MEMS) wafer (1200) bonded to a complementary metal oxide semiconductor (CMOS) wafer (1300), and have a front face (501) formed from a surface of the MEMS wafer (1200). The surface of the MEMS wafer (1200) may include an active region (502) of a capacitive micromachined ultrasound transducer (CMUT) cell and an input / output (I / O) region of an output contact disposed adjacent to the active region (502).

Description

Technical Field

[0001] Embodiments of the subject matter disclosed herein relate to transducers for medical imaging. Background Art

[0002] Microelectromechanical system (MEMS) ultrasound devices (hereinafter, MEMS devices) can be used to image and / or treat targets such as organs and soft tissues in the human body and non-human targets. For example, in addition to ultrasound imaging of humans, animals, etc., MEMS devices can also be used for applications such as ultrasound / acoustic sensing, non-destructive evaluation (NDE), ultrasound therapy (e.g., high-intensity focused ultrasound (HIFU)), etc. MEMS devices may include both electronic parts and moving parts, and may be formed of components ranging in size from 0.001 mm to 0.3 mm.

[0003] MEMS devices can use real-time, non-invasive high-frequency (e.g., in the range of 100KHz to tens of MHz) sound waves to produce a series of two-dimensional (2D) images and / or three-dimensional (3D) images. The sound waves can be emitted by a transmitting transducer, and the reflections of the emitted sound waves can be received by a receiving transducer. The received sound waves can then be processed to display an image of the target. For some types of MEMS devices used as transmitting transducers and / or receiving transducers, such as capacitive micromachined ultrasonic transducers (CMUTs), the CMUT may include a top electrode and a bottom electrode that may be separated by a gap or cavity.

[0004] In a probe used for medical imaging, such as an ultrasound probe, a CMUT array may be coupled to an electronic circuit, such as an application specific integrated circuit (ASIC). The ASIC may have a configuration that is specific to a particular CMUT array, and it may be expensive and laborious to make an ASIC with a new configuration to accommodate a different CMUT array. Therefore, it may be desirable to be able to adapt an existing ASIC die type for use with a different CMUT array arrangement. Summary of the invention

[0005] In one embodiment, an ultrasound probe includes an electro-acoustic module formed by a micro-electromechanical system (MEMS) wafer bonded to a complementary metal oxide semiconductor (CMOS) wafer as an application specific integrated circuit (ASIC) and having a front side formed by a surface of the MEMS wafer, the surface of the MEMS wafer including an active area of ​​a capacitive micro-machined ultrasound transducer (CMUT) cell and an input / output (I / O) area of ​​input and output contacts of the ASIC, the (I / O) area being arranged adjacent to the active area, the input and output contacts being redistributed to the surface of the MEMS wafer. In this way, an electro-acoustic module can be provided using a wafer-level manufacturing approach that allows different CMUT wafer configurations to fit a given ASIC structure.

[0006] It should be understood that the above brief description is provided to introduce in a simplified form selected concepts that are further described in the detailed description. It is not meant to identify key or essential features of the claimed subject matter, the scope of which is solely defined by the claims that follow the detailed description. Furthermore, the claimed subject matter is not limited to implementations that solve any disadvantages noted above or in any part of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be better understood by reading the following description of non-limiting embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 shows a block diagram of an exemplary ultrasound system that may be used for ultrasound imaging according to an embodiment;

[0009] Figure 2 shows a cross-sectional view of a CMUT cell according to an embodiment;

[0010] Figure 3 An example of an ASIC wafer that can be cut and used to form blocks of an electro-acoustic module (EAM) is shown;

[0011] Figure 4 Shown by Figure 3 The conventional configuration of ASIC blocks formed by the ASIC wafer;

[0012] Figure 5 shows the front side of an extended EAM block according to an embodiment;

[0013] Figure 6 According to the embodiment Figure 5 Final configuration of the extended EAM block;

[0014] Figure 7 According to the embodiment, Figure 6 The EAM formed by the extended EAM block;

[0015] Figure 8 According to the embodiment Figure 5 A first cross-sectional view of an extended EAM block;

[0016] Fig. 9 According to the embodiment Figure 5 a second cross-sectional view of an expanded EAM block;

[0017] Fig.10 A method for fabricating an extended EAM block using a wafer-level semiconductor approach according to an embodiment is shown;

[0018] Fig.11shows coupling of silicon on insulator (SOI) to a highly doped silicon wafer according to an embodiment, Fig.10 The method may include the coupling;

[0019] Fig.12 According to the embodiment, the Fig.11 A CMUT wafer formed by coupling an SOI wafer to a highly doped silicon wafer;

[0020] Fig.13 According to the embodiment Fig.12 Coupling of the CMUT wafer to the ASIC die; and

[0021] Fig.14 According to the embodiment, the Fig.10 The method forms the configuration of the extended EAM block. DETAILED DESCRIPTION

[0022] The following description relates to various embodiments of transducer probes (e.g., ultrasound probes), and more specifically, to methods for manufacturing CMUT arrays using a complementary metal oxide semiconductor (CMOS) approach. The methods described herein may allow for redistribution of input / output (I / O) connections of an electro-acoustic module (EAM) to achieve desired positioning and alignment of EAM components. The EAM may include a CMUT array coupled to an ASIC block or die, wherein the EAM may be fabricated using CMOS technology to achieve wafer-to-wafer bonding between the CMUT wafer and the CMOS wafer. The CMOS wafer may be cut and tiled to form an ASIC die with an extended footprint (e.g., an enlarged area).

[0023] EAMs can be used in ultrasound imaging systems (as one example, such as Figure 1 The EAM may include a plurality of CMUT cells, such as Figure 2 As shown, the plurality of CMUT cells may be combined into a CMUT array. Each CMUT array may be coupled to at least one ASIC block that may be cut from a wafer, wherein each pair of CMUT array and ASIC die forms an EAM block. In conventional systems, such as Figure 3 As shown, the ASIC wafer can be cut using dicing streets to form ASIC blocks, which are coupled to CMUT dies to form EAM blocks. In one example, as described herein, the dicing streets can be used to redistribute I / O connections by extending the ASIC die area to include the dicing streets, such as Figure 4 An ASIC die may be coupled to a CMUT array to form an EAM having I / O connection accessibility at its front side. Figure 5 and Figure 62 and 3 illustrate EAM blocks of an EAM with and without an interconnect circuit (such as a flexible circuit), respectively. Figure 7 The final configuration of the EAM is shown in . Figure 8 and Fig. 9 Depicted in Figure 5 and Figure 6 , illustrating direct coupling of a CMUT device to an ASIC, wherein no interposer, such as an interposer and / or a flex circuit, is arranged between the CMUT and the ASIC.

[0024] Fig.10 A method for fabricating an EAM via a wafer-level semiconductor approach is shown, and Figures 11 to 14 The steps involved in the method are illustrated. For example, the wafer-level approach may include semiconductor processing techniques such as bonding of a silicon-on-insulator (SOI) wafer to a highly doped silicon wafer, such as Fig.11 As shown, to form Fig.12 The CMUT chip depicted. The CMOS chip can be coupled to the CMUT chip, such as Fig.13 exemplified, and processed to form Fig.14 The extended EAM block shown.

[0025] As used herein, the term "image" refers broadly to both a visible image and data representing a visible image. However, many embodiments generate (or are configured to generate) at least one visible image. In addition, as used herein, the phrase "image" is used to refer to ultrasound modes, such as B-mode (2D mode), M-mode, three-dimensional (3D) mode, CF mode, PW Doppler, CW Doppler, MGD, and / or a sub-mode of B-mode and / or CF, such as shear wave elastography (SWEI), TVI, Angio, B-flow, BMI, BMI_Angio, and in some cases also includes MM, CM, TVD, wherein "image" and / or "plane" includes a single beam or multiple beams.

[0026] Furthermore, as used herein, the term processor or processing unit refers to any type of processing unit, whether single-core or multi-core: CPU, accelerated processing unit (APU), graphics board, DSP, FPGA, ASIC, or a combination thereof, that can perform the required computations required by various implementations.

[0027] Figure 1 is a block diagram of an exemplary ultrasound system that may be used for ultrasound imaging according to various embodiments. Figure 1, a block diagram of an exemplary ultrasound system 100 is shown. The ultrasound system 100 includes a transmitter 102, an ultrasound probe 104, a transmit beamformer 110, a receiver 118, a receive beamformer 120, an A / D converter 122, an RF processor 124, an RF / IQ buffer 126, a user input device 130, a signal processor 132, an image buffer 136, a display system 134, and an archive 138. The circuit 111 is a non-limiting example of a bias of a CMUT, and variations in the configuration of the circuit 111 are possible without departing from the scope of the present disclosure.

[0028] The transmitter 102 may include suitable logic, circuitry, interfaces, and / or code that may be operable to drive the ultrasound probe 104. The ultrasound probe 104 may include, for example, a single element CMUT, a 1D array of CMUTs, a 2D array of CMUTs, an annular (ring) array of CMUTs, and the like. Thus, the ultrasound probe 104 may include a set of transducer elements 106 that may be, for example, CMUTs. In certain embodiments, the ultrasound probe 104 may be operable to acquire ultrasound image data covering, for example, at least a majority of an anatomical structure, such as a heart, a blood vessel, or any suitable anatomical structure. Each of the transducer elements 106 may be referred to as a channel.

[0029] The transmit beamformer 110 may include suitable logic, circuitry, interfaces, and / or code operable to control the transmitter 102, which drives the set of transducer elements 106 to transmit ultrasound transmit signals into an area of ​​interest (e.g., a person, an animal, an underground cavity, a physical structure, etc.). The transmitted ultrasound signals may be backscattered from structures (such as blood cells or tissue) in the object of interest to produce echoes. The transducer elements 106 may then receive the echoes. For example, one or more drive circuits 111 may be coupled to and drive or control electrodes of each transducer element 106. For example, one or more drive circuits may be coupled to separate AC voltage sources and DC voltage sources.

[0030] The set of transducer elements 106 in the ultrasound probe 104 may be operable to convert the received echoes into analog signals and transmit to the receiver 118. The receiver 118 may comprise suitable logic, circuitry, interfaces, and / or code that may be operable to receive the signals from the ultrasound probe 104. The analog signals may be transmitted to one or more of the plurality of A / D converters 122.

[0031] Thus, the ultrasound system 100 may be multiplexed so that ultrasound transmit signals are transmitted during certain time periods and echoes of these ultrasound signals are received during other time periods. Although not explicitly shown, various embodiments of the present disclosure may allow for the transmission of ultrasound signals and the reception of echoes from these signals to be performed concurrently. In such cases, the probe may include a transmitting transducer element and a receiving transducer element.

[0032] The plurality of A / D converters 122 may include suitable logic components, circuits, interfaces, and / or codes that are operable to convert analog signals from the receiver 118 into corresponding digital signals. The plurality of A / D converters 122 are disposed between the receiver 118 and the RF processor 124. Nevertheless, the present disclosure is not limited in this regard. Therefore, in some embodiments, the plurality of A / D converters 122 may be integrated within the receiver 118.

[0033] The RF processor 124 may include suitable logic components, circuits, interfaces and / or codes that are operable to demodulate the digital signals output by the plurality of A / D converters 122. According to an embodiment, the RF processor 124 may include a complex demodulator (not shown) that is operable to demodulate the digital signals to form I / Q data pairs representing corresponding echo signals. The RF data (which may be, for example, I / Q signal data, real-valued RF data, etc.) may then be transmitted to the RF / IQ buffer 126. The RF / IQ buffer 126 may include suitable logic components, circuits, interfaces and / or codes that are operable to provide temporary storage of RF or I / Q signal data generated by the RF processor 124.

[0034] Thus, various embodiments may cause, for example, the RF processor 124 to process real-valued RF data or any other equivalent representation of the data with an appropriate RF buffer 126. The receive beamformer 120 may include suitable logic, circuitry, interfaces, and / or code that may be operable to perform digital beamforming processing to, for example, sum delayed channel signals, phase-shifted channel signals, and / or weighted channel signals received from the RF processor 124 via the RF / IQ buffer 126 and output a beam summed signal. The delayed channel data, phase-shifted channel data, and / or weighted channel data may be summed to form a scan line output from the receive beamformer 120, where the scan line may be, for example, complex-valued or non-complex-valued. The specific delay of the channel may be provided, for example, by the RF processor 124 or any other processor configured to perform this task. The delayed channel data, phase-shifted channel data, and / or weighted channel data may be referred to as delay-aligned channel data.

[0035] The resulting processed information may be a beam-summed signal output from the receive beamformer 120 and transmitted to the signal processor 132. According to some embodiments, the receiver 118, the plurality of A / D converters 122, the RF processor 124, and the beamformer 120 may be integrated into a single beamformer, which may be a digital beamformer. In various embodiments, the ultrasound system 100 may include a plurality of receive beamformers 120.

[0036] The user input device 130 may be used to input patient data, scan parameters, settings, select protocols and / or templates, etc. In an exemplary embodiment, the user input device 130 is operable to configure, manage, and / or control the operation of one or more components and / or modules in the ultrasound system 100. In this regard, the user input device 130 is operable to configure, manage, and / or control the operation of the transmitter 102, the ultrasound probe 104, the transmit beamformer 110, the receiver 118, the receive beamformer 120, the RF processor 124, the RF / IQ buffer 126, the user input device 130, the signal processor 132, the image buffer 136, the display system 134, and / or the archive 138. The user input device 130 may include switches, buttons, rotary encoders, touch screens, motion tracking, voice recognition, a mouse device, a keyboard, a camera, and / or any other device capable of receiving user guidance. In certain embodiments, for example, one or more of the user input devices 130 may be integrated into other components such as the display system 134 or the ultrasound probe 104. For example, user input device 130 may include a touch screen display.

[0037] The signal processor 132 may include suitable logic components, circuits, interfaces and / or codes that are operable to process ultrasound scan data (e.g., summed IQ signals) to generate ultrasound images for presentation on a display system 134. The signal processor 132 is operable to perform one or more processing operations based on a plurality of selectable ultrasound modalities on the acquired ultrasound scan data. In an exemplary embodiment, the signal processor 132 may be used to perform display processing and / or control processing, etc. The acquired ultrasound scan data may be processed in real time during a scanning session as echo signals are received. Additionally or alternatively, the ultrasound scan data may be temporarily stored in the RF / IQ buffer 126 during a scanning session and processed in an online operation or an offline operation. In various embodiments, the processed image data may be presented at the display system 134 and / or stored at the archive 138. The archive 138 may be a local archive, a picture archiving and communication system (PACS), or any suitable device for storing images and related information.

[0038] The signal processor 132 may include one or more central processing units, microprocessors, microcontrollers, etc. For example, the signal processor 132 may be an integrated component, or may be distributed in various locations. In an exemplary embodiment, the signal processor 132 may be capable of receiving input information from the user input device 130 and / or the archive 138, generating output that may be displayed by the display system 134, and manipulating the output in response to the input information from the user input device 130, etc. For example, the signal processor 132 may be capable of executing any of the methods and / or instruction sets discussed herein according to various embodiments.

[0039] The ultrasound system 100 is operable to continuously acquire ultrasound scan data at a frame rate suitable for the imaging situation under consideration. Typical frame rates may be in the range of 20 to 120, but may be lower or higher. The acquired ultrasound scan data may be displayed on the display system 134 at a display rate that is the same as the frame rate, or at a display rate that is slower or faster than the frame rate. An image buffer 136 is included to store processed frames of acquired ultrasound scan data that are not scheduled for immediate display. Preferably, the image buffer 136 has sufficient capacity to store frames of ultrasound scan data for at least several minutes. The frames of ultrasound scan data are stored in a manner that is easy to retrieve from them according to their acquisition order or time. The image buffer 136 may be embodied as any known data storage medium.

[0040] The display system 134 may be any device capable of conveying visual information to a user. For example, the display system 134 may include a liquid crystal display, a light emitting diode display, and / or any suitable one or more displays. The display system 134 may be operable to present an ultrasound image and / or any suitable information.

[0041] The archive 138 may be one or more computer-readable memories, such as a picture archiving and communication system (PACS), a server, a hard disk, a floppy disk, a CD, a CD-ROM, a DVD, a compact memory, a flash memory, a random access memory, a read-only memory, an electrically erasable and programmable read-only memory, and / or any suitable memory, that are integrated with the ultrasound system 100 and / or communicatively coupled (e.g., via a network) to the ultrasound system 100. The archive 138 may include, for example, a database, a library, a collection of information, or other memory that is accessed by and / or in conjunction with the signal processor 132. For example, the archive 138 may be capable of storing data temporarily or permanently. The archive 138 may be capable of storing medical image data, data generated by the signal processor 132, and / or instructions readable by the signal processor 132, etc.

[0042] The components of the ultrasound system 100 may be implemented in software, hardware, firmware, etc. The various components of the ultrasound system 100 are communicatively connected. The components of the ultrasound system 100 may be implemented separately and / or integrated in various forms. For example, the display system 134 and the user input device 130 may be integrated as a touch screen display. In addition, although the ultrasound system 100 is described as including a receive beamformer 120, an RF processor 124, and a signal processor 132, various embodiments of the present disclosure may use various numbers of processors. For example, various devices that execute code may generally be referred to as processors. Various embodiments may refer to each of these devices including each of the RF processor 124 and the signal processor 132 as a processor. In addition, there may be other processors to additionally perform the tasks described as being performed by these devices including the receive beamformer 120, the RF processor 124, and the signal processor 132, and for ease of description, all of these processors may be referred to as "processors".

[0043] As described above, the ultrasound probe may include an array of CMUTs that transmit or receive ultrasonic waves based on their electrostatic principles. Figure 2 An example of a CMUT cell 200 is depicted in FIG. A set of reference axes 201 including an x-axis, a y-axis, and a z-axis is provided. In one example, the z-axis may be parallel to the direction in which the acoustic signal is emitted. It should be understood that the CMUT cell 200 is a simplified representative implementation, and other examples may differ in configuration.

[0044] The CMUT cell 200 may be one CMUT cell in an array of CMUT cells that may be fabricated on a substrate 202, such as a heavily doped silicon wafer. For each CMUT cell 200, a thin membrane or diaphragm 204 is suspended above the substrate 202. The membrane 204 may be formed, for example, of silicon oxide, and may be supported on its periphery by an insulating support 206, which may be composed of silicon oxide or silicon nitride. A cavity 208 between the membrane 204 and the substrate 202 may be air or gas filled, or fully or partially evacuated. A film or layer of a conductive material, such as an aluminum alloy or another suitable conductive material, may form a first electrode 210 on the membrane 204. Another film or layer of a conductive material may form a second electrode 212 at the substrate 202. For example, the substrate 202 may be oxidized, and the second electrode 212 may be deposited along the outer surface of the substrate 202 and along the bottom of the CMUT cell 200 relative to the z-axis. Alternatively, the second electrode 212 may be formed by appropriate doping of the semiconductor substrate 202. By positioning the second electrode 212 at the bottom of the CMUT cell 200, outside the cavity 208, the second electrode 212 may be connected to an external circuit.

[0045] At least the first electrode 210 and the second electrode 212 separated by the cavity 208 can form a capacitor. When an impinging acoustic signal causes the diaphragm 204 to vibrate, the change in capacitance can be detected using electronics coupled to the CMUT cell 200. The acoustic signal can thereby be converted into an electrical signal, which can be transmitted to a device such as a CMUT cell 200 via a circuit coupled to the CMUT cell 200. Figure 1 Other electronic components of the imaging system shown. For example, the circuit can be at least one ASIC die, which can also be in the transducer probe (such as Figure 1 The probes 104 are arranged in an array.

[0046] The EAM of the ultrasound probe may include a CMUT array and an ASIC die. The ASIC die may have a configuration for coupling to the CMUT array that is specific to a given probe type, such as the size and positioning of the I / O connections and supply pads. The use of the ASIC die is thus limited to a given probe type and a corresponding CMUT array. Therefore, in order to use in any new (e.g., different) probe and CMUT array configuration, different ASIC dies need to be manufactured, which may require extended development time and high costs.

[0047] In order to broaden the use of a given ASIC die, for example, to allow the ASIC die to be used with more than one type of probe and CMUT array, an EAM can be made via a process that combines CMOS technology. For example, an ASIC die can be formed from a CMOS wafer and then bonded to a CMUT wafer to produce an EAM. This approach can allow the removal or exclusion of the cutting lanes of the CMOS wafer, thereby expanding the size of the ASIC die (hereinafter also referred to as an extended ASIC die). The extended ASIC die can make it possible to rearrange the I / O connections and bias connections to the front of the EAM through the CMUT wafer. As a result, the EAM can be manufactured via a low-cost scalable approach that achieves simplified and more accessible positioning of the I / O and bias connections. The systems and methods described herein also allow a given ASIC configuration to be used with a variety of CMUT arrays, thereby avoiding the need to make new ASIC dies for different probe types. A given ASIC die can thus be used for electrical coupling with more than one configuration of a CMUT array.

[0048] To illustrate the difference between conventional processing of an ASIC block for EAM and the formation of an extended ASIC die via wafer-level processing, Figure 3 A general configuration of an ASIC wafer 300 at an initial stage prior to dicing is depicted in FIG. Figure 4 The final configuration of the ASIC chip is depicted in Figure 3 300, which illustrates a plurality of contacts 301 distributed on the front side. Each of the plurality of contacts 301 may lead a CMUT cell of a monolithic CMUT die that is coupled to and stacked on an ASIC die or block 302 formed from the ASIC wafer 300. In one example, after processing to form the ASIC die 302, the ASIC wafer 300 may be coupled to a CMUT die that includes a transducer array through more than one interposer layer. For example, the transducer array may be coupled to an interposer flex (e.g., a flexible circuit), and the ASIC block 302 may be coupled to the ASIC flex. The flexes may be coupled to each other to provide electrical connectivity between the transducer array at the front side of the EAM and the ASIC die at the back side of the ASIC block 302. The complexity of the flexes may increase the overall cost of the EAM.

[0049] During fabrication, the ASIC wafer 300 may be double diced using first dicing streets 304 and second dicing streets 306 to form individual ASIC dies 302. The first dicing streets 304 may be parallel to the x-axis, and the second dicing streets 306 may be parallel to the y-axis. The dicing streets may remove unused areas 303 of the ASIC wafer, thereby separating and electrically isolating the ASIC dies 302 from each other.

[0050] After double dicing of the ASIC wafer 303 and removal of the first dicing street 304 and the second dicing street 306, the ASIC die 302 may be rearranged, such as Figure 4 As shown. The ASIC dies 302 may be positioned close to each other with a target minimum spacing therebetween. For example, a first distance 402 between the ASIC dies 302 along the y-axis may be 0.038 mm, and a second distance 404 between the ASIC dies 302 along the x-axis may be 0.013 mm.

[0051] The relative positioning of the ASIC die 302 and the stacking of the MEMS device (CMUT die) on top of the ASIC die 302 may make the I / O connections of the ASIC die 302 inaccessible from the front side of the EAM. The output I / O connections may be located at the outer perimeter 406 of the ASIC block 302 (and the EAM), and thus may be directed outward from the ASIC block 302. For example, for the I / O connections of the ASIC transferred to the top of the EAM via RDL, electrical interconnects may be formed via wire bonding, which may extend outward from the outer perimeter 406 of the EAM. The outer perimeter 406 of the EAM may be formed by an area of ​​the ASIC block 302 that extends beyond the perimeter 408 of a monolithic CMUT die that may be stacked on top of the EAM. Figure 4 The ASIC blocks are arranged on top.

[0052] In one example, an ASIC chip (e.g., Figure 3 The ASIC wafer 300 may be cut to redistribute the I / O connections and bias connections and make the I / O connections more accessible. For example, the size of the ASIC blocks 302 may be expanded in at least one direction (e.g., along the yx plane) by retaining at least one dicing street between the ASIC blocks 302. This may be accomplished by cutting the ASIC wafer separately along each of the y-axis and the x-axis rather than performing a double cut. The ASIC blocks 302 may be formed and separated without removing the ASIC blocks 302. Figure 3At least one of the first scribe line 304 and the second scribe line 306 of the ASIC block 302 may be removed. As an example, the first scribe line 304 may be retained while the second scribe line 306 may be removed. In other examples, both the first scribe line 304 and the second scribe line 306 may be at least partially retained. Thus, the usable area of ​​the ASIC block 302 may be expanded along at least the y-axis, and in some examples, along both the y-axis and the x-axis, without changing the arrangement of the plurality of contacts 301. In one example, the extended portion of the ASIC block may be used to incorporate a CMUT bias contact at the extended portion, which may otherwise be positioned around the outermost periphery of the CMUT die.

[0053] For example, ASIC block 302 may be expanded to have a footprint 410, such as Figure 4 The CMUT wafer can also be cut into dies with a size corresponding to the footprint 410 of the ASIC block 302. This can be achieved by making the EAM via a semiconductor approach, where the CMUT wafer is made according to the configuration of the CMOS wafer, as long as the acoustic requirements are met (i.e., the CMOS wafer is an ASIC wafer). The CMUT wafer and the CMOS wafer can be coupled to each other and then further processed to form a block of the EAM. Figures 5 to 14 Details of the EAM block and a semiconductor approach to fabricating the EAM block are provided.

[0054] As an example of an EAM with an extended die as described above, Figure 5 5 shows an extended EAM die 500 of an EAM in a top view showing details of a front side 501 of the extended EAM die 500, which is formed by the front-facing surface of the CMUT die. The extended EAM block 500 can be formed by singly dicing an EAM stack formed by a CMOS wafer coupled to a CMUT wafer to separate the EAM stack into EAM dies, each of which is formed by a CMUT die stacked on an ASIC die. The extended EAM die 500 is depicted before incorporating interconnect circuitry (such as a flex circuit) that can be added after the extended EAM die 500 is made to form the EAM.

[0055] The extended EAM die 500 includes an active area 502 formed by an array of transducers, wherein the transducers may be CMUT cells 504 (hereinafter referred to as CMUTs). Each CMUT in the CMUT 504 may be configured in a manner similar to, for example, Figure 2200. The extended EAM die 500 may also include an I / O region 506 including output contacts 508 and bias contacts 510. Thus, the bias contacts are redistributed to the I / O region 506, rather than being arranged around the outer periphery of the active area of ​​the CMUT die having a conventional arrangement. The bias contacts 510 may be electrically coupled to a bias metal plate 511 extending across the extended EAM die 500 along the x-axis near the upper edge (relative to the y-axis) of the extended EAM die 500. An optional bias via may extend through the CMUT die housing the CMUT 504 below the bias metal plate 511 relative to the z-axis to couple the bias metal plate 511 to a bias plane located at the underside of the CMUT wafer. Output contacts 508 may enable electrical signals to be transmitted from the extended EAM die 500 to other electrical components of the imaging system, while bias contacts 510 may allow a bias voltage to be applied to the CMUT cell 504. The I / O region 506 may form a region at the front side of the CMUT die along the x-axis adjacent to (e.g., near or beside) the active region 502. Furthermore, when multiple EAM dies are arranged to form a block, the I / O region 506 may be located along the periphery or outer edge of the EAM relative to the x-axis.

[0056] Compared to the I / O area, the active area 502 may occupy a larger area of ​​the extended EAM die 500. In one example, the active area 502 may include 50 columns (e.g., such as aligned along the y-axis) of CMUTs 504, while the I / O area 506 may include at least 4 columns (e.g., such as aligned along the y-axis). Figure 6 ) output contact 508. By relative Figure 3 and Figure 4 By extending the size of the extended EAM die 500 with the ASIC die 302, the output contacts 508 can be redistributed in the I / O region 506 to the front side 501 of the extended EAM die 500 (e.g., at the front-facing surface of the CMUT die), rather than being located at the outer periphery of the ASIC block that extends beyond the periphery of the monolithic CMUT die in a conventional EAM arrangement (e.g., Figure 4 In addition, the CMUT wafer can be directly coupled to the ASIC wafer without arranging one or more components therebetween to provide electrical continuity.

[0057] like Figure 6 As illustrated, when fabrication of the extended EAM die 500 is complete, a passivation layer may be added to the active area 502 of the extended EAM die 500, and the Figure 6The flex 602, partially shown in FIG. 5 , is coupled to the front side 501 of the extended EAM die 500 (and the CMUT die) across the I / O region 506. The flex 602 may be a flexible circuit that provides electrical connectivity from the extended EAM die 500 to other electrical devices and components. Thus, the flex 602 may be directly coupled to the bias contacts 510 and the output contacts 508 to transmit electrical signals to and from the I / O region.

[0058] Figure 7 An example of an EAM 700 is shown in FIG. Figure 6 5. The EAM 700 of the embodiment of the present invention is composed of four replicas 706, 708, 710 and 712 of the extended EAM die 500. The four replicas can have two different designs. In the first design, the biasing contact can be included in the replicas 708 and 710. In the second design, the biasing contact can be included in the replicas 706 and 712. On opposite sides of the EAM 700, the flexible member 602 can be coupled to the EAM 700 along the I / O area of ​​each extended EAM die 500. In one example, the total width 702 of the EAM 700 along the x-axis can be 25.8 mm, and the total height 704 of the EAM 700 along the y-axis can be 16.3 mm.

[0059] like Figure 6 As illustrated, in one example, each extended EAM die 500 may have a width 604 of 12.9 mm and a height 606 of 8.13 mm. The sub-width 608 of the I / O region 506 may be at least 1 mm, and may provide a gap distance 610 between the inner edge of the flex 602 and the outer perimeter of the CMUT 504. Due to the expansion of the area of ​​the ASIC die, the presence of the gap distance 610, which may be between 0.2 mm and 0.9 mm, and in the depicted example is 0.64 mm, may be achieved, and during attachment of the flex 602 to the extended EAM block 500, the gap distance 610 mitigates the oozing of organic material of the flex 602 into the CMUT 504.

[0060] Figure 8 and Fig. 9 A simplified cross-sectional view of an extended EAM is shown in FIG. Figure 8 Depicted along the Figure 5 The first cross section is obtained along the line AA', and Fig. 9 Depicted along the Figure 5The cross-sectional view is simplified in that a representative abbreviated number of CMUT cells 504 and output contacts 508 are shown, and some layers of the extended EAM block 500, such as metal layers and passivation layers, are omitted for simplicity. The extended EAM die 500 can be formed by a CMUT die 802 arranged above and coupled to an ASIC block 804 relative to the z-axis. For clarity, the CMUT die 802 and the ASIC block 804 are shown in FIG. Figure 8 and Fig. 9 5. They are shown as being spaced apart in FIG. 5, but are in contact with each other when fabrication of the extended EAM die 500 is completed.

[0061] In addition, although Figures 8 to 9 The x- and y-axes are roughly to scale, but Figures 8 to 9 The first cross-section and the second cross-section are not drawn to scale along the z-axis. By making the EAM die via a semiconductor approach described further below, the thickness of the EAM can be reduced relative to a conventional EAM configuration in which the CMUT wafer and the ASIC wafer are processed and cut separately. For example, the CMUT wafer of a conventional EAM configuration can be 300μm to 400μm thick (as defined along the z-axis), and the ASIC wafer can have a similar thickness. In the embodiment of the extended EAM block shown and described herein, the CMUT wafer can be thinner, having a thickness of, for example, 30μm, while the CMOS wafer from which the ASIC block is formed can be 300μm to 400μm thick. Therefore, Figure 8 and Fig. 9 The CMUT wafer 802 is shown thicker than shown to scale in order to more clearly depict its features.

[0062] like Figure 8 As shown, the first cross section includes an active area 502 separated by a gap distance 610 from an I / O region 506. The perimeter of the extended EAM 500 along the x-axis (as defined by cutting along the zy plane) is indicated by dashed line 806. Also indicated is an extended region 808 of the extended EAM die 500 relative to the width of a conventional EAM block.

[0063] In the active area 502, the CMUT cells 504 may be located at an upper surface (relative to the z-axis) of the CMUT die 802, which is disposed at a front surface of the EAM 700. A front surface metal 810 may be deposited over each of the CMUTs 504, which may be electrically coupled to a bottom surface contact 812 of each of the CMUTs 504 by a conductive via 814. The conductive via 814 may be formed by an insulating layer 814a surrounding a conductive core 814b, and may extend through a silicon substrate of the CMUT die 802. An oxide layer 816 of the CMUT die 802 may be etched to provide contact between a conductive core 814b of the conductive via 814 and the CMUT 504, and between a conductive core 814b of the conductive via 814 and a bottom surface contact 812 of the CMUT 504. A patterned metallization layer 818 may be deposited between the conductive core 814b and the bottom surface contact 812a at the bottom surface (relative to the z-axis) of the CMUT die 802, which may enable electrical energy to be transferred between the conductive core 814b and the bottom surface contact 812a. Thus, the conductive via 814b may extend through at least a portion of the thickness (as defined along the z-axis) of the CMUT die 802 to connect the front side metal 810 to the bottom surface contact 812 for each of the CMUT cells 504.

[0064] The bottom surface contacts 812 may protrude from the bottom surface of the CMUT die 802 and may be offset along the z-axis from the CMUT 504 to which the corresponding bottom surface contact 812 is electrically coupled. The bottom surface of the CMUT die 802 may also include a bias plane 821 disposed between the bottom surface contacts 812. The bias plane 821 may be electrically coupled to a bias contact (e.g., Fig. 9 The biasing contact 910 or Figure 5 and Figure 6 The biasing plane 821 may optionally be coupled to the biasing contact 510 by a through hole.

[0065] The bottom surface contact 812 of each CMUT cell in the CMUT cell 504 may be arranged to be in coplanar contact with the corresponding ASIC pad 820 of the ASIC block 804. The ASIC pad 820 may include a metal contact 820a and a metal layer 820b for wafer-to-wafer bonding. In one embodiment, the metal contact 820a may be composed of gold, eventually having a metal barrier layer analog between 820a and 820b, and the metal layer 820b may be composed of aluminum. Therefore, the bottom surface contact 812 of each CMUT in the CMUT 504 is in direct contact with the corresponding ASIC pad 820 of the ASIC block 804, and no other components or layers are arranged therebetween. As a result, the distance between the CMUT 504 and the ASIC block 804 is minimized, which reduces the loss caused during the signal transmission between the CMUT cell 504 and the ASIC contact 820, and reduces the number of components of the extended EAM die 500, and thus reduces the cost of the extended EAM die.

[0066] The upper surface of the CMUT die 802 does not include any CMUT cells 504 along the gap distance 610 and the I / O region 506. In the I / O region 506, the output contacts 508 each include an upper RDL 508a and a lower RDL 508b, wherein the upper RDL 508a and the lower RDL 508b are electrically coupled by a conductive via 814. One or more interface contacts 822 arranged at the bottom surface of the CMUT die 802 in the I / O region 506 may be electrically coupled to each of the output contacts 508 through the upper and lower RDLs 508a, 508b and the conductive via 814b.

[0067] The columns of output contacts 508 adjacent and near the gap distance 610 (e.g., as defined along the y-axis) can have a lower RDL 508 b that is elongated to extend along both the x-axis and the y-axis toward the active area 502. Each of the output contacts 508 in the columns near the gap distance 610 can be electrically coupled to both the interface contact 822 located directly below the corresponding output contact 508 and the additional interface contact 822 located in the gap distance 610.

[0068] Each of the interface contacts 822 can be in coplanar contact with the ASIC pad 820 aligned therewith along the z-axis. By extending the EAM block 500 along the x-axis by the extension region 808, the output contacts 508 can be positioned in the I / O region 506 at the upper surface of the CMUT die 802, thereby allowing the output contacts 508 to be reached at the front surface of the EAM 700, rather than being directed outward from the EAM along the outer periphery of the EAM 700 by, for example, wire bonds. As described above, the EAM die 500 can also be extended along the y-axis, such as Fig. 9 Indicated by the second cross-section.

[0069] The CMOS wafer may be cut along the yx plane, as indicated by dashed lines 902, to form extended EAM dies 500, which may have an extended area 904 extended relative to a conventional ASIC die. The extended EAM die 500 may optionally be further cut, as indicated by dashed lines 906, which removes dummy contacts 908 from the EAM block 500 and reduces the footprint of the EAM 500 along the y-axis. It should be understood that the EAM die 500 may also include some contacts 908 located near the edge of the EAM block 500 along the x-axis, as shown in FIG. Fig. 9 As an example, a reduced footprint of EAM 500 may be desirable for intercostal applications.

[0070] In other examples, the CMUT die 802 may include more or less than one dummy contact 908 along the y-axis, depending on the output contacts (e.g., Figures 5 and 6 The desired number of columns of output contacts 508 of the ASIC pads can be determined by configuring the CMUT wafer with dummy contacts. Therefore, by configuring the CMUT wafer with dummy contacts, the number of columns of output contacts (and dummy contacts) of the CMUT die in the I / O region can be different from the number of columns of ASIC pads. Thus, the CMUT wafer can be easily adapted to be coupled to an ASIC block regardless of the desired number of columns of output contacts on the EAM block.

[0071] As described above, the bottom surface contacts 812 of the CMUT die 802 may be in coplanar contact with the ASIC pads 820. The CMUT die 802 may also include biasing contacts 910. The biasing contacts 910 may enable the plane 821 of the CMUT cell 504 to be polarized through the front surface of the EAM die 500.

[0072] An EAM formed by extending an EAM die, such as Figures 5 to 9 The expansion of EAM block 500 can be achieved through Fig.10 The method 1000 depicted is fabricated by the method 1000. The method 1000 may be performed by a technician, by an automated system, or by a combination of both in conjunction with various manufacturing equipment and devices. In the method 1000, the EAM may be fabricated as a MEMS device. Figures 11 to 14 The processes described in method 1000 are illustrated in the figures, which are described in conjunction with the discussion of method 1000. It should be understood that method 1000 is a non-limiting example of how an EAM can be made. Other techniques and / or variations in the processes and / or order of processes detailed in method 1000 are possible without departing from the scope of the present disclosure.

[0073] Method 1000 includes partial fabrication of a CMUT wafer (1002-1014) and preparation of an ASIC die (1016-1022), which may or may not occur concurrently. For example, fabrication of the CMUT wafer and preparation of the ASIC wafer may be processes that are performed independently of each other. Thus, the processes may be performed according to any timing relative to each other. For example, the CMUT wafer may be fabricated before preparation of the ASIC wafer, or the ASIC wafer may be prepared before fabrication of the CMUT wafer. For another example, the CMUT wafer may be fabricated while the ASIC wafer is being prepared.

[0074] At 1002, method 1000 includes partially fabricating a CMUT wafer, which may be a MEMS wafer. The CMUT wafer may be partially fabricated in that the CMUT wafer may be thinned and top contacts may be fabricated in a second, later portion of fabrication of the CMUT wafer. The CMUT die may have a size corresponding to a specified (e.g., an existing ASIC die cut from a CMOS wafer), or the size of the CMUT die may correspond to a tiled configuration of the ASIC die. The EAM block formed by the CMUT die and the ASIC die may have an extended footprint along at least one dimension across the plane of the EAM block relative to a conventional EAM block, wherein the ASIC die of the conventional EAM block may be double cut using a dicing street that is subsequently removed. The CMUT wafer may be fabricated to have a spacing corresponding to the spacing of the ASIC pads of the ASIC die.

[0075] At 1004, fabricating the CMUT wafer includes oxidizing a first wafer, which may be a SOI (silicon on insulator) wafer. The first wafer may have a controlled target thickness and may be used as a handle during fabrication of the EAM until the thickness of the first wafer is reduced, as further described below. Fig.11 An example of an SOI wafer 1100 that can be used to fabricate a CMUT wafer in method 1000 is illustrated in FIG.

[0076] refer to Fig.11 , the SOI wafer 1100 may have a thickness 1106, including an embedded silicon oxide layer 1104 having a controlled target thickness and a highly doped silicon layer 1108 having a controlled thickness below the oxide layer 1104 relative to the z-axis. The SOI wafer 1100 may have an outer silicon oxide layer 1102 extending along the upper surface and the lower surface (relative to the z-axis), which may be formed during oxidation of the SOI wafer 1100 at 1004 of the method 1000.

[0077] Back to Fig.10At 1006 of method 1000, the second highly doped silicon wafer can be processed by forming a conductive via extending into the thickness of the second highly doped silicon wafer. Processing the second silicon wafer to form the conductive via at 1006 can occur concurrently with oxidizing the first wafer, before oxidizing the first wafer, or after oxidizing the first wafer. For example, the conductive via can be formed using deep reactive ion etching (DRIE) to create a trench extending vertically (along the z-axis) into the highly doped silicon wafer. The trench can be a blind trench extending into a portion of the thickness of the second silicon wafer, such as Fig.11 As shown, or it may be a through trench extending through the entire thickness of the second silicon wafer.

[0078] Forming the conductive vias may include oxidation and via filling with an insulator in the trenches formed in the second silicon wafer by DRIE. The layer may be deposited in the trenches by, for example, physical vapor deposition (PVD). After, for example, oxidation of the second silicon wafer at 1008, growth of the seed layer may then be promoted to fill the trenches. However, in other examples, the conductive via trenches may be formed at a later point during the fabrication of the CMUT wafers, or as a finishing step in the fabrication of the CMUT wafers.

[0079] At 1008, method 1000 includes oxidizing the second highly doped silicon wafer and filling the trench of the conductive via with an insulating material to form the conductive via. Furthermore, at 1008, an additional oxide layer may be deposited by physical vapor deposition (PECVD), and a cavity may be formed at a surface of the oxidized second silicon wafer (such as at an upper surface of the second silicon wafer interfacing with the first wafer). The cavity may be formed according to known techniques for forming a cavity of a CMUT cell. Fig.11 An example of a highly doped silicon wafer 1110 is illustrated in FIG. 1 after creating conductive vias, oxidation, and cavity formation.

[0080] Fig.11 The highly doped silicon wafer 1110 may have a standard thickness 1112 of, for example, 400 μm. The upper surface (relative to the z-axis) of the highly doped silicon wafer 1110 may include a cavity 1114 formed at 1006 of the method 1000 as described above. The highly doped silicon wafer 1110 may have an outer silicon oxide layer 1116 extending across the upper and lower surfaces of the highly doped silicon wafer 1110, and the cavity 1114 may be disposed in the outer silicon oxide layer 1116 at the upper surface. In addition, the highly doped silicon wafer 1110 may have a conductive via 1118 extending from the upper surface of the highly doped silicon wafer 1110 into a portion of the thickness 1112 of the highly doped silicon wafer 1110.

[0081] Return to Fig.10At 1010, method 1000 includes bonding a first SOI wafer and a second highly doped silicon wafer to each other. For example, the first wafer and the second silicon wafer may undergo oxide-oxide melt bonding and melt bonding annealing to adhere the wafers to each other. In one example, the melt bonding annealing may be performed at a temperature greater than 1000°C.

[0082] At 1012, the thickness of the second silicon wafer can be reduced by grinding the bottom of the second silicon wafer. The amount of the second highly doped silicon wafer removed can be the amount of the end of the exposed conductive via. For example, 370 μm can be removed from the thickness of the second silicon wafer. After grinding, the bottom surface can be processed by depositing a layer at the bottom surface of the second silicon wafer at 1014. The layer may include a first passivation layer in contact with the end of the conductive via, wherein the passivation layer may be patterned after deposition. The layer may also include a metal layer that is also patterned after deposition, and an optional second passivation layer. A bottom contact can then be formed at the bottom surface of the second silicon wafer. For example, the bottom contact may include a first aluminum layer and a thicker second gold layer. A barrier layer such as nickel, titanium tungstate or titanium nitride may be included between the first and second layers to inhibit the mutual diffusion of metals during wafer-to-wafer bonding. In addition, a dummy contact may be formed to provide mechanical support for the extended EAM die along the extended peripheral area of ​​the EAM block. Additionally, biasing components, such as biasing contacts and biasing planes, may be formed at 1014 .

[0083] Fig.12 1000 according to 1002-1014 of method 1000. CMUT wafer 1200 is composed of SOI wafer 1100 bonded to highly doped silicon wafer 1110 such that the bottom surface of SOI wafer 1100 is in coplanar contact with and bonded to the upper surface of highly doped silicon wafer 1110. Cavity 1114 may be enclosed within silicon oxide layers 1102 and 1116 of the wafer.

[0084] The thickness 1106 of the SOI wafer 1100 is relative to Fig.11The thickness 1112 of the highly doped silicon wafer 1110 is unchanged, but reduced, so that the conductive vias 1118 extend through the entire thickness 1112 of the highly doped silicon wafer 1110. At the bottom surface of the highly doped silicon wafer 1110, the CMUT wafer 1200 may include at least one patterned passivation layer 1202 formed of an inert material, such as a metal oxide or nitride. The bottom surface may also include: a metal layer 1204, which is used to provide electrical continuity from the upper surface to the bottom surface of the highly doped silicon wafer 1110 through the conductive vias 1118; and a bias plane 1206, which is used to deliver a bias voltage to the CMUT cells to be formed in the CMUT wafer 1200. The metal layer 1204 and the bias plane 1206 may each be in direct contact with one of the conductive vias 1118. Similar to Figures 8 to 9 The bottom contact 812 may form a bottom contact 1208 below the passivation layer 1202 (relative to the z-axis).

[0085] Back to Fig.10 At 1016 of method 1000, the ASIC wafer may be prepared for coupling to the CMUT wafer to form an EAM wafer. At 1018, preparing the ASIC wafer includes depositing at least one passivation layer and flattening the surface of the ASIC wafer. For example, the passivation layer may be deposited by plasma enhanced chemical vapor deposition (PECVD), and the deposited passivation layer may be flattened using chemical mechanical polishing (CMP). At 1020 of method 1000, the passivation layer is etched to provide access to the ASIC pads of the ASIC die, which may be covered by the passivation layer during the deposition of the passivation layer.

[0086] At 1022, preparing the ASIC wafer also includes depositing a metal onto the passivated and flattened upper surface of the ASIC wafer. The metal may be selected based on the desired interaction of the metal with the bottom surface contacts of the CMUT wafer for bonding therebetween. For example, a metal adhesion layer may be applied first, followed by a metal seed layer. In one example, the metal adhesion layer may be titanium, titanium tungsten alloy, titanium nitride, or a combination thereof, and the metal seed layer may be gold, which may be deposited by sputtering. The metal seed layer may form ASIC contacts, for example, Figures 8 to 9 A dummy contact (e.g., Fig.13 Dummy contacts 1312 are depicted to provide a plurality of dummy contacts 1312 for use in I / O areas such as Figures 5 and 6 The CMUT die is mechanically supported in the I / O region 506 of the Fig.13 shown.

[0087] Fig.131016-1022 of method 1000 for bonding to CMUT wafer 1200 is illustrated. An upper surface (relative to the z-axis) of ASIC wafer 1300 may include a first passivation layer 1302 and a second passivation layer 1304 stacked on the first passivation layer 1302, wherein the second passivation layer 1304 may be an optional layer. ASIC pads 1306 of ASIC die 1300 may include a metal adhesion layer 1308 and metal contacts 1310 formed of a seed metal. Dummy contacts 1312 may also be included at the upper surface of ASIC die 1300 along the periphery of ASIC die 1300.

[0088] Return to Fig.10 , method 1000 includes bonding the CMUT wafer and the ASIC wafer to each other to form an EAM wafer at 1024. For example, gold-gold thermocompression bonding can be used to adhere the bottom surface contacts of the CMUT wafer to the metal contacts of the ASIC wafer. Fig.13 As shown, the bottom surface contacts 1208 of the CMUT wafer 1200 may be placed in coplanar contact with the metal contacts 1310 of the ASIC wafer 1300 and bonded to each other.

[0089] At 1026 of method 1000, the second highly doped silicon layer (eg, Figures 11 to 13 The thickness of the first SOI wafer is thinned by forming a highly doped silicon layer 1108 of the present invention, and then the oxide layer is etched to form a diaphragm (e.g., a CMUT diaphragm) above the cavity. The front side of the EAM is metallized by depositing a metal (such as aluminum or an aluminum alloy) over the diaphragm. The metal can be patterned to provide electrical contact between the diaphragm and the conductive vias. At 1028, a passivation layer is deposited over the metal and patterned. In addition, at 1028, output contacts and bias contacts, such as , are formed at the front side of the EAM. Figure 5 The output contacts 508 and the bias contacts 510 of the probe are provided. At 1030 of the method 1000, the EAMs are arranged relative to other EAM blocks according to a desired array of EAMs of the probe.

[0090] Fig.14 The final configuration of the extended EAM 1400 is illustrated in FIG. Figure 12 to Figure 13 The CMUT wafer 1200 is bonded to Fig.13 The thickness 1106 of the first SOI wafer 1100 is relative to Figures 11 to 13 The diaphragm 1402 may be formed by a highly doped silicon layer 1108 (e.g., Figure 11 to Figure 31400) is formed over cavity 1114. Metal layer 1406 may be deposited over diaphragm 1402 and may make contact with metal contacts 1410 of conductive vias 1412 of extended EAM 1400. Bias contacts 1408 may be formed over dummy contacts 1312 of ASIC die 1300 relative to the z-axis. The formation of output contacts and bias contacts is thus defined based on the final passivation of the EAM, and the positioning of the output contacts and bias contacts along the periphery of the EAM allows them to be compatible with attachment of flexible circuits.

[0091] In this way, a reproducible and scalable process can be used to reduce the development time and cost for making EAM. The process includes preparing a MEMS wafer (e.g., a CMUT wafer) and a CMOS wafer (e.g., an ASIC wafer) for bonding to each other to form an extended EAM block. The extended EAM block can be arranged into an array of EAMs for the probe, and compared with an EAM block configured with an ASIC common to the extended EAM block but cut in a conventional manner, the extended EAM block can have an extended area. By extending the area of ​​the extended EAM block, an I / O area can be set along the periphery of the positive side of the EAM block adjacent to the active area of ​​the EAM block, wherein the output contact and the bias contact are positioned in the active area. The output contact and the bias contact can be redistributed from the upper surface of the ASIC die where the access to the output contact and the bias contact may originally be constrained. The extended EAM block can be made at the wafer level, making it possible to utilize a cost-effective high-capacity manufacturing approach that relies on known wafer-to-wafer bonding technology and does not require the imposition of additional manufacturing steps for manufacturing MEMS devices. Furthermore, the number of output contacts at the front side of the EAM block may be independent of the number of ASIC pads in the I / O area.

[0092] Figures 2 to 9 and Figures 11 to 14An example configuration with relative positioning of various parts is shown. In at least one example, if shown as directly contacting or directly coupling each other, such elements may be referred to as directly contacting or directly coupling, respectively. Similarly, in at least one example, elements shown as being adjacent or adjacent to each other may be adjacent or adjacent to each other, respectively. For example, parts placed in coplanar contact with each other may be referred to as being in coplanar contact. For another example, in at least one example, elements positioned to be spaced apart from each other and having only space therebetween without other parts may be described and quoted as such. For another example, elements shown as being located above / below each other, located on opposite sides of each other, or located on the left / right side of each other may be described and quoted as such relative to each other. In addition, as shown in the figure, in at least one example, the topmost element or the point of the element may be referred to as the "top" of the part, and the bottommost element or the point of the element may be referred to as the "bottom" of the part. As used herein, top / bottom, upper / lower, above / below may be relative to the vertical axis of the figure, and may be used to describe the positioning of the elements in the figure relative to each other. Thus, in one example, elements shown as being above other elements are positioned vertically above other elements. For another example, the shapes of the elements depicted in the figures may be referred to as having those shapes (e.g., such as being round, straight, planar, curved, rounded, chamfered, angled, etc.). In addition, in at least one example, elements shown as intersecting each other may be referred to as intersecting elements or intersecting each other. In addition, in one example, elements shown as being within another element or being shown as being outside another element may be described and referenced as such. Figures 3 to 7 Shown approximately to scale.

[0093] As used herein, the elements or steps listed in the singular and beginning with the word "one" or "a kind of" should be understood as not excluding a plurality of said elements or steps, unless such exclusion is explicitly stated. In addition, reference to "an embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also include the described features. In addition, unless explicitly stated to the contrary, "comprising", "including" or "having" an embodiment of an element or multiple elements with a specific characteristic may include additional such elements that do not have the characteristic. The terms "including" and "in..." are used as the concise language equivalents of the corresponding terms "including" and "wherein". In addition, the terms "first", "second" and "third" etc. are only used as marks, and are not intended to impose numerical requirements or specific positional order on their objects.

[0094] The present disclosure also provides support for an ultrasound probe, the ultrasound probe comprising an electro-acoustic module, the electro-acoustic module being formed by a micro-electromechanical system (MEMS) wafer bonded to a complementary metal oxide semiconductor (CMOS) wafer as an application specific integrated circuit (ASIC), and having a front side formed by a surface of the MEMS wafer, the surface of the MEMS wafer comprising an active area of ​​a capacitive micro-machined ultrasonic transducer (CMUT) unit and an input / output (I / O) region of input and output contacts of the ASIC, the (I / O) region being arranged adjacent to the active area, the input and output contacts being redistributed to the surface of the MEMS wafer. In a first example of the system, the CMOS wafer is cut in no more than one direction to form an ASIC die, and wherein the size of the MEMS wafer along the plane of the MEMS wafer is equal to the size of the CMOS wafer along the plane of the CMOS wafer. In a second example of the system, optionally including the first example, on opposite sides of the active area, the I / O region is positioned along the periphery of the electro-acoustic module, and wherein the I / O region also includes CMUT bias contacts. In a third example of the system, optionally including one or both of the first and second examples, the I / O area is configured to be coupled to an interconnection circuit extending away from the active area. In a fourth example of the system, optionally including one or more or each of the first to third examples, a gap distance is set between the active area and the I / O area, and no CMUT unit or output contact is positioned in the gap distance. In a fifth example of the system, optionally including one or more or each of the first to fourth examples, the I / O area also includes a dummy contact located at the lower side of the MEMS wafer and the upper surface of the CMOS wafer, and the dummy contact is configured to provide mechanical support to the electro-acoustic module along the periphery of the electro-acoustic module. In a sixth example of the system, optionally including one or more or each of the first to fifth examples, the MEMS wafer is directly coupled to the CMOS wafer without an insert or flexible circuit arranged therebetween. In a seventh example of the system, optionally including one or more or each of the first to sixth examples, a thickness of the MEMS wafer is less than a thickness of the CMOS wafer.

[0095] The present disclosure also provides support for a method comprising: making a capacitive micromachined ultrasonic transducer (CMUT) wafer having bottom contacts configured to mate with pads of an ASIC die; coupling the CMUT wafer to the ASIC die to form an electroacoustic module (EAM) stack having output contacts at the front of the CMUT wafer; and cutting the EAM stack along no more than one axis across the plane of the EAM stack to form an EAM block. In a first example of the method, making the CMUT wafer comprises bonding a silicon-on-insulator (SOI) wafer to a highly doped silicon wafer, the SOI wafer having an embedded silicon oxide layer and a highly doped silicon layer, and the highly doped silicon wafer having a cavity etched into the silicon oxide layer of the highly doped silicon wafer. In a second example of the method, optionally including the first example, making the CMUT wafer comprises: forming a trench through at least a portion of the thickness of the highly doped silicon wafer, and filling the trench to form a conductive via. In a third example of the method, optionally including one or both of the first and second examples, after bonding the SOI wafer and the highly doped silicon wafer to each other, reducing the thickness of the highly doped silicon wafer to expose the end of the conductive via at the bottom surface of the highly doped silicon wafer, and depositing a plurality of layers at the bottom surface and patterning the plurality of layers, the plurality of layers including at least one passivation layer, a bias plane, and a metal layer. In a fourth example of the method, optionally including one or more or each of the first to third examples, after depositing the plurality of layers and patterning the plurality of layers, forming a metal contact at the bottom surface of the highly doped silicon wafer. In a fifth example of the method, optionally including one or more or each of the first to fourth examples, the method further includes: before coupling to the CMUT wafer, preparing the ASIC wafer by depositing a passivation layer on the upper surface of the ASIC die and flattening the upper surface, the upper surface including an ASIC pad. In a sixth example of the method, optionally including one or more or each of the first to fifth examples, the method further includes: before coupling the CMUT wafer to the ASIC wafer, etching the passivation layer to provide access to the ASIC pad. In a seventh example of the method, optionally including one or more or each of the first to sixth examples, the CMUT wafer is bonded to the ASIC wafer by gold-to-gold thermocompression bonding. In an eighth example of the method, optionally including one or more or each of the first to seventh examples, the method further includes: reducing the thickness of the EAM to form a CMUT diaphragm at the front face of the EAM, forming an output contact and a bias contact on the front face, and optionally, depositing a passivation layer on the front face.

[0096] The present disclosure also provides support for an electro-acoustic module (EAM), the EAM comprising a plurality of blocks, each block comprising: an array of capacitive micromachined ultrasonic transducers (CMUTs), an application specific integrated circuit (ASIC) disposed below and electrically coupled to the array of CMUTs, and output contacts positioned along the periphery of the respective block and adjacent to the array of CMUTs at the front face of the block. In a first example of the system, the output contacts are disposed in an input / output (I / O) region adjacent to the array of CMUTs, and wherein the number of columns of the output contacts is not equal to the number of columns of ASIC pads of the ASIC in the I / O region. In a second example of the system, optionally including the first example, the ASIC is compatible with electrical coupling to more than one configuration of the array of CMUTs.

[0097] This written description uses examples to disclose the invention, including the best mode, and also to enable a person of ordinary skill in the relevant art to practice the invention, including making and using any devices or systems and performing any included methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to a person of ordinary skill in the art. Such other examples are intended to fall within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insignificant differences from the literal language of the claims.

Claims

1. An ultrasound probe (104), comprising: An electroacoustic module is formed by a microelectromechanical system (MEMS) wafer (1200) bonded to a complementary metal oxide semiconductor (CMOS) wafer (1300) as an application specific integrated circuit (ASIC), and has a front side (501) formed by a surface of the MEMS wafer (1200), the surface of the MEMS wafer (1200) including an active area (502) of a capacitive micromachined ultrasonic transducer (CMUT) unit (504) and an input / output (I / O) area (506) of input and output contacts (508) of the ASIC, the input / output (I / O) area being arranged adjacent to the active area (502), the input and output contacts being redistributed to the surface of the MEMS wafer (1200).

2. The probe according to claim 1, wherein the CMOS wafer (1300) is cut in no more than one direction to form an ASIC die, and wherein the size of the MEMS wafer (1200) along the plane of the MEMS wafer (1200) is equal to the size of the CMOS wafer (1300) along the plane of the CMOS wafer (1300).

3. The probe of claim 1 , wherein the I / O regions ( 506 ) are located along a periphery of the electro-acoustic module on opposite sides of the active area ( 502 ), and wherein the I / O regions ( 506 ) further include CMUT bias contacts.

4. The probe of claim 1, wherein the I / O region (506) is configured to couple to interconnect circuitry extending away from the active area (502).

5. The probe head according to claim 4, wherein a gap distance is provided between the active area (502) and the I / O region (506), and wherein no CMUT cell (504) or output contact (508) is positioned in the gap distance.

6. The probe according to claim 1, wherein the I / O area (506) further includes dummy contacts located at the lower side of the MEMS wafer (1200) and the upper surface of the CMOS wafer (1300), and the dummy contacts are configured to provide mechanical support to the electro-acoustic module along the periphery of the electro-acoustic module.

7. The probe according to claim 1, wherein the MEMS wafer (1200) is directly coupled to the CMOS wafer (1300) without an interposer or a flexible circuit disposed therebetween.

8. The probe according to claim 1, wherein the thickness of the MEMS wafer (1200) is smaller than the thickness of the CMOS wafer (1300).

9. A method comprising: Fabricating a capacitive micromachined ultrasonic transducer (CMUT) wafer having bottom surface contacts (1002) configured to mate with pads of an ASIC wafer; coupling the CMUT wafer to the ASIC wafer to form an electro-acoustic module (EAM) stacked wafer (1024) having output contacts at a front side of the CMUT wafer; as well as The EAM stack wafer is cut along no more than one axis across the plane of the EAM stack to form EAM blocks.

10. The method of claim 9, wherein fabricating the CMUT wafer comprises bonding a silicon-on-insulator (SOI) wafer to a highly doped silicon wafer (1010), the SOI wafer having an embedded silicon oxide layer and a highly doped silicon layer, and the highly doped silicon wafer having a cavity etched into the silicon oxide layer of the highly doped silicon wafer.

11. The method according to claim 10, wherein manufacturing the CMUT wafer comprises: A trench is formed through at least a portion of the thickness of the highly doped silicon wafer, and the trench is filled with an insulator to form a conductive via (1008).

12. The method according to claim 11, wherein after bonding the SOI wafer and the highly doped silicon wafer to each other, the thickness of the highly doped silicon wafer is reduced (1012) to expose the end of the conductive via at the bottom surface of the highly doped silicon wafer, and a plurality of layers are deposited at the bottom surface and patterned (1014), the plurality of layers comprising at least one passivation layer, a bias plane and a metal layer.

13. The method of claim 12, wherein after depositing and patterning the plurality of layers, a metal contact (1014) is formed at the bottom surface of the highly doped silicon wafer.

14. The method according to claim 9, further comprising: Prior to coupling to the CMUT wafer, the ASIC wafer is prepared (1018) by depositing a passivation layer over an upper surface of the ASIC wafer and planarizing the upper surface, the upper surface including ASIC pads.

15. The method according to claim 14, further comprising: Prior to coupling the CMUT wafer to the ASIC wafer, the passivation layer is etched to provide access to the ASIC pads (1020).

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