A communication method for chip testing machine based on PCIE multi-machine cascading and routing

Abstract

The invention discloses a communication method for a chip tester based on PCIE multi-machine cascade and routing, and relates to the technical field of integrated circuit testing, including building a chip tester communication system, wherein the chip tester communication system connects all FPGAs in each ATE into one path. The invention sets a control port, a PCIE multi-machine cascade management module and an integrated circuit design module, and designs a special routing protocol to realize intelligent routing of data in a PCIE cascade network. According to the configuration of the tester, the state of a data channel and the communication demand, the optimal data transmission path is dynamically selected, and integrated circuit test data and corresponding analysis results are managed, visualized and stored, which is helpful to realize integrated circuit test management through Internet cloud management and control, and improve the intelligent level of integrated circuit test management. The efficient communication method enables test data to be transmitted to the tester more quickly and accurately, thereby improving the precision and accuracy of the test.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a communication method of a chip testing machine based on PCIE multi-machine cascading and routing. Background Art

[0002] With the rapid development of integrated circuit technology, the complexity of chips continues to increase, and the demand for chip testing is becoming more urgent. Traditional chip testers often use a single test device, resulting in low test efficiency, high cost, and lack of flexibility. PCIE is a high-speed serial computer expansion bus standard with high bandwidth and low latency, which is very suitable for high-performance data transmission. Introducing PCIE multi-machine cascade technology in chip testers can effectively solve the shortcomings of traditional testers and realize high-speed communication and resource sharing between multiple test devices.

[0003] In the prior art, CMNT No. 1, FPGA board No. 1 and FPGA board No. 1 form an ATE. If the PC wants to give an instruction to FPGA board No. 1, the process is as follows: PC sends a signal to CMNT No. 1, CMNT No. 1 sends a signal to FPGA board No. 1 after receiving the signal, FPGA board No. 1 starts to execute, and FPGA board No. 1 sends another signal to CMNT No. 1 after the execution is completed, and CMNT No. 1 sends it to PC, and PC can know that FPGA board No. 1 has completed execution. The sequence can be summarized as PC—CMNT No. 1—FPGA board No. 1, FPGA board No. 1—CMNT No. 1—PC to form a closed loop. If FPGA board No. 1 completes the execution of an instruction, FPGA board No. 2 is required to execute an instruction; if FPGA board No. 1 completes the execution of an instruction, FPGA board No. 3 in another ATE is required to continue execution; if there are multiple FPGA boards between FPGA board No. 1 and FPGA board No. 2, and the instruction needs to be executed on the previous board before the next board can execute it, the time required in the middle is very long.

[0004] Therefore, if FPGA board No. 1 and FPGA board No. 2 are a group of FPGAs, FPGA board No. 2 will send a feedback signal based on the feedback signal of FPGA board No. 1. To test the synchronization between the feedback signal of FPGA board No. 1 and the signal sent by FPGA board No. 2, there will inevitably be errors when using the above method. In addition, the data transmission speed and bandwidth limitations during the test process have also become bottlenecks, affecting the timeliness and accuracy of the test results.

[0005] Therefore, the present invention needs to design a chip tester communication method based on PCIE multi-machine cascading and routing to solve the above-mentioned problems. Summary of the invention

[0006] The purpose of the present invention is to provide a communication method for a chip tester based on PCIE multi-machine cascading and routing in order to solve the above problems, thereby solving the problems mentioned in the background technology.

[0007] In order to solve the above problems, the present invention provides a technical solution:

[0008] A communication method of a chip tester based on PCIE multi-machine cascade and routing, the communication method comprising: the PCIE multi-machine cascade comprises ATE, FPGA and CMNT;

[0009] ATE is automatic test equipment, which is used to test the functions and performance of electronic equipment;

[0010] FPGA is a field programmable gate array, which is an integrated circuit that can be configured by programming in the field;

[0011] CMNT is a commercial multi-node test module used for testing in a multi-node environment;

[0012] S1. Construct a chip tester communication system. The chip tester communication system connects all FPGAs in each ATE into one path. The main FPGAs are recorded as FPGA No. 1 and FPGA No. 2, and the main ATEs are recorded as ATE No. 1 and ATE No. 2.

[0013] S2, when FPGA No. 1 finishes executing an instruction, FPGA No. 1 sends a signal to CMNT No. 1 and sends an execution signal to FPGA No. 2 at the same time;

[0014] S3, setting FPGA No. 1 and FPGA No. 2 as a group of FPGAs, FPGA No. 2 will send a feedback signal based on the feedback signal of FPGA No. 1, which is used to test the synchronization between the feedback signal of FPGA No. 1 and the signal sent by FPGA No. 2. Using the above method will reduce the error;

[0015] S4. The chip tester communication system connects each CMNT into one path. When FPGA No. 1 finishes executing the instruction, FPGA No. 3 in ATE No. 2 continues to execute and completes a communication cycle, which saves time compared to the original solution.

[0016] As a preferred technical solution, in step S1, each of the ATEs is externally connected to a PC, and the PC is connected to a chip tester, and the chip tester is used to perform function, performance and stability tests on the chip.

[0017] As a preferred technical solution, the execution order in step S2 is summarized as PC, CMNT No. 1, FPGA No. 1, FPGA No. 1, CMNT No. 1, PC and FPGA No. 1, FPGA No. 2, CMNT No. 1, PC.

[0018] As a preferred technical solution, the execution order in step S4 is summarized as PC, CMNT No. 1, FPGA No. 1, FPGA No. 1, CMNT No. 1, PC and FPGA No. 1, CMNT No. 1, CMNT No. 2, FPGA No. 3.

[0019] As a preferred technical solution, when there are multiple FPGA boards between FPGA No. 1 and FPGA No. 2 in step S2, the instructions in step S2 are executed in the order of the previous board and the next board, which can save a lot of time.

[0020] As a preferred technical solution, when a communication cycle is completed in step S4, the working status and communication quality of each chip tester are monitored in real time through an external monitoring device to ensure the stable operation of each device.

[0021] As a preferred technical solution, a chip tester communication system is constructed before performing step S1. The chip tester communication system includes a control port, a PCIE multi-machine cascade management module and an integrated circuit design module. The output end of the control port is communicatively connected to the input end of the PCIE multi-machine cascade management module. The PCIE multi-machine cascade management module and the integrated circuit design module are bidirectionally communicatively connected.

[0022] As a preferred technical solution, the control port is used to control the real-time operation of the PC and the chip tester respectively;

[0023] The control port includes a PC control unit, a chip tester control unit and a visualization unit, and the output ends of the PC control unit and the chip tester control unit are both communicatively connected to the input end of the visualization unit;

[0024] The PC control unit is used to manage the real-time communication data between each ATE and the PC;

[0025] The chip tester control unit is used to control the real-time test data of the PC and the chip tester, and adopts PCIE technology to flexibly add or delete chip testers as needed to meet the test needs of different scales;

[0026] The visualization unit is used to perform corresponding visualization processing on the data imaging request instructions generated by the PC and the chip tester, and is used for the staff to remotely monitor the real-time operation of the chip tester communication system in real time.

[0027] As a preferred technical solution, the PCIE multi-machine cascade management module includes a PCIE interface unit, a CMNT maintenance unit and an intelligent routing protocol unit, the CMNT maintenance unit and the intelligent routing protocol unit are bidirectionally connected in communication, and the PCIE interface unit and the intelligent routing protocol unit are bidirectionally connected in communication;

[0028] The PPCIE interface unit is used to connect multiple devices or hosts together through the PCIE interface to achieve data transmission and resource sharing;

[0029] The CMNT maintenance unit is used to illustrate, explain or describe the non-executable part added to a certain code segment, and to group and label the CMNTs that appear;

[0030] The intelligent routing protocol unit is used to dynamically select the optimal data transmission path according to the configuration of the chip tester, the state of the data channel and the communication requirements.

[0031] As a preferred technical solution, the integrated circuit design module includes an input-output block unit, a group management unit and an embedded data access unit, the output end of the embedded data access unit is communicatively connected to the input end of the input-output block unit, and the input-output block unit is bidirectionally communicatively connected to the group management unit;

[0032] The input and output block unit is used to connect the FPGA board with external devices, process input and output signals, and support various voltage standards;

[0033] The grouping management unit is used to group and label multiple FPGA boards;

[0034] The embedded data access unit is used to access embedded RAM, DSP, and on-chip processor resources, providing more functions and flexibility for implementing specific control logic or processing functions.

[0035] The beneficial effects of the present invention are as follows: the present invention constructs a complete chip tester communication system by setting a control port, a PCIE multi-machine cascade management module and an integrated circuit design module, which is convenient for remote supervision by staff during use. During actual use, a chip tester communication system is constructed, and the chip tester communication system connects all FPGAs in each ATE into one path, and the mainly used FPGAs are recorded as FPGA No. 1 and FPGA No. 2, and the mainly used ATEs are recorded as ATE No. 1 and ATE No. 2. When FPGA No. 1 completes the execution of an instruction, FPGA No. 1 transmits a signal to CMNT No. 1 and transmits an execution signal to FPGA No. 2 at the same time, and FPGA No. 1 and FPGA No. 2 are set as a group of FPGAs, and FPGA No. 2 will send a feedback signal based on the feedback signal of FPGA No. 1, which is used to test the synchronization between the feedback signal of FPGA No. 1 and the signal sent by FPGA No. 2. In this case, the chip tester communication system connects each CMNT into one path. When the No. 1 FPGA finishes executing the instruction, the No. 3 FPGA in the No. 2 ATE continues to execute and completes a communication cycle, which saves time compared to the original solution. By configuring the PCIE interface to connect with the host or other testers, a cascade network is formed to process the data transmission of the PCIE protocol in real time. A special routing protocol is designed to realize intelligent routing of data in the PCIE cascade network. According to the configuration of the tester, the status of the data channel and the communication requirements, the optimal data transmission path is dynamically selected, and the integrated circuit test data and the corresponding analysis results are managed, visualized and stored, which is helpful to realize integrated circuit test management through Internet cloud management and control, and improve the intelligence level of integrated circuit test management. The efficient communication method enables the test data to be transmitted to the tester more quickly and accurately, thereby improving the precision and accuracy of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] For ease of explanation, the present invention is described in detail with reference to the following specific implementations and the accompanying drawings.

[0037] Figure 1 It is a structural connection diagram of a chip tester communication method based on PCIE multi-machine cascading and routing of the present invention;

[0038] Figure 2 It is a flow chart of a communication method of a chip tester based on PCIE multi-machine cascading and routing of the present invention;

[0039] Figure 3 The present invention discloses a chip tester communication system topology diagram of a chip tester based on a communication method of PCIE multi-machine cascading and routing. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0041] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings, and "multiple" generally includes at least two.

[0042] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0043] It should be understood that although the terms first, second, third, etc. may be used to describe in the embodiments of the present application, these descriptions should not be limited to these terms. These terms are only used to distinguish the descriptions. For example, without departing from the scope of the embodiments of the present application, the first may also be referred to as the second, and similarly, the second may also be referred to as the first.

[0044] As used herein, the words "if" and "if" may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0045] It should also be noted that the term "includes", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that a commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the commodity or device including the elements.

[0046] It should be particularly noted that any symbols and / or numbers in the specification that are not marked in the accompanying drawings are not drawing marks.

[0047] like Figure 1 , Figure 2 and Figure 3 As shown, this specific implementation adopts the following technical solutions:

[0048] A chip tester communication method based on PCIE multi-machine cascading and routing,

[0049] The PCIE multi-machine cascade includes ATE, FPGA and CMNT;

[0050] ATE is automatic test equipment, which is used to test the functions and performance of electronic equipment;

[0051] FPGA is a field programmable gate array, which is an integrated circuit that can be configured by programming in the field;

[0052] CMNT is a commercial multi-node test module used for testing in a multi-node environment;

[0053] The communication method comprises:

[0054] S1. Construct a chip tester communication system. The chip tester communication system connects all FPGAs in each ATE into one path. The main FPGAs used are recorded as FPGA No. 1 and FPGA No. 2, and the main ATEs used are recorded as ATE No. 1 and ATE No. 2. In step S1, each of the ATEs is externally connected to a PC, and the PC is connected to a chip tester. The chip tester is used to perform function, performance and stability tests on the chip.

[0055] S2, when FPGA No. 1 finishes executing an instruction, FPGA No. 1 sends a signal to CMNT No. 1 and sends an execution signal to FPGA No. 2 at the same time. The execution order can be summarized as PC—CMNT No. 1—FPGA No. 1, FPGA No. 1—CMNT No. 1—PC and FPGA No. 1—FPGA No. 2—CMNT No. 1—PC. When there are multiple FPGA boards between FPGA No. 1 and FPGA No. 2, the instructions in step S2 are executed in the order of the previous board and the next board, which can save a lot of time.

[0056] S3, setting FPGA No. 1 and FPGA No. 2 as a group of FPGAs, FPGA No. 2 will send a feedback signal based on the feedback signal of FPGA No. 1, which is used to test the synchronization between the feedback signal of FPGA No. 1 and the signal sent by FPGA No. 2. Using the above method will reduce the error;

[0057] S4. The chip tester communication system connects each CMNT into one path. When FPGA No. 1 finishes executing the instruction, FPGA No. 3 in ATE No. 2 continues to execute and completes a communication cycle. When a communication cycle is completed, the working status and communication quality of each chip tester are monitored in real time through external monitoring equipment to ensure the stable operation of each device. Compared with the original plan, time is saved. The execution sequence can be summarized as PC—CMNT No. 1—FPGA No. 1, FPGA No. 1—CMNT No. 1—PC, and FPGA No. 1—CMNT No. 1—CMNT No. 2—FPGA No. 3.

[0058] Before performing step S1, a chip tester communication system is constructed, wherein the chip tester communication system includes a control port, a PCIE multi-machine cascade management module and an integrated circuit design module, wherein an output end of the control port is communicatively connected to an input end of the PCIE multi-machine cascade management module, and the PCIE multi-machine cascade management module is bidirectionally communicatively connected to the integrated circuit design module;

[0059] The control port is used to control the real-time operation of the PC and the chip tester respectively; the control port includes a PC control unit, a chip tester control unit and a visualization unit, and the output ends of the PC control unit and the chip tester control unit are both communicatively connected to the input end of the visualization unit; the PC control unit is used to manage the real-time communication data between each ATE and the PC; the chip tester control unit is used to control the real-time test data of the PC and the chip tester, and adopts PCIE technology to flexibly add or delete chip testers as needed to meet the test requirements of different scales; the visualization unit is used to perform corresponding visualization processing on the data imaging request instructions generated by the PC and the chip tester, so as to enable the staff to remotely monitor the real-time operation of the chip tester communication system in real time;

[0060] The PCIE multi-machine cascade management module includes a PCIE interface unit, a CMNT maintenance unit and an intelligent routing protocol unit. The CMNT maintenance unit and the intelligent routing protocol unit are bidirectionally connected, and the PCIE interface unit and the intelligent routing protocol unit are bidirectionally connected; the PCIE interface unit is used to connect multiple devices or hosts together through the PCIE interface to achieve data transmission and resource sharing; the CMNT maintenance unit is used to illustrate, explain or describe the non-executable part added to a certain section of code, and to group and label the CMNT that appears; the intelligent routing protocol unit is used to dynamically select the optimal data transmission path according to the configuration of the chip tester, the status of the data channel and the communication requirements;

[0061] The integrated circuit design module includes an input-output block unit, a grouping management unit and an embedded data access unit. The output end of the embedded data access unit is communicatively connected to the input end of the input-output block unit, and the input-output block unit is bidirectionally communicatively connected to the grouping management unit. The input-output block unit is used to connect the FPGA board card with external devices, process input and output signals, and support various voltage standards. The grouping management unit is used to group and label multiple FPGA boards. The embedded data access unit is used to access embedded RAM, DSP, and on-chip processor resources, providing more functions and flexibility for realizing specific control logic or processing functions. Example

[0062] When PCIE multiple machines are cascaded and routed to the chip test management:

[0063] S1. The staff checks the required equipment one by one. After verifying that they are all correct, the chip tester communication system is started. The real-time communication data between each ATE and PC is managed through the PC control unit. The chip tester control unit controls the real-time test data of the PC and the chip tester. The PCIE technology is used to flexibly add or delete chip testers as needed to meet the test needs of different scales. The visualization unit performs corresponding visualization processing on the data imaging request instructions generated by the PC and the chip tester, which is used for the staff to remotely monitor the real-time operation of the chip tester communication system in real time and build a chip tester communication system. The chip tester communication system connects all FPGAs in each ATE into one, and the main FPGAs used are recorded as FPGA No. 1 and FPGA No. 2, and the main ATEs used are recorded as ATE No. 1 and ATE No. 2. The outside of each ATE is connected to the PC for communication, and the PC is connected to the chip tester for communication. The chip tester is used as the core test equipment and is responsible for function, performance and stability testing of the chip;

[0064] S2, the PCIE interface unit connects multiple devices or hosts together through the PCIE interface to achieve data transmission and resource sharing. The CMNT maintenance unit is used to illustrate, explain or describe the non-executable part added to a certain code segment, and to group and label the CMNT that appears. The intelligent routing protocol unit is used to dynamically select the optimal data transmission path according to the configuration of the chip tester, the state of the data channel and the communication requirements. When FPGA No. 1 completes the execution of an instruction, FPGA No. 1 sends a signal to CMNT No. 1 and sends an execution signal to FPGA No. 2 at the same time. The execution sequence can be summarized as PC—CMNT No. 1—FPGA No. 1, FPGA No. 1—CMNT No. 1—PC and FPGA No. 1—FPGA No. 2—CMNT No. 1—PC. When there are multiple FPGA boards between FPGA No. 1 and FPGA No. 2, the instructions in step S2 are executed in the order of the previous board and the next board, which can save a lot of time.

[0065] S3, setting FPGA No. 1 and FPGA No. 2 as a group of FPGAs, FPGA No. 2 will send a feedback signal based on the feedback signal of FPGA No. 1, which is used to test the synchronization between the feedback signal of FPGA No. 1 and the signal sent by FPGA No. 2. Using the above method will reduce the error;

[0066] S4. The input and output block unit connects the FPGA board with external devices, processes input and output signals, and supports various voltage standards. The group management unit groups and labels multiple FPGA boards. The embedded data access unit is used to access embedded RAM, DSP, and on-chip processor resources, providing more functions and flexibility for realizing specific control logic or processing functions. The chip tester communication system connects each CMNT into one path. When the No. 1 FPGA executes the instruction, the No. 3 FPGA in the No. 2 ATE continues to execute and completes a communication cycle. When a communication cycle is completed, the working status and communication quality of each chip tester are monitored in real time through an external monitoring device to ensure the stable operation of each device. Compared with the original plan, time is saved. The execution sequence can be summarized as PC—No. 1 CMNT—No. 1 FPGA, No. 1 FPGA—No. 1 CMNT—PC, and No. 1 FPGA—No. 1 CMNT—No. 2 CMNT—No. 3 FPGA, so that the test data can be transmitted to the tester more quickly and accurately, thereby improving the precision and accuracy of the test.

[0067] Specifically: In actual applications, there are multiple control ports, which are respectively used in conjunction with the PCIE multi-machine cascade management module and the integrated circuit design module. The multiple control ports are respectively located in different geographical locations. The present invention constructs a complete chip tester communication system by setting control ports, PCIE multi-machine cascade management module and integrated circuit design module, which is convenient for remote supervision by staff during use. During actual use, a chip tester communication system is constructed. The chip tester communication system connects all FPGAs in each ATE into one path, and the main FPGAs used are recorded as FPGA No. 1 and FPGA No. 2, and the main ATEs used are recorded as ATE No. 1 and ATE No. 2. When FPGA No. 1 completes the execution of an instruction, FPGA No. 1 sends a signal to CMNT No. 1 and sends an execution signal to FPGA No. 2 at the same time. FPGA No. 1 and FPGA No. 2 are set as a group of FPGAs, and FPGA No. 2 sends a feedback signal based on the feedback signal of FPGA No. 1. It is used to test the synchronization between the feedback signal of FPGA No. 1 and the signal sent by FPGA No. 2. The chip tester communication system connects each CMNT into one path. When FPGA No. 1 finishes executing the instruction, FPGA No. 3 in ATE No. 2 continues to execute and completes a communication cycle, which saves time compared with the original solution. By configuring the PCIE interface to connect with the host or other testers, a cascade network is formed to process the data transmission of the PCIE protocol in real time. A special routing protocol is designed to realize intelligent routing of data in the PCIE cascade network. According to the configuration of the tester, the status of the data channel and the communication requirements, the optimal data transmission path is dynamically selected to manage, visualize and store the integrated circuit test data and the corresponding analysis results, which is helpful to realize the integrated circuit test management through Internet cloud management and control, and improve the intelligence level of integrated circuit test management. The efficient communication method enables the test data to be transmitted to the tester more quickly and accurately, thereby improving the precision and accuracy of the test.

[0068] Those of ordinary skill in the art will appreciate that the modules and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0069] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices, equipment and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0070] In the several embodiments provided in the present application, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or units can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or equipment, which can be electrical, mechanical or other forms.

[0071] The modules for controlling ports, PCIE multi-machine cascade management, and integrated circuit design may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0072] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0073] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program instructions, such as a USB flash drive, a mobile hard disk, a read-only storage server, a random access storage server, a magnetic disk or an optical disk.

[0074] In addition, it should be noted that the combination of the various technical features in this case is not limited to the combination described in the claims of this case or the combination described in the specific embodiments. All technical features described in this case can be freely combined or combined in any way unless there is a contradiction between them.

[0075] It should be noted that the above examples are only specific embodiments of the present invention, and the present invention is obviously not limited to the above examples, and there are many similar variations. All variations directly derived or associated from the contents disclosed by the technicians in this field should fall within the protection scope of the present invention.

[0076] The above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A communication method for a chip tester based on PCIE multi-machine cascading and routing, characterized in that: The PCIE multi-machine cascade includes ATE, FPGA and CMNT; ATE is automatic test equipment, which is used to test the functions and performance of electronic equipment; FPGA is a field programmable gate array, which is an integrated circuit that can be configured by programming in the field; CMNT is a commercial multi-node test module used for testing in a multi-node environment; The communication method comprises: S1. Construct a chip tester communication system. The chip tester communication system connects all FPGAs in each ATE into one path. The main FPGAs are recorded as FPGA No. 1 and FPGA No. 2, and the main ATEs are recorded as ATE No. 1 and ATE No.

2. S2, when FPGA No. 1 finishes executing an instruction, FPGA No. 1 sends a signal to CMNT No. 1 and sends an execution signal to FPGA No. 2; S3, setting FPGA No. 1 and FPGA No. 2 as a group of FPGAs, FPGA No. 2 will send a feedback signal based on the execution signal of FPGA No. 1, and the feedback signal is used to test the synchronization between the feedback signal of FPGA No. 1 and the signal sent by FPGA No. 2; S4. The chip tester communication system connects each CMNT into one path. When FPGA No. 1 finishes executing the instruction, FPGA No. 3 in ATE No. 2 continues to execute, completing a communication cycle.

2. The communication method of a chip tester based on PCIE multi-machine cascading and routing according to claim 1, characterized in that: In step S1, each of the ATEs is externally connected to a PC, and the PC is connected to a chip tester, which is used to perform function, performance and stability tests on the chip.

3. The communication method of a chip tester based on PCIE multi-machine cascading and routing according to claim 2, characterized in that: The execution order in step S2 is summarized as PC, CMNT No. 1, FPGA No. 1, FPGA No. 1, CMNT No. 1, PC, and FPGA No. 1, FPGA No. 2, CMNT No. 1, PC.

4. The communication method of a chip tester based on PCIE multi-machine cascading and routing according to claim 2, characterized in that: The execution order in step S4 is summarized as PC, CMNT No. 1, FPGA No. 1, FPGA No. 1, CMNT No. 1, PC, and at the same time, FPGA No. 1, CMNT No. 1, CMNT No. 2, FPGA No.

3.

5. The communication method of a chip tester based on PCIE multi-machine cascading and routing according to claim 2, characterized in that: When there are multiple FPGA boards between the first FPGA and the second FPGA in step S2, the instructions in step S2 are executed in the order of the previous board and the next board.

6. The communication method of a chip tester based on PCIE multi-machine cascading and routing according to claim 5, characterized in that: When one communication cycle is completed in step S4, the working status and communication quality of each chip tester are monitored in real time through an external monitoring device.

7. The communication method of a chip tester based on PCIE multi-machine cascading and routing according to claim 1, characterized in that: Before performing step S1, the method further includes: A chip tester communication system is constructed, which includes a control port, a PCIE multi-machine cascade management module and an integrated circuit design module. The output end of the control port is communicatively connected to the input end of the PCIE multi-machine cascade management module, and the PCIE multi-machine cascade management module is bidirectionally communicatively connected to the integrated circuit design module.

8. The communication method of a chip tester based on PCIE multi-machine cascading and routing according to claim 7, characterized in that: The control port is used to control the real-time operation of the PC and the chip tester respectively; The control port includes a PC control unit, a chip tester control unit and a visualization unit, and the output ends of the PC control unit and the chip tester control unit are both communicatively connected to the input end of the visualization unit; The PC control unit is used to manage the real-time communication data between each ATE and the PC; The chip tester control unit is used to control the real-time test data of the PC and the chip tester; The visualization unit is used to perform corresponding visualization processing on the data imaging request instructions generated by the PC and the chip tester, so that the staff can remotely monitor the real-time operation of the chip tester communication system in real time.

9. The communication method of a chip tester based on PCIE multi-machine cascading and routing according to claim 7, characterized in that: The PCIE multi-machine cascade management module includes a PCIE interface unit, a CMNT maintenance unit and an intelligent routing protocol unit, the CMNT maintenance unit and the intelligent routing protocol unit are bidirectionally connected in communication, and the PCIE interface unit and the intelligent routing protocol unit are bidirectionally connected in communication; The PCIE interface unit is used to connect multiple devices or hosts together through the PCIE interface to achieve data transmission and resource sharing; The CMNT maintenance unit is used to illustrate, explain or describe the non-executable part added to a certain code segment, and to group and label the CMNTs that appear; The intelligent routing protocol unit is used to dynamically select the optimal data transmission path according to the configuration of the chip tester, the state of the data channel and the communication requirements.

10. The communication method of a chip tester based on PCIE multi-machine cascading and routing according to claim 7, characterized in that: The integrated circuit design module includes an input-output block unit, a group management unit and an embedded data access unit, wherein the output end of the embedded data access unit is communicatively connected to the input end of the input-output block unit, and the input-output block unit is bidirectionally communicatively connected to the group management unit; The input and output block unit is used to connect the FPGA board and external devices to process input and output signals; The grouping management unit is used to group and label multiple FPGA boards; The embedded data access unit is used to access embedded RAM, DSP, and on-chip processor resources to implement specific control logic or processing functions.

Images