An LDO circuit with soft start and foldback current limiting protection functions

Abstract

The present invention discloses an LDO circuit with soft start and foldback current limiting protection functions, including a bandgap reference module, a soft start module, a voltage selection module, a current limiting protection module, a first error amplifier, an output power tube, a first voltage divider resistor, and a second voltage divider resistor; the present invention realizes that there is no overshoot when the LDO is powered on, and the power consumption of the chip after entering the foldback current limiting is greatly reduced, thereby ensuring the safety of the chip. By reusing the control signal of the soft start circuit, the problem of failure to start with a constant current load in the traditional foldback protection circuit is solved, and the ability to power on with a load is improved. At the same time, it can be easily adjusted by V SET The voltage can flexibly adjust the current limit value at power-on according to the load requirements, providing good protection for the chip while meeting the application requirements.

Description

Technical Field

[0001] The present invention belongs to the field of safety protection, and in particular relates to an LDO circuit with soft start and foldback current limiting protection functions. Background Art

[0002] In the field of integrated circuit design, low-dropout linear regulators (LDOs) are widely used in the internal low-voltage power supply circuits of various chips due to their low power consumption, low noise, and simple structure. The load current of an LDO directly affects the voltage of its output power signal. However, as an internal power supply for chips, its load capacity is often limited, so current limiting protection for the LDO's load current is essential.

[0003] There are two common current limiting methods: fixed current limiting and foldback current limiting. Fixed current limiting means that the LDO can only provide a certain maximum current value to the load, which is independent of the output voltage. Foldback current limiting, on the other hand, enters foldback current limiting when the load exceeds the maximum limit, and the current limit value decreases as the output voltage decreases.

[0004] The general steps to implement foldback current limiting are:

[0005] 1. Monitor output current: monitor output current by current sampling current;

[0006] 2. Compare the current with the set value: the set value is related to the output voltage. When the output voltage decreases, the current limit value decreases to ensure that the power consumption of the output power tube is within the rated value.

[0007] 3. Feedback control: When the current exceeds the current limit, the current limiting loop starts to adjust the power tube gate;

[0008] When the LDO chip is in normal working state, that is, no current overload occurs, the output voltage of the chip is controlled by the main loop. Once the current sampling module determines that there is an overload or a short circuit in the output voltage, the current limiting module takes over the loop control.

[0009] However, the introduction of foldback current limiting protection can easily cause the chip to fail to start when it is loaded with a constant current that exceeds the short-circuit protection current, as shown below Figure 1 As shown in the figure: During the startup process, since the output voltage has not risen to the rated value, the circuit will mistakenly judge it as a short-circuit state. Therefore, the output current capacity of the power tube is insufficient to meet the current requirement of the load, resulting in startup failure.

[0010] Based on the above, Chinese patent CN113009956A proposes a low-dropout linear regulator and its control circuit. This invention solves the problem of starting a constant-current load by adding an output detection circuit module to disable the foldback current limiting function during power-up. However, this solution does not allow for flexible adjustment of the current limit value during normal power-up. Therefore, those skilled in the art need to solve the problem of conventional foldback current limiting protection chips being unable to start a constant-current load exceeding the short-circuit current value, and to provide flexible adjustment of the current limit value during power-up. Summary of the Invention

[0011] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide an LDO circuit with soft start and return current limiting protection, which has reliable current limiting protection and short-circuit protection functions. Based on the original soft start circuit module, the control signal of the module is reused, and no additional detection circuit is required. At the same time, the current limiting value during the power-on process can be flexibly adjusted.

[0012] The present invention is implemented as follows: an LDO circuit with soft start and foldback current limiting protection includes a bandgap reference module, a soft start module, a voltage selection module, a current limiting protection module, a first error amplifier EA1, an output power tube M p , the first voltage-dividing resistor R1, the second voltage-dividing resistor R2; the output of the bandgap reference module is connected to the input of the soft-start module and the first input of the voltage selection module; the two outputs of the soft-start module are connected to the second and third inputs of the voltage selection module; the fourth input of the voltage selection module is connected to the positive input of the first error amplifier EA1, one end of the first voltage-dividing resistor R1, one end of the second voltage-dividing resistor R2, and the fifth input is connected to the soft-start current limiting voltage V SET The two output terminals are connected to the negative input terminal of the first error amplifier EA1 and one input terminal of the current limiting protection module respectively; the output terminal of the first error amplifier EA1 is connected to the output terminal of the current limiting protection module and the output power tube M p The other input terminal of the current limiting protection module is connected to the other end of the second voltage divider resistor R2 and the output power tube M p The drain output V OUT The power input terminal of the bandgap reference module, the power input terminal of the current limiting protection module, the power input terminal of the first error amplifier EA1, the output power tube M p The source is connected to the input power supply V IN The ground terminal of the bandgap reference module, the ground terminal of the soft start module, the ground terminal of the current limiting protection module, the ground terminal of the first error amplifier EA1, and the other end of the first voltage divider resistor R1 are grounded.

[0013] As an example, the soft start module circuit includes a voltage comparator, a first transistor M n3 , current source I CHARGE, soft start capacitor C SS , the first inverter INV1; the negative input terminal of the voltage comparator is connected to the starting capacitor C SS One end of the current source I CHARGE The output terminal of the first transistor M n3 The positive input terminal is connected to the bandgap reference voltage V BG , the power supply terminal is connected to the input power supply V IN , the ground terminal is grounded, and the control terminal is connected to the control signal V CTRL The output end of the first inverter INV1 is connected to the input end of the first inverter INV1; the output end of the first inverter INV1 outputs the control signal V CTRL ;Soft start capacitor C SS The other end of the first transistor M n3 The source of the first transistor M is grounded; n3 The gate of the current source I is connected to the enable signal EN; CHARGE The input terminal is connected to the input power supply V IN .

[0014] As an example, the voltage comparator inside the soft start module is composed of an operational amplifier with an asymmetric structure, specifically including a second transistor M n1 , the third transistor M n2 , the fourth transistor M p1 , the fifth transistor M p2 , the sixth transistor M p3 , a third resistor R3, a current source I1; a sixth transistor M p3 The source is connected to the input power supply V IN , the gate is connected to the control signal V CTRL , the drain is connected to the fourth transistor M p1 The source of the fifth transistor M p2 The source of the fourth transistor M p1 The gate of the fifth transistor M p2 The gate of the fifth transistor M p2 The drain of the third transistor M n2 The drain of the second transistor M n1 The output voltage of the comparator after the drain is V COMP ; The second transistor M n1 The source is connected to one end of the third resistor R3 and the input end of the current source I1, and the gate is connected to the soft start voltage V S ; The third transistor M n2 The source is connected to the other end of the third resistor R3, and the gate is connected to the bandgap reference voltage V BG .

[0015] Preferably, the voltage selection module includes a seventh transistor M n4 , the eighth transistor Mn5 , the ninth transistor M n6 , the tenth transistor M n7 , the second inverter INV2; control voltage V CTRL The input terminal of the second inverter INV2 and the seventh transistor M n4 The gate of the ninth transistor M n6 The output terminal of the second inverter INV2 outputs an inverted control voltage / V CTRL ; The seventh transistor M n4 The source is connected to V BG , the drain is connected to the eighth transistor M n5 The output reference voltage V REF ; The eighth transistor M n5 The source of the soft start voltage V S , the gate is connected to the inverting control voltage / V CTRL ; Ninth transistor M n6 The source is connected to the feedback voltage V FB , the drain is connected to the tenth transistor M n7 Output current limit setting voltage after drain V P ; Tenth transistor M n7 The source of the soft start current limiting voltage V SET , the gate is connected to the inverting control voltage / V CTRL .

[0016] Preferably, the current limiting protection module includes an output current sampling module and a current limiting foldback module;

[0017] The output current sampling module includes a second error amplifier EA2, a current sampling tube M S , the eleventh transistor M P4 The negative input terminal of the second error amplifier EA2 is connected to the current sampling tube M S The drain of the eleventh transistor M P4 The positive input terminal is connected to the output voltage V OUT , the output end is connected to the eleventh transistor M P4 The gate power supply terminal is V IN , the ground terminal is grounded; the current sampling tube M S The source is connected to V IN , the gate is connected to the output power tube M p The gate control voltage V G ; Eleventh transistor M P4 The drain serves as the output end of the output current sampling module;

[0018] The current limiting foldback module includes a third error amplifier EA3, a twelfth transistor M p5, the fourth resistor R4; the negative input terminal of the third error amplifier EA3 is connected to the output terminal of the output current sampling module 1, one end of the fourth resistor R4, and the positive input terminal is connected to the current limiting setting voltage V P , the output terminal is connected to the twelfth transistor M p5 The gate power supply terminal is V IN , the ground terminal is grounded; the twelfth transistor M p5 The source is connected to V IN , the drain is connected to the output power tube M p The gate control voltage V G ; The other end of the fourth resistor R4 is grounded.

[0019] As a preference, in the soft start phase, the current limiting voltage V P The voltage selection module controls the soft start current limiting voltage V SET , at this time, the foldback current limiting function is turned off;

[0020] One end of the fourth resistor R4 is connected to the negative input terminal V of the third error amplifier EA3. N , one end is grounded; current sampling tube M S The output sampling current flows through the fourth resistor R4 to form a voltage drop. As the load current increases, the current flowing through the fourth resistor R4 increases, and then the negative input voltage V N Increase, if V N Increases to exceed the current limit voltage V P , will trigger the current limiting protection, the output voltage of the third error amplifier EA3 V B Decreases, making the output power tube M P The gate control voltage V G Rising, then the power tube M P The output current decreases, forming negative feedback to stabilize the output current value; if the negative input voltage V N If the current limit protection is not triggered, the current limiting amplifier outputs a high level, so that the twelfth transistor M P5 In the non-conducting state, the output voltage and output current of the LDO chip are still controlled by the output voltage of the first error amplifier EA1; after the soft start is completed, the current limiting voltage V is controlled by the voltage selection module. P = feedback voltage V FB , the foldback current limiting function is turned on;

[0021] Current limiting current I CL The descriptions of the various work stages are as follows:

[0022] Soft start stage: current limiting voltage V P =Soft start current limit voltage V SET , current limiting current I CL= Soft-start current limit I SET ;

[0023] After soft start is completed: current limiting voltage V P = feedback voltage V FB ; According to the different working states of the LDO chip, including the following situations: When the LDO chip is in normal load, the feedback voltage V FB = Bandgap reference voltage V BG , at this time the current limiting current I CL = Maximum current limit I MAX ; When the LDO chip triggers the current limit, the output voltage V OUT Falling, feedback voltage V FB Will decrease in proportion, at this time the current limiting current I CL = Foldback current limit I FB ;When the LDO chip triggers the current limit, the output voltage V OUT Continues to drop until it reaches 0V, and the LDO chip is in a short-circuit state: the feedback voltage V FB =0V, at this time the current limiting current I CL = short-circuit current I SHORT .

[0024] The beneficial effects of the present invention are:

[0025] 1. The present invention proposes an LDO circuit with soft-start and foldback current limiting protection, which has reliable current limiting and short-circuit protection functions. The use of an asymmetric operational amplifier in the soft-start circuit facilitates the design of the soft-start voltage threshold. The use of an asymmetric operational amplifier in the current limiting amplifier, combined with a power transistor as an input pair, facilitates the design of the maximum current limit value and the short-circuit current value.

[0026] 2. In addition to playing the soft start function and preventing the LDO output voltage from overshooting during power-on, the soft start module of the present invention also outputs a control signal V CTRL It is also used to control the voltage selection module and set the current limit value for the current limiting protection module in different working stages. Without increasing the circuit complexity, it solves the problem of traditional foldback current limiting protection chips that cannot start constant current loads exceeding the short-circuit current value.

[0027] 3. The current limit value in the power-on stage can be adjusted by designing different V SET Flexible settings to suit different applications;

[0028] The present invention is an LDO circuit with soft start and foldback current limiting protection functions. The LDO has no overshoot when powered on and the power consumption of the chip is greatly reduced after entering the foldback current limiting mode, ensuring the safe use of the chip. By reusing the control signal of the soft start circuit, the problem of failure to start with a constant current load in the traditional foldback protection circuit is solved, and the ability to power on with a load is improved. At the same time, it can be easily adjusted by V SET The voltage can flexibly adjust the current limit value at power-on according to the load requirements, providing good protection for the chip while meeting the application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 This is a schematic diagram of the constant current load startup principle under the existing foldback current limiting protection.

[0031] FIG2 is a block diagram of an LDO circuit with soft start and foldback current limiting protection provided by an embodiment of the present invention.

[0032] FIG3 is a schematic diagram of the circuit structure of the soft start module provided by an embodiment of the present invention.

[0033] FIG4 is a schematic diagram of the structure of a voltage comparator circuit according to an embodiment of the present invention.

[0034] Figure 5 It is a schematic diagram of the circuit structure of the voltage selection module provided by an embodiment of the present invention.

[0035] Figure 6 This is a schematic diagram of the circuit structure of the foldback current limiting module provided by an embodiment of the present invention.

[0036] Figure 7 4 is a schematic diagram of the structure of a third error amplifier circuit provided by an embodiment of the present invention.

[0037] Figure 8 It is the current limiting value of each stage provided by the embodiment of the present invention.

[0038] Figure 9 This is a simulation waveform provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0040] like Figure 2As shown, an LDO circuit with soft start and foldback current limiting protection provided by an embodiment of the present invention includes a bandgap reference module, a soft start module, a voltage selection module, a current limiting protection module, a first error amplifier EA1, an output power tube M p , the first voltage divider resistor R1, the second voltage divider resistor R2; the output end of the bandgap reference module is connected to the input end of the soft start module and the first input end of the voltage selection module; the two output ends of the soft start module are connected to the second and third input ends of the voltage selection module; the fourth input end of the voltage selection module is connected to the positive input end of the first error amplifier EA1, one end of the first voltage divider resistor R1, one end of the second voltage divider resistor R2, and the fifth input end is the soft start current limiting voltage V SET The two output terminals are connected to the negative input terminal of the first error amplifier EA1 and one input terminal of the current limiting protection module respectively; the output terminal of the first error amplifier EA1 is connected to the output terminal of the current limiting protection module and the output power tube M p The other input terminal of the current limiting protection module is connected to the other end of the second voltage divider resistor R2 and the output power tube M p The drain output V OUT The power input terminal of the bandgap reference module, the power input terminal of the current limiting protection module, the power input terminal of the first error amplifier EA1, the output power tube M p The source is connected to the input power supply V IN The ground terminal of the bandgap reference module, the ground terminal of the soft start module, the ground terminal of the current limiting protection module, the ground terminal of the first error amplifier EA1, and the other end of the first voltage divider resistor R1 are grounded.

[0041] The first error amplifier EA1 is a conventional operational amplifier for amplifying the reference voltage V REF With the feedback voltage V FB The error signal between the output control signal drives the output power tube M P .

[0042] The bandgap reference module is a conventional bandgap reference voltage circuit that generates a bandgap reference voltage V BG .

[0043] As shown in FIG3 , the soft start module circuit includes a voltage comparator, a first transistor M n3 , current source I CHARGE , soft start capacitor C SS , the first inverter INV1; the negative input terminal of the voltage comparator is connected to the starting capacitor C SS One end of the current source I CHARGE The output terminal of the first transistor M n3 The positive input terminal is connected to the bandgap reference voltage V BG , the power supply terminal is connected to the input power supply V IN, the ground terminal is grounded, and the control terminal is connected to the control signal V CTRL The output end of the first inverter INV1 is connected to the input end of the first inverter INV1; the output end of the first inverter INV1 outputs the control signal V CTRL ;Soft start capacitor C SS The other end of the first transistor M n3 The source of the first transistor M is grounded; n3 The gate of the current source I is connected to the enable signal EN; CHARGE The input terminal is connected to the input power supply V IN .

[0044] When the enable signal EN changes from high level to low level, the first transistor M n3 In the cut-off state, the soft start circuit starts working. CHARGE Give the soft start capacitor C SS Charging generates soft start voltage V S Bandgap reference voltage V BG Input voltage comparator positive input terminal, soft start voltage V S Input the negative input terminal of the voltage comparator. When V S The voltage rises to (V BG -V TH１ ), where the threshold voltage V TH１ The soft start process is completed by the voltage comparator. At this time, the output voltage of the voltage comparator V COMP By high level (high level voltage value equal to V IN ) turns to low level (low level voltage value is equal to 0V), V COMP Connect to the input of the first inverter INV1 and output the control signal V CTRL When high, the signal will be used to control the voltage selection module. CTRL The voltage comparator is turned off through the control terminal of the voltage comparator.

[0045] The soft start time T of the soft start module SS =C SS × .

[0046] like Figure 4 As shown, the voltage comparator inside the soft start module is composed of an operational amplifier with an asymmetric structure, specifically including a second transistor M n1 , the third transistor M n2 , the fourth transistor M p1 , the fifth transistor M p2 , the sixth transistor M p3 , a third resistor R3, a current source I1; a sixth transistor M p3 The source is connected to the input power supply V IN, the gate is connected to the control signal V CTRL , the drain is connected to the fourth transistor M p1 The source of the fifth transistor M p2 The source of the fourth transistor M p1 The gate of the fifth transistor M p2 The gate of the fifth transistor M p2 The drain of the third transistor M n2 The drain of the second transistor M n1 The output voltage of the comparator after the drain is V COMP ; The second transistor M n1 The source is connected to one end of the third resistor R3 and the input end of the current source I1, and the gate is connected to the soft start voltage V S ; The third transistor M n2 The source is connected to the other end of the third resistor R3, and the gate is connected to the bandgap reference voltage V BG .

[0047] Voltage comparison threshold V TH１ Set by the current source I1 and the third resistor R3, V TH１ =0.5×R3×I1, 0.5 is a fixed coefficient determined by the differential structure of the voltage comparator. Bandgap reference voltage V BG Connect the positive input of the voltage comparator, the soft start voltage V S Connect the negative input of the voltage comparator, the output voltage of the voltage comparator is V COMP Connect the input terminal of the first inverter INV1, the control signal V CTRL Connected to transistor M p3 When the soft start is completed, the control signal V CTRL When the sixth transistor M is high, p3 In the cut-off state, the voltage comparator stops working, which can save circuit power consumption.

[0048] like Figure 5 As shown, the voltage selection module includes a seventh transistor M n4 , the eighth transistor M n5 , the ninth transistor M n6 , the tenth transistor M n7 , the second inverter INV2; control voltage V CTRL The input terminal of the second inverter INV2 and the seventh transistor M n4 The gate of the ninth transistor M n6 The output terminal of the second inverter INV2 outputs an inverted control voltage / V CTRL ; The seventh transistor M n4 The source is connected to V BG , the drain is connected to the eighth transistor M n5The output reference voltage V REF ; The eighth transistor M n5 The source of the soft start voltage V S , the gate is connected to the inverting control voltage / V CTRL ; Ninth transistor M n6 The source is connected to the feedback voltage V FB , the drain is connected to the tenth transistor M n7 Output current limit setting voltage after drain V P ; Tenth transistor M n7 The source of the soft start current limiting voltage V SET , the gate is connected to the inverting control voltage / V CTRL .

[0049] The function of the voltage selection module is to set the negative input voltage of the first error amplifier and the current limiting voltage of the current limiting module. P Select voltage. Control signal V CTRL The second inverter INV2 outputs the inverted control voltage / V CTRL , control signal V CTRL Connect the seventh transistor M n4 With the eighth transistor M n6 Gate, inverting control voltage / V CTRL Connect the eighth transistor M n5 With the tenth transistor M n7 During the soft start phase, the control signal V CTRL Low level, inverting control voltage / V CTRL is high level, at this time the eighth transistor M n5 With the tenth transistor M n7 is turned on, the reference voltage V REF =Soft start voltage V S , current limiting voltage V P =Soft start current limit voltage V SET When the soft start is completed, the control signal V CTRL High level, inverting control voltage / V CTRL is low level, at this time the seventh transistor M n4 With the eighth transistor M n6 On, reference voltage V REF = Bandgap reference voltage V BG , current limit setting voltage V P = feedback voltage V FB .

[0050] like Figure 6 As shown, the current limiting protection module includes an output current sampling module 1 and a current limiting foldback module 2.

[0051] The output current sampling module 1 includes a second error amplifier EA2, a current sampling tube M S , the eleventh transistor M P4 The negative input terminal of the second error amplifier EA2 is connected to the current sampling tube M S The drain of the eleventh transistor M P4 The positive input terminal is connected to the output voltage V OUT , the output end is connected to the eleventh transistor M P4 The gate power supply terminal is V IN , the ground terminal is grounded; the current sampling tube M S The source is connected to V IN , the gate is connected to the output power tube M p The gate control voltage V G ; Eleventh transistor M P4 The drain serves as the output end of the output current sampling module 1.

[0052] The negative input of the second error amplifier is connected to the current sampling tube M S The drain terminal of the LDO is connected to the positive input terminal of the LDO output voltage V OUT , the output end is connected to the eleventh transistor M P4 The gate of the current sampling tube M S The drain voltage is close to the output voltage V OUT , making current sampling more accurate. Current sampling tube M S With the output power tube M P The ratio of the width to length is 1:A, and sampling is performed in the form of mirror current, where A is the set current scaling factor.

[0053] The second error amplifier is a conventional operational amplifier, which is used to make the current sampling tube M S The drain voltage is close to the output voltage V OUT , making current sampling more accurate.

[0054] The current limiting foldback module 2 realizes the current limiting foldback function, including a third error amplifier EA3, a twelfth transistor M p5 , the fourth resistor R4; the negative input terminal of the third error amplifier EA3 is connected to the output terminal of the output current sampling module 1, one end of the fourth resistor R4, and the positive input terminal is connected to the current limiting setting voltage V P , the output terminal is connected to the twelfth transistor M p5 The gate power supply terminal is V IN , the ground terminal is grounded; the twelfth transistor M p5 The source is connected to V IN , the drain is connected to the output power tube M p The gate control voltage V G ; The other end of the fourth resistor R4 is grounded.

[0055] During the soft start phase, the current limiting voltage V P The voltage selection module controls the soft start current limiting voltage V SET At this time, the foldback function is turned off and the current limit value is based on V SET The voltage can be selected to set different soft start current limit I SET , I SET =(V SET +0.5×I2×R5) / R4; in this example, V SET Voltage Select is connected to the bandgap reference voltage V BG .

[0056] One end of the fourth resistor R4 is connected to the negative input terminal V of the third error amplifier EA3. N , one end is grounded; current sampling tube M S The output sampling current flows through the fourth resistor R4 to form a voltage drop. As the load current increases, the current flowing through the fourth resistor R4 increases, and then the negative input voltage V N Increase, if V N Increases to exceed the current limit voltage V P , will trigger the current limiting protection, the output voltage of the third error amplifier EA3 V B Decreases, making the output power tube M P The gate control voltage V G Rising, then the power tube M P The output current decreases, forming negative feedback to stabilize the output current value. If the negative input voltage V N If the current limit protection is not triggered, the current limiting amplifier outputs a high level, so that the twelfth transistor M P5 In the non-conducting state, the output voltage and output current of the LDO chip are still controlled by the output voltage of the first error amplifier EA1. After the soft start is completed, the voltage selection module controls the current limiting voltage V P = feedback voltage V FB , the foldback current limiting function is turned on. I CL It is the general name of the current limiting value in each current limiting stage. The current limiting current I CL By the current limiting voltage V P Decide to satisfy I CL =(V P +0.5×I2×R5) / R4, the current limiting value in each working stage is described as follows: 1. Soft start stage: current limiting voltage V P =Soft start current limit voltage V SET , current limiting current I CL = Soft-start current limit I SET =(V SET+0.5×I2×R5) / R4; 2. After soft start is completed: current limiting voltage V P = feedback voltage V FB According to the different working states of the LDO chip, there are three cases: When the LDO chip is in normal load (current limit is not triggered, the output voltage is normal), the feedback voltage V FB = Bandgap reference voltage V BG , at this time the current limiting current I CL = Maximum current limit I MAX =(V BG +0.5×I2×R5) / R4; When the LDO chip triggers the current limit, the output voltage V OUT Falling, feedback voltage V FB Will decrease in proportion, at this time the current limiting current I CL = Foldback current limit I FB =(V FB +0.5×I2×R5) / R4; When the LDO chip triggers the current limit, the output voltage V OUT Continues to drop until it reaches 0V, and the LDO chip is in a short-circuit state: the feedback voltage V FB =0V, at this time the current limiting current I CL = short-circuit current I SHORT =0.5×I2×R5 / R4.

[0057] like Figure 7 As shown, the third error amplifier EA3 is composed of an operational amplifier with an asymmetric structure, and the specific components include a thirteenth transistor M p6 , the fourteenth transistor M p5 , the first depletion transistor M ndep1 , the second depletion transistor M ndep2 , tail current source I2, fifth resistor R5. thirteenth transistor M p6 The source is connected to V IN , the drain is connected to the thirteenth transistor M p6 The gate of the fourteenth transistor M p5 The gate of the first depletion transistor M ndep1 The drain of the fourteenth transistor M p5 The source is connected to V IN , the drain is connected to the second depletion transistor M ndep2 The drain is connected to V B ; First depletion mode transistor M ndep1 The gate is connected to V P The source is connected to the input end of the tail current source I2 and one end of the fifth resistor R5; the second depletion transistor M ndep2 The gate is connected to V N , the source is connected to the other end of the fifth resistor R5; the output end of the tail current source I2 is grounded.

[0058] Figure 8 Shows the change of current limit value in each stage after power on, meeting the current limit current I CL =(V P +0.5×I2×R5) / R4, where I CL It is the general name of the current limiting value in each current limiting stage; the current limiting voltage V P Different voltage values ​​correspond to different working stages; 0.5 is a fixed coefficient determined by the differential structure of the error amplifier; the tail current source I2, the fourth resistor R4, and the fourth resistor R5 are set according to the target current limit value. In this example, the current limit value is designed for an LDO chip with a load capacity of 500mA. t1~t2 is the soft start stage, and the soft start current limit I SET =(V SET +0.5×I2×R5) / R4. In this example, V SET Set to V BG t2~t3 is after the soft start is completed, the LDO chip is in the normal load stage, and the current limit value is I MAX = (V BG +0.5×I2×R5) / R4; t3~t4 is the foldback current limiting stage. After the LDO chip triggers the current limiting, the output voltage V OUT Falling, feedback voltage V FB Will decrease in proportion, return current limit value I FB =(V FB +0.5×I2×R5) / R4; t4~t5 is the short-circuit protection stage, the output voltage of the LDO chip drops to 0V, and it is in a short-circuit state. The corresponding current limiting current is the short-circuit current I SHORT =0.5×I2×R5 / R4.

[0059] like Figure 9 As shown in the simulation waveform, the waveforms from top to bottom correspond to the output voltage V OUT , Bandgap reference voltage V BG , control voltage V CTRL , load current I LOAD t1~t2 is the soft start phase. In this example, V SET =V BG , at this time the soft start current limit I SET The maximum current limit value I when the chip is in normal load after soft start is completed MAX The simulation is consistent, and the full load of 500mA can start normally, which meets the design goal; At t2, the soft start is completed, V CTRL From low level (0V) to high level (power supply voltage V IN ) controls the voltage selection module. At this time, the foldback current limiting function is turned on, and the LDO chip is in the normal load stage, corresponding to the maximum current limit value IMAX , maximum current limit value I MAX =676mA; at t3, the load current I LOAD It gradually increases and triggers the current limiting protection at time t4; t4~t5 is the foldback current limiting stage, corresponding to the foldback current limiting value I FB , as the output voltage V OUT Falling, foldback current limit value I FB Decrease; enter the short circuit protection stage at t5, the short circuit current I SHORT =121mA.

[0060] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. An LDO circuit with soft start and foldback current limiting protection, characterized in that It includes a bandgap reference module, a soft start module, a voltage selection module, a current limiting protection module, a first error amplifier EA1, an output power tube M p , the first voltage-dividing resistor R1, the second voltage-dividing resistor R2; the output of the bandgap reference module is connected to the input of the soft-start module and the first input of the voltage selection module; the two outputs of the soft-start module are connected to the second and third inputs of the voltage selection module; the fourth input of the voltage selection module is connected to the positive input of the first error amplifier EA1, one end of the first voltage-dividing resistor R1, one end of the second voltage-dividing resistor R2, and the fifth input is connected to the soft-start current limiting voltage V SET The two output terminals are connected to the negative input terminal of the first error amplifier EA1 and one input terminal of the current limiting protection module respectively; the output terminal of the first error amplifier EA1 is connected to the output terminal of the current limiting protection module and the output power tube M p The other input terminal of the current limiting protection module is connected to the other end of the second voltage divider resistor R2 and the output power tube M p The drain output V OUT The power input terminal of the bandgap reference module, the power input terminal of the current limiting protection module, the power input terminal of the first error amplifier EA1, the output power tube M p The source is connected to the input power supply V IN The ground terminal of the bandgap reference module, the ground terminal of the soft start module, the ground terminal of the current limiting protection module, the ground terminal of the first error amplifier EA1, and the other end of the first voltage divider resistor R1 are grounded; the soft start module circuit includes a voltage comparator, a first transistor M n3 , current source I CHARGE , soft start capacitor C SS , a first inverter INV1; the voltage comparator inside the soft start module is composed of an operational amplifier with an asymmetric structure, specifically including a second transistor M n1 , the third transistor M n2 , the fourth transistor M p1 , the fifth transistor M p2 , the sixth transistor M p3 , a third resistor R3, a current source I1; a sixth transistor M p3 The source is connected to the input power supply V IN , the gate is connected to the control signal V CTRL , the drain is connected to the fourth transistor M p1 The source of the fifth transistor M p2 The source of the fourth transistor M p1 The gate of the fifth transistor M p2 The gate of the fifth transistor M p2 The drain of the third transistor M n2 The drain of the second transistor M n1 The output voltage of the comparator after the drain is V COMP ; The second transistor M n1 The source is connected to one end of the third resistor R3 and the input end of the current source I1, and the gate is connected to the soft start voltage V S ; The third transistor M n2 The source is connected to the other end of the third resistor R3, and the gate is connected to the bandgap reference voltage V BG .

2. The LDO circuit according to claim 1, wherein: The negative input terminal of the voltage comparator is connected to the starting capacitor C SS One end of the current source I CHARGE The output terminal of the first transistor M n3 The positive input terminal is connected to the bandgap reference voltage V BG , the power supply terminal is connected to the input power supply V IN , the ground terminal is grounded, and the control terminal is connected to the control signal V CTRL The output end of the first inverter INV1 is connected to the input end of the first inverter INV1; the output end of the first inverter INV1 outputs the control signal V CTRL ;Soft start capacitor C SS The other end of the first transistor M n3 The source of the first transistor M is grounded; n3 The gate of the current source I is connected to the enable signal EN; CHARGE The input terminal is connected to the input power supply V IN .

3. The LDO circuit according to claim 2, wherein: The voltage selection module includes a seventh transistor M n4 , the eighth transistor M n5 , the ninth transistor M n6 , the tenth transistor M n7 , the second inverter INV2; control voltage V CTRL The input terminal of the second inverter INV2 and the seventh transistor M n4 The gate of the ninth transistor M n6 The output terminal of the second inverter INV2 outputs an inverted control voltage / V CTRL ; The seventh transistor M n4 The source is connected to V BG , the drain is connected to the eighth transistor M n5 The output reference voltage V REF ; The eighth transistor M n5 The source of the soft start voltage V S , the gate is connected to the inverting control voltage / V CTRL ; Ninth transistor M n6 The source is connected to the feedback voltage V FB , the drain is connected to the tenth transistor M n7 Output current limit setting voltage after drain V P ; Tenth transistor M n7 The source of the soft start current limiting voltage V SET , the gate is connected to the inverting control voltage / V CTRL .

4. The LDO circuit according to claim 3, wherein: The current limiting protection module comprises an output current sampling module (1) and a current limiting foldback module (2); The output current sampling module (1) comprises a second error amplifier EA2, a current sampling tube M S , the eleventh transistor M P4 The negative input terminal of the second error amplifier EA2 is connected to the current sampling tube M S The drain of the eleventh transistor M P4 The positive input terminal is connected to the output voltage V OUT , the output end is connected to the eleventh transistor M P4 The gate power supply terminal is V IN , the ground terminal is grounded; the current sampling tube M S The source is connected to V IN , the gate is connected to the output power tube M p The gate control voltage V G ; Eleventh transistor M P4 The drain of the output current sampling module (1) is used as the output terminal; The current limiting foldback module (2) includes a third error amplifier EA3, a twelfth transistor M p5 , the fourth resistor R4; the negative input terminal of the third error amplifier EA3 is connected to the output terminal of the output current sampling module (1) and one end of the fourth resistor R4, and the positive input terminal is connected to the current limiting setting voltage V P , the output terminal is connected to the twelfth transistor M p5 The gate power supply terminal is V IN , the ground terminal is grounded; the twelfth transistor M p5 The source is connected to V IN , the drain is connected to the output power tube M p The gate control voltage V G ; The other end of the fourth resistor R4 is grounded.

5. The LDO circuit according to claim 4, wherein: The first error amplifier EA1 is used to amplify the reference voltage V output by the voltage selection module. REF With the feedback voltage V FB The error signal between the output control signal V CTRL Drive output power tube M P .

6. The LDO circuit according to claim 5, wherein: When the enable signal EN changes from high level to low level, the first transistor M n3 In the cut-off state, the soft start circuit starts working; the current source I CHARGE Give the soft start capacitor C SS Charge, generate soft start voltage V S ; The bandgap reference module generates a bandgap reference voltage V BG , bandgap reference voltage V BG Input voltage comparator positive input terminal, soft start voltage V S Input the negative input terminal of the voltage comparator. When V S The voltage rises to (V BG -V TH1 ), where the threshold voltage V TH1 The soft start process is completed by the voltage comparator. At this time, the output voltage of the voltage comparator V COMP From high level to low level, V COMP Connect to the input of the first inverter INV1 and output the control signal V CTRL When high, the signal will be used to control the voltage selection module. CTRL The voltage comparator is turned off through the control terminal of the voltage comparator.

7. The LDO circuit according to claim 6, wherein: Voltage comparison threshold V TH1 Set by the current source I1 and the third resistor R3, V TH1 =0.5×R3×I1; bandgap reference voltage V BG Connect the positive input of the voltage comparator, the soft start voltage V S Connect the negative input of the voltage comparator, the output voltage of the voltage comparator is V COMP Connect the input terminal of the first inverter INV1, the control signal V CTRL Connected to transistor M p3 When the soft start is completed, the control signal V CTRL When the sixth transistor M is high, p3 In the cut-off state, the voltage comparator stops working.

8. The LDO circuit according to claim 6, wherein: The voltage selection module is the negative input voltage of the first error amplifier and the current limiting voltage V P Select voltage; control signal V CTRL The second inverter INV2 outputs the inverted control voltage / V CTRL , control signal V CTRL Connect the seventh transistor M n4 With the eighth transistor M n6 Gate, inverting control voltage / V CTRL Connect the eighth transistor M n5 With the tenth transistor M n7 gate; in the soft start phase, the control signal V CTRL Low level, inverting control voltage / V CTRL is high level, at this time the eighth transistor M n5 With the tenth transistor M n7 is turned on, the reference voltage V REF =Soft start voltage V S , current limiting voltage V P =Soft start current limit voltage V SET ; When the soft start is completed, the control signal V CTRL High level, inverting control voltage / V CTRL is low level, at this time the seventh transistor M n4 With the eighth transistor M n6 On, reference voltage V REF = Bandgap reference voltage V BG , current limiting voltage V P = feedback voltage V FB .

9. The LDO circuit according to claim 8, wherein: During the soft start phase, the current limiting voltage V P The voltage selection module controls the soft start current limiting voltage V SET , at this time, the foldback current limiting function is turned off; One end of the fourth resistor R4 is connected to the negative input terminal V of the third error amplifier EA3. N , one end is grounded; current sampling tube M S The output sampling current flows through the fourth resistor R4 to form a voltage drop. As the load current increases, the current flowing through the fourth resistor R4 increases, and then the negative input voltage V N Increase, if V N Increases to exceed the current limit voltage V P , will trigger the current limiting protection, the output voltage of the third error amplifier EA3 V B Decreases, making the output power tube M P The gate control voltage V G Rising, then the power tube M P The output current decreases, forming negative feedback to stabilize the output current value; if the negative input voltage V N If the current limit protection is not triggered, the current limiting amplifier outputs a high level, so that the twelfth transistor M P5 In the non-conducting state, the output voltage and output current of the LDO chip are still controlled by the output voltage of the first error amplifier EA1; after the soft start is completed, the current limiting voltage V is controlled by the voltage selection module. P = feedback voltage V FB , the foldback current limiting function is turned on; Current limiting current I CL The descriptions of the various work stages are as follows: Soft start stage: current limiting voltage V P =Soft start current limit voltage V SET , current limiting current I CL = Soft-start current limit I SET ; After soft start is completed: current limiting voltage V P = feedback voltage V FB ; According to the different working states of the LDO chip, including the following situations: When the LDO chip is in normal load, the feedback voltage V FB = Bandgap reference voltage V BG , at this time the current limiting current I CL = Maximum current limit I MAX ; When the LDO chip triggers the current limit, the output voltage V OUT Falling, feedback voltage V FB Will decrease in proportion, at this time the current limiting current I CL = Foldback current limit I FB ;When the LDO chip triggers the current limit, the output voltage V OUT Continues to drop until it reaches 0V, and the LDO chip is in a short-circuit state: the feedback voltage V FB =0V, at this time the current limiting current I CL = short-circuit current I SHORT .

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