Reference voltage circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a reference voltage circuit, a chip and electronic equipment, the reference voltage circuit comprises an operational amplifier module, a first output power tube, a feedback module and a zero compensation module, the first output power tube is connected with the output end of the operational amplifier module and is used for outputting a reference voltage; the feedback module is used for outputting feedback voltage according to the reference voltage; the first input end of the operational amplifier module receives band-gap reference voltage, and the second input end of the operational amplifier module is connected with the feedback module to receive feedback voltage and is used for amplifying the band-gap reference voltage; and the zero compensation module is connected with the first output power tube and is used for adjusting a zero compensation position according to the load current of the reference voltage circuit and performing zero compensation. And the zero compensation module adjusts the zero compensation position according to the load current of the reference voltage circuit and performs zero compensation, so that the phase margin requirements under light load and heavy load can be met at the same time.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a reference voltage circuit, a chip and an electronic device. Background Art

[0002] The voltage reference (VREF) circuit usually uses a bandgap reference voltage (VBG) with a weaker driving capability as the input voltage, outputs a reference voltage with a certain driving capability, and can output different reference voltage values ​​by configuring the switch position, which can be used as a reference for circuits such as analog-to-digital converters (ADC) and digital-to-analog converters (DAC), or as an input voltage for circuits such as temperature sensors.

[0003] The VREF circuit usually includes an op amp, an output power tube, a feedback voltage divider resistor, and a gear selection switch. The positive input of the op amp is the bandgap reference voltage VBG generated by the bandgap reference module, and the negative input is the feedback voltage generated by the output voltage (i.e., VREF) through the feedback network. For load capacity and noise considerations, the output of the VREF circuit is usually connected to an external load capacitor. Due to the presence of load capacitance and load resistance, there are two poles in the VREF circuit, one at the output node and the other at the gate end of the output power tube. In the related art, a zero point is formed by a compensation network composed of capacitors and resistors, and the phase attenuation of one pole is offset by the compensation network, so that only one pole exists in the bandwidth to ensure the stability of the loop. When the load capacitance is large, the main pole is located at the output node, and the position of the main pole is related to the load resistance. When the load resistance is small, the load current is large, and the position of the main pole is closer to the right than when there is no load current. The compensation network composed of capacitors and resistors has a fixed zero point. It is difficult to meet the phase margin requirements under light load and heavy load at the same time by using such a compensation network to compensate for phase attenuation. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a reference voltage circuit, a chip and an electronic device to solve the above technical problems.

[0005] In the first aspect, the embodiment of the present application provides a reference voltage circuit, including: an operational amplifier module, a first output power tube, a feedback module and a zero-point compensation module, wherein: the first output power tube is connected to the output end of the operational amplifier module and is used to output a reference voltage; the feedback module is used to output a feedback voltage according to the reference voltage; the operational amplifier module, whose first input end receives a bandgap reference voltage, and whose second input end is connected to the feedback module to receive the feedback voltage; the zero-point compensation module is connected to the first output power tube and is used to adjust the zero-point compensation position and perform zero-point compensation according to the load current of the reference voltage circuit. The zero-point compensation module adjusts the zero-point compensation position and performs zero-point compensation according to the load current of the reference voltage circuit, and can simultaneously meet the phase margin requirements under light load and heavy load.

[0006] In a second aspect, an embodiment of the present application provides a chip, comprising the above-mentioned reference voltage circuit.

[0007] In a third aspect, an embodiment of the present application provides an electronic device, including a device body and the above-mentioned chip disposed in the device body.

[0008] The reference voltage circuit, chip and electronic device provided in the embodiments of the present application, the zero-point compensation module adjusts the zero-point compensation position and performs zero-point compensation according to the load current of the reference voltage circuit, and can meet the phase margin requirements under light load and heavy load at the same time.

[0009] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A structural schematic diagram of a VREF circuit in the related art is shown.

[0012] Figure 2 A schematic structural diagram of a reference voltage circuit provided in an embodiment of the present application is shown.

[0013] Figure 3 A schematic structural diagram of a reference voltage circuit provided in an embodiment of the present application is shown.

[0014] Figure 4 A structural schematic diagram of another reference voltage circuit provided in an embodiment of the present application is shown.

[0015] Figure 5The system architecture of a reference voltage circuit according to an embodiment of the present application is shown.

[0016] Figure 6 Shows Figure 5 An exemplary circuit diagram of the operational amplifier module in FIG. DETAILED DESCRIPTION

[0017] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0018] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0019] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0020] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0021] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0022] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0023] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0024] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0025] The first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source.

[0026] In the circuit structure provided in the embodiments of the present application, the nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0027] Figure 1 FIG. 4 shows a schematic diagram of a VREF circuit in the related art. Figure 1As shown, the VREF circuit in the related art consists of an operational amplifier VREF_OP, an output power transistor MP1, a compensation network RC, a feedback network, and gear selection switches S1 and S2. Among them, the compensation network includes a compensation resistor Rc and a compensation capacitor Cc, and the feedback network includes feedback resistors R1 to R3. The positive input terminal ( Figure 1 shown as “+” in Figure 1 ) of the operational amplifier VREF_OP is the bandgap reference voltage VBG generated by the bandgap reference module, and the negative input terminal (

[0028] shown as “-” in Figure 1 ) is the feedback voltage VFB generated by the output voltage VREF through the feedback network. When different switch gears are selected, different feedback voltages ( shown as the first feedback voltage VFB1 and the second feedback voltage VFB2 in

[0029] ) can be generated to generate different VREFs. When switch S1 is closed and S2 is open, the output voltage is VREF1. According to the virtual short characteristic of the operational amplifier, Figure 1 When switch S2 is closed and S1 is open, the output voltage is VREF2. According to the virtual short characteristic of the operational amplifier, Obviously, VREF1 < VREF2. Due to the existence of the load capacitor CL and the load resistor RL, there are two poles in the VREF circuit, one at the output node (i.e., the drain terminal of the output power transistor MP1), and the other at the gate terminal of the output power transistor MP1. The compensation network Rc and Cc form a zero point. By reasonably designing the values of Rc and Cc, the phase attenuation of one pole can be offset, so that only the effect of one pole exists within the bandwidth to ensure the stability of the loop. p In the VREF circuit shown in , when the load capacitor CL is large and the main pole is at the output node, the position of the main pole is

[0030] where r Figure 1In the VREF circuit shown, when the switch S1 is closed and S2 is open, the VREF circuit outputs the first reference voltage VREF1, and the voltages of the two input terminals of VREF_OP are equal, that is, VBG is equal to the first feedback voltage VFB1. When the state of the switch S1 being closed and S2 being open is switched to the state of S2 being closed and S1 being open, that is, when the first reference voltage VREF1 is switched to the second reference voltage VREF2, the initial bandgap reference voltage VBG changes from being equal to the first feedback voltage VFB1 to being less than the second feedback voltage VFB1, and the output of VREF_OP decreases, and the output power tube MP1 charges the load capacitor CL to increase the reference voltage until the bandgap reference voltage VBG is equal to the second feedback voltage VFB2, and the reference voltage reaches the second reference voltage VREF2. In the process of increasing the reference voltage, since the output power tube MP1 can provide a large current to charge the load capacitor CL, the reference voltage increase process is established quickly.

[0031] When the switch S2 is closed and S1 is open, the VREF circuit outputs the second reference voltage VREF2, and the voltages of the two input terminals of VREF_OP are equal, that is, VBG is equal to the second feedback voltage VFB2. When the switch S2 is closed and S1 is open, the switch is switched to the S1 is closed and S2 is open, that is, when the second reference voltage VREF2 is switched to the first reference voltage VREF1, the initial VBG changes from being equal to the second feedback voltage VFB2 to being greater than the first feedback voltage VFB1, and the load capacitor CL discharges through the feedback resistors R1 to R3 and the load resistor RL to reduce the reference voltage until the bandgap reference voltage VBG is equal to the first feedback voltage VFB1.

[0032] Due to consideration of static power consumption, the feedback resistors R1~R3 ​​are usually designed to be larger to reduce branch current. Therefore, when the circuit is in a light-load state, the discharge current of the load capacitor CL is small, the reference voltage drops slowly, and a longer settling time is required.

[0033] Furthermore, when VREF is used as the reference voltage of the ADC, the output noise of VREF will be transmitted to the ADC, thereby affecting the accuracy of the ADC. Therefore, the design of the VREF circuit needs to reduce the noise as much as possible. For Σ-Δ ADCs, high-frequency noise can be limited by the oversampling rate (OSR), and the MOS tube flicker noise, which accounts for a large proportion of low-frequency noise, is inversely proportional to the area. Therefore, without taking other measures, achieving low noise in the low-frequency band requires a large area. At the same time, the increase in the area of ​​the MOS tube will also increase the parasitic capacitance.

[0034] The present application embodiment provides a reference voltage circuit, such as Figure 2As shown, the reference voltage circuit 200 of the embodiment of the present application includes an operational amplifier module 210 , an output power tube 220 , a feedback module 230 and a zero compensation module 240 .

[0035] The output power tube 220 is connected to the output end of the operational amplifier module 210, and is used to output the reference voltage VREF. The feedback module 230 is used to output the feedback voltage VFB according to the reference voltage VREF. The first input end of the operational amplifier module 210 receives the bandgap reference voltage VBG, and the second input end is connected to the feedback module 230 to receive the feedback voltage VFB. The zero point compensation module 240 is connected to the output power tube 220, and is used to adjust the zero point compensation position according to the load current of the reference voltage circuit 200 and perform zero point compensation.

[0036] Specifically, when the load current increases, the load resistance decreases, the main pole moves to the right relative to the original pole, and the zero-point compensation module 240 adjusts the zero-point compensation position to the right to offset the phase change; when the load current decreases, the load resistance increases, the main pole moves to the left relative to the original pole, and the zero-point compensation module 240 adjusts the zero-point compensation position to the left to offset the phase change.

[0037] By adopting the embodiment of the present application, the zero-point compensation module adjusts the zero-point compensation position according to the load current of the reference voltage circuit and performs zero-point compensation, which can meet the phase margin requirements under light load and heavy load at the same time.

[0038] In an embodiment of the present application, the operational amplifier module 210 may include various types of operational amplifiers, usually operational amplifiers that do not include an output power tube. The operational amplifier that does not include an output power tube is mainly used to amplify and process voltage signals, and the output power is relatively small. In the reference voltage circuit 200, a larger output power is provided by the output power tube 220. In a specific implementation, the operational amplifier module 210 may adopt a cascode amplifier, a five-transistor operational amplifier, a two-stage operational amplifier, etc., and the embodiments of the present application are not limited to this.

[0039] The feedback module 230 may include a feedback resistor. In some examples, the feedback module 230 may include multiple feedback resistors, multiple feedback circuits are connected in series to form a voltage-dividing resistor string, the voltage-dividing resistor string may include at least two voltage-dividing nodes, and each voltage-dividing node may generate a feedback voltage. The feedback module 230 may also include multiple switches, each switch is connected between a voltage-dividing node of the voltage-dividing resistor string and the second input terminal of the operational amplifier module 210.

[0040] As an implementation method, Figure 3 As shown, the output power tube 220 may include a first output power tube M21, and the zero compensation module 240 may include: a first compensation capacitor C21 and a first compensation MOS tube M22. The first output power tube M21 is used to output a reference voltage VREF, and its gate terminal is connected to the output terminal of the operational amplifier module 210, and its first terminal is connected to the first voltage terminal ( Figure 3 The first compensation MOS tube M22 has a gate terminal connected to the gate terminal of the first output power tube, a first terminal of the first compensation MOS tube M22 is connected to the first voltage terminal, and a first compensation capacitor C21 is connected between the second terminal of the first compensation MOS tube M22 and the gate terminal of the first output power tube M21.

[0041] Please continue reading Figure 3 As a typical implementation, the first output power tube M21 can be a PMOS tube, and the first compensation MOS tube M22 can be a PMOS tube. This implementation utilizes the characteristic that the on-resistance of the MOS tube working in the linear region is inversely proportional to the gate-source voltage difference (VGS). The specific working principle is as follows: Due to the load capacitance RL, the main pole of the reference voltage circuit is at the drain end of the first output power tube M21, and the secondary pole is at the gate end of the first output power tube M21. The zero point compensation at the gate end of the first output power tube M21 can change the zero point compensation position according to the load current. When the load current is light, the load current becomes smaller, the main pole moves to the left, the gate end voltage of the first output power tube M21 increases, and the gate-source voltage difference of the first compensation MOS tube M22 decreases, so that the on-resistance of the first compensation MOS tube M22 increases, so the compensation zero point also moves to the left. When the load current is heavy, the main pole moves to the right, the gate voltage of the first output power tube M21 decreases, and the gate-source voltage difference of the first compensation MOS tube M22 increases, so that the on-resistance of the first compensation MOS tube M22 decreases, and the compensation zero point also moves to the right. Therefore, the loop stability of the circuit under light load and heavy load can be guaranteed at the same time.

[0042] The present application embodiment also provides another reference voltage circuit, such as Figure 4 As shown, the reference voltage circuit 400 of the embodiment of the present application includes an operational amplifier module 410, a feedback module 430 and a zero compensation module 440. The first input terminal of the operational amplifier module 410 receives the bandgap reference voltage VBG, the second input terminal is connected to the feedback module 430 to receive the feedback voltage VFB, and the output terminal of the operational amplifier module 410 outputs the reference voltage VREF. The zero compensation module 440 is located inside the operational amplifier module 410, and is used to adjust the zero compensation position according to the load current of the reference voltage circuit 400 and perform zero compensation.

[0043] In the reference voltage circuit 400, the operational amplifier module 410 includes an output power tube, so that the operational amplifier module 410 can provide a larger output power without additionally setting an output power tube. Figure 4 , the operational amplifier module 410 may include an input stage 411, an intermediate stage 412, and an output stage 413. The first input terminal and the second input terminal are located at the input stage 411, the first input terminal receives the bandgap reference voltage VBG, and the second input terminal receives the feedback voltage VFB. Among them, the output stage 413 may include: a first output power tube M31 and a second output power tube M32. The gate terminal of the first output power tube M31 is connected to the intermediate stage 412, and the first terminal of the first output power tube M31 is connected to the first voltage terminal ( Figure 4 The gate end of the second output power tube M32 is connected to the intermediate stage 412, the first end of the second output power tube M32 is connected to the second end of the first power output MOS tube output power tube M31, and the second end of the second output power tube M32 is connected to the second voltage end ( Figure 4 The node where the first output power tube M31 and the second output power tube M32 are connected serves as the output end of the operational amplifier module 410 .

[0044] The first output power tube M31 and the second output power tube M32 are a complementary transistor pair. Figure 4 As a typical implementation, the first output power tube M31 is a PMOS tube, the second output power tube M32 is an NMOS tube, and the output stage 413 is a classAB structure. When the voltage at the first input terminal (i.e., the bandgap reference voltage) is greater than the voltage at the second input terminal (i.e., the feedback voltage), the first output power tube M31 is turned on, and the second output power tube M32 is turned off; when the voltage at the first input terminal (i.e., the bandgap reference voltage) is less than the voltage at the second input terminal (i.e., the feedback voltage), the second output power tube M32 is turned on, and the first output power tube M31 is turned off. The first output power tube M31 can charge the load capacitor during the reference voltage rising process, so that the reference voltage VREF rising process is quickly established. The second output power tube M32 can discharge the load capacitor during the reference voltage falling process, so that the reference voltage VREF falling process is also quickly established.

[0045] Specifically, it is assumed that the reference voltage includes a first reference voltage VREF1 and a second reference voltage VREF2 , and the first reference voltage VREF1 is lower than the second reference voltage VREF2 .

[0046] When the reference voltage circuit 400 outputs the first reference voltage VREF1, the voltages at the first input terminal and the second input terminal of the operational amplifier module 410 are equal, that is, the voltage at the first input terminal of the operational amplifier module 410 (bandgap reference voltage VBG) is equal to the first feedback voltage VFB1. When switching from the first reference voltage VREF1 to the second reference voltage VREF2, that is, when increasing from a lower voltage to a higher voltage, the feedback voltage changes from the larger first feedback voltage VFB1 to the smaller second feedback voltage VFB2. At this time, the voltage at the first input terminal of the operational amplifier module 410 (initial bandgap reference voltage VBG) is greater than the voltage at the second input terminal (that is, VFB2), and the first output power tube M31 is turned on. The first output power tube M31 can provide a large current to charge the load capacitor, so that the reference voltage can quickly increase from the first reference voltage VREF1 to the second reference voltage VREF2, so that the reference voltage VREF rising process is quickly established.

[0047] Further, when the reference voltage circuit 400 outputs the second reference voltage VREF2, the voltages at the first input terminal and the second input terminal of the operational amplifier module 410 are equal, that is, the voltage at the first input terminal of the operational amplifier module 410 (the bandgap reference voltage VBG) is equal to the second feedback voltage VFB2. When switching from the second reference voltage VREF2 to the first reference voltage VREF1, that is, when decreasing from a higher voltage to a lower voltage, the feedback voltage changes from the smaller second feedback voltage VFB2 to the larger first feedback voltage VFB1. At this time, the voltage at the first input terminal of the operational amplifier module 410 (the initial bandgap reference voltage VBG) is less than the voltage at the second input terminal (that is, VFB1), and the second output power tube M32 is turned on. The second output power tube M32 can discharge the load capacitor, so that the reference voltage can be quickly reduced from the second reference voltage VREF2 to the first reference voltage VREF1, so that the reference voltage VREF decrease process is also quickly established.

[0048] Please continue reading Figure 4 , the zero point compensation module 440 may include a first zero point compensation unit, whose first output power tube M31 is connected to the first zero point compensation unit. The first zero point compensation unit may include a first compensation capacitor C41 and a first compensation MOS tube M41. The gate end of the first compensation MOS tube M41 is connected to the gate end of the first output power tube M31, and the first end of the first compensation MOS tube M41 is connected to the first voltage end ( Figure 4 The first compensation capacitor C41 is connected between the second end of the first compensation MOS tube M41 and the gate end of the first output power tube M31.

[0049] Please continue reading Figure 4In some embodiments, the zero point compensation module 440 may further include a second zero point compensation unit, whose second output power tube M32 is connected to the second zero point compensation unit. The second zero point compensation unit may include: a second compensation capacitor C42 and a second compensation MOS tube M42. The gate terminal of the second compensation MOS tube M42 is connected to the gate terminal of the second output power tube M32, and its first terminal is connected to the second voltage terminal ( Figure 4 The second compensation capacitor C42 is connected between the second end of the second compensation MOS tube M42 and the gate end of the second output power tube M32.

[0050] Continuing with the aforementioned typical implementation, Figure 4 As shown, the first output power tube M31 is a PMOS tube, the second output power tube M32 is an NMOS tube, the first compensation MOS tube M41 is a PMOS tube, and the second compensation MOS tube M42 is an NMOS tube. The zero point compensation at the gate end of the first output power tube and the second output power tube can change the zero point compensation position according to the load current size.

[0051] Specifically, when the load is lightly loaded, the load current decreases, the main pole moves to the left compared to the original pole, and the current provided by the output stage 413 also decreases. At this time, the gate terminal voltage of the first output power tube M31 and the second output power tube M32 increases, the gate-source voltage difference of the first compensation MOS tube M41 and the second compensation MOS tube M42 decreases, and the on-resistance increases, so the compensation zero point also shifts to the left. When the load is heavy, the load current increases, the main pole moves to the right compared to the original pole, and the current provided by the output stage 413 also increases. At this time, the gate terminal voltage of the first output power tube M31 and the second output power tube M32 decreases, the gate-source voltage of the first compensation MOS tube M41 and the second compensation MOS tube M42 increases, and the on-resistance decreases, so the compensation zero point also shifts to the right. In summary, the zero point compensation module 440 can simultaneously ensure the loop stability of the circuit under light load and heavy load.

[0052] Figure 5 The system architecture of a reference voltage circuit according to an embodiment of the present application is shown. Figure 6 Shows Figure 5 For an exemplary circuit diagram of the operational amplifier module in Figure 5 and Figure 6 As shown, the reference voltage circuit 500 includes an operational amplifier module 510 and a feedback module 520 . Figure 5 The reference voltage circuit shown is Figure 4 A typical implementation of the reference voltage circuit 400 shown in FIG. Figure 6 The amplification module 510 shown is Figure 4 A typical implementation of the operational amplifier module 410 is shown.

[0053] refer to Figure 5As shown, as an implementation, the feedback module 520 may include a first resistor R51, a second resistor R52, and a third resistor R53, as well as a first switch S51 and a second switch S52. The first resistor R51, the second resistor R52, and the third resistor R53 are connected in series to form a voltage-dividing resistor string, and the voltage-dividing resistor string is connected between the operational amplifier module 510 and the power ground. The first switch S51 is connected to a first voltage node, which is a voltage node between the first resistor R51 and the second resistor R52, and the feedback voltage formed is VFB1; the second switch S52 is connected to a second voltage node, which is a voltage node between the second resistor R52 and the third resistor R53, and the feedback voltage formed is VFB2. The reference voltage VREF can be adjusted to the corresponding gear by turning on the first switch S51 or the second switch S52.

[0054] refer to Figure 6 As shown, the operational amplifier module 510 may include: a first input terminal VINP, a second input terminal VINN, an input stage, an intermediate stage, an output stage, and a bias circuit.

[0055] As an implementation method, Figure 6 As shown, the input stage may include a first differential MOS transistor pair 511 and a second differential MOS transistor pair 512. The first differential MOS transistor pair 511 may include a MOS transistor MP13 and a MOS transistor MP14. The second differential MOS transistor pair 512 may include a MOS transistor MN6 and a MOS transistor MN7.

[0056] As an implementation method, Figure 6 As shown, the intermediate stage may include a current mirror load 513, a floating current source 514, and a bias current source 515. The bias current source 515 generates a bias current based on a bias voltage of a bias circuit, wherein an exemplary bias circuit includes a MOS transistor MP9, a MOS transistor MP10, and a MOS transistor MN11. The bias current source 515 is used to provide a bias current to the current mirror load 513 and the floating current source 514. The floating current source 514 is used to output a first bias voltage POUTP of the first output power transistor MP1, and a second bias voltage POUTN of the second output power transistor MN1.

[0057] Please continue to refer to Figure 6As shown, the reference voltage circuit 500 may further include a chopping module. The chopping module may include: a first chopping switch unit 516, connected to the input end of the input stage, for modulating the input signal to the chopping frequency and its odd harmonic frequency; a second chopping switch unit 517, connected between the output end of the input stage and the first end of the floating current source 514, for demodulating the modulated input signal back to the fundamental frequency, and modulating the offset voltage and low-frequency noise. In some embodiments, the chopping module may further include: a third chopping switch unit 518, connected between the second end of the floating current source 514 and the current mirror load 513, for dynamically switching the MOS tube of the current mirror load 513 to reduce the noise and mismatch of the current mirror. Reference Figure 6 In the circuit shown, the input signal is modulated twice, while the low-frequency noise and offset voltage of the op amp are modulated only once, so the low-frequency noise and offset voltage are modulated to the chopping frequency and its odd harmonic frequencies. These frequency components can be filtered out by a low-pass filter, thereby achieving the effect of reducing the low-frequency noise and offset voltage. The chopping module can reduce low-frequency noise and improve the accuracy of the subsequent circuit (such as ADC) without consuming more area; it can reduce the offset voltage and keep the temperature coefficient of the reference voltage VREF consistent with the temperature coefficient of the previous bandgap reference voltage VBG.

[0058] As an implementation method, Figure 6 As shown, the output stage may include a first output power tube MP1 and a second output power tube MN1. The node where the first output power tube MP1 and the second output power tube MN1 are connected serves as the output end of the operational amplifier module 510, and the output end outputs a reference voltage. Further, the first output power tube MP1 is a PMOS tube, the second output power tube MN1 is an NMOS tube, and the output stage is a classAB structure. When the voltage at the first input end (i.e., the bandgap reference voltage) is greater than the voltage at the second input end (i.e., the feedback voltage), the first output power tube MP1 is turned on, and the second output power tube MN1 is turned off; when the voltage at the first input end (i.e., the bandgap reference voltage) is less than the voltage at the second input end (i.e., the feedback voltage), the second output power tube MN1 is turned on, and the first output power tube MP1 is turned off. When VREF is switched from a low voltage gear to a high voltage gear, a large current is provided by the first output power tube MP1 to charge the load capacitor, and the reference voltage VREF rises quickly. When the load end current changes or the voltage gear is switched, the second output power tube MN1 discharges the load capacitor, and the reference voltage VREF decreases quickly. For the specific working process, please refer to Figure 4 The description of the first output power tube M31 and the second output power tube M32 is not repeated here.

[0059] Please continue reading Figure 6The operational amplifier module 510 may further include a zero compensation module 519. The zero compensation module 519 may include: a first compensation capacitor C1 and a first compensation MOS tube MP2. The gate terminal of the first compensation MOS tube MP2 is connected to the gate terminal of the first output power tube MP1, and the first terminal of the first compensation MOS tube MP2 is connected to the first voltage terminal ( Figure 6 The first compensation capacitor C1 is connected between the second end of the first compensation MOS tube MP2 and the gate end of the first output power tube MP1.

[0060] Please continue reading Figure 6 In some embodiments, the zero compensation module 519 may further include: a second compensation capacitor C2 and a second compensation MOS transistor MN2. The gate terminal of the second compensation MOS transistor MN2 is connected to the gate terminal of the second output power transistor MN1, and the first terminal thereof is connected to the second voltage terminal ( Figure 6 The second compensation capacitor C2 is connected between the second end of the second compensation MOS transistor MN2 and the gate end of the second output power transistor MN1.

[0061] Continuing with the aforementioned typical implementation, Figure 6 As shown, the first compensation MOS tube MP2 is a PMOS tube, and the second compensation MOS tube MN2 is an NMOS tube. The zero point compensation at the gate end of the output power tube can change the zero point compensation position according to the load current. When the load current is light, the load current becomes smaller, the main pole moves to the left compared to the original pole, and the current provided by the output stage also becomes smaller. At this time, the gate terminal voltage (i.e., POUTP and POUTN) of the first output power tube MP1 and the second output power tube MN1 becomes higher, the gate-source voltage difference of the first compensation MOS tube MP2 and the second compensation MOS tube MN2 becomes smaller, and the on-resistance becomes larger, so the compensation zero point also moves to the left. When the load current is heavy, the load current becomes larger, the main pole moves to the right compared to the original pole, and the current provided by the output stage also becomes larger. At this time, the gate terminal voltage (i.e., POUTP and POUTN) of the first output power tube MP1 and the second output power tube MN1 becomes lower, the gate-source voltage of the first compensation MOS tube MP2 and the second compensation MOS tube MN2 becomes larger, and the on-resistance becomes smaller, so the compensation zero point also moves to the right. In summary, the zero point compensation module 519 can ensure the loop stability of the circuit under light load and heavy load at the same time.

[0062] In the embodiment of the present application, the compensation zero point position of the zero compensation circuit can be changed according to the load current size, while satisfying the loop stability under light load and heavy load. The op amp with classAB structure is adopted, and the NMOS tube of the output stage is used as the discharge path to accelerate the establishment of VREF. While accelerating the voltage establishment when the VREF gear is switched, the loop stability is also guaranteed within a wide load current range. The chopping module achieves better noise performance and improves the consistency of the VREF temperature coefficient with the previous stage VBG.

[0063] The embodiment of the present application also provides a chip, which includes the above-mentioned reference voltage circuit. The chip is also called an integrated circuit (IC), and the chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. The chip can meet the phase margin requirements under light load and heavy load at the same time by adjusting the zero point compensation position according to the load current of the reference voltage circuit and performing zero point compensation.

[0064] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above disposed in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights. The electronic device can simultaneously meet the phase margin requirements under light load and heavy load by adjusting the zero compensation position according to the load current of the reference voltage circuit and performing zero compensation.

[0065] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A reference voltage circuit, characterized in that: include: Operational amplifier module, first output power tube, feedback module and zero compensation module, wherein: The first output power tube is connected to the output end of the operational amplifier module and is used to output a reference voltage; The feedback module is used to output a feedback voltage according to the reference voltage; The operational amplifier module has a first input terminal receiving a bandgap reference voltage, and a second input terminal connected to the feedback module to receive the feedback voltage; The zero point compensation module is connected to the first output power tube and is used to adjust the zero point compensation position and perform zero point compensation according to the load current of the reference voltage circuit.

2. The reference voltage circuit according to claim 1, characterized in that: The zero point compensation module comprises: A first compensation capacitor; A first compensation MOS tube, whose gate terminal is connected to the gate terminal of the first output power tube, and whose first terminal is connected to the first voltage terminal; The first compensation capacitor is connected between the second end of the first compensation MOS tube and the gate end of the first output power tube.

3. The reference voltage circuit according to claim 1, wherein: The operational amplifier module includes an input stage, an intermediate stage and an output stage; The first node of the input stage serves as the first input terminal, and the second node of the input stage serves as the second input terminal; The output stage comprises: The first output power tube has a gate terminal connected to the intermediate stage and a first terminal connected to the first voltage terminal; A second output power tube, whose gate end is connected to the intermediate stage, whose first end is connected to the second end of the first output power tube, and whose second end is connected to the second voltage end; Wherein: the node where the first output power tube and the second output power tube are connected serves as the output end of the operational amplifier module.

4. The reference voltage circuit according to claim 3, characterized in that: The zero point compensation module comprises: A first zero point compensation unit, connected to the first output power tube; The second zero-point compensation unit is connected to the second output power tube.

5. The reference voltage circuit according to claim 4, characterized in that: The first zero compensation unit includes: a first compensation capacitor; a first compensation MOS tube, whose gate end is connected to the gate end of the first output power tube and whose first end is connected to the first voltage end; the first compensation capacitor is connected between the second end of the first compensation MOS tube and the gate end of the first output power tube; The second zero-point compensation unit includes: a second compensation capacitor; a second compensation MOS tube, whose gate end is connected to the gate end of the second output power tube and whose first end is connected to the second voltage end; the second compensation capacitor is connected between the second end of the second compensation MOS tube and the gate end of the second output power tube.

6. The reference voltage circuit according to any one of claims 3 to 5, characterized in that: The intermediate stage includes a floating current source, and the floating current source is used to output a first bias voltage of the first output power tube and a second bias voltage of the second output power tube; The reference voltage circuit further includes a chopping module, and the chopping module includes: A first chopping switch unit, connected to the input end of the input stage, for modulating the input signal to the chopping frequency and its odd harmonic frequencies; The second chopping switch unit is connected between the output end of the input stage and the first end of the floating current source, and is used for demodulating the modulated input signal back to the fundamental frequency and modulating the offset voltage and the low-frequency noise.

7. The reference voltage circuit according to claim 6, characterized in that: The intermediate stage further includes a current mirror load connected to the second end of the floating current source; the chopping module further includes: The third chopper switch unit is connected between the second end of the floating current source and the current mirror load, and is used for dynamically switching the current mirror load MOS tube to reduce the noise and mismatch of the current mirror.

8. The reference voltage circuit according to claim 6, wherein: The input stage comprises: A first differential MOS tube pair; A second differential MOS transistor pair has one end connected to the first differential MOS transistor pair and the other end connected to the second chopper switch unit.

9. A chip, characterized in that: The reference voltage circuit comprises any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a device body and the chip as claimed in claim 9 arranged in the device body.

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