Memory device and operating method thereof

Abstract

The storage device includes a first non-volatile memory device storing data; a first selector connected to the first non-volatile memory device; a plurality of channels connected to the first selector; and a memory controller connected to the plurality of channels, transmitting a command for sensing a state of a channel to the plurality of channels so as to transmit data to a first non-volatile memory device, receiving a channel state signal indicating whether each channel is in an idle state from the plurality of channels as a response to the command, a first channel is selected among the plurality of channels based on the channel state signal, and a channel selection signal including information of the first channel is output to a first selector such that the first selector connects the first channel and the first non-volatile memory device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0088450 filed in the Korean Intellectual Property Office on July 7, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a storage device and an operating method of the storage device. Background Art

[0004] A storage device is a device that stores data under the control of a host device such as a computer, smartphone, or smart tablet. Storage devices can include devices that store data on magnetic disks, such as hard disk drives (HDDs, hard disk drives), and devices that store data in semiconductor memories, particularly non-volatile memories, such as solid-state drives (SSDs) and memory cards.

[0005] In the storage device, the memory controller may check the state of the nonvolatile memory device, such as the ready / busy of each of the plurality of nonvolatile memory devices, so as to control the plurality of nonvolatile memory devices in the storage device. In addition, the memory controller may send a plurality of commands and data for performing read and write operations to the plurality of nonvolatile memory devices. In this case, the memory controller may include a scheduling module that schedules the sending order of the plurality of commands according to the command scheduling method so as to efficiently send the plurality of commands.

[0006] At the same time, the plurality of channels connected to the memory controller may output signals corresponding to the plurality of commands and data sent from the memory controller so as to control the operation of the plurality of nonvolatile memory devices. Since the plurality of nonvolatile memory devices are fixedly connected to each channel, when the traffic in the plurality of memories connected to one channel increases, timing loss occurs. Summary of the invention

[0007] The present disclosure is directed to increasing the utilization of channels while maintaining the size of the channels in a storage device.

[0008] The present disclosure is used to implement channel interleaving of a storage device.

[0009] The present disclosure is used to reduce the timing loss of a storage device.

[0010] A storage device according to some example embodiments includes: a first nonvolatile memory device storing data; a first selector connected to the first nonvolatile memory device; a plurality of channels connected to the first selector; and a memory controller connected to the plurality of channels, configured to: send a command for sensing states of the channels to the plurality of channels so as to send the data to the first nonvolatile memory device, receive channel state signals from the plurality of channels as a response to the command, the channel state signals indicating whether each channel is in an idle state, select a first channel among the plurality of channels based on the channel state signals, and output a channel selection signal including information of the first channel to the first selector, so that the first selector connects the first channel and the first nonvolatile memory device.

[0011] A storage device according to some example embodiments includes: a plurality of channels; a plurality of nonvolatile memory devices; and a first selector connected to a first nonvolatile memory device among the plurality of nonvolatile memory devices, configured to receive a first signal from an external memory controller and connect the first channel among the plurality of channels and the first nonvolatile memory device based on the first signal.

[0012] An operating method of a storage device according to some example embodiments includes: determining, by a memory controller based on a scheduling scheme, to send data to a first nonvolatile memory device among a plurality of nonvolatile memory devices; selecting, in order to send the data to the first nonvolatile memory device, a channel through which the data is sent among the plurality of channels connected to the memory controller, and outputting a channel selection signal including information of the selected channel; and receiving the channel selection signal by a first selector connected to the first nonvolatile memory device, and connecting the channel corresponding to the channel selection signal and the first nonvolatile memory device based on the channel selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram illustrating a storage device.

[0014] Figure 2 is a block diagram illustrating a storage device according to some example embodiments.

[0015] Figure 3 It is shown Figure 2 s memory controller's view.

[0016] Figure 4 It is shown Figure 2 A view of the memory devices.

[0017] Figure 5 is a view illustrating a selector according to some example embodiments.

[0018] Figure 6 is a timing diagram illustrating an enable signal, a ready / busy signal, and a data signal of a nonvolatile memory device during a read operation according to a comparative example.

[0019] Figure 7 is a timing diagram illustrating a channel enable signal, an enable signal of a nonvolatile memory device, a ready / busy signal, and a data signal during a read operation according to some example embodiments.

[0020] Figure 8 is a timing diagram illustrating an enable signal, a ready / busy signal, and a data signal of a nonvolatile memory device during a write operation according to a comparative example.

[0021] Fig. 9 is a timing diagram illustrating a channel enable signal, an enable signal of a nonvolatile memory device, a ready / busy signal, and a data signal during a write operation according to some example embodiments.

[0022] Fig.10 is a diagram illustrating a memory device according to some example embodiments.

[0023] Fig.11 is a diagram illustrating a memory device according to some example embodiments.

[0024] Fig.12 is a diagram illustrating a memory device according to some example embodiments.

[0025] Fig.13 is a diagram illustrating a memory device according to some example embodiments.

[0026] Fig.14 is a block diagram illustrating a storage system according to some example embodiments. DETAILED DESCRIPTION

[0027] In the following detailed description, only some example embodiments of the present disclosure are shown and described by way of illustration. As those skilled in the art will appreciate, the described example embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0028] Therefore, the drawings and description are to be considered as illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals represent the same elements. In the flowcharts described with reference to the drawings, the order of operations may be changed, several operations may be combined, some operations may be divided, and specific operations may not be performed.

[0029] In addition, unless an explicit expression such as "one" or "single" is used, an expression written in the singular may be interpreted as singular or plural. Terms including ordinal numbers such as first, second, etc. will only be used to describe various components and should not be interpreted as limiting these components. These terms may be used for the purpose of distinguishing one constituent element from other constituent elements.

[0030] Figure 1 is a block diagram illustrating a storage device.

[0031] refer to Figure 1 , the storage device 1 may store data or process data in response to an instruction from the host. For example, the storage device 1 may be a solid state drive (SSD), a smart SSD, an embedded multimedia card (eMMC), an embedded universal flash storage (UFS) memory device, a UFS memory card, a compact flash (CF), an SD (Secure Digital), a micro secure digital (Micro-SD), a mini secure digital (Mini-SD), an extreme digital (xD), or a memory stick.

[0032] The memory device 1 may include a memory controller 10 and a memory device 20. The memory controller 10 may control the operation of the memory device 1. For example, the memory controller 10 may control the operation of the plurality of nonvolatile memory devices 40 through the plurality of channels 30 based on a request from a host. For example, upon receiving a command from the host, the memory controller 10 may control each of the plurality of nonvolatile memory devices 40 through the plurality of channels 30 according to the received command.

[0033] The memory device 20 may include a plurality of channels 30 and a plurality of nonvolatile memory devices (NVM) 40_0, 40_1, ..., 40_m. For example, the memory device 20 may include four or eight channels, and two or four nonvolatile memory devices may be connected to each channel.

[0034] The plurality of channels 30 may be connected to the plurality of nonvolatile memory devices 40 and the memory controller 10. The plurality of channels 30 may output a plurality of signals for controlling operations of the plurality of nonvolatile memory devices 40 based on commands transmitted from the memory controller 10. The plurality of channels 30 may output signals corresponding to commands transmitted from the memory controller 10 so as to control operations of the plurality of nonvolatile memory devices 40. The memory controller 10 may be connected to some of the plurality of nonvolatile memory devices 40 or all of the plurality of nonvolatile memory devices 40 through the plurality of channels 30.

[0035] Each of the plurality of nonvolatile memory devices 40 may store data. In some example embodiments, each of the plurality of nonvolatile memory devices 40 may be a nonvolatile memory. In some example embodiments, the nonvolatile memory may include a NAND flash memory. Furthermore, in another embodiment, the nonvolatile memory may include an EEPROM (Electrically Erasable Programmable Read-Only Memory), a PRAM (Phase Change Random Access Memory), a ReRAM (Resistance RAM), a RRAM (Resistance Random Access Memory), a NFGM (Nano Floating Gate Memory), a PoRAM (Polymer Random Access Memory), an MRAM (Magnetic Random Access Memory), a FRAM (Ferroelectric Random Access Memory), or a memory similar thereto.

[0036] Each of the plurality of nonvolatile memory devices 40 may perform a write operation, a read operation, and / or an erase operation under the control of the memory controller 10. For example, during a write operation, the nonvolatile memory device 40 may receive a command, an address, and data from the memory controller 10 through the plurality of channels 30 and perform a write operation. During a read operation, the nonvolatile memory device 40 may receive a command and an address from the memory controller 10 through the plurality of channels 30 and output read data to the memory controller 10 through the plurality of channels 30.

[0037] However, since the plurality of nonvolatile memory devices 40_0 and 40_1 are fixedly connected to each channel (e.g., CH0), there is a problem of timing loss when the traffic from the memory controller 10 to the plurality of nonvolatile memory devices 40_0 and 40_1 increases. For example, since the memory controller 10 sends a command to the first nonvolatile memory device 40_0 and the second nonvolatile memory device 40_1 through the first channel CH0, the first channel CH0 cannot send a command to the second nonvolatile memory device 40_1 during the period in which the first channel CH0 sends a command to the first nonvolatile memory device 40_0. This is also the same in the case where other channels (e.g., CH1, CH2, ..., CHn) are not in use (i.e., in an idle state).

[0038] The present disclosure relates to a storage device for increasing the utilization of a channel while maintaining the size of the channel. The storage device may also include a selector between a non-volatile memory device and a plurality of channels, and channel interleaving may be implemented using the selector. As described above, there may be an effect of improving the memory performance of the storage device 1. Alternatively or additionally, as described above, because the performance of the storage device 1 (e.g., based on improving channel utilization and timing) has been improved, there may be an effect of improving the storage device 1 and memory performance and therefore device performance, improving power consumption by improving power utilization, etc.

[0039] Figure 2 is a block diagram illustrating a storage device according to some example embodiments.

[0040] Reference Figure 2 , a memory device 2 according to some example embodiments may include a memory controller 10 and a memory device 20. In addition, the memory device 20 may include a plurality of channels 30, a plurality of selectors 32, and a plurality of nonvolatile memory devices 40. Figure 2 It is shown that the plurality of channels 30 and the plurality of selectors 32 are included inside the memory device 20 , but are not limited thereto, and the plurality of channels 30 and the plurality of selectors 32 may be outside the memory device 20 or located inside the memory controller 10 .

[0041] In some example embodiments, the memory controller 10 may be connected to a plurality of channels 30, and the plurality of channels 30 may be connected to a plurality of selectors 32. Each selector may be connected to a plurality of channels 30, and each selector may be fixedly connected to each nonvolatile memory device (40_0, 40_1, ..., 40_m). In some example embodiments, each selector may connect one of the plurality of channels 30 to the nonvolatile memory device (40_0, 40_1, ..., 40_m) connected to the selector.

[0042] The memory controller 10 may include a scheduler 11. Figure 3 The memory controller 10 is described in detail in .

[0043] Figure 3 It is shown Figure 2 s memory controller's view.

[0044] refer to Figure 3 , the storage device 2 may include a memory controller 10 and a memory device 20, and the memory controller 10 may include a scheduler 11, a processor 12, a flash translation layer (FTL) 13, an error checking and correction (ECC) 14, a buffer memory 15 and a memory interface 16, a bus 17, etc.

[0045] The processor 12 may control the overall operation of the memory controller 10. The processor 12 may control the memory controller 10 by driving firmware loaded in the FTL 13. In some example embodiments, the processor 12 may include a central processing unit (CPU), a controller, an application specific integrated circuit (ASIC), or the like.

[0046] A flash translation layer (FTL) 13 may include firmware or software that manages data read, write, and erase operations of the nonvolatile memory device 40. The firmware in the FTL 13 may be executed by the processor 12.

[0047] The FTL 13 may perform an address mapping operation that converts a logical block address received from the host into a physical address for actually storing data in the nonvolatile memory device 40. For example, the FTL 13 may map the logical block address from the host and the physical address of the nonvolatile memory device 40 by using an address mapping table. The address mapping operation may be an operation of conversion or mapping between a logical block address managed by the host and a physical address of the nonvolatile memory device 40.

[0048] The ECC 14 is an error correction unit, and can detect and correct errors included in data read from the memory device 20 .

[0049] The buffer memory 15 may store instructions and data executed and processed by the memory controller 10. The buffer memory 15 may temporarily store data stored or to be stored in the nonvolatile memory device 40. The processor 12 may use the buffer memory 15 as a working memory of the processor 12.

[0050] The memory interface 16 may provide signal transmission / reception with the memory device 20. The memory interface 16 may transmit a command to the memory device 20 together with data to be written in the nonvolatile memory device 40, or receive data read from the memory device 20.

[0051] In addition, the memory controller 10 may include a scheduler 11. When the host requests a read, write, and erase operation to the memory controller 10, in order to efficiently send a plurality of commands for executing the requested operation to the non-volatile memory device 40, the scheduler 11 may schedule the sending order of the plurality of commands according to a predetermined (or alternatively, expected or determined) command scheduling method. In some example embodiments, the command scheduling method may refer to scheduling commands with reference to a priority of command execution. The priority of command execution may be determined based on the state of the non-volatile memory device executing the command, but is not limited thereto.

[0052] Reference Figure 4 and Figure 5 The memory device 20 of the storage device 2 is described.

[0053] Figure 4 It is shown Figure 2 A view of the memory devices. Figure 5 is a view showing a selector in a memory device.

[0054] In some example embodiments, the memory device 20 may include a plurality of channels 30, a plurality of selectors 32, and a plurality of nonvolatile memory devices 40 (such as 40_0, 40_1, ...). The command CMD, the address ADDR, and the data DATA output from the memory controller 10 may be transmitted to the nonvolatile memory devices 40_0, 40_1, ... through the channels CH0, CH1, ..., CHn in the memory device 20, and the selectors 32_0, 32_1, ...

[0055] In some example embodiments, the memory controller 10 may transmit commands, addresses, and data for performing read, write, and erase operations to the memory device 20 through the memory interface 16 according to a request of a host.

[0056] In some example embodiments, the memory interface 16 may include a signal memory 16_0 for transmitting commands, addresses, and data to the transceiver device 20 and a channel signal detector 16_1 for receiving a channel signal CH_EN indicating a channel state. In addition, the memory controller 10 may be connected to a plurality of selectors 32 through a data bus (not shown) within the memory device 2.

[0057] In some example embodiments, the channel signal detector 16_1 may perform a channel state read operation for sensing the state of at least one channel among the plurality of channels 30. For example, the memory controller 10 may send a channel state command to at least one channel among the plurality of channels through the channel signal detector 16_1. In response to the channel state command, at least one channel among the plurality of channels 30 may output a channel signal CH_EN indicating the state of the corresponding channel. For example, if the first channel CH0 is in use, that is, if the first channel CH0 is sending commands, addresses, and data to the first nonvolatile memory device 40_0, the channel signal detector 16_1 may receive a channel signal CH0_EN (e.g., a low level) indicating that the first channel CH0 is in use from the first channel CH0. For example, if the second channel CH1 is not in use, that is, the second channel CH1 does not send commands, addresses, and data to any nonvolatile memory device, the channel signal detector 16_1 may receive a channel signal CH1_EN (e.g., a high level) indicating that the second channel CH1 is in an idle state from the second channel CH1.

[0058] In some example embodiments, the scheduler 11 may schedule the transmission order of multiple commands according to a predetermined (or alternatively, expected or determined) command scheduling scheme. In some example embodiments, the command scheduling scheme may be determined based on the state of the non-volatile memory device 40. In some example embodiments, the scheduler 11 may determine the order of sending commands based on the ready / busy state of the non-volatile memory device 40. For example, when the host requests the memory controller 10 to perform an operation such as read or write, the memory controller 10 may check the state of the non-volatile memory device. That is, the memory controller 10 may perform a status read operation to check the state of the multiple non-volatile memory devices 40. At this time, if the first non-volatile memory device 40_0 is in a busy state and the second non-volatile memory device 40_1 is in a ready state, the scheduler 11 may schedule the memory controller 10 to first send a command to the second non-volatile memory device 40_1.

[0059] In some example embodiments, if the scheduler 11 determines the priority of the command based on the state of the nonvolatile memory device 40, the memory controller 10 may transmit the command and data to the nonvolatile memory device 40 through the channel 30 and the selector 32 according to the determined priority. Hereinafter, a process of transmitting the command and data from the memory controller 10 to the nonvolatile memory device 40 through the channel 30 and the selector 32 will be described in detail.

[0060] In some example embodiments, if the channel signal detector 16_1 of the memory controller 10 transmits a channel status command to at least one of the plurality of channels 30, in response thereto, at least one of the plurality of channels 30 may output a channel signal CH_EN indicating a status of the corresponding channel. In some example embodiments, the memory controller 10 may select channels CH0, CH1, . . . , CHn based on the channel signal CH_EN received by the channel signal detector 16_1 to transmit commands, addresses, and data to the nonvolatile memory device 40. For example, if the channel signal detector 16_1 of the memory controller 10 receives a high level channel signal CH0_EN indicating that the first channel CH0 is in an idle state, the memory controller 10 may transmit a command to the first nonvolatile memory device 40_0 using the first channel CH0.

[0061] In some example embodiments, the memory controller 10 may transmit a command, an address, and data to the nonvolatile memory device 40 through the channel 30 by using the selector 32. Figure 5 The structure and method of operation of the selector 32 are described in further detail.

[0062] refer to Figure 5, the selector 32 may be connected to each nonvolatile memory device 40 (such as 40_0, 40_1, ...) and a plurality of channels CH. For example, the first selector 32_0 may include a first interface 90_0 including a plurality of pins for receiving signals corresponding to commands, addresses, and data from a plurality of channels CH0, CH1, ..., CHn, and a second interface 31_0 including pins P31_0, ..., P38_0 for transmitting signals corresponding to commands, addresses, and data transmitted from the selected channel to the nonvolatile memory device 40_0.

[0063] In some example embodiments, if the channel signal detector 16_1 of the memory controller 10 receives the channel signal CH_EN from a channel in an idle state, the memory controller 10 may transmit a channel selection signal SEL indicating the selection of the corresponding channel by the selector through the data bus within the memory device 2. For example, when the channel signal detector 16_1 of the memory controller 10 receives the channel signal CH0_EN of a high level indicating that the first channel CH0 is in an idle state, based on the channel signal CH0_EN, the memory controller 10 may transmit the channel selection signal SEL to the first selector 32_0 connected to the first nonvolatile memory device 40_0, and indicate that the first nonvolatile memory device 40_0 and the first channel CH0 are connected. The selection unit 100_0 of the first selector 32_0 may select the first channel CH0 from the plurality of channels 30 based on the channel selection signal SEL, and transmit the plurality of signals transmitted from the first channel CH0 to the first nonvolatile memory device 40_0 through the plurality of pins P31_0, ..., P38_0.

[0064] In some example embodiments, the memory device 2 including the selector 32 may increase channel utilization while maintaining the channel size of the memory device 20. For example, as described above, when the memory controller 10 sends a command, an address, and data to the first nonvolatile memory device 40_0 through the first channel CH0, the memory controller 10 may also send a command to the second nonvolatile memory device 40_1 based on a request from the host. When the memory controller 10 receives a request from the host, the memory controller 10 may send a channel status command to at least one of the plurality of channels 30 through the channel signal detector 16_1. The channel signal detector 16_1 may receive a channel signal CH1_EN indicating that the second channel CH1 is in an idle state from the second channel CH1 and a channel signal CH0_EN indicating that the first channel CH0 is in use from the first channel CH0. Based on the channel signal CH1_EN, the memory controller 10 may send a channel selection signal SEL to the second selector 32_1 connected to the second nonvolatile memory device 40_1 and indicate that the second nonvolatile memory device 40_1 and the second channel CH1 are connected. The selection unit 100_1 of the second selector 32_1 can select the second channel CH1 from the plurality of channels 30 based on the channel selection signal SEL, and transmit the plurality of signals transmitted from the second channel CH1 to the second non-volatile memory device 40_1 through the plurality of pins P31_1, ..., P38_1. In this way, the memory device 2 including the selector 32 can implement channel interleaving by increasing the utilization of the channel while maintaining the size of the channel. As described above, there may be an effect of improving memory performance and / or reducing the size of the memory device 1. Alternatively or additionally, as described above, because the size of the memory device 1 (e.g., based on improving channel utilization and timing) has been reduced, there may be an effect of improving the memory device 1 and memory performance and therefore device performance, improving power consumption by improving power utilization, etc.

[0065] Reference again Figure 4 In some example embodiments, the plurality of channels 30 may include a controller interface 70 (such as 70_1, 70_2, ..., 70_n) including a plurality of pins for receiving commands, addresses, and data from the memory controller 10 to control the plurality of nonvolatile memory devices 40. The plurality of channels 30 may include a selector interface 80 including a plurality of pins for transmitting signals corresponding to the commands, addresses, and data received from the memory controller 10 to the selector 32. The selector interface 80 may include a plurality of pins P81_0, ..., P88_0 for transmitting and receiving signals with the plurality of nonvolatile memory devices 40_0, 40_1, ...

[0066] In some example embodiments, the nonvolatile memory device 40_0 may include a memory internal interface 41_0 , a control logic 50_0 , and a memory cell array 60_0 .

[0067] In some example embodiments, the memory internal interface 41_0 may receive a chip enable signal CE through the first pin P41_0. The chip enable signal CE may be a signal for the memory controller 10 to indicate a specific nonvolatile memory device 40_0 among the plurality of nonvolatile memory devices 40 connected to the memory controller 10.

[0068] In some example embodiments, the memory internal interface 41_0 in the nonvolatile memory device 40_0 selected according to the chip enable signal CE may use the second pin P42_0, the third pin P43_0, the fourth pin P44_0, the fifth pin P45_0, the sixth pin P46_0, the seventh pin P47_0, and the eighth pin P48_0 to transmit and receive signals with the memory controller 10. For example, the memory internal interface 41_0 in the nonvolatile memory device 40_0 that receives the chip enable signal CE in an enable state (e.g., a low level) may transmit and receive signals with the memory controller 10 through the second pin P42_0 to the eighth pin P48_0.

[0069] The memory internal interface 41_0 may receive the command latch enable signal CLE through the second pin P42_0.

[0070] The command latch enable signal CLE may be a signal indicated by the memory controller 10 to the nonvolatile memory device 40_0 so that a command provided to the nonvolatile memory device 40_0 through the seventh pin P47_0 is loaded into a command register of the nonvolatile memory device 40_0. The command register may store a command received from the memory controller 10.

[0071] The memory internal interface 41_0 may receive the address latch enable signal ALE through the third pin P43_0.

[0072] The address latch enable signal ALE may be a signal indicated by the memory controller 10 to the nonvolatile memory device 40_0 so that the address provided to the nonvolatile memory device 40_0 through the seventh pin P47_0 is loaded into the address register by the nonvolatile memory device 40_0. The address register may store the address received from the memory controller 10.

[0073] The memory internal interface 41_0 may receive the write enable signal nWE through the fourth pin P44_0 .

[0074] The write enable signal nWE may be a signal indicated by the memory controller 10 to the nonvolatile memory device 40_0 in order to transmit a command, an address, and data from the memory controller 10 to the nonvolatile memory device 40_0 .

[0075] The memory internal interface 41_0 may receive the read enable signal nRE through the fifth pin P45_0 .

[0076] The read enable signal nRE may be a signal indicated by the memory controller 10 to the nonvolatile memory device 40_0 in order to transmit data from the nonvolatile memory device 40_0 to the memory controller 10 .

[0077] The memory internal interface 41_0 may receive the data strobe signal DQS through the sixth pin P46_0.

[0078] The memory controller 10 or the nonvolatile memory device 40_0 may receive the data signal DQ or transmit the data signal DQ in synchronization with the data strobe signal DQS.

[0079] The memory internal interface 41_0 may receive the data signal DQ through the seventh pin P47_0.

[0080] As described above, the data signal DQ may include a command, an address, and data. In some example embodiments, the data signal DQ may be transmitted through a plurality of data signal lines.

[0081] Figure 4 It is shown that the data signal DQ is sent and received through one seventh pin P47_0, but the present disclosure is not limited thereto, and the data signal DQ may be sent and received through a plurality of pins. Hereinafter, the pin for sending and receiving the data signal DQ is referred to as a data pin. For example, the memory internal interface circuit 41_0 may include eight data pins to send and receive 8-bit data, and each of the plurality of pins may send and receive 1-bit data.

[0082] The memory internal interface 41_0 can output a ready / busy signal R / B through the eighth pin P48_0. The memory internal interface circuit 41_0 can send the state data of the nonvolatile memory device 40_0 to the memory controller 10 through the ready / busy output signal R / B. At this time, the eighth pin P48_0 can be called a state output pin of the nonvolatile memory device 40_0.

[0083] The control logic 50_0 may generally control various operations of the nonvolatile memory device 40_0. The control logic 50_0 may receive a command CMD and an address ADDR acquired from the memory internal interface 41_0. The control logic 50_0 may generate a control signal for controlling other constituent elements within the nonvolatile memory device 40_0 according to the received command CMD and address ADDR. For example, the control logic 50_0 may generate various control signals for writing data DATA into each memory cell array 60_0 or reading data DATA from each memory cell array 60_0.

[0084] In some example embodiments, the memory cell array 60_0 may store data DATA acquired from the memory internal interface circuit 41_0 under the control of the control logic 50_0. Each of the memory cell arrays 60_0 may output the stored data DATA to the memory internal interface circuit 41_0 under the control of the control logic 50_0.

[0085] The memory cell array 60_0 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells may be resistive random access memory (RRAM) cells, ferroelectric random access memory (FRAM) cells, phase change random access memory (PRAM) cells, thyristor random access memory (TRAM) cells, magnetic random access memory (MRAM) cells. Hereinafter, some exemplary embodiments of the present disclosure will be described focusing on some exemplary embodiments in which the memory cells are NAND flash memory cells.

[0086] Figure 6 is a timing diagram illustrating an enable signal, a ready / busy signal, and a data signal shown in a nonvolatile memory device during a read operation according to a comparative example.

[0087] For example, Figure 6 It shows that according to Figure 1 1 is a timing diagram of an enable signal, a ready / busy signal, and a data signal of a nonvolatile memory device 40_0 and 40_1 of a storage device of FIG. Here, for ease of understanding, channel signals CH0_EN and CH1_EN are shown, and hereinafter, the description of the nonvolatile memory devices 40_0 and 40_1 can also be applied to the nonvolatile memory device 40_m.

[0088] First, at t601, if the host requests the memory controller 10 to perform a read operation, the memory controller 10 may send a read command 601 to the first nonvolatile memory device 40_0 based on the state of the nonvolatile memory device 40. If the memory controller 10 sends the read command to the first nonvolatile memory device 40_0, the chip enable signal CE of the first nonvolatile memory device 40_0 may be turned into an enable level (e.g., a low level).

[0089] exist Figure 1 In the embodiment, since the first nonvolatile memory device 40_0 is connected to the memory controller 10 through the first channel CH0, the first channel CH0 may send a first command 6001 to the first nonvolatile memory device 40_0 through the first data signal DQ based on the command of the memory controller 10 during the period when the chip enable signal CE is maintained at a low level. The first command 6001 may include an address ADDR and a read command of a memory array in the first nonvolatile memory device 40_0. When the first command 6001 is sent to the first nonvolatile memory device 40_0 (t601 to t603), the first channel CH0 is in use. Therefore, the channel signal CH0_EN may be turned into a low level.

[0090] At t603, in response to receiving the first command 6001, the first nonvolatile memory device 40_0 may perform an internal operation for preparing data corresponding to the received first command 6001. That is, at t603, the state signal RnB of the first nonvolatile memory device 40_0 may transition to a busy state (e.g., a low level), and the chip enable signal CE of the first nonvolatile memory device 40_0 may transition from a low level to a high level.

[0091] Meanwhile, at t603, if the host requests the memory controller 10 to perform a read operation, the memory controller 10 may send a read command 603 to the second nonvolatile memory device 40_1 based on the state of the nonvolatile memory device 40. If the memory controller 10 sends the read command to the second nonvolatile memory device 40_1, the chip enable signal CE of the second nonvolatile memory device 40_1 may be turned to an enable level (e.g., a low level).

[0092] exist Figure 1In the embodiment, since the second nonvolatile memory device 40_1 is connected to the memory controller 10 through the first channel CH0, and the chip enable signal CE is kept at a low level, the first channel CH0 can send a second command 6003 to the second nonvolatile memory device 40_1 through the second data signal DQ based on the command of the memory controller 10. While the second command 6003 is sent from the memory controller 10 to the second nonvolatile memory device 40_1 (t603 to t605), the first channel CH0 is in use. Therefore, the channel signal CH0_EN can be at a low level.

[0093] At t605, in response to receiving the second command 6003, the second nonvolatile memory device 40_1 may perform an internal operation to prepare data corresponding to the received second command 6003. When the second nonvolatile memory device 40_1 is performing the internal operation (t605 to t609), the state signal RnB of the second nonvolatile memory device 40_1 may transition to a busy state (e.g., a low level), and since the first channel CH0 is not in use, the channel signal CH0_EN may transition to a high level indicating an idle state.

[0094] When the second nonvolatile memory device 40_1 is performing an internal operation (t605 to t609), at t607, when the internal operation of the first nonvolatile memory device 40_0 is completed, the read first data 6005 may be transmitted through the first channel CH0 to the memory controller 10. Therefore, since the first channel CH0 is in use, the channel signal CH0_EN may transition to a low level again.

[0095] While the first data 6005 is being transferred from the first nonvolatile memory device 40_0 to the memory controller 10 , internal operations of the second nonvolatile memory device 40_1 may be completed at t609 .

[0096] At t607 to t611, since the first data 6005 read from the first nonvolatile memory device 40_0 is transmitted to the memory controller 10 through the first channel CH0, the read second data 6007 cannot be transmitted to the memory controller 10 at time t609 when the internal operation of the second nonvolatile memory device 40_1 is completed. That is, the second nonvolatile memory device 40_1 may transmit the second data 6007 to the memory controller 10 after time t611 when the transmission of the first data 6005 is completed. Therefore, in the operation of transmitting the read second data 6007 to the memory controller 10, a timing loss may occur as much as, for example, time t609 to t611.

[0097] Meanwhile, at t611 to t613, while the second data 6007 read from the second nonvolatile memory device 40_1 is transmitted to the memory controller 10 through the first channel CH0, at t611, the memory controller 10 may transmit a read command 611 to the first nonvolatile memory device 40_0 based on the request of the host. In addition, at t613, the memory controller 10 may also transmit a read command 613 to the second nonvolatile memory device 40_1 based on the request of the host.

[0098] Since the first nonvolatile memory device 40_0 and the second nonvolatile memory device 40_1 are connected to the memory controller 10 through the first channel CH0, the first channel CH0 may transmit the third command 6009 to the first nonvolatile memory device 40_0 based on the command of the memory controller 10 after the time t613 when the transmission of the second data 6007 is completed. And the first channel CH0 may transmit the fourth command 6011 to the second nonvolatile memory device 40_1 based on the command of the memory controller 10 after the time t615 when the transmission of the third command 6009 is completed. That is, in the operation of transmitting the command from the memory controller 10 to the first nonvolatile memory device 40_0 and the second nonvolatile memory device 40_1, a timing loss may occur as much as, for example, the time t611 to t613 or the time t613 to t615.

[0099] As described above, since the first nonvolatile memory device 40_0 and the second nonvolatile memory device 40_1 are fixedly connected to the first channel CH0, if the traffic to the first nonvolatile memory device and the second nonvolatile memory device increases, there is a problem that timing loss occurs during the operation of the memory device. This has a problem in that the utilization rate of the channel is reduced because even when another channel (for example, the second channel CH1) is not used, that is, in an idle state, it cannot be used.

[0100] Figure 7 is a timing diagram illustrating a channel enable signal, an enable signal of a nonvolatile memory device, a ready / busy signal, and a data signal during a read operation according to some example embodiments.

[0101] At t701, when the host requests the memory controller 10 to perform a read operation, the memory controller 10 may send a read command 701 to the first nonvolatile memory device 40_0 based on the state of the nonvolatile memory device 40. At this time, the memory controller 10 may send a channel status command to at least one of the multiple channels, and receive a channel signal CH0_EN indicating that the first channel CH0 is in an idle state as a response thereto. The memory controller 10 may send a channel selection signal SEL indicating that the first channel CH0 is selected to the first selector 32_0 connected to the first nonvolatile memory device 40_0. The first selector 32_0 may receive a signal corresponding to the command sent from the memory controller 10 from the first channel CH0 based on the channel selection signal SEL to send to the first nonvolatile memory device 40_0. Here, the time required for the memory controller to send the channel status command to receive the channel signal and send the channel selection signal to the selector, i.e., the waiting time, may be negligible.

[0102] If the first selector 32_0 transmits a signal from the first channel CH0 to the first nonvolatile memory device 40_0, the chip enable signal CE of the first nonvolatile memory device 40_0 may be turned into an enable level (e.g., a low level). While the chip enable signal CE of the first nonvolatile memory device 40_0 remains at a low level, the first channel CH0 may transmit a first command 700I to the first nonvolatile memory device 40_0 through the first data signal DQ based on a command of the memory controller 10. When the first command 7001 is transmitted from the first channel CH0 to the first nonvolatile memory device 40_0, since the first channel CH0 is in use, the channel signal CH0_EN may be turned into a low level.

[0103] At t703, when the host requests the memory controller 10 to perform a read operation, the memory controller 10 may send a read command 703 to the second non-volatile memory device 40_1 based on the state of the non-volatile memory device 40. At this time, the memory controller 10 may send a channel state command to at least one of the multiple channels, and receive a channel signal CH1_EN indicating that the second channel CH1 is in an idle state as a response thereto. The memory controller 10 may send a channel selection signal SEL indicating that the second selector 32_1 selects the second channel CH1. The second selector 32_1 may receive a signal corresponding to the command sent from the memory controller 10 from the second channel CH1 based on the channel selection signal SEL, and transmit the signal to the second non-volatile memory device 40_1. When the second command 7003 is sent from the second channel CH1 to the second non-volatile memory device 40_1, since the second channel CH1 is in use, the channel signal CH1_EN may be turned into a low level.

[0104] At t707, the first data 7005 read in response to the first command 7001 may be transmitted from the first nonvolatile memory device 40_0 to the memory controller 10 through the first channel CH0. When the first data 7005 is transmitted to the memory controller 10, since the first channel CH0 is in use, the channel signal CH0_EN may transition to a low level again.

[0105] At t709, the second data 7009 read in response to the second command 7003 may be transmitted from the second nonvolatile memory device 40_1 to the memory controller 10 through the second channel CH1. That is, regardless of the state of the first channel CH0, the second nonvolatile memory device 40_1 may transmit data to the memory controller 10. Therefore, no timing loss occurs during the operation of the memory device.

[0106] Next, commands 7007 and 7011 transmitted from the memory controller 10 to the nonvolatile memory device may also be transmitted to the nonvolatile memory device through the channel selected based on the state of the channel.

[0107] Figure 8 is a timing diagram illustrating an enable signal, a ready / busy signal, and a data signal of a nonvolatile memory device during a write operation according to a comparative example.

[0108] In detail, Figure 8 is based on Figure 1 1 is a timing diagram of an enable signal, a ready / busy signal, and a data signal of a nonvolatile memory device 40_0 and 40_1 of a storage device of FIG. Here, for better understanding, channel signals CH0_EN and CH1_EN are shown.

[0109] First, at t801, when the host requests the memory controller 10 to perform a write operation, the memory controller 10 may send a write command 801 to the first nonvolatile memory device 40_0 based on the state of the nonvolatile memory device 40. If the memory controller 10 sends the write command to the first nonvolatile memory device 40_0, the chip enable signal CE of the first nonvolatile memory device 40_0 may be turned into an enable level (e.g., a low level).

[0110] exist Figure 1In the embodiment, since the first nonvolatile memory device 40_0 is connected to the memory controller 10 through the first channel CH0, and the chip enable signal CE is kept at a low level, the first channel CH0 can send a first command 8001 and first data 8003 to the first nonvolatile memory device 40_0 through the first data signal DQ based on the command of the memory controller 10. The first command 8001 and the first data 8003 may include an address ADDR, a write command, and data of a memory array in the first nonvolatile memory device 40_0. When the first command 8001 and the first data 8003 are transmitted to the first nonvolatile memory device 40_0 (t801 to t805), the first channel CH0 is in use. Therefore, the channel signal CH0_EN may be turned into a low level.

[0111] At t803, when the host requests the memory controller 10 to perform a write operation, the memory controller 10 may send a write command 803 to the second nonvolatile memory device 40_1 based on the state of the nonvolatile memory device 40. However, since the first channel CH0 is in use at t803, the command cannot be sent through the first channel CH0.

[0112] At t805, if the transmission of the data to the first nonvolatile memory device 40_0 is completed, the first channel CH0 may transmit a second command 8005 and second data 8007 to the second nonvolatile memory device 40_1 based on the command of the memory controller 10. That is, in the operation of transmitting the command from the memory controller 10 to the second nonvolatile memory device 40_1, a timing loss may occur as much as, for example, time t803 to t805.

[0113] Meanwhile, at t807, the memory controller 10 may transmit a write command 807 to the first nonvolatile memory device 40_0 based on the request of the host. However, at t807, since the second nonvolatile memory device 40_1 receives the second data 8007 from the first channel CH0, the first channel CH0 may transmit the address, command, and data 8009 and 8011 to the first nonvolatile memory device 40_0 after time t809 when the transmission of the second data 8007 is completed. That is, in the operation of transmitting the third command 8009 from the memory controller 10 to the first nonvolatile memory device 40_0, a timing loss may occur as much as, for example, time t807 to t809.

[0114] In this way, when a plurality of nonvolatile memory devices 40_0 and 40_1 are fixedly connected to one channel CH0, there is a problem in that timing loss occurs as traffic to the nonvolatile memory devices 40_0 and 40_1 increases.

[0115] Fig. 9 is a timing diagram illustrating a channel enable signal, an enable signal of a nonvolatile memory device, a ready / busy signal, and a data signal during a write operation according to some example embodiments.

[0116] At t901, when the host requests the memory controller 10 to perform a write operation, the memory controller 10 may send a write command 901 to the first nonvolatile memory device 40_0 based on the state of the nonvolatile memory device 40. At this time, the memory controller 10 may send a channel status command and receive a channel signal CH0_EN indicating that the first channel CH0 is in an idle state as a response thereto. The memory controller 10 may send a channel selection signal SEL indicating that the first channel CH0 is selected to the first selector 32_0 connected to the first nonvolatile memory device 40_0. The first selector 32_0 may receive a signal corresponding to the command sent from the memory controller 10 from the first channel CH0 based on the channel selection signal SEL, and send the signal to the first nonvolatile memory device 40_0. When the first command 9001 and the first data 9003 are sent to the first nonvolatile memory device 40_0, since the first channel CH0 is in use, the channel signal CH0_EN may be turned into a low level.

[0117] At t903, if the host requests the memory controller 10 to perform a write operation, the memory controller 10 may send a write command 903 to the second nonvolatile memory device 40_0 based on the state of the nonvolatile memory device 40. At this time, the memory controller 10 may send a channel status command and receive a channel signal CH1_EN indicating that the second channel CH1 is in an idle state as a response thereto. The memory controller 10 may send a channel selection signal SEL indicating that the second channel CH1 is selected to the second selector 32_1. The second selector 32_1 may receive a signal corresponding to the command sent from the memory controller 10 from the second channel CH2 based on the channel selection signal SEL, and send the signal to the second nonvolatile memory device 40_1.

[0118] That is, in the period t903 to t905, the first nonvolatile memory device 40_0 can receive the first data 9003 from the first channel CH0, and the second nonvolatile memory device 40_1 can receive the second command 9005 and the second data 9007 from the second channel CH1. Therefore, no timing loss occurs during the operation of the memory device. This is also the same for the operation of commands 909 and 911 sent from the memory controller 10 thereafter.

[0119] like Figure 7 and Fig. 9As shown, the memory device according to some example embodiments has the advantage of reducing timing loss by increasing channel utilization and achieving channel interleaving.

[0120] Fig.10 is a diagram illustrating a memory device according to some example embodiments.

[0121] In some example embodiments, when a sequential / random workload is generated at the request of a user, the host may generate a sequential / random workload at the request of a user through a processor ( Figure 3 The memory controller 10 may further include a memory 12 of the processor 10 that executes a process corresponding to a sequential / random workload. The sequential / random workload may be a pattern of a process executed by a processor. In some example embodiments, the memory controller 10 may further include a workload signal SEL0 that notifies a pattern of the workload to the selector 32 based on the workload.

[0122] Reference together Figure 1 In the case of a sequential read / write operation, since commands are sequentially assigned to the plurality of nonvolatile memory devices 40, the memory device 20 can execute the command sent from the memory controller 10 without a timing loss. That is, the plurality of nonvolatile memory devices can be connected to a predetermined (or alternatively, desired or determined) channel without connecting the selector 32. However, in the case of a random read / write operation, since commands are randomly assigned to the plurality of nonvolatile memory devices 40, when the traffic in a specific nonvolatile memory device 40 increases, a timing loss may occur depending on the state of the channel 30.

[0123] refer to Fig.10 In some example embodiments, the selector 32 may change the connection mode between the nonvolatile memory device 40 and the channel 30 according to whether the workload is sequential or random. For example, when the memory controller 10 sends a workload signal SEL0 (e.g., a low level) indicating that the workload is sequential to the plurality of selectors 32 through the data bus, the plurality of selectors 32 may connect the nonvolatile memory device 40 to the predetermined (or alternatively, desired or determined) channels CH0, CH1, . . . , CHn, as shown in FIG. Figure 1 That is, the first selector 32_0 can connect the pins connected to the first channel CH0 among the plurality of pins in the first interface 90_0 to the first nonvolatile memory device 40_0 through the pins P31_0, ..., P38_0 in the second interface 31_0, and the second selector 32_1 can connect the pins connected to the first channel CH0 among the plurality of pins in the first interface 90_1 to the second nonvolatile memory device 40_1 through the pins P31_1, ..., P38_1 in the second interface 31_1.

[0124] As another example, if the memory controller 10 sends a workload signal SEL0 (eg, a high level) indicating that the workload is random to the plurality of selectors 32 through the data bus, similar to Figure 4 In the structure, multiple selectors 32 can be connected to multiple channels 30 in the memory device 20. That is, in order to send a command to the first nonvolatile memory device 40_0, the first selector 32_0 can connect the idle channels CH0, CH1, ..., CHn and the first nonvolatile memory device 40_0 based on the channel selection signal SEL1.

[0125] Fig.11 is a diagram illustrating a memory device according to some example embodiments.

[0126] refer to Fig.11 , some nonvolatile memory devices 40_0, 40_1, ..., 40_N among the multiple nonvolatile memory devices are fixedly connected to some channels CH0, CH1, ... among the multiple channels, and some nonvolatile memory devices 40_(m-3), 40_(m-2), ... among the multiple nonvolatile memory devices can be connected to some channels CH(n-1) and CHn among the multiple channels through selectors 32_(k-3), 32_(k-2), ...

[0127] In some example embodiments, some nonvolatile memory devices 40_0, 40_0, . . . fixedly connected to some channels CH0, CH1, . . . may be connected to Figure 1 The memory device 1 of FIG. 1 operates in the same manner as the memory device 1 of FIG. 1 , and some nonvolatile memory devices 40_(m-3), 40_(m-2), ... dynamically connected to some channels CH(n-1) and CHn through selectors 32_(k-3), 32_(k-2), ... can be connected to some channels CH(n-1) and CHn through selectors 32_(k-3), 32_(k-2), ... Figure 4 The storage device 2 operates similarly.

[0128] Fig.12 is a diagram illustrating a memory device according to some example embodiments

[0129] refer to Fig.12 , some nonvolatile memory devices 40_0, 40_1, ..., 40_(m-1) among the multiple nonvolatile memory devices are fixedly connected to some channels CH0, CH1, ..., CH_(n-1) among the multiple channels, and the first nonvolatile memory device 40_m among the multiple nonvolatile memory devices can be connected to the multiple channels CH0, ..., CHn through the selector 32.

[0130] In some example embodiments, in order to control the nonvolatile memory devices 40_0, ..., 40_(m-1) fixedly connected to the channels CH0, ..., CH(n-1), some channels among the multiple channels CH0, CH1, ..., CH(n-1) may output signals corresponding to commands sent from the memory controller 10.

[0131] In some example embodiments, the selector 32 may be connected to a plurality of channels CH0, ..., CHn, and may be fixedly connected to a first nonvolatile memory device 40_m among a plurality of nonvolatile memory devices. The memory controller 10 may send an operation command to the first nonvolatile memory device 40_m based on the state of the nonvolatile memory device 40. The memory controller 10 may send a channel state command to at least one channel among the plurality of channels, and receive a channel signal CH0_EN, ..., CH_EN as a response thereto. The memory controller 10 may control the operation of the first nonvolatile memory device 40 through one channel among the plurality of channels CH0, ..., CHn based on the channel signal.

[0132] according to Fig.11 and Fig.12 The memory device 20 has an advantage of reducing costs by optimizing the number of selectors 32 and data lines connected to the selectors.

[0133] Fig.13 is a diagram illustrating a memory device according to some example embodiments.

[0134] refer to Fig.13 , channels CH0, ..., CHn and non-volatile memory devices 40_0, ..., 40_m satisfy Figure 1 That is, this may be a structure in which a plurality of nonvolatile memory devices 40_0, ..., 40_m are fixedly connected to each channel CH0, ..., CHn. However, in some example embodiments, in the case where a plurality of channels CH0, ..., CHn are all in use, an additional channel CH(n+1) may be further added. For example, when a command is sent from the memory controller 10 to the nonvolatile memory devices 40_0, ..., 40_m, if all of the plurality of channels CH0, ..., CHn are in use, the command may be sent through at least one additional channel CH(n+1) to reduce timing loss.

[0135] In some example embodiments, in addition to the memory internal interfaces 41_0, 41_1, ..., 42_m, the nonvolatile memory devices 40_0, ..., 40_m may further include internal interfaces 42_0, 42_1, ..., 42_m. Hereinafter, each is referred to as a first memory internal interface 41_0, 41_1, ..., 41_m and a second memory internal interface 42_0, 42_1, ..., 42_m.

[0136] In some example embodiments, the selector (32_0, 32_1, ..., 32_m) may be connected to the extra channel (CH(n+1)) and may be fixedly connected to the second memory internal interface (42_0, 42_1, ..., 42_m) of the plurality of nonvolatile memory devices. When the memory controller 10 wants to send a command to the first nonvolatile memory device 40_0, in a case where all the plurality of channels CH0, ..., CHn are in use, for example, in a case where a chip enable (CE) signal of at least one nonvolatile memory device among the plurality of nonvolatile memory devices connected to each channel CH0, ..., CHn is an enable level, or in a case where at least one nonvolatile memory device among the plurality of nonvolatile memory devices connected to each channel CH0, ..., CHn is in a busy state, the memory controller 10 may use the extra channel CH(n+1). That is, the memory controller 10 may send a channel status command to the extra channel CH(n+1), and receive a channel signal CH_EN indicating that the channel CH(n+1) is in an idle state from the extra channel CH(n+1). Next, the memory controller 10 may transmit a channel selection signal SEL (not shown) to the first selector 32_0 connected to the first nonvolatile memory device 40_0 based on the channel signal CH_EN and instruct to connect the additional channel CH(n+1) and the first nonvolatile memory device 40_0.

[0137] In some example embodiments, Figures 2 to 5 as well as Figures 10 to 12 The selector is different. Fig.13The selectors 32_0, 32_1, ..., 32_m of the first nonvolatile memory device 40_0, 40_1, ... can be connected only to the additional channel CH(n+1). Therefore, the selection unit (not shown) in the selectors 32_0, 32_1, ..., 32_m can determine whether to connect the channel CH(n+1) to each nonvolatile memory device 40_0, 40_1, ..., that is, only turn on / off (on / off) based on the channel selection signal SEL. For example, when the first selector 32_0 receives the channel selection signal SEL from the memory controller 10 to connect the additional channel CH(n+1) and the first nonvolatile memory device 40_0, the first selector 32_0 can send the command, address and data signals sent from the additional channel CH(n+1) to the second memory internal interface 42_0 of the first nonvolatile memory device 40_0 through the second interface 31_0. This structure has the advantage of reducing timing loss by realizing channel interleaving.

[0138] Fig.14 is a block diagram illustrating a storage system according to some example embodiments.

[0139] refer to Fig.14 , the storage system 1000 may include a host 1100 and a storage device 1300. The storage device 1300 sends and receives signals with the host 1100 through a signal connector, and receives power through a power connector. The storage device 1300 may include a memory controller 1320, an auxiliary power supply 1310, and memory devices 1331, 1332, ..., 133n. The memory devices 1331, 1332, ..., 133n may be NAND flash memory devices. According to an embodiment, any of the memory devices 1331, 1332, ..., 133n may include a memory controller 1320, an auxiliary power supply 1310, and memory devices 1331, 1332, ..., 133n. Figures 2 to 5 and Figures 10 to 13 Multiple selectors.

[0140] In some example embodiments, any memory device 1331, 1332, ..., 133n may be connected to the memory controller 1320 through a plurality of channels. In some example embodiments, a plurality of selectors in any memory device 1331, 1332, ..., 133n may be connected to the plurality of channels.

[0141] In some example embodiments, the memory controller 1320 may send a status read command to the plurality of memory devices 1331, 1332, ..., 133n to detect the status of each of the plurality of memory devices 1331, 1332, ..., 133n. In addition, the memory controller 1320 may send a channel status command to the plurality of channels to detect the status of the channels connected to the plurality of memory devices 1331, 1332, ..., 133n. In some example embodiments, the memory controller 1320 may send a channel signal indicating the channel status to the plurality of selectors in the plurality of memory devices 1331, 1332, ..., 133n based on the status of the channel. In some example embodiments, the plurality of selectors may connect one of the plurality of channels and one of the plurality of memory devices based on the channel signal.

[0142] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but rather the latitude of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "approximately" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0143] As described herein, any electronic device and / or portion thereof according to any example embodiment may include one or more instances of processing circuitry, may be included in one or more instances of processing circuitry, and / or may be implemented by one or more instances of processing circuitry, such as hardware including logic circuitry; a hardware / software combination, such as a processor executing software; or any combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., a memory) storing an instruction program, such as a DRAM device, and a processor (e.g., a CPU) configured to execute the instruction program to implement the functions and / or methods performed by some or all of any device, system, module, unit, controller, circuit, architecture, and / or portion thereof according to any example embodiment and / or any portion thereof.

[0144] As described above, some example embodiments have been disclosed in the drawings and the specification. Although specific terms have been used in this specification to describe the example embodiments, they are only used for the purpose of explaining the technical concept of the present disclosure and are not used to limit the meaning or scope of the present disclosure described in the claims. Therefore, it will be understood by those of ordinary skill in the art that there may be many variations and other embodiments of the same. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the appended claims.

Claims

1. A storage device, comprising: a first non-volatile memory device configured to store data; a first selector connected to the first non-volatile memory device; a plurality of channels connected to a first selector; as well as A memory controller connected to the plurality of channels, the memory controller being configured to: sending a command for sensing the state of a channel to the plurality of channels so as to send the data to the first non-volatile memory device, receiving channel status signals from the plurality of channels as a response to the command, the channel status signals indicating whether each channel is in an idle state, selecting a first channel among the plurality of channels based on the channel status signal, and A channel selection signal including information of the first channel is output to the first selector so that the first selector connects the first channel and the first nonvolatile memory device.

2. The storage device according to claim 1, wherein: The first selector is configured to receive a signal corresponding to the data from the first channel and transmit the signal to the first nonvolatile memory device upon receiving a channel selection signal from the memory controller.

3. The storage device according to claim 1, further comprising: A second non-volatile memory device is secured and connected to the first channel.

4. The storage device according to claim 1, wherein: The first channel is in idle state.

5. The storage device according to claim 1, wherein: The storage device also includes: a second non-volatile memory device configured to store data, A second selector is connected between the second nonvolatile memory device and the plurality of channels, and the memory controller is configured to schedule a transmission order of data to be transmitted to the first nonvolatile memory device and the second nonvolatile memory device based on a scheduling scheme.

6. The storage device according to claim 5, wherein: The scheduling scheme is configured to determine a transmission order of data to be transmitted to the first nonvolatile memory device and the second nonvolatile memory device based on whether the first nonvolatile memory device and the second nonvolatile memory device are busy performing internal operations or ready to complete internal operations.

7. The storage device according to claim 1, wherein: The memory controller is further configured to output a workload signal indicative of a pattern of a workload of the memory controller.

8. The storage device according to claim 7, wherein: The first selector is also configured as: receiving the workload signal, and A connection mode of the plurality of channels and the first non-volatile memory device is changed based on the workload signal.

9. A memory device comprising: Multiple channels; a plurality of non-volatile memory devices; as well as A first selector is connected to a first nonvolatile memory device among the plurality of nonvolatile memory devices, the first selector being configured to receive a first signal from an external memory controller and to connect a first channel among the plurality of channels and the first nonvolatile memory device based on the first signal.

10. The memory device of claim 9, further comprising: A second selector is connected between a second nonvolatile memory device among the plurality of nonvolatile memory devices and the plurality of channels, the second selector being configured to receive a second signal from the outside and to connect a second channel among the plurality of channels and the second nonvolatile memory device based on the second signal.

11. The memory device of claim 10, wherein: The first selector is configured to connect a first channel among the plurality of channels and a first nonvolatile memory device based on a first signal, receive a first command to be transmitted to the first nonvolatile memory device from the first channel, and transmit first data output from the first nonvolatile memory device to the first channel by corresponding to the first command, and The second selector is configured to connect a second channel and a second nonvolatile memory device among the plurality of channels based on a second signal, receive a second command to be transmitted to the second nonvolatile memory device from the second channel, and transmit second data output from the second nonvolatile memory device to the second channel by corresponding to the second command when the first data is transmitted from the first nonvolatile memory device to the first channel.

12. The memory device of claim 11, wherein: The first selector is configured to receive a third signal from the outside and connect a third channel among the plurality of channels and the first nonvolatile memory device based on the third signal.

13. The memory device of claim 12, wherein: After transmitting the first data from the first nonvolatile memory device to the first channel, while transmitting the second data from the second nonvolatile memory device to the second channel, the first selector is configured to connect a third channel among the plurality of channels and the first nonvolatile memory device based on a third signal, receive a third command to be transmitted to the first nonvolatile memory device from the third channel, and transmit third data output from the first nonvolatile memory device to the third channel by corresponding to the third command.

14. The memory device of claim 9, wherein: A second nonvolatile memory device among the plurality of nonvolatile memory devices is fixedly connected to a second channel among the plurality of channels.

15. The memory device of claim 9, wherein: The first non-volatile memory device comprises: a first plurality of pins connected to the first selector and configured to receive data from the first selector; and A second plurality of pins are connected to a second channel among the plurality of channels and are configured to receive data from the second channel.

16. The memory device of claim 15, wherein: A second non-volatile memory device among the plurality of non-volatile memory devices further comprises: a third plurality of pins connected to a second selector corresponding to a second nonvolatile memory device and configured to receive data from the second selector, and A fourth plurality of pins is connected to a second channel among the plurality of channels and is configured to receive data from the second channel.

17. The memory device of claim 9, wherein: The first signal is a signal indicating a first channel in an idle state among a plurality of channels.

18. The memory device of claim 9, wherein: The first signal is a signal indicating a pattern of a first workload among a plurality of workload patterns.

19. A method for operating a storage device, comprising: Determining, by the memory controller based on the scheduling scheme, to send data to a first non-volatile memory device among the plurality of non-volatile memory devices; In order to transmit the data to the first nonvolatile memory device, selecting a channel through which the data is transmitted among the plurality of channels connected to the memory controller, and outputting a channel selection signal including information of the selected channel; as well as The channel selection signal is received by a first selector connected to a first nonvolatile memory device, and a channel corresponding to the channel selection signal and the first nonvolatile memory device are connected based on the channel selection signal.

20. The method for operating a storage device according to claim 19, wherein: Selecting a channel through which the data is sent from among the multiple channels includes: sending, by the memory controller, a command for sensing a state of a channel to at least one channel among the plurality of channels; and A channel status signal is received from at least one channel among the plurality of channels as a response to the command, the channel status signal indicating whether each channel is in an idle state.

Images