Memory management method and memory controller

Abstract

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring block use conditions of a plurality of physical blocks of a rewritable nonvolatile memory module and a working state of storage equipment; when the working state is a busy state, whether garbage collection operation is executed or not is judged according to the block use condition and the host write-in requirement; and dynamically adjusting the write-in speed of the write-in operation of the host according to the number of the plurality of residual blocks when executing the garbage collection operation during the write-in operation of the host. According to the method, the use condition of the physical block and the write-in behavior of the host are monitored in real time, and a dynamic write-in speed adjusting mechanism is combined, so that the execution efficiency of garbage collection operation is obviously improved, and the write-in performance of the storage equipment under the high-load condition is effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a memory management method and a memory controller. Background Art

[0002] Non-volatile memory refers to computer memory in which the stored data does not disappear when the current is cut off. It has the advantages of non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Common non-volatile memory is a memory configured with NAND Flash (such as a solid-state drive), which has the characteristics of high read and write speed and does not require a mechanical structure to access data.

[0004] In existing storage devices, the total number of available physical blocks of a rewritable non-volatile memory module (eg, NAND flash memory) is fixed. As the host system continues to perform write operations, the physical blocks in the storage device are continuously consumed. When the physical blocks are about to be exhausted, the firmware of the storage device must initiate a garbage collection operation to release the physical blocks occupied by invalid data. However, in order to ensure that the physical blocks are released faster than they are consumed, the storage device must limit the write speed of the host write operation. In the prior art, if the garbage collection operation releases the physical blocks slowly, the storage device will suddenly limit the host write operation to a lower speed range, and the resulting sudden drop in write speed may cause performance problems in the host system. Summary of the invention

[0005] The present invention provides a memory controller and a control method thereof for adjusting the write speed according to the working status of the storage device, the usage of the data block and the dynamics of the host behavior, which can solve the technical problem in the prior art that the write speed of the storage device suddenly decreases, causing the host system performance to stall.

[0006] One or more embodiments of the present disclosure provide a memory management method, which is applicable to a storage device equipped with a rewritable non-volatile memory module. The method includes: obtaining block usage of multiple physical blocks of the rewritable non-volatile memory module; obtaining the working state of the storage device; when the working state of the storage device is a busy state, then: judging whether to perform a garbage collection operation according to the block usage of the multiple physical blocks and the host write demand of the storage device; and when the garbage collection operation is performed during the host write operation, dynamically adjusting the write speed of the host write operation according to the number of multiple remaining blocks in the multiple physical blocks.

[0007] In one or more embodiments of the present disclosure, the method further includes: when the working state of the storage device is an idle state, obtaining a first total valid data amount of multiple first written physical blocks among the multiple physical blocks, and judging whether to perform a pre-garbage collection operation based on the first total valid data amount; and when a host write instruction is received during the execution of the pre-garbage collection operation, pausing the pre-garbage collection operation.

[0008] In one or more embodiments of the present disclosure, the step of determining whether to execute the pre-garbage collection operation based on the first total valid data amount includes: obtaining a first valid data ratio between the first total valid data amount and the total storage space of the multiple first written physical blocks; when the first valid data ratio is less than a first valid data ratio threshold, determining to execute the pre-garbage collection operation, wherein the step of suspending the pre-garbage collection operation includes: not limiting the write speed of another host write operation corresponding to the host write instruction.

[0009] In one or more embodiments of the present disclosure, the step of determining whether to perform the garbage collection operation based on the block usage of the multiple physical blocks and the host write demand of the storage device includes: obtaining a first total number of multiple remaining blocks that have not been written to the multiple physical blocks; recording a second total number of multiple second written physical blocks in the multiple remaining blocks; determining the host write demand when the ratio of the second total number to the first total number exceeds a usage threshold; and if the determined host write demand is a high demand, determining to perform the garbage collection operation; and if the determined host write demand is not the high demand, determining not to perform the garbage collection operation.

[0010] In one or more embodiments of the present disclosure, the step of determining the host write demand includes: obtaining a second total valid data amount of the multiple second written physical blocks; obtaining a second valid data ratio between the second total valid data amount and the total storage space of the multiple second written physical blocks; and when the second valid data ratio exceeds a second valid data ratio threshold, determining that the host write demand is a high demand.

[0011] In one or more embodiments of the present disclosure, the step of performing the garbage collection operation includes: selecting one or more target recovery physical blocks from the multiple physical blocks to perform the garbage collection operation on the one or more target recovery physical blocks, wherein the valid data ratio of each target recovery physical block is less than a recovery valid data ratio threshold.

[0012] In one or more embodiments of the present disclosure, the step of dynamically adjusting the write speed of the host write operation according to the number of the multiple remaining blocks in the multiple physical blocks includes: obtaining the recovery write speed of the garbage collection operation; adjusting the write speed of the current host write operation according to the first total number of the multiple remaining blocks that have not been written in the multiple physical blocks and the recovery write speed.

[0013] In one or more embodiments of the present disclosure, the step of adjusting the write speed of the current host write operation based on the first total number of the multiple remaining blocks that have not yet been written in the multiple physical blocks and the recovery write speed includes: obtaining a first remaining ratio between the first total number and the total number of the multiple physical blocks; and adjusting the write speed based on the first remaining ratio using the recovery write speed.

[0014] In one or more embodiments of the present disclosure, the step of adjusting the write speed using the recovery write speed according to the first remaining proportion includes: obtaining the current remaining proportion interval corresponding to the first remaining proportion; determining the corresponding speed adjustment ratio according to the remaining proportion interval, wherein the lower the remaining proportion interval corresponds to the lower the speed adjustment ratio; and adjusting the write speed using the recovery write speed of the garbage collection operation and the speed adjustment ratio, wherein if the remaining proportion interval is the highest remaining proportion interval, the write speed of the host write operation is not adjusted.

[0015] In one or more embodiments of the present disclosure, the step of dynamically adjusting the write speed of the host write operation according to the number of the multiple remaining blocks in the multiple physical blocks also includes: when the first total number of the multiple remaining blocks that have not yet been written in the multiple physical blocks reaches a critical remaining number, determining that the remaining proportion interval is the lowest remaining proportion interval, and performing the following steps: selecting one or more target recovery physical blocks from the multiple physical blocks to perform the garbage collection operation on the one or more target recovery physical blocks; obtaining the valid data proportion of each target recovery physical block; and adjusting the write speed of the host write operation according to the valid data proportion of the target recovery physical block and the target recovery write speed corresponding to the target recovery physical block.

[0016] In one or more embodiments of the present disclosure, the step of adjusting the write speed of the host write operation according to the valid data ratio of the target reclaimed physical block and the target reclaimed write speed corresponding to the target reclaimed physical block includes: determining an emergency speed adjustment ratio based on a comparison result of the valid data ratio with another reclaimed valid data ratio threshold; and using the target reclaimed write speed and the emergency speed adjustment ratio to adjust the write speed of the host write operation.

[0017] In one or more embodiments of the present disclosure, the step of pausing the pre-garbage collection operation also includes: obtaining the current execution progress of the pre-garbage collection operation; recording the interruption point information corresponding to the current execution progress; and setting a recovery flag based on the interruption point information, wherein when the host write instruction is executed, it is determined whether to resume the execution of the pre-garbage collection operation according to the recovery flag.

[0018] In one or more embodiments of the present disclosure, the step of determining the host write demand includes: setting a sliding time window; within the sliding time window, calculating the cumulative write data volume according to the logical address range of the received host write instructions; and when the cumulative write data volume exceeds a preset data volume threshold, determining that the host write demand is the high demand.

[0019] In one or more embodiments of the present disclosure, the step of adjusting the write speed using the recovery write speed of the garbage collection operation and the speed adjustment ratio includes: obtaining the last write speed; calculating the speed difference between the current target write speed and the last write speed; determining whether a smooth transition is required based on the speed difference; and if it is determined that the smooth transition is required, gradually adjusting the write speed to the target write speed within a preset transition period.

[0020] Based on the above, the memory management method and memory controller provided by the embodiments of the present disclosure effectively reduce the centralized recovery overhead when the physical blocks are about to be exhausted by pre-performing garbage collection according to the amount of valid data when the storage device is idle; use the host write behavior analysis mechanism to predict the write demand, and implement a graded speed limit strategy according to the number of remaining physical blocks, so that the adjustment of the write speed is smoother; in a critical state, the speed limit multiplier is dynamically adjusted based on the proportion of valid data in the target recovered physical block, avoiding a sudden drop in write speed due to too low garbage collection efficiency, and significantly improving the performance stability of the storage device under high load conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0022] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0023] Figure 2 is a flow chart of a memory management method according to an embodiment of the present invention;

[0024] Figure 3 is a flow chart of determining a host writing requirement according to an embodiment of the present invention;

[0025] Figure 4 is a flow chart of dynamically adjusting the writing speed according to an embodiment of the present invention;

[0026] Figure 5 is a flow chart of dynamically adjusting the writing speed under a critical state according to an embodiment of the present invention;

[0027] Figure 6 is a schematic diagram of the relationship between the speed adjustment ratio and the remaining proportion according to an embodiment of the present invention;

[0028] Figure 7 2 is a schematic diagram of the relationship between the emergency speed adjustment ratio and the effective data ratio according to an embodiment of the present invention.

[0029] Description of Figure Numbers

[0030] 10: Host system

[0031] 20: Storage Devices

[0032] 211: First processor

[0033] 110: Second processor

[0034] 120: Host memory

[0035] 130: Data transmission interface circuit

[0036] 210: Memory controller

[0037] 212: Data management circuit

[0038] 213: Memory interface control circuit

[0039] 214: Buffer memory

[0040] 220: Rewritable non-volatile memory module

[0041] 230: Connecting interface circuit

[0042] S210-S240: Steps of the memory management method

[0043] S310-S390: Steps for determining host write requirements

[0044] S410-S450: Steps to dynamically adjust write speed

[0045] S510-S540: Steps to dynamically adjust write speed in critical state

[0046] CT61: Graph showing the relationship between speed adjustment ratio and total number of remaining blocks

[0047] CT71: Graph showing the relationship between the emergency speed adjustment ratio and the percentage of valid data

[0048] RS61: Lowest remaining ratio range

[0049] RS62: Medium residual ratio

[0050] RS63: High residual ratio range

[0051] RS64: Highest remaining ratio range

[0052] RS71: Low effective data ratio area

[0053] RS72: Area with high effective data ratio

[0054] SL1, SL2: Slash DETAILED DESCRIPTION

[0055] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0056] Figure 1 FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present disclosure. Figure 1, the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In the present embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0057] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0058] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0059] In this embodiment, the number of the data transmission interface circuit 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0060] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use the fast non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol to transmit data.

[0061] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0062] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present disclosure is not limited thereto, and the host memory 120 may also be other suitable memories.

[0063] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10 .

[0064] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the storage device 20 is operating, these control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to implement the memory management method provided by the present disclosure. The control instructions / program codes corresponding to the memory management can be further implemented as a circuit unit in the form of hardware to implement the memory management method provided by the present disclosure.

[0065] It is worth mentioning that in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present disclosure is not limited thereto.

[0066] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0067] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation (also called a host write operation) is performed according to a write instruction (also called a host write instruction) from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (data can be read from one or more storage units in one or more physical units), and the read data is written to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211 .

[0068] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also called programming) operation, a read operation or an erase operation (also called an erasure operation) on the rewritable non-volatile memory module 220 .

[0069] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, and a physical address may be included.

[0070] In the present disclosure, the memory controller 210 establishes a logical to physical address mapping table (Logical To Physical address mapping table, also called L2P mapping table) and a physical to logical address mapping table (Physical To Logical address mapping tablee, also called P2L mapping table) to record the mapping relationship between the logical address of the logical unit (e.g., logical block, logical page or logical column) configured for the rewritable non-volatile memory module 220 and the physical address (physical address) of the physical unit (e.g., physical erase unit / physical block, physical page, physical column). In other words, the memory controller 210 can search for the physical unit mapped by a logical unit (e.g., search for the physical page mapped by a logical page; search for the physical address mapped by a logical address) through the logical to physical address mapping table (also called logical to physical mapping table), and the memory controller 210 can search for the logical unit mapped by a physical unit (e.g., search for the logical page mapped by a physical page; search for the logical address mapped by a physical address) through the physical to logical address mapping table (also called physical to logical mapping table).

[0071] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., various mapping tables, index tables, block usage information of physical blocks, various total valid data volumes, various valid data proportions, various remaining proportions, speed adjustment magnifications of various remaining proportion intervals, cumulative written data volume statistics within a sliding time window, interruption point information and its recovery identifier, etc. and system data associated with the present memory management method), so that the processor 211 can quickly access the data, instructions or system data from the buffer memory 214.

[0072] In one embodiment, the memory controller 210 reserves a specific area in the buffer memory 214 for storing various types of mapping tables and index information. The memory controller 210 caches these data hierarchically according to access frequency and importance: frequently accessed mapping table information is stored in a fast access area, while less frequently used information is stored in a normal area. When the buffer memory 214 is insufficient, the memory controller 210 gives priority to writing less frequently used information back to the rewritable non-volatile memory module 220. In order to improve data reliability, the memory controller 210 also periodically synchronizes important mapping information in the buffer memory 214 to the rewritable non-volatile memory module 220, and records the synchronization timestamp so that it can be restored to the most recent valid state in the event of a system anomaly.

[0073] In another embodiment, the memory controller 210 stores these data structures in a preset area in the buffer memory, and periodically synchronizes their update status to the rewritable non-volatile memory module to ensure data persistence and consistency. In some embodiments, when the memory controller 210 is restarted, the latest status of these data structures can be restored from the rewritable non-volatile memory module to ensure that the system can continue the previous storage management operation.

[0074] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store data written by the host system 10 .

[0075] In the present embodiment, the rewritable non-volatile memory module 220 has a plurality of word lines, wherein each of the plurality of word lines is electrically connected to a plurality of storage cells, also known as columns (also known as physical columns). The plurality of columns on the same word line constitute a physical programming unit (also known as a physical page or physical page). Each physical page corresponds to a physical address for recording the location of the data stored in the physical page. In addition, the plurality of physical pages may constitute a physical block (also known as a physical erase unit or physical block). Each memory grain (chip) of the plurality of memory grains of the rewritable non-volatile memory module has a plurality of planes, and each plane has a plurality of physical blocks. It should be noted that the present disclosure is not limited to the size of each physical page and logical page.

[0076] The storage cell type (also known as storage mode) can be used to indicate the number of bits that each memory cell (Memory Cell, also known as storage cell) can store. Common types include SLC (single-layer storage cell, each storage cell stores 1 bit), MLC (multi-layer storage cell, each storage cell stores 2 bits), TLC (triple-layer storage cell, each storage cell stores 3 bits), etc. Different storage modes vary in storage density, read and write speed, and durability, which affects the overall performance and characteristics of flash memory.

[0077] Figure 2 is a flow chart of a memory management method according to an embodiment of the present invention;

[0078] Reference Figure 2In one embodiment, the memory controller 210 performs a memory management method. Specifically, in step S210, the memory controller 210 obtains block usage of multiple physical blocks of the rewritable non-volatile memory module 220. The memory controller 210 communicates with the rewritable non-volatile memory module 220 through the memory interface control circuit 213 to obtain usage status information of each physical block, including data such as used space, remaining space, and effective data volume of each data block (written block). This information is cached in the buffer memory 214 for subsequent analysis by the processor 211.

[0079] Next, in step S220 , the memory controller 210 obtains the working status of the storage device 20 .

[0080] In one embodiment, the processor 211 monitors whether there is a write request from the host system 10 through the data management circuit 212. If no write request from the host system 10 is received within a predetermined time window, it is determined that the storage device 20 is in an idle state; conversely, if it is detected that the host system 10 is performing a write operation or waiting to perform a write operation, it is determined that the storage device 20 is in a busy state.

[0081] In another embodiment, the processor 211 may also comprehensively consider other factors to determine the working status, such as: system load level, current write queue length, and usage rate of the buffer memory 214.

[0082] Next, in step S230 , when the working state of the storage device 20 is a busy state, the memory controller 210 determines whether to perform a garbage collection operation according to the block usage of the plurality of physical blocks and the host write demand.

[0083] Figure 3 is a flow chart of determining a host writing requirement according to an embodiment of the present invention.

[0084] Reference Figure 3 In one embodiment, the memory controller 210 performs a method for determining a host write demand. When the working state of the storage device 20 is a busy state, the memory controller 210 determines the host write demand according to the following steps to determine whether to perform a garbage collection operation.

[0085] In step S310, the processor 211 obtains the first total number of the remaining blocks that have not been written in the multiple physical blocks of the rewritable non-volatile memory module 220 through the memory interface control circuit 213. The processor 211 temporarily stores the first total number in the buffer memory 214 for subsequent calculation and judgment.

[0086] Next, in step S320, the processor 211 obtains a second total number of multiple second written physical blocks in the most recent predetermined period. Specifically, the processor 211 continuously monitors and records the number of physical blocks in the remaining blocks actually consumed when the host system 10 performs a write operation in the predetermined period (e.g., the most recent 100 milliseconds or other time, the present disclosure is not limited thereto) through the data management circuit 212. The second total number is also temporarily stored in the buffer memory 214.

[0087] Then, in step S330, the processor 211 determines whether it is necessary to determine the host write demand based on the first total number and the second total number. Specifically, the processor 211 calculates the ratio of the second total number to the first total number. When the ratio exceeds a preset usage threshold (e.g., 10% or other predetermined ratios, the present disclosure is not limited thereto), it indicates that the physical block has been consumed at a faster rate in the recent period of time, and the processor 211 determines that it is necessary to further determine the host write demand (e.g., start executing the operation of determining the host write demand). On the contrary, if the ratio does not exceed the usage threshold, the processor 211 returns to step S310 and continues to monitor the usage of the physical block.

[0088] If it is determined in step S330 that the host write requirement needs to be determined, the processor 211 obtains the total valid data amount of the plurality of second written physical blocks in step S340.

[0089] In one embodiment, the processor 211 can obtain the second total valid data amount through a real-time counter mechanism. Specifically, when the host system 10 performs a write operation, the processor 211 maintains a valid data counter for each second written physical block. When new data is written, the counter of the corresponding physical block is increased by one; when data is overwritten or deleted, the counter of the source physical block is reduced by one, and the counter of the target physical block is increased by one. The processor 211 can obtain the second total valid data amount by accumulating the values ​​of these counters.

[0090] In another embodiment, the processor 211 may obtain the second total valid data amount by scanning a mapping table. Specifically, the processor 211 maintains a logical-to-physical mapping table in the buffer memory 214 to record whether each physical address stores valid data. By scanning the mapping table, the processor 211 can count the number of mapped addresses in each second written physical block, thereby calculating the second total valid data amount.

[0091] In another embodiment, the processor 211 may adopt a hybrid acquisition method. Specifically, a counter is used to perform real-time statistics during a normal writing process, and the count value is corrected by scanning a mapping table periodically, thereby improving the accuracy of the second total valid data amount statistics.

[0092] Next, in step S350, the processor 211 obtains the second valid data ratio between the second total valid data amount and the total storage space of the plurality of second written physical blocks. Specifically, the processor 211 first calculates the total storage space of the second written physical blocks, and then divides the second total valid data amount by the total storage space to obtain the second valid data ratio.

[0093] Next, in step S360, the processor 211 determines whether the second valid data ratio exceeds the second valid data ratio threshold. When the second valid data ratio exceeds a preset threshold (e.g., 90% or other predetermined ratios, the present disclosure is not limited thereto), it indicates that the recently written data block contains a large amount of valid data, and the processor 211 determines that the current host write demand is a high demand in step S370, and performs a garbage collection operation in step S380 (even if the host write operation is currently being performed, this garbage collection operation will be performed).

[0094] On the contrary, if the proportion of the second valid data does not exceed the threshold, the processor 211 determines in step S390 that the host write demand is not a high demand. In this case, the processor 211 may perform the following operations: First, the processor 211 maintains the current host write speed at a relatively high level without starting the write speed limit mechanism. Second, the processor 211 may allocate system resources to the host write operation first, and postpone the garbage collection operation until the storage device 20 is in an idle state. In this way, the memory controller 210 guarantees the host write performance.

[0095] In one embodiment, when it is determined that a garbage collection operation needs to be performed, the processor 211 selects one or more target recovery physical blocks from multiple physical blocks. Specifically, the processor 211 obtains the effective data ratio of each physical block, and selects a physical block whose effective data ratio is less than a recovery effective data ratio threshold (e.g., 30% or other predetermined ratio, the present disclosure is not limited thereto) as a target recovery physical block. By selecting a physical block with less effective data for garbage collection, the overhead of data movement can be reduced and the execution efficiency of garbage collection can be improved.

[0096] Through the above-mentioned multiple judgment mechanisms based on the physical block usage, the memory controller 210 can promptly identify the high-intensity write behavior of the host system 10 and start the garbage collection operation in advance, thereby avoiding the passive execution of garbage collection when the physical block resources are tight. This predictive management method significantly improves the performance of the storage device 20 under high load conditions.

[0097] In some embodiments, the processor 211 may dynamically adjust the above thresholds according to the actual application scenario of the storage device 20, for example:

[0098] (1) The second valid data ratio threshold can be lowered in high-performance mode. The advantage of lowering the second valid data ratio threshold in high-performance mode is that high-performance mode usually has high requirements for write speed and response time. Lowering the threshold means that even if the proportion of valid data in the data block is relatively low, it will be judged as a high write demand. In this way, lowering the second valid data ratio threshold in high-performance mode can trigger garbage collection operations earlier and release physical block resources in advance to avoid being forced to perform garbage collection when physical block resources are tight, thereby reducing write delays.

[0099] (2) The usage threshold can be increased in low power mode: The advantage of increasing the usage threshold in low power mode is that low power mode gives priority to reducing system resource consumption. Increasing the usage threshold means that a higher physical block consumption ratio is required to trigger garbage collection judgment. In this way, increasing the usage threshold in low power mode can reduce unnecessary garbage collection operations and reduce power consumption. In addition, since low power mode has lower performance requirements, higher write delays can be tolerated.

[0100] In one embodiment, if the processor 211 determines that the host write demand is a high demand, it decides to perform a garbage collection operation. On the contrary, if it is determined that the host write demand is not a high demand, the garbage collection operation is not performed temporarily. Through this judgment mechanism based on the analysis of the host write behavior, the memory controller 210 can start the garbage collection operation at an appropriate time, effectively balancing the storage performance and resource utilization efficiency.

[0101] In another embodiment, the processor 211 may use a sliding time window mechanism to determine the host write demand. Specifically, the processor 211 sets a sliding time window of a fixed size (e.g., 100 milliseconds or other predetermined time, the present disclosure is not limited thereto), and the window continues to move forward over time. Within the time window, the processor 211 records and accumulates the logical address range of each write instruction sent by the host system 10, and calculates the cumulative amount of written data. When the cumulative amount of written data exceeds a preset data volume threshold, the processor 211 determines that the current host write demand is a high demand. This judgment method based on a sliding time window can accurately reflect the write pressure of the host system 10 within a specific time period.

[0102] Back to Figure 2Then, in step S240, when a garbage collection operation is performed during a host write operation, the memory controller 210 dynamically adjusts the write speed of the host write operation according to the number of multiple remaining blocks. Specifically, the processor 211 obtains the recovery write speed of the garbage collection operation, and adjusts the write speed according to the first remaining ratio between the first total number of remaining blocks and the total number of physical blocks. For example, when the first remaining ratio is in different intervals, the processor 211 adopts different speed adjustment ratios, wherein a lower remaining ratio interval corresponds to a lower speed adjustment ratio. If the remaining ratio interval is the lowest remaining ratio interval, the processor 211 will further adjust the write speed according to the valid data ratio of the target recovered physical block to ensure a smooth transition of system performance.

[0103] Through the above steps, the memory controller 210 can dynamically adjust the write speed according to the host write behavior, effectively avoiding a sudden decrease in the write speed and improving the performance stability of the storage device 20.

[0104] In another embodiment, when the storage device 20 is in an idle state (e.g., no write command from the host system 10 is received for 100 milliseconds), the memory controller 210 performs preventive garbage collection management. Specifically, the processor 211 first obtains the first total valid data amount of the first written physical blocks in the rewritable non-volatile memory module 220 through the memory interface control circuit 213. The processor 211 temporarily stores the data amount information in the buffer memory 214.

[0105] Subsequently, the processor 211 calculates the first valid data ratio between the first total valid data amount and the total storage space of the plurality of first written physical blocks. Specifically, the processor 211 first obtains the total storage space size of the first written physical blocks, and then divides the first total valid data amount by the total storage space to obtain the first valid data ratio. When the first valid data ratio is less than a preset first valid data ratio threshold (e.g., 70% or other predetermined ratio, the present disclosure is not limited thereto), it indicates that there is a lot of invalid data in the current storage space, and the processor 211 determines that a pre-garbage collection operation needs to be performed accordingly.

[0106] During the execution of the pre-garbage collection operation, if the data management circuit 212 receives a write instruction from the host system 10, the processor 211 will immediately suspend the garbage collection operation currently being executed. Specifically, the processor 211 records the execution progress of the current garbage collection operation and allocates system resources to the host write operation in priority. It is worth noting that since the garbage collection operation is performed preventively during idle time, when suspending the operation and processing the host write instruction instead, the processor 211 will not impose any restrictions on the write speed of the host write operation, thereby ensuring that the host write performance is not affected.

[0107] When the pre-garbage collection operation is suspended, the processor 211 may perform a series of state saving operations. Specifically, the processor 211 first obtains the current execution progress of the garbage collection operation, including the number of processed physical blocks, the address of the physical block currently being processed, and the processing position within the physical block. Subsequently, the processor 211 records the interruption point information in the buffer memory 214, which can be used for the location positioning when the garbage collection operation is subsequently resumed.

[0108] The processor 211 also sets a recovery flag based on the recorded interruption point information. Specifically, the recovery flag includes multiple fields: the physical block identifier currently being processed, the offset address of the operation within the block, the percentage of garbage collection completed, and the priority of the garbage collection operation. This information is organized into a state description structure and stored in a predetermined area of ​​the buffer memory 214.

[0109] When the host write instruction is executed, the processor 211 determines whether to resume the pre-garbage collection operation according to the recovery flag. Specifically, the processor 211 first checks whether the storage device 20 has re-entered the idle state, and then evaluates the amount of unfinished garbage collection, and determines whether to resume the garbage collection operation immediately in combination with the current system resource usage. If the conditions are met, the processor 211 continues to perform the garbage collection operation from the interruption position according to the previously saved interruption point information to ensure that the storage space is effectively organized.

[0110] This pause and resume mechanism enables the memory controller 210 to dynamically switch between host write operations and garbage collection operations, thereby ensuring host write performance while not losing garbage collection progress information.

[0111] Through this preventive garbage collection mechanism, the memory controller 210 can fully utilize the system idle time to organize the storage space without affecting the normal write operation of the host system 10, thereby effectively improving the overall performance of the storage device 20.

[0112] Figure 4is a flow chart of dynamically adjusting the writing speed according to an embodiment of the present invention.

[0113] Reference Figure 4 In one embodiment, the memory controller 210 performs a method for dynamically adjusting a write speed. When a garbage collection operation is performed during a host write operation, the processor 211 dynamically adjusts the write speed of the host write operation according to the number of the plurality of remaining blocks in the plurality of physical blocks according to the following steps.

[0114] In step S410 , the processor 211 obtains the garbage collection write speed of the garbage collection operation. In short, the processor 211 monitors the actual write speed of copying valid data from the source physical block to the target physical block during the garbage collection process through the memory interface control circuit 213 .

[0115] In one embodiment, the memory controller 210 obtains the recovery write speed of the garbage collection operation in the following manner. Specifically, when the processor 211 performs the garbage collection operation, it monitors the process of data moving from the source physical block to the target physical block through the memory interface control circuit 213. The processor 211 records the number of bytes that complete the data move in each preset time interval (e.g., 1 millisecond) and stores the value in the buffer memory 214. By calculating the average number of bytes written in multiple consecutive time intervals, the processor 211 can obtain the actual recovery write speed of the current garbage collection operation.

[0116] In step S420, the processor 211 obtains a first remaining ratio between a first total number of the plurality of remaining blocks that have not been written to the plurality of physical blocks and the total number of the plurality of physical blocks. Specifically, the processor 211 first obtains the total number of the physical blocks that have not been written to (also referred to as the remaining blocks) in the rewritable non-volatile memory module 220 through the memory interface control circuit 213, and then divides the total number of the physical blocks to obtain the first remaining ratio.

[0117] In step S430, the processor 211 obtains the current remaining proportion interval corresponding to the first remaining proportion. Specifically, the processor 211 presets multiple remaining proportion intervals, for example: 50%-100% is the first interval (also called the highest remaining proportion interval), 30%-50% is the second interval (also called the high remaining proportion interval), 10%-30% is the third interval (also called the medium remaining proportion interval), and less than 10% is the fourth interval (also called the low remaining proportion interval). The processor 211 corresponds the currently calculated first remaining proportion to these preset intervals. It should be noted that the specific settings of each of the above intervals can vary according to actual needs.

[0118] In step S440, the processor 211 determines the corresponding speed adjustment ratio according to the remaining proportion interval. Specifically, a higher remaining proportion interval corresponds to a higher speed adjustment ratio. For example, the speed adjustment ratio corresponding to the first interval is unlimited speed, the speed adjustment ratio corresponding to the second interval is 5 times (also called high speed adjustment ratio), the speed adjustment ratio corresponding to the third interval is 3 times (also called medium speed adjustment ratio), and the speed adjustment ratio corresponding to the fourth interval is 1.5 times (also called low speed adjustment ratio). This design ensures that a higher write speed is maintained when the remaining space is sufficient, and the write speed is gradually reduced when the remaining space is insufficient. It should be noted that the above-mentioned values ​​of 5, 3, and 1.5 corresponding to the high speed adjustment ratio, the medium speed adjustment ratio, and the low speed adjustment ratio are all exemplary, which are used to illustrate the relative size association, and the present invention is not limited to this.

[0119] In step S450, the processor 211 uses the recycling write speed of the garbage collection operation and the speed adjustment ratio to adjust the write speed. Specifically, if the current first remaining ratio is in the first interval (i.e., the highest remaining ratio interval), the processor 211 does not limit the write speed of the host write operation. If the first remaining ratio is in other intervals, the processor 211 limits the host write speed to a corresponding multiple of the recycling write speed.

[0120] Through this multi-level speed limiting mechanism based on the number of remaining blocks, the memory controller 210 can reasonably adjust the host write speed while ensuring stable operation of the system.

[0121] Figure 6 2 is a schematic diagram of the relationship between the speed adjustment ratio and the remaining proportion according to an embodiment of the present invention.

[0122] Reference Figure 6 In one embodiment, a graph CT61 shows the relationship between the speed adjustment ratio of the memory controller 210 and the total number of remaining blocks. The horizontal axis represents the total number of remaining blocks, and the axis is divided into a lowest remaining proportion interval (RS61), a medium remaining proportion interval (RS62), a high remaining proportion interval (RS63), and a highest remaining proportion interval (RS64). The vertical axis represents the speed adjustment ratio.

[0123] Specifically, when the total number of remaining blocks is in the highest remaining proportion interval RS64, the processor 211 does not limit the host write speed. When the total number of remaining blocks is in other intervals, the processor 211 limits the host write speed according to the speed adjustment ratio corresponding to the current interval. Among them, the RS63 interval corresponds to a high speed adjustment ratio, the RS62 interval corresponds to a medium speed adjustment ratio, and the RS61 interval corresponds to a low speed adjustment ratio.

[0124] When the total number of remaining blocks reaches the critical remaining number, the processor 211 determines that it is currently in the lowest remaining percentage interval RS61. In this case, the processor 211 executes an emergency garbage collection strategy: first, one or more target recovery physical blocks (physical blocks used to perform pre-garbage collection operations) are selected from multiple physical blocks. The processor 211 obtains the effective data percentage of each target recovery physical block through the memory interface control circuit 213, and calculates the optimal data migration strategy based on these percentage information.

[0125] For each target recovery physical block, the processor 211 obtains its actual target recovery write speed and determines the corresponding write speed limit according to the effective data ratio of the physical block. Specifically, when the effective data ratio of the target recovery physical block is low, the processor 211 can adopt a relatively high write speed limit; when the effective data ratio is high, a lower write speed limit is adopted to ensure the reliability of data transfer. Through this mechanism, the memory controller 210 can still maintain the stable operation of the system in an emergency.

[0126] In one embodiment, when the processor 211 adjusts the write speed according to the effective data ratio of the target recovered physical block, the following steps are specifically performed. The processor 211 first compares the effective data ratio of the target recovered physical block with another preset effective data ratio threshold (e.g., 50% or other predetermined ratios, the present disclosure is not limited thereto). Specifically, if the effective data ratio of the target recovered physical block is lower than the threshold, the processor 211 sets the emergency speed adjustment ratio to, for example, 1 times, which means that the amount of effective data in the current target recovered physical block is small, and the garbage collection operation can be completed faster. For example, after a physical block is released in a pre-garbage collection operation, the host writes data to fill up an empty physical block.

[0127] On the contrary, if the proportion of valid data exceeds the threshold, the processor 211 sets the emergency speed adjustment ratio to, for example, 2 to 3 times to cope with a larger amount of data movement. For example, after a physical block is released by the pre-garbage collection operation, the host write data can fill 2 to 3 physical blocks to slow down the host write speed. Subsequently, the processor 211 uses the product of the target recovery write speed and the determined emergency speed adjustment ratio to set the write speed limit of the host write operation.

[0128] It is worth mentioning that Figure 6 The oblique lines SL1 and SL2 in indicate a smooth transition mechanism. In this embodiment, the processor 211 may calculate the speed adjustment ratio by linear interpolation at the boundaries of adjacent intervals to avoid a sudden change in the writing speed when switching between intervals.

[0129] More specifically, in one embodiment, to avoid sudden changes in the write speed, the processor 211 implements a smooth transition mechanism. Specifically, when the write speed needs to be adjusted, the processor 211 first obtains the last write speed value from the buffer memory 214. The processor 211 then calculates the speed difference between the current target write speed and the last write speed. When the difference exceeds a preset threshold (e.g., the current speed change exceeds 30% or other predetermined ratio of the last speed), the processor 211 determines that a smooth transition is required.

[0130] When performing a smooth transition, the processor 211 gradually adjusts the write speed from the previous value to the target write speed within a preset transition period (e.g., 10 milliseconds or other predetermined time). Specifically, the processor 211 evenly distributes the speed difference into multiple adjustment steps, and the time interval of each adjustment step is the same, thereby achieving a linear transition of the write speed. This smooth transition mechanism can avoid drastic fluctuations in the write speed.

[0131] Figure 5 is a flow chart of dynamically adjusting the writing speed under a critical state according to an embodiment of the present invention.

[0132] Reference Figure 5 In one embodiment, when the first total number of the plurality of remaining blocks that have not been written to in the plurality of physical blocks reaches a critical remaining number (e.g., 3), the memory controller 210 performs a special write speed adjustment process. It should be noted that the specific value of the critical remaining number can be determined according to the requirements.

[0133] In step S510, the processor 211 selects one or more target recovery physical blocks from the multiple physical blocks to perform garbage collection operations on these physical blocks. Specifically, the processor 211 scans the usage status of all physical blocks through the memory interface control circuit 213, and preferentially selects physical blocks with a lower percentage of valid data as target recovery physical blocks.

[0134] In step S520, the processor 211 obtains the effective data ratio of each target recovery physical block. The processor 211 reads the effective data distribution information in these physical blocks through the memory interface control circuit 213, and calculates the actual ratio of the effective data in each target recovery physical block to the storage space of each target recovery physical block.

[0135] In step S530, the processor 211 determines the emergency speed adjustment ratio based on the comparison result of the effective data ratio and another recovery effective data ratio threshold. Specifically, if the effective data ratio of the target recovery physical block is low, a larger speed adjustment ratio is used; if the effective data ratio is high, a smaller speed adjustment ratio is used to avoid excessive reduction of the write speed.

[0136] In step S540, the processor 211 uses the target recycling write speed and the emergency speed adjustment ratio to adjust the write speed of the host write operation. Through this dynamic adjustment mechanism based on the valid data ratio, the memory controller 210 can still maintain reasonable write performance in a critical state.

[0137] Figure 7 2 is a schematic diagram of the relationship between the emergency speed adjustment ratio and the effective data ratio according to an embodiment of the present invention.

[0138] Reference Figure 7 ,Chart CT71 shows the relationship between the emergency speed adjustment ratio and the valid data ratio under critical conditions.,The horizontal axis represents the valid data ratio of the target recovery physical block, and the horizontal axis is divided into two regions RS71 and RS72 by another recovery valid data ratio threshold.,The vertical axis represents the corresponding emergency speed adjustment ratio.

[0139] When the effective data ratio of the target recovered physical block is in the RS71 region (i.e., less than another recovery effective data ratio threshold), it indicates that the efficiency of the garbage collection operation is relatively high. At this time, the processor 211 adopts a lower emergency speed adjustment ratio (e.g., 1 times) because each garbage collection operation can release new free blocks faster.

[0140] On the contrary, when the effective data ratio is in the RS72 region (i.e., exceeds another effective data ratio threshold), it means that the garbage collection operation needs to move a large amount of effective data, and the efficiency is relatively low. At this time, the processor 211 adopts a higher emergency speed adjustment ratio (e.g., 2 to 3 times) to give the garbage collection operation more execution time and avoid drastic fluctuations in the write speed.

[0141] Through this differentiated adjustment mechanism based on the effective data ratio, the memory controller 210 can maintain stable operation of the system under critical conditions.

[0142] Finally, this embodiment also provides a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code. When the computer readable code runs in the processor of the host system, the processor 211 executes the process steps of the above-mentioned memory management method and realizes the functions of the memory controller 210. The computer program product can be implemented in hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium. In another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0143] Based on the above, the memory management method and memory controller provided by the embodiments of the present disclosure can achieve the following technical effects:

[0144] First, by pre-executing the garbage collection operation according to the first valid data ratio when the storage device 20 is idle, and pausing the operation in time when receiving the host write instruction, the recycling pressure of the storage device 20 under high load is reduced. Specifically, the processor 211 records the interruption point information and sets the recovery flag to ensure that the garbage collection operation can continue to be executed at an appropriate time, effectively balancing storage performance and resource utilization.

[0145] Second, based on the host write behavior analysis mechanism, the processor 211 can identify write requirements early and predict resource consumption trends. The processor 211 can accurately evaluate the host write requirements by monitoring the physical block usage and valid data ratio within a predetermined period, or by combining the accumulated write data volume within a sliding time window.

[0146] Third, a multi-level speed limit strategy is implemented according to the number of remaining physical blocks to avoid sudden changes in the write speed. The processor 211 presets multiple remaining proportion intervals and corresponding speed adjustment ratios, and adopts a multi-stage transition mechanism when switching between intervals to make the adjustment of the write speed more stable.

[0147] Fourth, a differentiated adjustment mechanism based on the effective data ratio is adopted in a critical state. The processor 211 selects a suitable emergency speed adjustment ratio by evaluating the effective data ratio of the target recovery physical block, thereby avoiding the problem of excessively limiting the write speed and causing a sudden drop in performance.

[0148] Fifth, the write speed is adjusted intelligently and smoothly. The processor 211 calculates the difference between the target write speed and the last write speed, and starts the smooth transition mechanism when necessary to ensure that the write speed is gradually adjusted to the target value within the preset transition period, thereby improving the operation stability of the storage device.

[0149] Through the above technical solutions, the memory management method provided by the present disclosure significantly improves the performance of the storage device under various load conditions, and is particularly suitable for application scenarios that require frequent data writing.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory management method, applicable to a storage device equipped with a rewritable non-volatile memory module, characterized in that: The method comprises: Acquiring block usage status of multiple physical blocks of the rewritable non-volatile memory module; When the storage device is in a busy state, determining whether to perform a garbage collection operation according to the block usage of the plurality of physical blocks and a host write demand of the storage device; and When the garbage collection operation is performed during a host write operation, a write speed of the host write operation is dynamically adjusted according to the number of remaining blocks in the plurality of physical blocks.

2. The memory management method according to claim 1, characterized in that: Also includes: When the storage device is in an idle state, obtaining a first total valid data amount of a plurality of first written physical blocks among the plurality of physical blocks, and determining whether to perform a pre-garbage collection operation according to the first total valid data amount: and When a host write instruction is received during the execution of the pre-garbage collection operation, the pre-garbage collection operation is suspended.

3. The memory management method according to claim 2, characterized in that: The step of determining whether to perform the pre-garbage collection operation according to the first total valid data amount includes: Obtaining a first valid data ratio between the first total valid data amount and the total storage space of the plurality of first written physical blocks; When the first valid data ratio is less than a first valid data ratio threshold, it is determined to execute the pre-garbage collection operation.

4. The memory management method according to claim 1, characterized in that: The step of determining whether to perform the garbage collection operation according to the block usage of the plurality of physical blocks and the host write requirement of the storage device comprises: Obtaining a first total number of a plurality of remaining blocks that have not been written to in the plurality of physical blocks; Recording a second total number of the plurality of second written physical blocks in the plurality of remaining blocks; When the ratio of the second total number to the first total number exceeds a usage threshold, determining the host write demand; and If it is determined that the host write demand is high, it is determined to perform the garbage collection operation.

5. The memory management method according to claim 4, characterized in that: The step of determining the host write requirement includes: Acquire a second total valid data amount of the plurality of second written physical blocks; Obtaining a second valid data ratio between the second total valid data amount and the total storage space of the plurality of second written physical blocks; and When the second valid data proportion exceeds a second valid data proportion threshold, the host write demand is determined to be a high demand.

6. The memory management method according to claim 5, characterized in that: The steps of performing the garbage collection operation include: One or more target recovery physical blocks are selected from the multiple physical blocks to perform the garbage collection operation on the one or more target recovery physical blocks, wherein the valid data ratio of each target recovery physical block is less than a recovery valid data ratio threshold.

7. The memory management method according to claim 1, characterized in that: The step of dynamically adjusting the write speed of the host write operation according to the number of the plurality of remaining blocks in the plurality of physical blocks comprises: Obtaining a recycling write speed of the garbage collection operation; The write speed of the current host write operation is adjusted according to a first total number of the plurality of remaining blocks that have not been written in the plurality of physical blocks and the reclaim write speed.

8. The memory management method according to claim 7, characterized in that: The step of adjusting the write speed of the current host write operation according to the first total number of the plurality of remaining blocks that have not been written in the plurality of physical blocks and the reclaim write speed comprises: Obtaining a first remaining ratio between the first total number and the total number of the plurality of physical blocks; The write speed is adjusted using the reclaim write speed according to the first remaining proportion.

9. The memory management method according to claim 8, characterized in that: The step of adjusting the write speed using the recycling write speed according to the first remaining proportion includes: Obtaining a current remaining proportion interval corresponding to the first remaining proportion; Determine a corresponding speed adjustment ratio according to the remaining proportion interval, wherein a lower remaining proportion interval corresponds to a lower speed adjustment ratio; and The write speed is adjusted using the reclaim write speed of the garbage collection operation and the speed adjustment factor.

10. The memory management method according to claim 9, characterized in that: The step of dynamically adjusting the write speed of the host write operation according to the number of the plurality of remaining blocks in the plurality of physical blocks further comprises: When the first total number of the plurality of remaining blocks that have not been written in the plurality of physical blocks reaches a critical remaining number, the remaining proportion interval is determined to be a minimum remaining proportion interval, and the following steps are performed: Selecting one or more target recovery physical blocks from the plurality of physical blocks to perform the garbage collection operation on the one or more target recovery physical blocks; Get the valid data ratio of each target reclaimed physical block; The write speed of the host write operation is adjusted according to the valid data ratio of the target reclaimed physical block and the target reclaimed write speed corresponding to the target reclaimed physical block.

11. The memory management method according to claim 10, characterized in that: The step of adjusting the write speed of the host write operation according to the valid data ratio of the target reclaimed physical block and the target reclaimed write speed corresponding to the target reclaimed physical block includes: Determining an emergency speed adjustment ratio based on a comparison result of the effective data ratio and another threshold value of the recovered effective data ratio; and The write speed of the host write operation is adjusted using the target reclaim write speed and the emergency speed adjustment ratio.

12. The memory management method according to claim 2, characterized in that: The step of pausing the pre-garbage collection operation also includes: Obtaining the current execution progress of the pre-garbage collection operation; Recording the interruption point information corresponding to the current execution progress; and Setting a recovery flag based on the interruption point information, After the host write instruction is executed, it is determined whether to resume the pre-garbage collection operation according to the resumption flag.

13. The memory management method according to claim 4, characterized in that: The step of determining the host write requirement includes: Set a sliding time window; In the sliding time window, according to the logical address range of the received host write instruction, the accumulated written data amount is calculated; and When the accumulated written data amount exceeds a preset data amount threshold, the host write demand is determined to be the high demand.

14. The memory management method according to claim 9, characterized in that: The step of adjusting the write speed using the recycling write speed of the garbage collection operation and the speed adjustment ratio comprises: Get the last write speed; Calculating a speed difference between a current target writing speed and the last writing speed; Determining whether a smooth transition is required according to the speed difference; and If it is determined that the smooth transition is required, the write speed is gradually adjusted to the target write speed within a preset transition period.

15. A memory controller for controlling a storage device equipped with a rewritable non-volatile memory module, characterized in that: The memory controller comprises: A memory interface control circuit, used for electrically connecting to the rewritable non-volatile memory module; a data management circuit electrically connected to the connection interface circuit of the storage device, for receiving data and instructions from a host system via the connection interface circuit; A buffer memory for caching data; and a processor electrically connected to the memory interface control circuit, the data management circuit and the buffer memory, wherein the processor is configured to: Acquiring block usage status of multiple physical blocks of the rewritable non-volatile memory module; Acquiring block usage status of multiple physical blocks of the rewritable non-volatile memory module; When the storage device is in a busy state, determining whether to perform a garbage collection operation according to the block usage of the plurality of physical blocks and a host write demand of the storage device; and When the garbage collection operation is performed during a host write operation, a write speed of the host write operation is dynamically adjusted according to the number of remaining blocks in the plurality of physical blocks.

16. The memory controller according to claim 15, characterized in that: The processor is also configured to: When the storage device is in an idle state, obtaining a first total valid data amount of a plurality of first written physical blocks among the plurality of physical blocks, and determining whether to perform a pre-garbage collection operation according to the first total valid data amount; as well as When a host write instruction is received during the execution of the pre-garbage collection operation, the pre-garbage collection operation is suspended.

17. The memory controller according to claim 16, wherein: The step of determining whether to perform the pre-garbage collection operation according to the first total valid data amount: Obtaining a first valid data ratio between the first total valid data amount and the total storage space of the plurality of first written physical blocks; When the first valid data ratio is less than a first valid data ratio threshold, it is determined to execute the pre-garbage collection operation.

18. The memory controller according to claim 15, wherein: The step of determining whether to perform the garbage collection operation according to the block usage of the plurality of physical blocks and the host write requirement of the storage device comprises: Obtaining a first total number of a plurality of remaining blocks that have not been written to in the plurality of physical blocks; Recording a second total number of the plurality of second written physical blocks in the plurality of remaining blocks; When the ratio of the second total number to the first total number exceeds a usage threshold, determining the host write demand; and If the determined host write demand is a high demand, it is determined to perform the garbage collection operation.

19. The memory controller according to claim 18, wherein: The step of determining the host write requirement includes: Acquire a second total valid data amount of the plurality of second written physical blocks; Obtaining a second valid data ratio between the second total valid data amount and the total storage space of the plurality of second written physical blocks; and When the second valid data proportion exceeds a second valid data proportion threshold, the host write demand is determined to be a high demand.

20. The memory controller according to claim 19, wherein: The steps of performing the garbage collection operation include: One or more target recovery physical blocks are selected from the multiple physical blocks to perform the garbage collection operation on the one or more target recovery physical blocks, wherein the valid data ratio of each target recovery physical block is less than a recovery valid data ratio threshold.

21. The memory controller according to claim 15, wherein: The step of dynamically adjusting the write speed of the host write operation according to the number of the plurality of remaining blocks in the plurality of physical blocks comprises: Obtaining a recycling write speed of the garbage collection operation; The write speed of the current host write operation is adjusted according to a first total number of the plurality of remaining blocks that have not been written in the plurality of physical blocks and the reclaim write speed.

22. The memory controller according to claim 21, wherein: The step of adjusting the write speed of the current host write operation according to the first total number of the plurality of remaining blocks that have not been written in the plurality of physical blocks and the reclaim write speed comprises: Obtaining a first remaining ratio between the first total number and the total number of the plurality of physical blocks; The write speed is adjusted using the reclaim write speed according to the first remaining proportion.

23. The memory controller according to claim 22, wherein: The step of adjusting the write speed using the recycling write speed according to the first remaining proportion includes: Obtaining a current remaining proportion interval corresponding to the first remaining proportion; Determine a corresponding speed adjustment ratio according to the remaining proportion interval, wherein a lower remaining proportion interval corresponds to a lower speed adjustment ratio; and The write speed is adjusted using the reclaim write speed of the garbage collection operation and the speed adjustment factor.

24. The memory controller according to claim 23, wherein: The step of dynamically adjusting the write speed of the host write operation according to the number of the plurality of remaining blocks in the plurality of physical blocks further comprises: When the first total number of the plurality of remaining blocks that have not been written in the plurality of physical blocks reaches a critical remaining number, the remaining proportion interval is determined to be a minimum remaining proportion interval, and the following steps are performed: Selecting one or more target recovery physical blocks from the plurality of physical blocks to perform the garbage collection operation on the one or more target recovery physical blocks; Get the valid data ratio of each target reclaimed physical block; The write speed of the host write operation is adjusted according to the valid data ratio of the target reclaimed physical block and the target reclaimed write speed corresponding to the target reclaimed physical block.

25. The memory controller according to claim 24, characterized in that: The step of adjusting the write speed of the host write operation according to the valid data ratio of the target reclaimed physical block and the target reclaimed write speed corresponding to the target reclaimed physical block includes: Determining an emergency speed adjustment ratio based on a comparison result of the effective data ratio and another threshold value of the recovered effective data ratio; and The write speed of the host write operation is adjusted using the target reclaim write speed and the emergency speed adjustment ratio.

26. The memory controller according to claim 16, wherein: The step of pausing the pre-garbage collection operation also includes: Obtaining the current execution progress of the pre-garbage collection operation; Recording the interruption point information corresponding to the current execution progress; and Setting a recovery flag based on the interruption point information, After the host write instruction is executed, it is determined whether to resume the pre-garbage collection operation according to the resumption flag.

27. The memory controller according to claim 18, wherein: The step of determining the host write requirement includes: Set a sliding time window; In the sliding time window, according to the logical address range of the received host write instruction, the accumulated written data amount is calculated; and When the accumulated written data amount exceeds a preset data amount threshold, the host write demand is determined to be the high demand.

28. The memory controller according to claim 23, wherein: The step of adjusting the write speed using the recycling write speed of the garbage collection operation and the speed adjustment ratio comprises: Get the last write speed; Calculating a speed difference between a current target writing speed and the last writing speed; Determining whether a smooth transition is required according to the speed difference; and If it is determined that the smooth transition is required, the write speed is gradually adjusted to the target write speed within a preset transition period.

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