A matrix storage method and apparatus

Abstract

A matrix storage method and apparatus are disclosed. In this method, multiple first sub-blocks corresponding to the original matrix to be stored are obtained. Each first sub-block is obtained by dividing the original matrix into sub-blocks of size M1×N1, and compressing the non-zero elements in each sub-matrix obtained after division in a specified direction, where M1 and N1 are positive integers. Each first sub-block is then divided into sub-blocks of size M2×N2 to obtain multiple second sub-blocks, where M2 is a positive integer not greater than M1, and N2 is a positive integer not greater than N1. The data of the multiple second sub-blocks are stored sequentially, using the second sub-blocks as storage units. This design provides a compressed storage method that can achieve row and column alignment of non-zero elements and block row and column alignment, improving data locality, data compression ratio, and parallelism of matrix data access.

Description

[0001] This application is a divisional application. The original application has the application number 202310875441.5 and the original application date is July 14, 2023. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of data processing technology, and in particular to a matrix storage method and apparatus. Background Art

[0003] Sparse matrix data format is one of the most important data types in artificial intelligence (AI), high-performance computing (HPC), graph computing, and graph neural network convolutional computation (GNN). Currently, the main sparse matrix data formats include: coordinate (COO) format, compressed sparse row (CSR) format, compressed sparse column (CSC) format, and elliptic equation format (ELLPACK format, ELL).

[0004] Currently, new types of matrix accelerators such as CPU, GPU, NPU, and PIM chips are developing rapidly. The efficiency gap between sparse computing and dense computing is gradually widening. Existing sparse compression formats may no longer be able to meet the high concurrency requirements of GPUs, vectors, and matrix units. There is an urgent need for a new compression storage method for sparse matrices. Summary of the Invention

[0005] This application provides a matrix storage method and apparatus, which provides a new compressed storage method for sparse matrices.

[0006] In a first aspect, this application provides a matrix storage method. This method can be executed by a device with data processing capabilities (such as a computing device) or by a component in the device (such as a processor). Taking a computing device as an example, in this method, the computing device can obtain multiple sub-blocks (denoted as first sub-blocks) corresponding to the original matrix. There are multiple ways to obtain them. For example, the computing device receives multiple first sub-blocks input by the user, or the computing device obtains multiple first sub-blocks stored in its own memory. The computing device first obtains the original matrix and then processes the original matrix to obtain the multiple first sub-blocks.

[0007] The multiple first sub-blocks are obtained by the computing device or other devices after the original matrix is ​​processed by cutting, compressing, etc. For example, the original matrix is ​​cut into sub-blocks of size M1×N1 (where M1 and N1 are positive integers) to obtain multiple sub-matrices of size M1×N1. Then, the non-zero elements in each sub-matrix are compressed in a specified direction (such as the row direction or the column direction) to obtain multiple first sub-blocks.

[0008] Next, the computing device further divides each first sub-block into multiple second sub-blocks, each with a size of M2×N2. Here, M2 is a positive integer not greater than M1, N2 is a positive integer not greater than N1, and the size of an M2×N2 sub-block is smaller than the size of an M1×N1 sub-block. The data of these multiple second sub-blocks are then stored sequentially, using the second sub-blocks as the storage unit.

[0009] Through the above design, multiple first sub-blocks corresponding to the original matrix are obtained. These multiple first sub-blocks are obtained by compressing the non-zero elements in multiple sub-matrices of the original matrix in a specified direction. Then, each first sub-block is further divided into smaller blocks to obtain multiple second sub-blocks corresponding to one first sub-block.

[0010] Dividing the original matrix into multiple first sub-blocks improves the compression ratio. Further dividing these first sub-blocks into multiple second sub-blocks enhances the compression ratio. This approach adapts to arbitrarily distributed sparse matrices and maintains a high compression ratio under any sparse matrix. Storing multiple second sub-blocks sequentially facilitates memory access; a single memory access can retrieve at least one complete second sub-block, reducing the number of memory accesses during sparse matrix computation. Since all rows and columns of the second sub-block have consistent lengths, it provides a more user-friendly data access method for vector or matrix processors. It can achieve good locality for row-order or column-order access, enabling efficient adaptation to dedicated hardware accelerators and improving the parallelism of sparse matrix computation. On one hand, a single memory access can retrieve multiple complete second sub-blocks, which can be computed in parallel by multiple dedicated hardware accelerators, thus improving multi-core parallelism. On the other hand, since a second sub-block can provide a sufficient amount of data to a dedicated hardware accelerator, it is more suitable for the dedicated hardware accelerator to accelerate the calculation, which is conducive to improving the intra-core parallelism of a single dedicated accelerator and the performance of the dedicated hardware accelerator can be greatly improved.

[0011] In one possible implementation, the method further includes:

[0012] The computing device obtains the index data of each first sub-block in several ways. For example, the computing device may receive the index data of each first sub-block input by the user; or, the computing device may obtain the index data of each first sub-block from its own storage; or, the computing device may determine the index data of each first sub-block based on the obtained original matrix. In some cases, the index data of the first sub-block can be obtained together with the first sub-block itself; this is not specifically limited.

[0013] Taking a first sub-block as an example, the index data of the first sub-block is used to indicate the position (index, i.e., row and column number) of each element within the first sub-block in the original matrix; the index data of the first sub-block includes the corresponding displacement value pair, index matrix, and index vector; these are described below:

[0014] In one example, when the specified direction is row direction:

[0015] (1) The displacement value pair includes a pair of displacement values, denoted as the first displacement value and the second displacement value, wherein the first displacement value is used to indicate the first offset of the corresponding row of the first sub-block (i.e., the starting row) in the original matrix relative to the starting row (e.g., row 0) of the original matrix, and the second displacement value is used to indicate the second offset of the corresponding column of the first sub-block (i.e., the first column) in the original matrix relative to the starting column (e.g., column 0) of the original matrix;

[0016] (2) The value of any element (such as the first element) in the index matrix is ​​equal to the difference between the column number of the element corresponding to the first element in the first sub-block in the original matrix and the second offset. Among them, multiple elements in the index matrix correspond one-to-one with multiple elements in the first sub-block.

[0017] (3) The value of any element in the index vector (such as the second element) is used to indicate the difference between the row number of the element corresponding to the second element in the first sub-block and the first offset in the original matrix. Among them, multiple elements in the index vector correspond one-to-one with each row of the first sub-block.

[0018] In another example, when the specified direction is column direction:

[0019] 1) The displacement value pair includes a pair of displacement values, denoted as the first displacement value and the second displacement value. The first displacement value is used to indicate the first offset of the corresponding row of the first sub-block (i.e., the starting row) in the original matrix relative to the starting row (e.g., row 0) of the original matrix. The second displacement value is used to indicate the second offset of the corresponding column of the first sub-block (i.e., the first column) in the original matrix relative to the starting column (e.g., column 0) of the original matrix.

[0020] 2) Multiple elements in the index matrix correspond one-to-one with multiple elements in the first sub-block. The value of any element in the index matrix (such as the first element) is equal to the difference between the row number of the element corresponding to the first element in the first sub-block in the original matrix and the first offset. Here, multiple elements in the index matrix correspond one-to-one with multiple elements in the first sub-block.

[0021] 3) The value of any element in the index vector (such as the second element) is used to indicate the difference between the column number of the element corresponding to the second element in the original matrix and the second offset. Multiple elements in the index vector correspond one-to-one with each row of the first sub-block.

[0022] Through the above design, the main optimization of the element index data by dividing the original matrix into submatrix shift value pairs, index arrays, and index vectors can be achieved. As those skilled in the art know, when the size of the original matrix is ​​large, the original global index data range is usually high precision, such as INT64 or INT32, and the data volume is also relatively large. After being divided into submatrixes by the method of this application embodiment, the index data range of each submatrix will be smaller, and only lower index precision is needed, such as using INT16 or INT8 to completely include the index range. Each submatrix only needs to store one shift value pair, and the amount of index data that the entire submatrix needs to store can be greatly reduced.

[0023] In one possible implementation, the method further includes: the aforementioned plurality of second sub-blocks include a plurality of third sub-blocks, wherein the plurality of third sub-blocks are obtained by dividing the index matrix corresponding to each first sub-block into sub-blocks of size M2×N2.

[0024] In one possible implementation, the computing device stores a mapping relationship between the second sub-block and the third sub-block, in which multiple second sub-blocks correspond one-to-one with multiple third sub-blocks. Specifically, taking a first sub-block as an example, in this mapping relationship, multiple second sub-blocks corresponding to the first sub-block correspond one-to-one with multiple third sub-blocks corresponding to the index matrix of the first sub-block.

[0025] The method for storing the second sub-block is as follows: First sub-blocks are selected in row or column order from the multiple first sub-blocks. Then, using the second sub-blocks as storage modules, second sub-blocks are sequentially selected from the selected first sub-blocks in the row direction for storage. Elements within each second sub-block can be stored in row or column order. Similarly, the method for storing the third sub-block is as follows: Third sub-blocks are selected sequentially from the index matrix corresponding to the selected first sub-blocks in the row direction for storage. Alternatively, all second sub-blocks corresponding to multiple first sub-blocks are arranged in row or column order, and then all arranged second sub-blocks are sequentially selected in row or column order for storage. Similarly, all third sub-blocks corresponding to multiple first sub-blocks are arranged in row or column order, and then all arranged third sub-blocks are sequentially selected in row or column order for storage.

[0026] Multiple second sub-blocks and multiple third sub-blocks can be stored separately or intermittently. Separate storage means that multiple second sub-blocks are stored in a first storage space, and these sub-blocks are stored sequentially within the first storage space. For example, one possible storage order within the first storage space is: second sub-block A, second sub-block B, second sub-block C, and so on. Similarly, multiple third sub-blocks are stored in a second storage space, and these sub-blocks are stored contiguously within the second storage space. For example, one possible storage order within the second storage space is: the third sub-block corresponding to second sub-block A, the third sub-block corresponding to second sub-block B, the third sub-block corresponding to second sub-block C, and so on. This way, when sequentially reading multiple second sub-blocks, the corresponding third sub-blocks can also be read sequentially.

[0027] Interleaved storage refers to storing data in an adjacent manner, where the second and third sub-blocks are adjacent. That is, a second sub-block and its corresponding third sub-block form a storage module, and each second sub-block and its corresponding third sub-block are stored sequentially. For example, one storage order might be: second sub-block A, second sub-block A's corresponding third sub-block, second sub-block B, second sub-block B's corresponding third sub-block, second sub-block C, and so on. In this way, a single memory access can continuously read the second sub-block and its corresponding third sub-block.

[0028] Optionally, the addresses of multiple second sub-blocks and / or multiple third sub-blocks can be stored sequentially, which facilitates data reading and prefetching.

[0029] Through the above design, this storage method can complete the data access of multiple consecutive second and / or third sub-blocks in a single data access, which facilitates memory access, helps reduce the number of memory accesses during sparse matrix calculation, can be adapted to dedicated hardware accelerators with high efficiency, and helps improve the parallelism of sparse matrix calculation.

[0030] In one possible implementation, each second sub-block stored by the computing device includes at least one non-zero element; in some cases, before the computing device sequentially stores the values ​​of the elements within each second sub-block, it includes: removing second sub-blocks that include all-zero elements.

[0031] With the above design, the second sub-block containing all zeros can be completely deleted without needing to be stored. In this way, it can adapt to sparse matrices with arbitrary distributions and maintain a high compression ratio under any sparse matrix.

[0032] Secondly, embodiments of this application provide a matrix computing device. This device has the function of implementing the computing device behavior in the first aspect and any possible implementation method example of the first aspect. The beneficial effects can be found in the description of the first aspect and will not be repeated here. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions. In one possible design, the device structure includes an acquisition module, a processing module, and a storage module. These modules can perform the functions of the computing device behavior in the first aspect and any possible implementation method example of the first aspect, as detailed in the method examples, and will not be repeated here.

[0033] Thirdly, embodiments of this application provide a computing device that has the functionality to implement the computing device behavior described in the first aspect and any possible implementation method example of the first aspect. The beneficial effects are described in the first aspect and will not be repeated here. The computing device includes a processor and a memory. The processor is configured to support the device in executing the corresponding functions of the computing device in the method example of the first aspect. The memory is coupled to the processor and stores necessary program instructions and data for the communication device. The communication device also includes a communication interface for communicating with other devices.

[0034] Fourthly, this application also provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the methods described in the first aspect and various possible embodiments of the first aspect, or cause the computer to perform the methods described in the first aspect and various possible embodiments of the first aspect.

[0035] Fifthly, this application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the methods described in the first aspect and various possible implementations of the first aspect, or cause the computer to perform the methods described in the first aspect and various possible implementations of the first aspect.

[0036] In a sixth aspect, this application also provides a computer chip connected to a memory, the chip being used to read and execute software programs stored in the memory, to execute the methods described in the first aspect and various possible designs of the first aspect, or to cause a computer to execute the methods described in the first aspect and various possible implementations of the first aspect. Attached Figure Description

[0037] Figures 1 to 7 This is a schematic diagram of a sparse matrix data format;

[0038] Figure 8 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0039] Figure 9 This is a flowchart illustrating a matrix storage method provided in an embodiment of this application.

[0040] Figure 10 A schematic diagram of a matrix blocking process provided in an embodiment of this application;

[0041] Figure 11 This is a schematic diagram illustrating a process for compressing a submatrix, provided as an embodiment of this application.

[0042] Figure 12 A schematic diagram of a submatrix and its corresponding element value array provided in an embodiment of this application;

[0043] Figure 13 This is a schematic diagram illustrating another method of compressing a submatrix, as provided in an embodiment of this application.

[0044] Figure 14 A schematic diagram illustrating the cutting of a small piece according to an embodiment of this application;

[0045] Figure 15 A schematic diagram illustrating a small-block storage method provided in an embodiment of this application;

[0046] Figure 16 A schematic diagram illustrating another small-block storage method provided in an embodiment of this application;

[0047] Figure 17 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0048] To better explain the embodiments of this application, the relevant terms or technologies used in this application will be explained first:

[0049] I. Row Vectors

[0050] A row vector is a 1×m matrix, where m is any positive integer, for example: x = [x1 x2 … xm].m ].

[0051] II. Column Vectors

[0052] A column vector is an n×1 matrix, where n is any positive integer, for example:

[0053] III. Matrix Size / Scale

[0054] An m×n matrix is ​​a rectangular array consisting of m rows and n columns of elements. For example:

[0055]

[0056] In a matrix, each number that makes up the matrix is ​​called an element of the matrix. For example, A 11 A 12 A mn All of these are elements of matrix A. The index (or coordinate) of an element indicates its position within the matrix; it can be the row number (or row coordinate) or column number (or column coordinate). For example, A 11 The subscript "11" indicates that the element is located in the first row and first column of matrix A. 21 This indicates that the element is located in the second row and first column of matrix A. Additionally, the element's subscript can have different representations, such as A... 11 It can also be written as A 1，1 A 21 It can also be written as A 2，1 Similar details will not be repeated below.

[0057] It should be noted that the row number of the first row of a matrix is ​​not limited to 1, but can also be other values, such as 0. Similarly, the column number of the first column of a matrix is ​​not limited to 1, but can also be 0 or other data. For example, if the row number of the first row and the column number of the first column of the matrix above are 0 and 0 respectively, then the index of the first element in the matrix is ​​"00", which means that the element is in the 0th row and 0th column of the matrix.

[0058] IV. Matrix addition

[0059] Matrix addition refers to the addition of two matrices of the same size (i.e., the two matrices have the same number of rows and columns), such as A and B, which are both m×n matrices, and matrix C = A + B.

[0060]

[0061] Similarly, matrix subtraction refers to subtracting the elements at the same positions in two matrices of the same size.

[0062] V. Matrix multiplication

[0063] For two matrices to be multiplied (such as matrices D and E), the number of columns in D must be the same as the number of rows in E. For example, if D is an m×n matrix and E is an n×p matrix, then their product will be an m×p matrix. For instance:

[0064]

[0065] VI. Sparse matrix / Dense matrix

[0066] Matrices are classified into sparse and dense matrices based on the proportion of non-zero elements in the matrix. A non-zero element is an element whose value is not 0, while a zero element is an element whose value is 0.

[0067] A matrix is ​​considered dense if most (more than 50%) of its elements are non-zero. Conversely, a matrix is ​​considered sparse if most of its elements are zero. Sparsity reflects the proportion of non-zero elements in a sparse matrix; higher sparsity indicates a lower proportion of non-zero elements. Below is an example of a sparse matrix:

[0068]

[0069]

[0070] It's understandable that large matrices require significant memory for storage, while sparse matrices contain mostly zero values. Therefore, when storing and manipulating sparse matrices in a computer, the elements are typically encoded using sparse codes. These codes usually only include information about the non-zero elements (such as their values ​​and indices), saving memory overhead during operations. In contrast, matrices in uncompressed formats are generally called dense matrices. Dense matrices only contain the values ​​of their elements and do not store their coordinates.

[0071] The following is an introduction to several common sparse coding formats (also known as sparse matrix data formats):

[0072] (1) Coordinate Format (COO): Matrix is ​​represented by triples, which consist of three values: row number, column number, and element value. The row and column numbers identify the position of the element value within the original matrix. See also... Figure 1 , Figure 1The coordinate format corresponding to a simple sparse matrix is ​​shown as an example. Note that, for the sake of brevity, Figure 1 The sparse matrix in the figure only shows non-zero elements, and the rest are zero elements. Similarities will not be repeated below.

[0073] (2) Compressed Sparse Column (CSC): Sparse matrices are represented using three types of data: column offsets, row numbers, and element values. The difference between CSC and COO is that CSC uses column offsets instead of column numbers. The column offset represents the starting offset position of the first non-zero element in a given column within the numerical data.

[0074] Figure 2 An example of CSC compression is shown below. The three types of data are described below:

[0075] like Figure 2 As shown, based on the index pointer (011467), several intervals can be obtained, namely: [0,1), [1,1), [1,4), [4,6), [6,7). These intervals correspond to the elements in columns 0, 1, 2, 3, and 4, respectively. That is, [0,1) corresponds to column 0, [1,1) corresponds to column 1, [1,4) corresponds to column 2, and so on.

[0076] Based on [0,1), the 0th row number is selected in indices, i.e., 0. Since [1,1) has no valid range, the row number selected in indices based on [1,1) is none. Based on [1,4), the 1st to 3rd row numbers are selected in indices, i.e., 0, 1, and 4. Based on [4,6), the 4th and 5th row numbers are selected in indices, i.e., 4 and 6. Based on [6,7), the 6th row number is selected in indices, i.e., 4.

[0077] Based on the data, we can determine that [0,1) corresponds to the element 8 in the 0th row of the 0th column. [1,1) has no corresponding element. [1,4) corresponds to the element 2 in the 0th row of the 2nd column, the element 5 in the 1st row of the 2nd column, and the element 5 in the 4th row of the 2nd column. [4,6) corresponds to the element 1 in the 4th row of the 3rd column, and the element 9 in the 6th row of the 3rd column. [6,7) corresponds to the element 9 in the lower 4 rows of the 4th column.

[0078] (3) Compressed Sparse Row (CSR): Sparse matrices are represented using three types of data: row offset, column number, and element value. The difference between CSR and COO is that CSR uses row offset instead of row number. The row offset represents the starting offset position of the first non-zero element in the data within a given row. Figure 3 An example of compression in CSR format is shown below. The row offset values ​​of CSR are used in a similar way to the column offset values ​​of CSC, as described above, and will not be repeated here.

[0079] (4) Elliptic equation format (ELLPACK format, ELL): Two matrices with the same number of rows as the original matrix are used to store the values ​​and column indices, respectively. The matrix used to store the column indices can be called the column index matrix, and the matrix used to store the values ​​can be called the value matrix. If there are no elements in either matrix, they are padded with 0s up to the set row length.

[0080] Figure 4 An example of ELL compression is shown. It can be seen that if a row contains too much attribute information, the column number matrix and the numerical matrix will become abnormally "fat". Other rows will have many padding zeros at the end, wasting storage space and affecting the compression ratio, which may be relatively low.

[0081] (5) Sliced ​​Elliptic Equation Format (SELL): SELL is an extension of the ELL format. It divides the input matrix into C adjacent rows of slices, sorts the rows within each slice according to the number of non-zero elements, and stores each slice in ELL format. The number of non-zero elements stored in an ELL may vary from slice to slice, and each slice can have different row lengths. This reduces the amount of zero-padding in each slice, thereby improving the compression ratio. Furthermore, it introduces sorting to save storage overhead. Another variation is to restrict the matrix sorting range to σ, meaning that the format sorts the matrix rows not globally but within σ consecutive rows, further reducing the additional computational cost introduced by sorting. Finally, each slice can be divided into arrays of various sizes according to the sorted element distribution for storage, further reducing the compression ratio.

[0082] Figure 5 Here is a sample of a SELL compression, such as Figure 5As shown, the original matrix is ​​divided into two strips. Within each strip, rows are sorted from largest to smallest according to row length (measured by the number of non-zero elements), and the data for each strip is stored in ELL format. The first strip consists of an 8×6 array and a 3×6 array, and the second strip consists of a 9×6 array and a 3×6 array.

[0083] The above text introduced several sparse matrix data formats. Currently, sparse matrix data formats are important data types in the fields of artificial intelligence (AI), high-performance computing (HPC), graph computing, and graph neural network convolutional computing (GNN). For example, these compressed data are widely used in many matrix operation scenarios such as sparse matrix-vector multiplication (SpMV), sparse matrix-sparse vector multiplication (SpMSpV), sparse matrix-matrix multiplication (SpMM), and sparse matrix-sparse matrix multiplication (SpGEMM, SpMSpM, or SpSpMM).

[0084] Among these, Compressed Sparse Column Format (CSC), Compressed Sparse Row Format (CSR), and Coordinate Format Matrix (COO) are the more mainstream data formats. The idea behind these formats is to compress non-zero elements along the row or column direction to store their values ​​and indices. Specifically, as mentioned earlier, CSC and CSR use two independent arrays to store the values ​​of all non-zero elements in the original sparse matrix, along with their row or column indices, and a third array to provide pointers to the starting positions of each row or column. In practice, the main drawback of CSC and CSR is their poor locality of access to the values ​​or indices of the sparse matrix. Locality can be understood as the tendency for processors (such as CPUs) to cluster within a small, contiguous region when accessing memory (such as main memory), whether accessing instructions or data. For example, see... Figure 6 As shown in (a), CSC exhibits good locality for data storage and access in the column direction, but poor locality for access in the row direction. Similarly, see... Figure 6 As shown in (b), CSR exhibits good locality for data storage and access in the row direction, but poor locality for access in the column direction. Furthermore, the inconsistent row or column lengths in this format make it difficult to access multiple vectors simultaneously. This is because a single vector instruction can only access row or column vectors of a fixed length; when row or column lengths are inconsistent, multiple vectors cannot be accessed with a single instruction. This also makes it difficult to use processors with higher parallelism to accelerate matrix calculations.

[0085] In recent years, the elliptic equation scheme (ELLPACK) has also received considerable attention. The elliptic equation scheme is designed to improve the execution efficiency of vector processors. See also... Figure 7 As shown, compared to the compressed sparse row format, it uses zero-padding to ensure that the length of non-zero elements in each row is consistent. For a matrix A of size m×n with a maximum row length (the number of non-zero elements in that row) of size k, it requires an array of size m×k to store matrix A. The main drawback of the elliptic equation format is that if the distribution of non-zero elements in the original sparse matrix is ​​irregular, it will lead to a large difference in row length after compression. This results in more zero-padding in the array of the elliptic equation format, leading to a decrease in compression ratio and a corresponding decrease in the computational efficiency of the vector processor.

[0086] Therefore, based on the elliptic equation format (ELLPACK), some improved data formats have been derived, such as the sliced ​​elliptic equation format (SELL). Return Figure 5 It is understood that although the slice elliptic equation scheme can further reduce the compression ratio compared to the elliptic equation scheme, the slice elliptic equation scheme has the same problem as the elliptic equation scheme, namely, when the distribution of non-zero elements within a slice (such as a strip) is irregular, the compression ratio is still relatively low.

[0087] In summary, existing sparse matrix compression formats all have some drawbacks. These drawbacks prevent existing data formats from meeting the high-concurrency requirements of new types of vector processors (or matrix accelerators), thus limiting the development of vector processors. A data format that can satisfy data locality and high compression ratio is very important and is also a key technology driving the development of sparse matrix computing acceleration chips.

[0088] In view of this, this application provides a matrix storage method based on a novel sparse matrix data format provided in this application. This data format is applicable to sparse matrices with arbitrary sparsity and arbitrary distribution of non-zero elements, solving the problem of determining existing data formats and exhibiting good locality and high compression ratio. In simple terms, taking execution by a computing device as an example, the computing device processes the original matrix based on this data format to obtain the sparse encoding of the data format, and stores the sparse encoding of the data format at a fixed-size array granularity. This storage method saves storage overhead and has good data locality, high compression ratio, and parallelism.

[0089] The technical solutions provided in the embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0090] Figure 8This is a schematic diagram of a computing device 800 provided in this application. The computing device 800 includes a processor 801 and a memory 802. Optionally, the device 800 may further include a communication interface 804 and a matrix arithmetic unit 806. The processor 801, memory 802, matrix arithmetic unit 806, and communication interface 804 can be interconnected via a communication line 805. The communication line 805 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication line 805 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 8 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0091] The processor 801 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an artificial intelligence (AI) chip, a system-on-chip (SoC), a complex programmable logic device (CPLD), a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, or one or more integrated circuits used to control the execution of the program of the present application.

[0092] Please note that Figure 8 Only one processor 801 is shown in this embodiment. In practical applications, there can be multiple processors 801. These multiple processors 801 may include multiple processors of the same type or multiple processors of different types. For example, the multiple processors 801 may include multiple CPUs. Alternatively, the multiple processors 801 may include at least one CPU and at least one GPU. Each CPU may have one or more CPU cores. This embodiment does not limit the number of processors 801 or the number of CPU cores.

[0093] Specifically, the processor 801 is used to process data access requests from outside the computing device 800 (such as other computing devices), and also to process requests generated internally by the computing device 800. For example, the request may be a write data request, which includes an original matrix, which may be a sparse matrix. After receiving the write data request, the processor 801 can execute the matrix storage method provided in this embodiment to process the original matrix and save the processed data in the memory 802. As another example, the request may also be a read data request, which requests to read matrix data. The matrix data may include part or all of the original matrix. After receiving the read data request, the processor 801 reads the matrix data from the memory 802.

[0094] In addition to the above, processor 801 is also used for other data calculations or processing, such as matrix operations, specifically sparse matrix-vector multiplication (SpMV), sparse matrix-sparse vector multiplication (SpMSpV), sparse matrix-matrix multiplication (SpMM), sparse matrix-sparse matrix multiplication (SpGEMM, SpMSpM, or SpSpMM), etc., without limitation. Optionally, the above matrix operations can also be assigned to matrix arithmetic unit 806 for execution. In some cases, when processor 801 has multiple cores, or computing device 800 includes multiple processors 801, or computing device 800 includes multiple matrix arithmetic units 806, multiple cores, multiple processors 801, or multiple matrix arithmetic units 806 can execute matrix operations in parallel, which will not be elaborated here.

[0095] The matrix operator 806 can be used to handle matrix operations, as described above. The matrix operator 806 can include, but is not limited to, vector processors (VP), vector processor systems (VPS), matrix processors, matrix accelerators, etc.

[0096] The communication interface 804 uses any transceiver-like device to communicate with other devices or communication networks, such as Ethernet, radio access networks (RAN), wireless local area networks (WLAN), and wired access networks. For example, it can be used to obtain read data requests, write data requests, matrix data, etc.

[0097] Memory 802 is used to store data and computer-executable program code. Data includes, but is not limited to, the original matrix data and the sparse encoding of a sparse matrix. The executable program code may include the program code of the matrix storage method provided in the embodiments of this application. Processor 801 executes the executable program code to implement the matrix storage method provided in this embodiment. That is, memory 1406 stores computer execution instructions for executing the scheme of this application, and the processor 801 controls the execution. Processor 801 is used to execute the computer execution instructions stored in memory 802 to implement the matrix storage method provided in the above embodiments of this application.

[0098] For example, memory 802 may also store a sparse matrix function library (spares blas), which may include, but is not limited to, one or more instructions provided in this embodiment: block instructions (the function of which can be found in the description of step 902, and will not be repeated here), compression instructions (the function of which can be found in the description of step 903, and will not be repeated here), zero-filling instructions, and tiling instructions (the function of which can be found in the description of step 904, and will not be repeated here). The function library may also include other instructions, such as instructions for implementing existing sparse matrix data formats, such as instructions for compressing sparse column formats, elliptic equation formats, etc. Memory 802 may also store matrix operation instructions, such as vector read instructions, sparse matrix-vector multiplication (SpMV), sparse matrix-sparse vector multiplication (SpMSpV), sparse matrix-matrix multiplication (SpMM), sparse matrix-sparse matrix multiplication (SpGEMM or SpMSpM or SpSpMM), etc. Optionally, memory 802 may also store source code implementing any instruction or function in the function library.

[0099] The memory 802 can exist independently and be connected to the processor via communication line 805. Alternatively, the memory 802 can be integrated with the processor. Specifically, the memory 802 can include RAM or a hard disk. RAM refers to the internal storage that directly exchanges data with the processor 801. It can read and write data at any time and at a very fast speed, serving as temporary data storage for the operating system or other running programs. Unlike RAM, the hard disk reads and writes data more slowly and is typically used for persistent data storage. In some applications, the processor 801 can temporarily store data (such as sparse coding of sparse matrices) in RAM. When the total amount of data in RAM reaches a certain threshold, the processor 801 sends the data stored in RAM to the hard disk for persistent storage. This data can be obtained from external devices, input by the user, or generated by the computing device 800; there are no specific limitations. Alternatively, the processor 801 can read data from RAM. If a memory cache miss occurs, the processor 801 reads the data from the hard disk into RAM and then reads the data from RAM again.

[0100] The memory includes at least two types of storage, such as random access memory (RAM) and read-only memory (ROM). For example, RAM can be dynamic random access memory (DRAM) or storage class memory (SCM). Memory can also include other types of RAM, such as static random access memory (SRAM). For read-only memory, examples include programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM). Additionally, the memory can be a dual in-line memory module (DIMM), i.e., a module composed of DRAM. In practical applications, the computing device 800 can be configured with multiple memory modules of different types. This embodiment does not limit the number or type of memory.

[0101] A hard drive can specifically be a disk or other type of storage medium, such as a solid-state drive (SSD), a hard disk drive (HDD), a shingled magnetic recording hard disk, a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, universal optical discs, Blu-ray discs, etc.), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.

[0102] It should be noted that, Figure 8 The structure of the computing device 800 shown is merely an example. In practical applications, the computing device 800 may have more or fewer components. For example, the computing device 800 may also include input / output devices such as a keyboard, mouse, and display screen. This application embodiment does not limit this.

[0103] Next, let's apply it to... Figure 8 Taking the computing device shown as an example, the data format and corresponding matrix storage method provided in the embodiments of this application will be described in detail.

[0104] Figure 9 This is a flowchart illustrating the compressed storage method provided in the embodiments of this application. This method can be executed by a computing device with data processing capabilities (such as computing device 800), or by a component of that computing device, such as processor 801 or matrix arithmetic unit 806. For ease of explanation, the following description uses computing device 800 as an example. Figure 9 As shown, the method includes:

[0105] Step 901: Obtain the matrix data of the original matrix to be processed.

[0106] There are several ways to acquire matrix data. One method is for the processor 801 to receive matrix data input from an external source. For example, the matrix data could be input by a user through a terminal device to the computing device 800, or directly input by the user to the computing device 800. Accordingly, the computing device 800 (processor 801) receives the matrix data directly or indirectly input by the user. Another method is for the processor 801 to acquire matrix data locally from the computing device 800, such as by acquiring matrix data from memory 802.

[0107] The matrix data can be the original matrix data, which can be a dense matrix or a sparse matrix of arbitrary sparsity. Alternatively, the matrix data can be a sparse encoding of a sparse matrix, and the data format used for this sparse encoding can be any sparse matrix data format other than those provided in this application, such as, but not limited to, CSC, CSR, COO, ELLPACK, etc. In short, any sparse encoding capable of recovering the original matrix is ​​applicable to the embodiments of this application. Alternatively, the matrix data can also be data after further value-added processing of the sparse encoding, such as deduplication, compression, etc., which are not specifically limited.

[0108] The above is merely an example; in practical applications, any type of matrix data and the method of obtaining it are applicable to the embodiments of this application.

[0109] Step 902: The original matrix is ​​divided into blocks of size M1×N1 to obtain multiple sub-matrices.

[0110] Step 902 will be described using the example of an original matrix being a sparse matrix.

[0111] Figure 10This is a schematic diagram illustrating the segmentation of a sparse matrix in this embodiment. Assume the sparse matrix has a size of X×Y, and the sub-block size is M1×N1, where M1 and N1 are positive integers, and M1×N1 is less than X×Y. In one case, M1 is a positive integer less than X, and N1 is a positive integer not greater than Y; alternatively, M1 is a positive integer not greater than X, and N1 is a positive integer less than Y. Typically, M1 is a positive integer less than X, N1 is a positive integer less than Y, M1 can be equal to N1, and X can be equal to Y. For ease of explanation, assume... Figure 10 In the given diagram, M1 = N1 = 3. Dividing the sparse matrix into 3×3 sub-blocks yields at least one 3×3 sub-matrix, effectively dividing the sparse matrix into multiple 3×3 sub-matrices. These sub-matrices are sequentially adjacent and do not overlap. Furthermore, since X may not be an integer multiple of M1, and / or Y may not be an integer multiple of N1, the sizes of these sub-matrices may be identical, completely different, or not identical.

[0112] like Figure 10 As shown in (a), the sparse matrix A is divided into four sub-matrices of size 3×3, each of which is the same size. Figure 10 As shown in (b), the sparse matrix B is divided into four sub-matrices of size 3×3. These four sub-matrices are not all the same size; the top two sub-matrices are 3×3, and the bottom two are 3×2. For example... Figure 10 As shown in (c), the sparse matrix C is divided into four submatrices of size 3×3. These four submatrices have completely different sizes: 3×3, 2×3, 3×2, and 2×2. Note that... Figure 10 The size of the sparse matrix and the size of the sub-blocks are just examples. In actual applications, the size of the sparse matrix is ​​usually quite large, and this application does not limit it.

[0113] Step 903: Compress each submatrix to obtain compressed data corresponding to each submatrix.

[0114] Taking a submatrix as an example, the compression process provided in this application may include: the processor 801 compresses the non-zero elements in the submatrix in a specified direction (such as the row direction or the column direction) to obtain the compressed data of the submatrix.

[0115] The compression method provided in this embodiment will be described below, considering both row and column directions. In the following text, compression along the row direction can also be simply referred to as row compression; both have the same meaning. Similarly, compression along the column direction can also be simply referred to as column compression.

[0116] 1. Specify the direction as row direction.

[0117] See Figure 11 ,exist Figure 11 In the diagram, the sparse matrix is ​​divided into four sub-matrices by a sub-block of size M1×N1. The four sub-matrices are denoted as sub-matrix 1, sub-matrix 2, sub-matrix 3, and sub-matrix 4 in order from left to right and from top to bottom.

[0118] Firstly Figure 11 Taking submatrix 1 as an example, the specific process of compression processing of submatrix 1 by processor 801 may include:

[0119] The non-zero elements in submatrix 1 are compressed row-wise to generate compressed data for submatrix 1. The compressed data for submatrix 1 includes: an array of element values ​​(e.g., block data) and index data.

[0120] (1) The array of element values ​​of submatrix 1 includes the non-zero elements in submatrix 1.

[0121] The element value array comprises the non-zero elements of submatrix 1 arranged in row order. Non-zero elements in the same row of the original matrix remain in the same row in the element value array, and there are no gaps between them. The compression process to obtain this element value array can include: compressing the non-zero elements in submatrix 1 row by row (if the submatrix contains rows with all elements, the entire row with zero elements can be compressed), and zero-padding according to the maximum row length after compression, to obtain the element value array (also called the element value matrix) corresponding to submatrix 1. Optionally, zero-padding according to the maximum row length after compression of submatrix 1 can also be performed to obtain the element value data corresponding to submatrix 1, where all rows and columns have the same length. The compression process for the element value arrays of the remaining submatrixes is the same and will not be described further here.

[0122] (2) The subscript data (e.g., global index) of submatrix 1 is used to indicate the position (or subscript, hereinafter referred to as the original position / original subscript) of each non-zero element in the element value array within the original matrix. The original subscript includes the original row number and the original column number. The original row number refers to the row number of the non-zero element in the element value array within the original matrix, and the original column number refers to the column number of the non-zero element in the element value array within the original matrix. For example, in... Figure 11 In the original matrix, the element in the 0th row and 0th column of the element value array has an original index of (0,0). For example, the element in the 0th row and 1st column of the element value array has an original index of (0,2) in the original matrix. Another example is the element in the 0th row and 2nd column of the element value array, which has an original index of (0,6) in the original matrix.

[0123] The subscript data of submatrix 1 includes the displacement pairs of submatrix 1, the index array (or index matrix), and the index vector.

[0124] 1) First, let's introduce the displacement value pairs:

[0125] The subscript data of submatrix 1 includes the displacement pairs (such as block offset) of the submatrix. The displacement pairs include row offset and column offset. The row offset refers to the offset between the starting row of the submatrix and the starting row of the original matrix. The column offset refers to the offset between the starting column of the submatrix and the starting column of the original matrix.

[0126] Combination Figure 11 Understand, assume the size of the sub-block is M1×N1=16×16. The starting row number and starting column number of the original matrix are 0. The (original row number of the starting row, original column number of the starting column) of sub-matrix 1 is (0, 0); the (original row number of the starting row, original column number of the starting column) of sub-matrix 2 is (0, 16); the (original row number of the starting row, original column number of the starting column) of sub-matrix 3 is (16, 0); and the (original row number of the starting row, original column number of the starting column) of sub-matrix 4 is (16, 16).

[0127] Based on this, the row offset of submatrix 1 = the original row number of the starting row of submatrix 1 - the row number of the starting row of the original matrix = 0 - 0 = 0, and the column offset of submatrix 1 = the original column number of the starting column of submatrix 1 - the column number of the starting column of the original matrix = 0. That is, the displacement value pair of submatrix 1 is (0,0).

[0128] The row offset of submatrix 2 = the original row number of the starting row of submatrix 2 - the row number of the starting row of the original matrix = 0 - 0 = 0. The column offset of submatrix 2 = the original column number of the starting column of submatrix 2 - the column number of the starting column of the original matrix = 16 - 0 = 16. That is, the displacement value pair of submatrix 2 is (0, 16).

[0129] The row offset of submatrix 3 = the original row number of the starting row of submatrix 3 - the row number of the starting row of the original matrix = 16 - 0 = 16, and the column offset of submatrix 3 = the original column number of the starting column of submatrix 3 - the column number of the starting column of the original matrix = 0 - 0 = 0. That is, the displacement value pair of submatrix 3 is (16, 0).

[0130] The row offset of submatrix 4 = the original row number of the starting row of submatrix 4 - the row number of the starting row of the original matrix = 16 - 0 = 16, and the column offset of submatrix 4 = the original column number of the starting column of submatrix 4 - the column number of the starting column of the original matrix = 16 - 0 = 16. That is, the displacement value pair of submatrix 4 is (16, 16).

[0131] 2) The following describes indexed arrays and indexed vectors:

[0132] When the specified direction is different, the elements in the index array and index vector have different meanings. As follows, the direction is specified as row direction, and the index data and index vector of submatrix 1 are introduced.

[0133] The values ​​of elements in the index array of submatrix 1 and the column offset of submatrix 1 are used to indicate the original column number of the corresponding element in the element value array of submatrix 1. Specifically, as shown in Formula 1: the original column number of any element (denoted as the first element) in the element value array of submatrix 1 = the column offset of submatrix 1 + the value of the element corresponding to the first element in the index array of submatrix 1 (denoted as the second element). In simpler terms, the original column number of a non-zero element = row offset + the value of the corresponding element in the index array.

[0134] The elements in the index array of submatrix 1 correspond one-to-one with the elements in the value array of submatrix 1. One-to-one correspondence means that two elements at the same position in the index array and the value array correspond exactly to each other. In other words, the element at position (i,j) in the index array (e.g., the first element) corresponds to the element at position (i,j) in the value array (e.g., the second element). For example, the element at position (0,0) in the index array corresponds to the element at position (0,0) in the value array, the element at position (0,1) in the index array corresponds to the element at position (0,1) in the value array, the element at position (16,4) in the index array corresponds to the element at position (16,4) in the value array, and so on.

[0135] Based on Formula 1, the value of any element in the index array of submatrix 1 equals the original column number of the corresponding element in the element value array of submatrix 1 minus the column offset of submatrix 1. For example, see below. Figure 11 For example, the element at position (0,1) in the element value array of submatrix 1 (such as...) Figure 11 The original column number of the element identified by "a" in the matrix is ​​2. Since the column offset of submatrix 1 is 0, the value of the element at position (0,1) in the index array of submatrix 1 is 2 - 0 = 2. For example, the element at position (0,2) in the element value array of submatrix 1 (such as...) Figure 11 The original column number of the element identified by "b" in the matrix is ​​6. Since the column offset of submatrix 1 is 0, the value of the element at position (0,2) in the index array of submatrix 1 is 6 - 0 = 6. For example, the element at position (1,0) in the element value array of submatrix 1 (such as...) Figure 11 The original column number of the element identified by "c" is 3. Since the column offset of submatrix 1 is 0, the value of the element at position (1,0) in the index array of submatrix 1 is 3 - 0 = 3.

[0136] The values ​​of the elements in the index vector of submatrix 1 and the row offset of submatrix 1 are used to indicate the original row number of the corresponding element in the element value array of submatrix 1. Specifically, as shown in Formula 2: the original row number of any element (denoted as the first element) in the element value array of submatrix 1 = the row offset of submatrix 1 + the value of the element in the index vector of submatrix 1 corresponding to the first element (such as the second element). Simply put, the original row number of a non-zero element = row offset + the value of the corresponding element in the index vector.

[0137] The elements of the index vector correspond one-to-one with the rows of the element value array. For example, the 0th element of the index vector corresponds to the 0th row of the element value array, the 1st element of the index vector corresponds to the 1st row of the element value array, the ith element of the index vector corresponds to the ith row of the element value array, and so on. Alternatively, it can be said that the element in the ith row of the element value array corresponds to the ith element of the index vector.

[0138] Based on Formula 2, the value of any element in the index vector of submatrix 1 is equal to the original row number of the corresponding row element in the element value array of submatrix 1 minus the row offset of submatrix 1. Here, the index vector can be a 1×n matrix, or an n×1 matrix. Assume the index vector of submatrix 1 is x = [x0 x1…x…]. n-1 See also: Figure 11 For example, if the original row number of the elements in the 0th row of the element value array of submatrix 1 is 0, and since the row offset of submatrix 1 is 0, then the value of the 0th element in the index vector of submatrix 1 (e.g., x0) = 0 - 0 = 0. As another example, if the original row number of the elements in the 1st row of the element value array of submatrix 1 is 1, and since the row offset of submatrix 1 is 0, then the value of the 1st element in the index vector of submatrix 1 (e.g., x1) = 1 - 0 = 1. And as yet another example, if the original row number of the elements in the 15th row of the element value array of submatrix 1 is 15, and since the row offset of submatrix 1 is 0, then the value of the 15th element in the index vector of submatrix 1 (e.g., x1) = 1 - 0 = 1. 15 The value of ) = 15 - 0 = 15. That is, the index vector of submatrix 1 is [0 1 2 3…14 15]. It can be understood that when submatrix 1 does not include rows with all zero elements, the value of the element in the index vector of submatrix 1 is the original row number of the corresponding row element in the element value array.

[0139] The above describes the process of determining the compressed data of submatrix 1. The following is a brief example of determining the compressed data of other submatrixes.

[0140] As mentioned earlier, the displacement pairs of submatrix 2 are (0, 16), combined with Figure 11 and Figure 12For example, the element at position (0,0) in the element value array of submatrix 2 (such as...) Figure 11 The original index of the element marked with "e" in the matrix is ​​(3,19), and the value of the element at position (0,0) in the index array of submatrix 2 is 19-16=3.

[0141] For example, the element at position (0,1) in the array of values ​​of submatrix 2 (such as...) Figure 12 The original index of the element identified by "f" in submatrix 2 is (3, 20). The value of the element at position (0, 1) in the index array of submatrix 2 is 20 - 16 = 4. The value of the 0th element in the index vector of submatrix 2 (corresponding to the element in the 0th row of the element value array, such as e, f) is 3 - 0 = 3.

[0142] For example, the element at position (1,0) in the element value array of submatrix 2 (such as...) Figure 12 The original index of the element identified by "g" in submatrix 2 is (7,17). The value of the element at position (1,0) in the index array of submatrix 2 is 17-16=1. The value of the first element in the index vector of submatrix 2 (corresponding to the element in the first row of the element value array, such as g) is 7-0=7.

[0143] Similarly, determine the index array and index vector of submatrix 2.

[0144] As mentioned earlier, the displacement pair of submatrix 3 is (16,0), combined with Figure 11 and Figure 12 For example, the element at position (0,0) in the element value array of submatrix 3 (such as...) Figure 12 The original index of the element identified by "h" in submatrix 3 is (16,6). The value of the element at position (0,0) in the index array of submatrix 3 is 6 - 0 = 6. The value of the 0th element in the index vector of submatrix 3 (corresponding to the element in the 0th row of the element value array, such as h) is 16 - 16 = 0.

[0145] For example, the element at position (2,0) in the element value array of submatrix 3 (such as...) Figure 12 The original index of the element identified by "k" in submatrix 3 is (18, 3). The value of the element at position (2, 0) in the index array of submatrix 3 is 3 - 0 = 3. The value of the second element in the index vector of submatrix 3 (corresponding to the element in the second row of the element value array, such as k) is 18 - 16 = 2.

[0146] For example, the element at position (3,1) in the element value array of matrix 3 (such as...) Figure 12The original index of the element marked "o" in submatrix 3 is (19, 6). The value of the element at position (3, 1) in the index array of submatrix 3 is 6 - 0 = 6. The value of the third element in the index vector of submatrix 3 (corresponding to the element in the second row of the element value array, such as "o") is 19 - 16 = 3.

[0147] Similarly, determine the index array and index vector of submatrix 3.

[0148] As mentioned earlier, the displacement pair of submatrix 4 is (16, 16), combined with Figure 11 and Figure 12 For example, the element at position (0,1) in the element value array of submatrix 4 (e.g.) Figure 12 The original index of the element identified by "y" in submatrix 3 is (17, 18). The value of the element at position (0, 1) in the index array of submatrix 3 is 18 - 16 = 2. The value of the 0th element in the index vector of submatrix 4 (corresponding to the element in the 0th row of the element value array, such as y) is 17 - 16 = 1.

[0149] For example, the element at position (1,1) in the element value array of submatrix 4 (such as...) Figure 12 The original index of the element identified by "w" in submatrix 4 is (20, 19). The value of the element at position (1, 1) in the index array of submatrix 4 is 19 - 16 = 3. The value of the first element in the index vector of submatrix 4 (corresponding to the element in the first row of the element value array, such as w) is 20 - 16 = 4.

[0150] Similarly, determine the index array and index vector of submatrix 4.

[0151] As can be seen from the above design, dividing the original matrix into blocks can mainly optimize the subscript data of the elements. The global subscript data of the original matrix is ​​split into shift value pairs, index arrays, and index vectors of the submatrixes. Those skilled in the art know that when the size of the original matrix is ​​large, the original global subscript data range is usually high precision, such as INT64 or INT32, and the data volume is also relatively large. After being divided into blocks by the method of this application embodiment, the subscript data range of each submatrix will be smaller, and only lower subscript precision is needed, such as using INT16 or INT8 to completely include the subscript range. Each submatrix only needs to store one shift value pair, and the amount of subscript data that the entire submatrix needs to store can be greatly reduced.

[0152] The previous section introduced the process of compressing data in the row direction to obtain compressed data for each submatrix. The following section introduces the process of compressing data in the column direction to obtain compressed data for each submatrix.

[0153] 2. Specify the direction as column direction.

[0154] Please note that regardless of whether the compression direction is row-wise or column-wise, it does not affect the displacement pairs of the submatrix; that is, the determined displacement pairs of the submatrix are the same. See the section above on how to determine the displacement pairs of the submatrix, which will not be repeated here. The following only explains the differences.

[0155] Figure 13 This is a schematic diagram illustrating the compression of a submatrix along the column direction, as provided in this embodiment. Figure 13 Taking submatrix 1 as an example, submatrix 1 is compressed along the column direction to obtain compressed data of submatrix 1. The compressed data of submatrix 1 includes the element value array and index data of submatrix 1.

[0156] The element value array of submatrix 1 consists of the non-zero elements arranged column-wise in submatrix 1. Non-zero elements in the same column of the original matrix remain in the same column in the element value array, and there are no gaps between non-zero elements. The compression process to obtain this element value array can include: compressing the non-zero elements in submatrix 1 along the column direction (if the submatrix contains a column of all elements, the entire column of all zero elements can be compressed), then zero-filling according to the maximum column length after compression, thus obtaining the element value array corresponding to this submatrix. The compression process for the element value arrays of the other submatrixes is the same and will not be described further here.

[0157] The subscript data of submatrix 1 includes the displacement pairs, index array, and index vector of submatrix 1.

[0158] In this formula, the values ​​of the elements in the index array of submatrix 1 and the row offset of submatrix 1 are used to indicate the original row number of the corresponding element in the element value array of submatrix 1. Specifically, as shown in Formula 3: the original row number of any element (denoted as the first element) in the element value array of submatrix 1 = the column offset of submatrix 1 + the value of the element (denoted as the second element) in the index array of submatrix 1 corresponding to the first element. Simply put, the original row number of a non-zero element = row offset + the value of the corresponding element in the index array.

[0159] Based on Formula 3, the value of any element in the index array of submatrix 1 equals the original row number of the corresponding element in the element value array of submatrix 1 minus the row offset of submatrix 1. For example, see... Figure 13For example, if the original row number of the element at position (0,1) in the element value array of submatrix 1 is 4, and the row offset of submatrix 1 is 0, then the value of the element at position (0,1) in the index array of submatrix 1 is 4 - 0 = 4. As another example, if the original row number of the element at position (3,2) in the element value array of submatrix 1 is 7, and the row offset of submatrix 1 is 0, then the value of the element at position (3,2) in the index array of submatrix 1 is 7 - 0 = 7. As yet another example, if the original row number of the element at position (5,5) in the element value array of submatrix 1 is 12, and the row offset of submatrix 1 is 0, then the value of the element at position (5.5) in the index array of submatrix 1 is 12 - 0 = 12. And so on.

[0160] The values ​​of the elements in the index vector of submatrix 1 and the column offset of submatrix 1 are used to indicate the original column number of the corresponding element in the element value array of submatrix 1. Specifically, as shown in Formula 4: the original column number of any element (denoted as the first element) in the element value array of submatrix 1 = the row offset of submatrix 1 + the value of the element corresponding to the first element in the index vector of submatrix 1 (such as the second element). Simply put, the original column number of a non-zero element = column offset + the value of the corresponding element in the index vector.

[0161] Based on Formula 4, the value of any element in the index vector of submatrix 1 is equal to the original column number of the corresponding row element in the element value array of submatrix 1 minus the column offset of submatrix 1. Here, the index vector can be a 1×m matrix, or an m×1 matrix. For example, see... Figure 13 Suppose that the index vector of submatrix 1 is a 1×m matrix, for example: y = [y0 y1…y m-1 In the submatrix index vector, m = the number of columns in the element value array. For example, if the original column number of the element in column 0 of submatrix 1 is 0, and the column offset of submatrix 1 is 0, then the value of the element in column 0 (e.g., y0) in the index vector of submatrix 1 is 0 - 0 = 0. Similarly, if the original column number of the element in column 1 of submatrix 1 is 1, then the value of the element in column 1 (e.g., y1) in the index vector of submatrix 1 is 1 - 0 = 1. And so on. When submatrix 1 does not contain a column of all zero elements, the value of the element in the index vector of submatrix 1 is the original column number of the corresponding row element in the element value array.

[0162] The above section introduced two compression methods with different compression directions. This application does not limit each matrix to using row compression or column compression. In practical applications, the choice between row compression and column compression can be determined based on the needs of matrix multiplication. For example, in sparse matrix multiplication (SpGEMM), the left matrix (one of the two matrices to be multiplied in SpGEMM) can be stored using row compression, while the right matrix (the other of the two matrices to be multiplied in SpGEMM) can be stored using column compression. This achieves better locality and is also suitable for use with GPU and vector processor architectures.

[0163] It should be noted that this application can also compress different submatrices of an original matrix in different directions. However, to improve processing efficiency, in step 903, the compression method of each submatrix can be the same. For example, if compressed in the row direction, each submatrix of an original matrix is ​​compressed in the row direction. If compressed in the column direction, each submatrix of an original matrix is ​​compressed in the column direction.

[0164] It should also be noted that steps 901-903 are optional and not mandatory. For example, computing device 800 can also obtain compressed data corresponding to each submatrix from other devices.

[0165] Step 904: For each submatrix, the arrays (such as the element value array and the index array) in the compressed data are tiled into smaller blocks of size M2×N2 to obtain multiple smaller blocks corresponding to each submatrix.

[0166] Taking a submatrix as an example, the process of dividing the compressed data of the submatrix into smaller blocks can include: dividing the element value array of the submatrix into smaller blocks of size M2×N2, resulting in multiple smaller blocks (denoted as the second sub-block). Dividing the index array of the submatrix into smaller blocks of size M2×N2, resulting in multiple smaller blocks (denoted as the third sub-block). Here, M2 is a positive integer not greater than M1, N2 is a positive integer not greater than N1, and M2×N2 is less than M1×N1. In one case, M2 is a positive integer less than M1 and N2 is a positive integer not greater than N1; or, M2 is a positive integer not greater than M1 and N2 is a positive integer less than N1. That is, the size of the sub-block is usually smaller than the size of the element value array or the index array.

[0167] by Figure 12 Taking the array of element values ​​shown as an example, Figure 14 This is a schematic diagram illustrating how to divide the element value array of each submatrix into smaller blocks, as provided in an embodiment of this application. Figure 14 In this context, the size of the sub-block is M2×N2=2×2, such as... Figure 14As shown, the processor 801 can divide each element value array into smaller blocks of size 2×2 along the row direction, so that each element value array is divided into multiple smaller blocks, each of the same size (e.g., ...). Figure 14 All elements are 2×2 in size and do not overlap. Optionally, if the last element in either the row or column direction of the element value array is less than 2×2, zero-padding is performed to make it 2×2. For example, see... Figure 14 At the bottom of the element value array of block2, tile22 is a small block filled with zeros, where the zero-filled elements within the small block are indicated by dashed boxes.

[0168] Similarly, processor 801 divides the index array of the submatrix into smaller blocks of M²×N², resulting in multiple smaller blocks of the index array, each of the same size and non-overlapping. The effect of dividing the index array into smaller blocks can be seen in [reference needed]. Figure 14 The effect of cutting the array of element values ​​of a submatrix into smaller pieces, as shown, will not be elaborated here.

[0169] Please understand. Figure 14 The 2×2 sub-block size shown is merely an example. This embodiment does not limit the size of the sub-blocks used for cutting smaller blocks. This embodiment also provides a method for determining the sub-block size, such as determining it based on the data bit width of a matrix operator such as a vector processor or matrix accelerator. For example, if the length of the vector processor is 2, then it can be cut into smaller blocks based on 2×2 sub-blocks. Or, if the length of the vector processor is 4, then it can be cut into smaller blocks based on 4*4 sub-blocks to adapt to the data bit width of the matrix operator. This is just one example of determining the sub-block size. This embodiment can also apply other methods to determine the sub-block size in this step, and there is no specific limitation.

[0170] It should be noted that the above Figures 11-14 The element value arrays and index arrays shown are illustrated with zero-padding as an example of compression processing. The compression processing in this embodiment may also exclude zero-padding, such as the element value arrays and index arrays not including zero elements, for example, removing zero elements. Figures 11-15 The zero elements in the value array and index array are then filled with zeros when the value array and index array with zero elements removed are cut into smaller blocks.

[0171] Step 905: Using M2×N2 sub-blocks as storage units, store the data of the small blocks corresponding to each sub-matrix in a specified order.

[0172] Specifically, step 905 includes storing the element value array and index data of each submatrix. When storing the element value array and index array, the data of each small block corresponding to the stored element value array and index array is stored in a specified order using M2×N2 sub-blocks as storage units.

[0173] This embodiment provides multiple methods for storing small blocks:

[0174] Storage method 1:

[0175] by Figure 14 Taking the array of element values ​​shown as an example, this embodiment can select small blocks according to row order. For example, in one implementation, for each small block included in multiple arrays of element values ​​belonging to the same sparse matrix, the sub-blocks are selected sequentially according to the row order between the small blocks. Optionally, small blocks with all zero elements can be removed, that is, small blocks with all zero elements are not stored. This will not be repeated below. Figure 15 As shown, the selection order of the small blocks can be: tile00, tile01, tile02, tile10, tile11, tile12, tile13, tile20, tile21, tile22, tile30, tile31, tile40, ..., tile70, tile80, tile81, tile82, tile90, tile91, ..., tile121.

[0176] For each selected block, the data of each block is stored sequentially. For example, following the selection order of the blocks mentioned above, for tile00, the elements (0,0), (0,1), (1,0), and (1,1) of tile00 are stored sequentially. Then, the elements (0,0), (0,1), (1,0), and (1,1) of tile01 are stored sequentially. After that, the elements (0,0), (0,1), (1,0), and (1,1) of tile02 are stored sequentially. After that, the elements (0,0), (0,1), (1,0), and (1,1) of tile10 are stored sequentially, and so on.

[0177] In another implementation, a submatrix is ​​used as the object, and the small blocks corresponding to each submatrix are stored sequentially in row order. For example, combining... Figure 15 First, store the blocks corresponding to submatrix 1, then the blocks corresponding to submatrix 2, then the blocks corresponding to submatrix 3, and finally the blocks corresponding to submatrix 4. The blocks within each submatrix can be stored sequentially or in parallel; in short, the blocks within each submatrix are stored contiguously. For multiple blocks corresponding to a single submatrix, they can be selected in row-order. (See details in the following section.) Figure 15The selection order of the small blocks can be: tile00, tile01, tile10, tile11, ..., tile70, tile02, tile12, tile13, tile22, tile80, tile81, tile90, ..., tile120, tile121, tile82, ..., tile91. Similarly, for each selected small block, the values ​​of the elements of each small block are stored sequentially, as described in the previous introduction, which will not be repeated here.

[0178] Store the sub-blocks corresponding to the index array in the manner described above. For ease of explanation, the sub-blocks corresponding to the element value data are denoted as the second sub-blocks, and the sub-blocks corresponding to the index arrays are denoted as the third sub-blocks.

[0179] In this application, a submatrix corresponds to multiple second sub-blocks and multiple third sub-blocks with a mapping relationship. This mapping relationship ensures a one-to-one correspondence between the multiple second sub-blocks and multiple third sub-blocks corresponding to the submatrix. One-to-one correspondence means that two sub-blocks at the same position correspond to each other. For example, dividing the submatrix into sub-blocks, the second sub-block in the 0th row and 0th column of the element value array of submatrix 1 (e.g., ...) Figure 14 tile00 in the matrix and the third sub-block in the 0th row and 0th column of the index array of submatrix 1 ( Figure 14 As shown in the diagram, the second sub-block (e.g., tile01) in the 0th row and 1st column of the element value array in submatrix 1 corresponds to the third sub-block (e.g., tile01) in the 0th row and 1st column of the block array in submatrix 1. Similarly, the second sub-block (e.g., tile10) in the 1st row and 0th column of the element value array corresponds to the third sub-block (e.g., tile10) in the 1st row and 0th column of the block array in submatrix 1, and so on.

[0180] Furthermore, this application provides two methods in its embodiments. Method 1: The second and third sub-blocks are stored independently. For example, multiple second sub-blocks are stored in a storage space A, and multiple third sub-blocks are stored in a storage space B. Based on the order of the second sub-blocks selected above, the arrangement order of multiple second sub-blocks in storage space A can be: tile00, tile01, tile02, tile10, tile11, tile12, tile13, tile20, tile21, tile22, tile30, tile31, tile40, ..., tile70, tile80, tile81, tile82, tile90, tile91, ..., tile121. The selection order of the third sub-block can be the same as that of the second sub-block. For example, in storage space B, the arrangement order of multiple third sub-blocks can be: tile00', tile01', tile02', tile10', tile11', tile12', tile13', tile20', tile21', tile22', tile30', tile31', tile40', ..., tile70', tile80', tile81', tile82', tile90', tile91', ..., tile121'.

[0181] Method 2: Store the second and third sub-blocks alternately. For example, consider a second sub-block and its corresponding third sub-block as a storage object. Refer to the order in which the second sub-blocks are selected above, and store the selected second sub-block and its corresponding third sub-block in sequence. For example, one storage order could be: tile00, tile00', tile01, tile01', tile02, tile02', tile10, tile10', tile11, tile11', tile12, tile12', and so on.

[0182] Specifically, taking computing device 800 as an example, the storage location of the above data can be memory 802, or it can be a storage device outside computing device 800. Alternatively, some data can be stored in memory 802 and the rest in a storage device outside computing device 800. There are no specific limitations.

[0183] In this embodiment of the application, based on the second sub-block and the third sub-block corresponding to the second sub-block, the displacement value pairs of the sub-matrix and the index vector of the sub-matrix, the values ​​of the corresponding elements and the original subscripts of the elements in the original matrix can be recovered.

[0184] Storage Method Two:

[0185] Still with Figure 14Taking the array of element values ​​shown as an example, this embodiment can select the second sub-block according to the column order. For example, in one implementation, for each small block included in multiple arrays of element values ​​belonging to the same sparse matrix, the sub-blocks are selected sequentially according to the column order between the small blocks. Optionally, small blocks with all zero elements can be removed, that is, small blocks with all zero elements are not stored. This will not be repeated below. Figure 16 As shown, the selection order of the small blocks can be: tile00, tile10, tile20, tile30, tile40, tile50, tile60, tile70, tile80, tile90, tile100, tile110, tile120, tile01, tile11, tile21, tile31, ..., tile81, tile91, tile101, ..., tile121, tile02, tile12, tile22, tile82, tile91, tile13, tile83, tile84.

[0186] Similarly, in another implementation, a submatrix is ​​used as the object, and the corresponding blocks of each submatrix are stored sequentially according to column order, as described above, and will not be repeated here. Regardless of the selection method, for each selected block, the data of each block is stored sequentially, as described above, and will not be repeated here.

[0187] Store the blocks corresponding to the index array sequentially as described above. The blocks corresponding to the element value array and the blocks corresponding to the index array can be stored serially or in parallel.

[0188] The above design involves dividing the original matrix into blocks, then compressing each resulting submatrix to obtain compressed data for each submatrix. The element value arrays and index data within the compressed data are further divided into smaller blocks, resulting in multiple second sub-blocks. These second sub-blocks are then stored as storage units. This application divides the first sub-block into multiple second sub-blocks, allowing for the complete deletion of all-zero second sub-blocks. This approach adapts to arbitrarily distributed sparse matrices and maintains a high compression ratio even under arbitrary sparse matrix conditions.

[0189] Furthermore, this application can be used with dedicated hardware accelerators (such as vector processors or matrix processors) to divide the data into smaller blocks based on the data bit width. For example, if the data bit width of the hardware accelerator is n, the first sub-block can be divided into smaller blocks of size n×n. The smaller blocks (i.e., the second sub-blocks) are used as storage units, and then stored in the row or column direction of the smaller blocks, which facilitates memory access. At least one complete second sub-block can be read out in one data access, reducing the number of memory accesses during sparse matrix calculation. Since all rows and columns of the second sub-block have the same length, it provides a more user-friendly data access method for vector processors or matrix processors. It can achieve good locality for row-order or column-order access, and can be adapted to dedicated hardware accelerators with high efficiency, which is beneficial to improving the parallelism of sparse matrix calculation. On the one hand, multiple complete second sub-blocks can be read in one memory access, and these multiple second sub-blocks can be calculated in parallel by multiple dedicated hardware accelerators, which can improve multi-core parallelism. On the other hand, since a second sub-block can provide a sufficient amount of data to a dedicated hardware accelerator, it is more suitable for the dedicated hardware accelerator to accelerate the calculation, which is conducive to improving the internal parallelism of a single dedicated accelerator. For example, taking an nxn block as a unit, such as n=16, that is, the block size is 16x16, for a sparse matrix multiplication operation, assuming it is a 16x16 second sub-block A×16x16 second sub-block B, this application can realize the reading of 16 sets of vectors of the second sub-block A and the second sub-block B through a vector instruction, and the vectors are aligned after being read. The dedicated hardware accelerator can complete 256 16×1 vector inner product calculations in one cycle. In this way, the dedicated hardware accelerator can achieve a parallelism of 256, and the performance can be greatly improved.

[0190] In summary, the storage method provided in this application can improve data locality, increase data compression rate, and enhance the parallelism of matrix calculation.

[0191] It is worth noting that the above description uses a sparse matrix as an example. The original matrix in this application embodiment can also be a dense matrix. That is, dense matrices are also applicable to the data format and storage method provided in this embodiment. This can unify the format and accelerate the calculation between sparse and dense matrices, such as the multiplication of sparse matrices with dense vectors, sparse matrices with sparse vectors, sparse matrices with dense matrices, and sparse matrices with sparse matrices. This can greatly improve the matrix compression rate, matrix operation parallelism, and data locality in various scenarios.

[0192] Based on the same inventive concept as the method embodiments, this application also provides a matrix storage device for performing the above-described... Figure 9 The method of the method embodiment. For example... Figure 17As shown, the device 1700 includes an acquisition module 1701, a processing module 1702, and a storage module 1703. Specifically, in this device 1700, the modules are connected through a communication path. In one application scenario, the memory 802 stores executable program code, and the processor 801 executes the executable program code to implement the functions of the aforementioned acquisition module 1701, processing module 1702, and storage module 1703, thereby realizing the matrix storage method provided in this embodiment.

[0193] The acquisition module 1701 is used to acquire multiple first sub-blocks corresponding to the original matrix. These multiple first sub-blocks are obtained by dividing the original matrix into sub-blocks of size M1×N1, and compressing the non-zero elements in each sub-matrix obtained after division in a specified direction, where M1 and N1 are positive integers; see details in [link to documentation]. Figure 9 The descriptions of steps 901 to 903 in the method embodiments will not be repeated here.

[0194] Processing module 1702 is used to divide each first sub-block into sub-blocks of size M2×N2 to obtain multiple second sub-blocks, where M2 is a positive integer not greater than M1 and N2 is a positive integer not greater than N1; see details below. Figure 9 The description of step 904 in the method embodiment will not be repeated here.

[0195] Storage module 1703 is used to sequentially store the values ​​of elements within each second sub-block. See details... Figure 9 The description of step 905 in the method embodiment will not be repeated here.

[0196] In one possible implementation, the specified direction is the row direction;

[0197] The acquisition module 1701 is further configured to acquire the index data of each first sub-block, wherein the index data is used to indicate the position of each element within the first sub-block in the original matrix; wherein the index data of each first sub-block includes a displacement value pair, an index matrix, and an index vector corresponding to the first sub-block; wherein the displacement value pair includes a first displacement value and a second displacement value, the first displacement value is used to indicate a first offset of the first row of the first sub-block relative to the starting row of the original matrix, and the second displacement value is used to indicate a second offset of the first column of the first sub-block relative to the starting column of the original matrix; the value of any element in the index matrix is ​​equal to the difference between the column number of the corresponding element in the original matrix corresponding to the first sub-block and the second offset; the value of any element in the index vector is used to indicate the difference between the row number of the corresponding element in the original matrix corresponding to the first sub-block and the first offset.

[0198] In one possible implementation, the specified direction is the column direction;

[0199] The acquisition module 1701 is further configured to generate subscript data for each first sub-block, wherein the subscript data indicates the position of each element within the first sub-block in the original matrix; wherein the subscript data for each first sub-block includes a displacement value pair, an index matrix, and an index vector corresponding to the first sub-block. The displacement value pair includes a first displacement value and a second displacement value, wherein the first displacement value indicates a first offset of the first row of the first sub-block relative to the starting row of the original matrix, and the second displacement value indicates a second offset of the first column of the first sub-block relative to the starting column of the original matrix; the value of any element in the index matrix is ​​equal to the difference between the row number of the corresponding element in the original matrix corresponding to the first sub-block and the first offset; the value of any element in the index vector indicates the difference between the column number of the corresponding element in the original matrix corresponding to the first sub-block and the second offset.

[0200] In one possible implementation, the processing module 1702 is further configured to: divide the index matrix corresponding to each first sub-block into sub-blocks of size M2×N2 to obtain multiple third sub-blocks; the storage module 1703 is further configured to: sequentially store the values ​​of the elements in each third sub-block.

[0201] In one possible implementation, for each first sub-block, a plurality of second sub-blocks obtained based on the first sub-block correspond one-to-one with a plurality of third sub-blocks obtained based on the index matrix corresponding to the first sub-block; the order in which the third sub-blocks are stored is the same as the order in which the second sub-blocks are stored.

[0202] In one possible implementation, when storing the values ​​of elements within each second sub-block sequentially, the storage module 1703 is specifically configured to: select each second sub-block by row or by column, and store the values ​​of elements within each selected second sub-block by row, or store the values ​​of elements within each selected second sub-block by column.

[0203] In one possible implementation, each stored second sub-block includes at least one non-zero element; before storing the values ​​of the elements within each second sub-block sequentially, the storage module 1703 is also used to: remove second sub-blocks that include all-zero elements.

[0204] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions, capable of running on a computing device or stored on any usable medium. When the computer program product is run on at least one computer device, it causes the at least one computer device to perform the above-described... Figure 9The method of the embodiment is described in the preceding text and will not be repeated here.

[0205] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium capable of being stored by a computing device or a data storage device containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct a computing device to perform the above-described... Figure 9 The methods performed in the embodiments are described in the preceding text and will not be repeated here.

[0206] Optionally, the computer execution instructions in the embodiments of this application may also be referred to as application code, and the embodiments of this application do not specifically limit this.

[0207] Those skilled in the art will understand that the various numerical designations, such as "first," "second," etc., used in this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, nor do they indicate a sequential order. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one" refers to one or more. "At least two" refers to two or more. "At least one," "any one," or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. "Multiple" refers to two or more, and other quantifiers are similar. Furthermore, for elements appearing in the singular forms "a," "an," and "the," unless the context explicitly specifies otherwise, they do not imply "one or only one," but rather "one or more." For example, "a device" implies one or more such devices.

[0208] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0209] The various illustrative logic units and circuits described in the embodiments of this application can be implemented or operate the described functions using a general-purpose processor, digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor; alternatively, it can also be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented using a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0210] The steps of the methods or algorithms described in the embodiments of this application can be directly embedded in hardware, software units executed by a processor, or a combination of both. The software units can be stored in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and storage medium can be housed in an ASIC.

[0211] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0212] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely illustrative descriptions of the application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Thus, if such modifications and modifications fall within the scope of the claims and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A matrix storage method, characterized in that, include: Obtain multiple first sub-blocks, which are obtained by dividing the original matrix into sub-blocks of size M1×N1, and compressing the non-zero elements in each sub-block in a specified direction, where M1 and N1 are positive integers. Each first sub-block is divided into sub-blocks of size M2×N2 to obtain multiple second sub-blocks, where M2 is a positive integer not greater than M1 and N2 is a positive integer not greater than N1. The value of each element in the second sub-block is stored using the second sub-block as the storage unit.

2. The method as described in claim 1, characterized in that, The specified direction is the row direction; The method further includes: Obtain the index data of each first sub-block, the index data being used to indicate the position of each element within the first sub-block in the original matrix; The subscript data for each first sub-block includes a displacement value pair, an index matrix, and an index vector corresponding to the first sub-block. The displacement value pair includes a first displacement value and a second displacement value. The first displacement value indicates a first offset of the first row of the first sub-block relative to the starting row of the original matrix, and the second displacement value indicates a second offset of the first column of the first sub-block relative to the starting column of the original matrix. The value of any element in the index matrix is ​​equal to the difference between the column number of the corresponding element in the original matrix corresponding to the first sub-block and the second offset. The value of any element in the index vector indicates the difference between the row number of the corresponding element in the original matrix corresponding to the first sub-block and the first offset.

3. The method as described in claim 1, characterized in that, The specified direction is the column direction; The method further includes: Obtain the index data of each first sub-block, the index data being used to indicate the position of each element within the first sub-block in the original matrix; The subscript data for each first sub-block includes a displacement value pair, an index matrix, and an index vector corresponding to the first sub-block. The displacement value pair includes a first displacement value and a second displacement value. The first displacement value indicates a first offset of the first row of the first sub-block relative to the starting row of the original matrix, and the second displacement value indicates a second offset of the first column of the first sub-block relative to the starting column of the original matrix. The value of any element in the index matrix is ​​equal to the difference between the row number of the corresponding element in the original matrix corresponding to the first sub-block and the first offset. The value of any element in the index vector indicates the difference between the column number of the corresponding element in the original matrix corresponding to the first sub-block and the second offset.

4. The method as described in claim 2 or 3, characterized in that, The method further includes: The index matrix corresponding to each first sub-block is divided into sub-blocks of size M2×N2 to obtain multiple third sub-blocks; Store the values ​​of the elements within each third sub-block sequentially.

5. The method as described in claim 4, characterized in that, For each first sub-block, there is a one-to-one correspondence between multiple second sub-blocks obtained based on the first sub-block and multiple third sub-blocks obtained based on the index matrix corresponding to the first sub-block; The storage order of the third sub-block is the same as that of the second sub-block.

6. The method according to any one of claims 1-5, characterized in that, Store the values ​​of the elements within each second sub-block, including: Select each second sub-block by row or column and store the values ​​of the elements within each selected second sub-block by row, or store the values ​​of the elements within each selected second sub-block by column.

7. The method according to any one of claims 1-6, characterized in that, Each second sub-block of storage includes at least one non-zero element.

8. A matrix storage device, characterized in that, The matrix storage device includes an acquisition module, a processing module, and a storage module: The acquisition module is used to acquire multiple first word blocks, which are obtained by dividing the original matrix into sub-blocks of size M1×N1, and compressing the non-zero elements in each sub-block in a specified direction, where M1 and N1 are positive integers. The processing module is used to cut each first sub-block into sub-blocks of size M2×N2 to obtain multiple second sub-blocks, where M2 is a positive integer not greater than M1 and N2 is a positive integer not greater than N1. The storage module is used to sequentially store the values ​​of elements within each second sub-block.

9. The apparatus as claimed in claim 8, characterized in that, The specified direction is the row direction; The acquisition module is further configured to acquire the index data of each first sub-block, the index data being used to indicate the position of each element within the first sub-block in the original matrix; The subscript data for each first sub-block includes a displacement value pair, an index matrix, and an index vector corresponding to the first sub-block. The displacement value pair includes a first displacement value and a second displacement value. The first displacement value indicates a first offset of the first row of the first sub-block relative to the starting row of the original matrix, and the second displacement value indicates a second offset of the first column of the first sub-block relative to the starting column of the original matrix. The value of any element in the index matrix is ​​equal to the difference between the column number of the corresponding element in the original matrix corresponding to the first sub-block and the second offset. The value of any element in the index vector indicates the difference between the row number of the corresponding element in the original matrix corresponding to the first sub-block and the first offset.

10. The apparatus as claimed in claim 8, characterized in that, The specified direction is the column direction; The acquisition module is further configured to generate index data for each first sub-block, the index data being used to indicate the position of each element within the first sub-block in the original matrix; The subscript data for each first sub-block includes a displacement value pair, an index matrix, and an index vector corresponding to the first sub-block. The displacement value pair includes a first displacement value and a second displacement value. The first displacement value indicates a first offset of the first row of the first sub-block relative to the starting row of the original matrix, and the second displacement value indicates a second offset of the first column of the first sub-block relative to the starting column of the original matrix. The value of any element in the index matrix is ​​equal to the difference between the row number of the corresponding element in the original matrix corresponding to the first sub-block and the first offset. The value of any element in the index vector indicates the difference between the column number of the corresponding element in the original matrix corresponding to the first sub-block and the second offset.

11. The apparatus as claimed in claim 8 or 9, characterized in that, The processing module is also used to: divide the index matrix corresponding to each first sub-block into sub-blocks of size M2×N2 to obtain multiple third sub-blocks; The storage module is also used to: sequentially store the values ​​of elements within each third sub-block.

12. The apparatus as claimed in claim 11, characterized in that, For each first sub-block, there are multiple second sub-blocks obtained based on the first sub-block and multiple third sub-blocks obtained based on the index matrix corresponding to the first sub-block; the order in which the third sub-blocks are stored is the same as the order in which the second sub-blocks are stored.

13. The apparatus according to any one of claims 8-12, characterized in that, When the storage module sequentially stores the values ​​of elements within each second sub-block, it is specifically used to: select each second sub-block by row or by column, and store the values ​​of elements within each selected second sub-block by row, or store the values ​​of elements within each selected second sub-block by column.

14. The apparatus according to any one of claims 8-13, characterized in that, Each second sub-block of storage includes at least one non-zero element.

15. A computing device, characterized in that, The computing device includes a processor and a memory; The memory is used to store computer program instructions; The processor executes computer program instructions in the memory to perform the method as described in any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that, When the computer-readable storage medium is executed by the storage device, the storage device performs the method according to any one of claims 1 to 7.

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