Memory request address processing method and device, electronic equipment and storage medium

Abstract

The invention discloses a memory request address processing method and device, electronic equipment and a storage medium, and relates to the technical field of memory mapping.The method comprises the steps that for any memory controller, after a memory request address sent by a processing node is received, the address offset condition of the memory request address is detected; when the address offset condition is that address offset exists, performing offset removal on an address in a low-order space in the memory request address to obtain a shift address; determining a to-be-removed bit in the shift address according to a preset address mapping mode, and removing the to-be-removed bit in the shift address to obtain a processed memory request address; and performing address mapping on the processed memory request address based on a preset address mapping mode to obtain a memory row and column address. According to the method and the device, the address is subjected to offset removal and address displacement removal before address mapping of the memory controller, so that repeated reading of scrubbers at the hole is avoided, and the effect of improving DDR performance is achieved.

Description

Technical Field

[0001] The present application relates to the field of memory mapping technology, and in particular to a method, device, electronic device and storage medium for processing a memory request address. Background Art

[0002] Since the memory request node will divide a section of the request address and distribute it to different processing nodes in the process of requesting the memory address, and perform a certain hashing process on the allocated address in each processing node, and map the hashed address to different DDR (Double Data Rate, double rate synchronous dynamic random access memory) controllers, the address received by the DDR will be discontinuous and have holes. Therefore, when the address mapping module of the DDR controller performs memory row and column address conversion, the specific address bits in the received address are removed to make the address continuous. The scrubber (memory inspection) inside the DDR controller is configured before the DDR controller, and will periodically read the DDR memory data to determine whether the memory data has ECC (Error Correcting Code, error correction code) errors, and then take corresponding processing measures. The working mode of the scrubber is to perform incremental access within a section of the address space based on the configured time interval. Therefore, when the DDR controller receives an address with holes, it will cause the scrubber to read the same address repeatedly at the hole, and the read request generated by the scrubber will compete for resources with the normal DDR read and write requests, thereby affecting the performance of the DDR. Summary of the invention

[0003] The main purpose of this application is to provide a memory request address processing method, device, electronic device and storage medium, aiming to solve the technical problem of poor DDR performance.

[0004] To achieve the above object, the present application proposes a memory request address processing method, the memory request address processing method comprising:

[0005] For any memory controller, after receiving the memory request address sent by the processing node, detecting the address offset of the memory request address;

[0006] In the case where the address offset situation is that there is an address offset, the address of the low-order space in the memory request address is offset and removed to obtain a shift address, wherein the low-order space is a preset address range with a minimum address value in the memory request address;

[0007] Determine the bits to be removed in the shift address according to a preset address mapping method, and remove the bits to be removed in the shift address to obtain a processed memory request address;

[0008] The processed memory request address is address mapped based on the preset address mapping method to obtain memory row and column addresses.

[0009] In one embodiment, the step of offsetting and removing the address of the low-order space in the memory request address to obtain the shift address includes:

[0010] Obtaining an address in the low-order space and an address offset of the address;

[0011] The address offset is subtracted from the address to obtain the shift address.

[0012] In one embodiment, the step of determining the bits to be removed in the shift address according to a preset address mapping method comprises:

[0013] Determine a method for performing bit shifting on the shift address according to the preset address mapping method;

[0014] In the case where the bit removal method is low-bit removal, a mapping mode between the processing node and the memory controller is acquired, and the bit to be removed is determined based on the mapping mode.

[0015] In one embodiment, the step of determining the bits to be removed based on the mapping mode comprises:

[0016] In the case where the mapping mode is a scattering mode, based on the corresponding numbers of processing nodes and memory controllers in the scattering mode and a preset cross granularity configured in the memory controller, a first preset address bit removal table is queried to obtain the bit to be removed;

[0017] When the mapping mode is the direct mode, the target processing nodes and the target memory controller that have a mapping relationship in the direct mode are obtained, and based on the first number of the target processing nodes and the second number of the target memory controllers, the second preset address bit removal table is queried to obtain the bit to be removed.

[0018] In one embodiment, the memory request address processing method further includes:

[0019] In the case where the bit removal method is high-bit removal, the step of removing the to-be-removed bits in the shift address is skipped, and the shift address is used as the processed memory request address.

[0020] In one embodiment, after the step of removing the bits to be removed in the shift address, the step further includes:

[0021] Obtaining the original address length of the shift address;

[0022] The high bits of the shifted address after the bits to be removed are padded with zeros based on the original address length.

[0023] In one embodiment, before the step of detecting the address offset of the memory request address, the step further includes:

[0024] Comparing the memory request address with a plurality of preset security address ranges to determine a target preset security address range where the memory request address is located;

[0025] Obtaining a reference security attribute configured for the target preset security address range, and performing security verification on the security attribute corresponding to the memory request address based on the reference security attribute;

[0026] In the event that the security attribute verification fails, the step of detecting the address offset of the memory request address is performed, and a preset identifier is attached to the memory request address so that the memory requested by the memory request address can identify the status information of the memory request address according to the preset identifier.

[0027] In addition, to achieve the above-mentioned purpose, the present application also proposes a memory request address processing device, the memory request address processing device comprising:

[0028] A detection module, configured to detect, for any memory controller, an address offset of the memory request address after receiving the memory request address sent by the processing node;

[0029] A shift module, used for, when the address offset situation is that there is an address offset, offsetting and removing the address of the low-order space in the memory request address to obtain a shift address, wherein the low-order space is a preset address range with the smallest address corresponding value in the memory request address;

[0030] A bit removal module, used for determining the bits to be removed in the shift address according to a preset address mapping method, and removing the bits to be removed in the shift address to obtain a processed memory request address;

[0031] A mapping module is used to perform address mapping on the processed memory request address based on the preset address mapping method to obtain memory row and column addresses.

[0032] In addition, to achieve the above-mentioned purpose, the present application also proposes an electronic device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the memory request address processing method as described above.

[0033] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by the processor, the steps of the memory request address processing method described above are implemented.

[0034] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the memory request address processing method described above are implemented.

[0035] One or more technical solutions proposed in this application have at least the following technical effects:

[0036] The present application detects the address offset of any memory controller after receiving the memory request address sent by the processing node, so as to avoid the problem of address overlap in the low-order space of the memory request address during the mapping process due to the address offset, thereby providing an effective data basis for timely discovering address overlap; when the address offset is that there is an address offset, the address of the low-order space in the memory request address is offset and removed to obtain a shifted address, so as to ensure that no address overlap occurs in the process of requesting the memory address; the bits to be removed in the shifted address are determined according to a preset address mapping method, and the bits to be removed in the shifted address are removed to obtain a processed memory request address, so as to remove the address bits before address mapping is performed on the address in the memory controller, thereby avoiding repeated reading behavior generated by the scrubber when reading DDR memory data; the processed memory request address is address mapped based on the preset address mapping method to obtain memory row and column addresses, so as to realize the conversion of the memory request address into memory row and column addresses recognizable by the memory.

[0037] In summary, the present application performs offset removal and address bit removal on the address before address mapping in the memory controller, and maps the processed continuous and hole-free addresses to memory rows and columns, so that the address data faced by the scrubber when reading DDR memory data is continuous and hole-free, thereby avoiding the problem of the scrubber affecting DDR performance due to repeated reading at the holes, and achieving the effect of improving DDR performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 A flowchart of the first embodiment of the method for processing a memory request address of the present application is provided;

[0041] Figure 2 A schematic diagram of offset removal of the memory request address processing method provided in Embodiment 1 of the present application;

[0042] Figure 3 A schematic diagram of a selection process of a memory request address processing method provided in Embodiment 1 of the present application;

[0043] Figure 4 A flowchart diagram of the second embodiment of the memory request address processing method of the present application is provided;

[0044] Figure 5 A brief flowchart of the memory request address processing method provided in Example 2 of the present application;

[0045] Figure 6 This is a schematic diagram of the module structure of the memory request address processing device according to an embodiment of the present application;

[0046] Figure 7 A schematic diagram of the device structure of the hardware operating environment involved in the memory request address processing method in the embodiment of the present application.

[0047] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0048] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0049] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0050] The main solution of the embodiment of the present application is: for any memory controller, after receiving the memory request address sent by the processing node, the address offset of the memory request address is detected; when the address offset is that there is an address offset, the address of the low-order space in the memory request address is offset and removed to obtain a shifted address, wherein the low-order space is a preset address range with the smallest address corresponding to the address in the memory request address; the bits to be removed in the shifted address are determined according to the preset address mapping method, and the bits to be removed in the shifted address are removed to obtain a processed memory request address; the processed memory request address is address mapped based on the preset address mapping method to obtain a memory row and column address.

[0051] Since the scrubber inside the DDR controller is configured before the DDR controller, it will periodically read the DDR memory data to determine whether the memory data has ECC errors, and then take corresponding processing measures. The working mode of the scrubber is to perform incremental access within a range of address space based on the configured time interval. Therefore, when the DDR controller receives an address with a hole, it will cause the scrubber to repeatedly read the same address at the hole, and the read request generated by the scrubber will compete for resources with normal DDR read and write requests, thereby affecting the performance of DDR.

[0052] The present application provides a solution, which performs offset removal and address bit removal on the address before address mapping in the memory controller, and maps the processed continuous and hole-free addresses to memory rows and columns, so that the address data faced by the scrubber when reading DDR memory data is continuous and hole-free, avoiding the problem of the scrubber affecting DDR performance due to repeated reading at the holes, and achieving the effect of improving DDR performance.

[0053] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device that can realize the above functions. The following takes an electronic device as an example to illustrate this embodiment and the following embodiments.

[0054] Based on this, the embodiment of the present application provides a memory request address processing method, referring to Figure 1 , Figure 1 This is a flowchart diagram of the first embodiment of the memory request address processing method of the present application.

[0055] In this embodiment, the memory request address processing method includes steps S10 to S40:

[0056] Step S10, for any memory controller, after receiving the memory request address sent by the processing node, detecting the address offset of the memory request address;

[0057] It should be noted that a processing node refers to a node in a CMN (Coherent Mesh Network) mesh that performs hash mapping on the physical address sent by a CPU (Central Processing Unit) for requesting memory; a memory request address refers to an address sent by a processing node and pointing to a specific location in memory; an address offset refers to whether there is an offset in the address space, such as whether the address space starts from an all-zero address and increases incrementally.

[0058] It is understandable that when there is an address offset in the memory request address, address overlap will occur during the address mapping process, causing part of the address space to be unavailable. Therefore, performing step S10 can avoid the inability to identify address overlap and provide a reliable basis for subsequent correction of the address offset.

[0059] Step S20, when the address offset situation is that there is an address offset, offset and remove the address of the low-order space in the memory request address to obtain a shift address, wherein the low-order space is a preset address range with the smallest address corresponding value in the memory request address;

[0060] It should be noted that the low space refers to the partial address range in the memory request address that represents smaller data, and this address range has a special mark; the shift address refers to the new address after removing the offset address.

[0061] It is understandable that since the address offset will cause address overlap and affect the normal use of part of the address space, performing step S20 can avoid the problem of part of the address space being unavailable, and further avoid the problem of the address space being segmented too much, which makes it difficult for related hardware to configure resources. This ensures the normal use of the address space while reducing the resource configuration requirements of the related hardware.

[0062] In a feasible implementation manner, the step of offsetting and removing the address of the low-order space in the memory request address to obtain the shift address in step S20 may include steps S21 to S22:

[0063] Step S21, obtaining the address in the low-order space and the address offset of the address;

[0064] It should be noted that the address offset refers to the difference between the memory request address and the base address in the low-order space.

[0065] Exemplarily, when the memory request address is a 128G segment, that is, the address space from 0x0000_8000_0000 to 0x1020_0000_0000, the address in the lower 2G low-order space, that is, the address in the range of 0x0000_8000_0000 to 0x0000_ffff_ffff, is obtained. At this time, the address offset of the address is 0x0000_8000_0000.

[0066] Step S22, subtracting the address offset from the address to obtain the shift address.

[0067] For example, please refer to Figure 2 , the shift address is obtained through the following calculation logic: addr_in

[44] ? addr_in:(addr_in-0x0000_8000_0000), where addr_in

[44] is the lower 2G address of the memory request address to avoid the address in the range of 0x0000_8000_0000 to 0x0000_ffff_ffff from overlapping with the address in the range of 0x1000_8000_0000 to 0x1000_ffff_ffff.

[0068] In this implementation, by performing low-bit analysis and offset removal on the memory request address, the offset in the memory request address is eliminated, thereby avoiding the problem of part of the address space being unavailable, and further avoiding the problem of the address space being segmented too much, which makes it difficult for related hardware to configure resources. This ensures that the address space in the memory request address is used normally, while reducing the resource configuration requirements for the related hardware.

[0069] Step S30, determining the bits to be removed in the shift address according to a preset address mapping method, and removing the bits to be removed in the shift address to obtain a processed memory request address;

[0070] It should be noted that the address mapping method refers to a set of rules or algorithms used in the memory controller to convert physical addresses. The address mapping method is determined by the registers configured in the memory controller and defines the specific method of address conversion, including how to handle special bits of the address; the bits to be removed are determined in real time according to the address mapping method, and are specific address bits that need to be deleted in the shifted address.

[0071] In addition, it should be noted that the preset address mapping method is consistent with the mapping method for address mapping the physical address issued by the CPU in the processing node, that is, the register in the memory controller where the preset address mapping method is located is consistent with the register configuration configured in the processing node, which can avoid the software calculating the bit removal in various address mapping modes, improve the efficiency of bit removal in the memory controller, and thus improve the performance of the memory controller.

[0072] It is understandable that since the address received by the memory controller is discontinuous and has holes, step S30 is performed to remove the special address bits that need to be removed in the address, thereby ensuring that the address faced by the scrubber when reading DDR memory data is continuous and has no holes, thereby avoiding the impact on the normal read and write requests of DDR and improving the read and write performance of DDR.

[0073] In a feasible implementation manner, the step of determining the bits to be removed in the shift address according to the preset address mapping method in step S30 may include steps S31 to S33:

[0074] Step S31, determining a method for performing bit shifting on the shift address according to the address mapping method;

[0075] Exemplarily, the address mapping configured in the register of the memory controller is as follows:

[0076] SN selection mode 3'b000:1-SN mode(SN0);

[0077] 3'b001:3-SN mode(SN0,SN1,SN2);

[0078] 3'b010:6-SN mode(SN0,SN1,SN2,SN3,SN4,SN5);

[0079] 3'b011:5-SN mode(SN0,SN1,SN2,SN3,SN4);

[0080] 3'b100:2-SN mode(SN0,SN1)power of 2hashing;

[0081] 3'b101:4-SN mode(SN0,SN1,SN2,SN3)power of 2hashing;

[0082] 3'b110:8-SN mode(SN0,SN1,SN2,SN3,SN4,SN5,SN6,SN7)

[0083] power of 2hashing;

[0084] Others:Reserved ，The above configuration indicates that the memory controller needs to remove the low bits of the shift address in 1-SN mode, 2-SN mode, 4-SN mode, and 8-SN mode, and the remaining 3 / 6 / 5-SN mode needs to remove the high bits.

[0085] Step S32, when the bit removal method is low bit removal, obtaining a mapping mode between the processing node and the memory controller, and determining the bit to be removed based on the mapping mode;

[0086] It should be noted that the mapping mode refers to the correspondence between the processing node and the memory controller. For example, 1-SN mode means that the mapping mode between the processing node and the memory controller is a one-to-one mapping, 2-SN mode means that the mapping mode between the processing node and the memory controller is one processing node mapping two memory controllers, 4-SN mode means that the mapping mode between the processing node and the memory controller is one processing node mapping four memory controllers, and so on.

[0087] In a feasible implementation manner, the step of determining the bit to be removed based on the mapping mode in step S32 may include steps S321 to S322:

[0088] Step S321, when the mapping mode is a scattering mode, based on the corresponding number of processing nodes and memory controllers in the scattering mode and a preset cross granularity configured in the memory controller, query a first preset address bit removal table to obtain the bit to be removed;

[0089] It should be noted that the scattering mode refers to a one-to-many correspondence between processing nodes and memory controllers, that is, mapping modes such as 2-SN mode, 4-SN mode and 8-SN mode; the corresponding number refers to the number of corresponding relationships between processing nodes and memory controllers in the scattering mode, for example, the corresponding number of 2-SN mode is 2-SN, the corresponding number of 4-SN mode is 4-SN, the corresponding number of 8-SN mode is 8-SN, etc.; the preset cross-granularity refers to the address unit configured in the address mask register in the memory controller.

[0090] Exemplarily, when the mapping mode is the scattering mode, that is, the mapping mode is the 2-SN mode, the 4-SN mode or the 8-SN mode, the corresponding number 2-SN, 4-SN or 8-SN is determined. As shown in the following table:

[0091]

[0092] Table 1

[0093] Table 1 shows that the address mask register is configured as 46'h3fff_ffff_ffc0, that is, the 51st to 6th bits in the 64-bit address are masked, and the rest are reserved. At this time, the cross granularity configured in the memory controller is 64B, that is, the physical space is in units of 64Byte.

[0094] At this time, query the first preset address bit removal table as follows:

[0095]

[0096]

[0097] Table 2

[0098] Table 2 shows that when the corresponding number is 2-SN and the cross granularity is 64B, the bit to be removed is the sixth bit of the address; when the corresponding number is 4-SN and the cross granularity is 64B, the bits to be removed are the sixth to seventh bits of the address, and so on.

[0099] Step S322, when the mapping mode is the direct mode, obtain the target processing nodes and target memory controllers that have a mapping relationship in the direct mode, and based on the first number of the target processing nodes and the second number of the target memory controllers, query the second preset address bit removal table to obtain the bit to be removed.

[0100] It should be noted that the direct mode refers to a mapping mode in which the correspondence between the processing node and the memory controller is a one-to-one relationship, that is, a 1-SN mode (direct mode).

[0101] Exemplarily, the target processing nodes HN-Fs and the target memory controllers SN-Fs that have a mapping relationship in the direct mode are obtained, and the second preset address bit removal table is queried based on the first number Number of HN-Fs of the target processing nodes and the second number Number of SN-Fs of the target memory controllers as follows:

[0102]

[0103] Table 3

[0104] Table 3 shows that when the first number is 2 and the second number is 1, the address bit is not removed; when the first number is 2 and the second number is 2, the bit to be removed is the sixth bit of the address; when the first number is 4 and the second number is 4, the bits to be removed are the sixth to seventh bits of the address, and so on.

[0105] In this implementation, by querying the preset address bit removal table based on the actual mapping situation in the two mapping modes, the special address bits that need to be removed in the address are accurately determined. While ensuring that the memory request address can be correctly mapped in the memory controller after the address bit is removed, the address bit is removed before the address in the memory controller is mapped, thereby avoiding repeated reading behavior caused by the scrubber when reading DDR memory data.

[0106] Step S33, when the bit removal method is high-bit removal, skip the step of removing the to-be-removed bits in the shift address, and use the shift address as the processed memory request address.

[0107] It can be understood that when the removal method is high-bit removal, that is, when the corresponding mapping mode is 3 / 6 / 5-SNmode, there is no need to remove the low bits of the address, so step S33 is performed. By skipping the bit removal operation on the address, the delay of the memory controller in processing the address is reduced, and the operating efficiency of the memory controller is improved.

[0108] For example, please refer to Figure 3 By adopting mux, when the removal mode is high-bit removal, the step of bit removal, i.e., bit_ctrl, is skipped after ofs_ctrl is performed, wherein the interconnection network config copy indicates an address mapping mode that is consistent with that in the processing node and configured in the memory controller.

[0109] Step S40, performing address mapping on the processed memory request address based on the preset address mapping method to obtain memory row and column addresses.

[0110] Exemplarily, in a DDR inner address map module in the memory controller, address mapping is performed on the processed memory request address based on a preset address mapping method to obtain a memory row / col address.

[0111] This embodiment provides a memory request address processing method, by performing offset removal and address bit removal on the address before address mapping in the memory controller, and mapping the processed continuous addresses without holes to memory rows and columns, so that the address data faced by the scrubber when reading DDR memory data is continuous data without holes, avoiding the problem of the scrubber affecting DDR performance due to repeated reading at holes, and achieving the effect of improving DDR performance.

[0112] In a feasible implementation manner, after the step of removing the to-be-removed bits in the shift address in step S30, steps S301 to S302 may also be included:

[0113] Step S301, obtaining the original address length of the shift address;

[0114] It should be noted that the original address length refers to the number of address bits before the shift address is shifted.

[0115] Step S302, padding the high bits of the shifted address after the bits to be removed are removed with zeros based on the original address length.

[0116] It should be noted that high-order zero padding refers to adding 0 in front of a digital address to keep the number of bits in the address unchanged.

[0117] Exemplarily, when the shift address is 1011 and becomes 10 after the to-be-removed bit 11 is removed, the high bits of the address 10 are padded with zeros based on the original address length 4 to obtain the address 0010.

[0118] In this implementation, by padding the high bits of the address after bit removal with zeros, the problems of shortened address length and address space mismatch caused by removing specific address bits are avoided, and the integrity of the address space is maintained, thereby ensuring the correct addressing of the memory request address in the memory, thereby ensuring the accuracy of memory access and the stability of system operation.

[0119] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 4 , Figure 4 This is a flow chart of the second embodiment of the memory request address processing method of the present application.

[0120] Before step S10, the memory request address processing method further includes steps S01 to S04:

[0121] Step S01, comparing the memory request address with a plurality of preset security address ranges to determine a target preset security address range where the memory request address is located;

[0122] It should be noted that the preset security address range refers to an address area pre-defined in the memory controller and configured with special security attribute standards; the target preset security address range refers to the preset security address range into which the memory request address falls.

[0123] In addition, it should be noted that performing security verification on the address before removing the address bits of the memory request address can avoid the need to perform complex configuration adjustments on the security verification process based on the specific removal of the address bits after removing the address bits first, thereby reducing the complexity of processing the memory request address and improving the performance of DDR.

[0124] It is understandable that since the memory request address received by the memory controller may be illegal or unsafe, step S01 is performed to perform a range judgment on the memory request address, thereby providing a basis for judging different security attributes. This can avoid illegal access or out-of-bounds access to the memory, thereby causing system errors, data corruption or security vulnerabilities, etc., and ensure that only legal address requests are processed, thereby improving the stability and security of the system.

[0125] Step S02, obtaining a reference security attribute configured for the target preset security address range, and performing security verification on the security attribute corresponding to the memory request address based on the reference security attribute;

[0126] It should be noted that the reference security attribute refers to a set of security characteristics or identifications corresponding to the target preset security address range. These characteristics are used to verify whether the security attributes of the memory request address are consistent with the characteristics; the security attribute refers to a set of security characteristics or identifications related to the memory request address. These characteristics are used to determine the legality of the request, access rights, data sensitivity and other information. This security attribute is part of memory access control.

[0127] It is understandable that since there are often specific security requirements in the memory access process, performing step S02 can avoid security issues such as unauthorized access, data leakage or malicious operation. By verifying security attributes, the legitimacy and security of memory requests are ensured, thereby protecting the system from security threats and maintaining data integrity and stable operation of the system.

[0128] Step S03, when the security attribute verification fails, executing the step of detecting the address offset of the memory request address, and adding a preset identifier to the memory request address, so that the memory requested by the memory request address can identify the status information of the memory request address according to the preset identifier;

[0129] It should be noted that the preset identifier refers to data used to inform the memory of the specific status of the memory request address. For example, when the preset identifier is used to indicate that the memory request address for reading memory data is not compliant, the memory returns zero data / no data after identifying the preset identifier; when the preset identifier is used to indicate that the memory request address for writing memory data is not compliant, the memory rejects the write operation of the request after identifying the preset identifier.

[0130] Step S04, when the security attribute verification passes, executing the step of detecting the address offset of the memory request address.

[0131] In this embodiment, by comparing the memory request address with the preset address range and verifying the security attributes, it is ensured that only legitimate requests that meet security requirements are processed, thereby preventing potential memory access errors and security threats and improving the overall security and reliability of the system.

[0132] For example, to help understand the implementation process of the memory request address processing method obtained by combining this embodiment with the above-mentioned embodiment 1, please refer to Figure 5 , Figure 5 A brief flowchart of a method for processing a memory request address is provided, specifically:

[0133] After multiple CPUs send out physical addresses requesting memory, the physical addresses are processed by the CMN mesh, i.e., processing nodes, and the processed physical addresses are sent to the memory controller. First, security verification is performed in the memory controller, i.e., a comparison of the preset security address range and verification of security attributes are performed. After security verification, the address is input into the addr_ctrl module for address offset removal and address bit removal, and then the address after removing the specific address bit is address mapped to obtain the memory row and column addresses, wherein a scrubber module is provided before the address mapping module for periodically reading DDR memory data to determine whether there is an ECC error, and if so, taking corresponding measures. This application adds an addr_ctrl module before the address mapping module to perform offset removal and address bit removal on the address before address mapping, so that the address data faced by the scrubber when reading the DDR memory data is continuous data without holes, avoiding the problem of the scrubber affecting DDR performance due to repeated reading at the holes, and achieving the effect of improving DDR performance.

[0134] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the memory request address processing method of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0135] This application also provides a memory request address processing device, please refer to Figure 6 , the memory request address processing device comprises:

[0136] The detection module 10 is used for detecting the address offset of the memory request address for any memory controller after receiving the memory request address sent by the processing node;

[0137] A shift module 20, configured to, when the address offset condition is that there is an address offset, offset and remove the address of the low-order space in the memory request address to obtain a shift address, wherein the low-order space is a preset address range with the smallest address corresponding value in the memory request address;

[0138] A bit removal module 30, configured to determine the bits to be removed in the shift address according to a preset address mapping method, and remove the bits to be removed in the shift address to obtain a processed memory request address;

[0139] The mapping module 40 is used to perform address mapping on the processed memory request address based on the preset address mapping method to obtain memory row and column addresses.

[0140] Optionally, the shift module 20 is further used for:

[0141] Obtaining an address in the low-order space and an address offset of the address;

[0142] The address offset is subtracted from the address to obtain the shift address.

[0143] Optionally, the bit removal module 30 is further used for:

[0144] Determine a method for performing bit shifting on the shift address according to the preset address mapping method;

[0145] In the case where the bit removal method is low-bit removal, a mapping mode between the processing node and the memory controller is acquired, and the bit to be removed is determined based on the mapping mode.

[0146] Optionally, the bit removal module 30 is further used for:

[0147] In the case where the mapping mode is a scattering mode, based on the corresponding numbers of processing nodes and memory controllers in the scattering mode and a preset cross granularity configured in the memory controller, a first preset address bit removal table is queried to obtain the bit to be removed;

[0148] When the mapping mode is the direct mode, the target processing nodes and the target memory controller that have a mapping relationship in the direct mode are obtained, and based on the first number of the target processing nodes and the second number of the target memory controllers, the second preset address bit removal table is queried to obtain the bit to be removed.

[0149] Optionally, the bit removal module 30 is further used for:

[0150] In the case where the bit removal method is high-bit removal, the step of removing the to-be-removed bits in the shift address is skipped, and the shift address is used as the processed memory request address.

[0151] Optionally, the bit removal module 30 is further used for:

[0152] Obtaining the original address length of the shift address;

[0153] The high bits of the shifted address after the bits to be removed are padded with zeros based on the original address length.

[0154] Optionally, the verification module 50 in the memory request address processing device is used to:

[0155] Comparing the memory request address with a plurality of preset security address ranges to determine a target preset security address range where the memory request address is located;

[0156] Obtaining a reference security attribute configured for the target preset security address range, and performing security verification on the security attribute corresponding to the memory request address based on the reference security attribute;

[0157] In the event that the security attribute verification fails, the step of detecting the address offset of the memory request address is performed, and a preset identifier is attached to the memory request address so that the memory requested by the memory request address can identify the status information of the memory request address according to the preset identifier.

[0158] The memory request address processing device provided by the present application adopts the memory request address processing method in the above embodiment, which can solve the technical problem of poor DDR performance. Compared with the prior art, the beneficial effects of the memory request address processing device provided by the present application are the same as the beneficial effects of the memory request address processing method provided by the above embodiment, and other technical features in the memory request address processing device are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0159] The present application provides an electronic device, which includes: at least one processor; and a memory that is communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the memory request address processing method in the above-mentioned embodiment one.

[0160] Reference below Figure 7 , which shows a schematic diagram of the structure of an electronic device suitable for implementing the embodiments of the present application. The electronic devices in the embodiments of the present application may include but are not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 7 The electronic device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0161] like Figure 7 As shown, the electronic device may include a processing device 1001 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the electronic device are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows an electronic device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0162] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0163] The electronic device provided by the present application adopts the memory request address processing method in the above embodiment to solve the technical problem of poor DDR performance. Compared with the prior art, the beneficial effects of the electronic device provided by the present application are the same as the beneficial effects of the memory request address processing method provided by the above embodiment, and other technical features in the electronic device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0164] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0165] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0166] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, wherein the computer-readable program instructions are used to execute the memory request address processing method in the above-mentioned embodiment.

[0167] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0168] The computer-readable storage medium may be included in the electronic device, or may exist independently without being installed in the electronic device.

[0169] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by an electronic device, the electronic device: for any memory controller, after receiving the memory request address sent by the processing node, detects the address offset of the memory request address; when the address offset is that there is an address offset, offsets and removes the address of the low-order space in the memory request address to obtain a shift address, wherein the low-order space is a preset address range with the smallest address corresponding to the address in the memory request address; determines the bits to be removed in the shift address according to a preset address mapping method, and removes the bits to be removed in the shift address to obtain a processed memory request address; performs address mapping on the processed memory request address based on the preset address mapping method to obtain a memory row and column address.

[0170] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0171] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0172] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0173] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned memory request address processing method, and can solve the technical problem of poor DDR performance. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the memory request address processing method provided by the above-mentioned embodiment, and will not be repeated here.

[0174] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned memory request address processing method when executed by a processor.

[0175] The computer program product provided by this application can solve the technical problem of poor DDR performance. Compared with the prior art, the beneficial effects of the computer program product provided by this application are the same as the beneficial effects of the memory request address processing method provided by the above embodiment, which will not be repeated here.

[0176] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A memory request address processing method, characterized in that: The memory request address processing method comprises: For any memory controller, after receiving the memory request address sent by the processing node, detecting the address offset of the memory request address; In the case where the address offset situation is that there is an address offset, the address of the low-order space in the memory request address is offset and removed to obtain a shift address, wherein the low-order space is a preset address range with a minimum address value in the memory request address; Determine the bits to be removed in the shift address according to a preset address mapping method, and remove the bits to be removed in the shift address to obtain a processed memory request address; The processed memory request address is address mapped based on the preset address mapping method to obtain memory row and column addresses.

2. The memory request address processing method according to claim 1, characterized in that: The step of offsetting and removing the address of the low-order space in the memory request address to obtain a shift address comprises: Obtaining an address in the low-order space and an address offset of the address; The address offset is subtracted from the address to obtain the shift address.

3. The memory request address processing method according to claim 1, characterized in that: The step of determining the bits to be removed in the shift address according to a preset address mapping method comprises: Determine a method for performing bit shifting on the shift address according to the preset address mapping method; In the case where the bit removal method is low-bit removal, a mapping mode between the processing node and the memory controller is acquired, and the bit to be removed is determined based on the mapping mode.

4. The memory request address processing method according to claim 3, characterized in that: The step of determining the bits to be removed based on the mapping mode comprises: In the case where the mapping mode is a scattering mode, based on the corresponding numbers of processing nodes and memory controllers in the scattering mode and a preset cross granularity configured in the memory controller, a first preset address bit removal table is queried to obtain the bit to be removed; When the mapping mode is the direct mode, the target processing nodes and the target memory controller that have a mapping relationship in the direct mode are obtained, and based on the first number of the target processing nodes and the second number of the target memory controllers, the second preset address bit removal table is queried to obtain the bit to be removed.

5. The memory request address processing method according to claim 3, characterized in that: The memory request address processing method also includes: In the case where the bit removal method is high-bit removal, the step of removing the to-be-removed bits in the shift address is skipped, and the shift address is used as the processed memory request address.

6. The memory request address processing method according to claim 1, characterized in that: After the step of removing the bit to be removed in the shift address, the following step is further included: Obtaining the original address length of the shift address; The high bits of the shifted address after the bits to be removed are padded with zeros based on the original address length.

7. The memory request address processing method according to claim 1, characterized in that: Before the step of detecting the address offset of the memory request address, the step further includes: Comparing the memory request address with a plurality of preset security address ranges to determine a target preset security address range where the memory request address is located; Obtaining a reference security attribute configured for the target preset security address range, and performing security verification on the security attribute corresponding to the memory request address based on the reference security attribute; In the event that the security attribute verification fails, the step of detecting the address offset of the memory request address is performed, and a preset identifier is attached to the memory request address so that the memory requested by the memory request address can identify the status information of the memory request address according to the preset identifier.

8. A memory request address processing device, characterized in that: The memory request address processing device comprises: A detection module, configured to detect, for any memory controller, an address offset of the memory request address after receiving the memory request address sent by the processing node; A shift module, used for, when the address offset situation is that there is an address offset, offsetting and removing the address of the low-order space in the memory request address to obtain a shift address, wherein the low-order space is a preset address range with the smallest address corresponding value in the memory request address; A bit removal module, used for determining the bits to be removed in the shift address according to a preset address mapping method, and removing the bits to be removed in the shift address to obtain a processed memory request address; A mapping module is used to perform address mapping on the processed memory request address based on the preset address mapping method to obtain memory row and column addresses.

9. An electronic device, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the memory request address processing method according to any one of claims 1 to 7.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the memory request address processing method according to any one of claims 1 to 7 are implemented.

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