System and method for accessing a storage device as a memory

Abstract

Aspects of the embodiments are directed to systems, devices, and methods for accessing a storage device as memory. The embodiments include a microprocessor comprising a microprocessor system agent and a field programmable gate array (FPGA). The FPGA includes the FPGA system agent that processes memory access requests received from the microprocessor system agent across a communication link; a memory controller communicatively coupled to the system agent; and a high-speed serial interface linking the system agent with the storage system. The embodiments may also include a storage device connected to the FPGA via the high-speed serial interface.

Description

Technical Field

[0001] The present disclosure relates to systems and methods for accessing storage-as-memory. Background Art

[0002] Storage devices are often accessed as devices on high-latency hardware interfaces through inefficient software layers. With the advent of low-latency storage devices, the access latency to these devices is becoming extremely low, approaching the latency of typical DDR memory accesses. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 An embodiment of a block diagram for a computing system including a multi-core processor is illustrated.

[0004] Figure 2 is a schematic diagram of an example multi-chip platform including a field programmable gate array and a system agent according to an embodiment of the present disclosure.

[0005] Figure 3 is a schematic diagram of another example multi-chip platform including a field programmable gate array and a system agent according to an embodiment of the present disclosure.

[0006] Figure 4 is a schematic diagram of an example multi-chip platform including a field programmable gate array and a system agent illustrating an in-line accelerator circuit according to an embodiment of the present disclosure.

[0007] Figure 5A is a schematic diagram of an example multi-chip platform including a field programmable gate array and a system agent for connecting to a fabric-connected storage device as memory according to an embodiment of the present disclosure.

[0008] Figure 5B is a schematic diagram of a storage device connected as a memory according to an example configuration of an embodiment of the present disclosure.

[0009] Figure 6A is a flowchart of a process for processing a memory access request according to an embodiment of the present disclosure.

[0010] Figure 6B is a process flow diagram for asynchronous memory access execution according to an embodiment of the present disclosure.

[0011] Figure 6C is a flowchart of a process for performing online data processing according to an embodiment of the present disclosure.

[0012] Figure 7 is a schematic diagram of an embodiment of a fabric consisting of point-to-point links interconnecting a set of components according to an embodiment of the present disclosure.

[0013] Figure 8 is a schematic diagram of an embodiment of a layered protocol stack according to an embodiment of the present disclosure.

[0014] Figure 9 is a schematic diagram of an embodiment of a PCIe transaction descriptor according to an embodiment of the present disclosure.

[0015] Figure 10 is a schematic diagram of an embodiment of a PCIe serial point-to-point configuration according to an embodiment of the present disclosure.

[0016] Figure 11 is a schematic block diagram of an exemplary computer system formed using a processor including execution units that execute instructions, wherein one or more of the processors are interconnected to implement one or more features according to one embodiment of the present disclosure.

[0017] Figure 12 is a schematic block diagram of a system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] In the following description, many specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements / heights, specific processor pipeline stages and operations, etc., in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that these specific details need not be adopted to practice the present disclosure. In other instances, well-known components or methods, such as specific and alternative processor architectures, specific logic circuits / code for the described algorithms, specific firmware code, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expressions of algorithms in code, specific power down and gating techniques / logic, and other specific operational details of computer systems, are not described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0019] Although the following embodiments may be described with reference to energy conservation and energy efficiency in specific integrated circuits (such as in computing platforms or microprocessors), other embodiments may be applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein can be applied to other types of circuits or semiconductor devices that may also benefit from improved energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™. They may also be used in other devices such as handheld devices, tablets, other thin laptops, system-on-a-chip (SoC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include microcontrollers, digital signal processors (DSPs), system-on-a-chips, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system capable of performing the functions and operations taught below. Furthermore, the apparatus, methods, and systems described herein are not limited to physical computing devices but may also involve software optimization for energy conservation and efficiency. As will become readily apparent from the following description, embodiments of the methods, apparatus, and systems described herein (whether in hardware, firmware, software, or a combination thereof) are crucial to a "green technology" future that is balanced against performance considerations.

[0020] As computing systems advance, the components within them become more complex. Consequently, the interconnect architectures used to couple and communicate between components are also increasing in complexity to ensure bandwidth requirements are met for optimized component operation. Furthermore, different market segments demand different aspects of the interconnect architecture to suit their needs. For example, servers demand higher performance, while the mobile ecosystem can sometimes sacrifice overall performance for power savings. However, providing the highest possible performance with maximum power savings is the singular goal of most architectures. Below, several interconnects are discussed that could potentially benefit from the disclosed aspects described herein.

[0021] See also Figure 1 , an embodiment of a block diagram for a computing system including a multi-core processor is depicted. Processor 100 comprises any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system on a chip (SoC), or other device that executes code. In one embodiment, processor 100 includes at least two cores—101 and 102—which may include asymmetric cores or symmetric cores (in the embodiment shown). However, processor 100 may include any number of processing elements that may be symmetric or asymmetric.

[0022] In one embodiment, a processing element refers to hardware or logic used to support a software thread. Examples of hardware processing elements include: thread units, thread slots, threads, process units, contexts, context units, logical processors, hardware threads, cores, and / or any other element capable of saving state (such as execution state or architectural state) for a processor. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with code (such as a software thread, operating system, application, or other code). A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.

[0023] A core generally refers to logic located on an integrated circuit that is capable of maintaining an independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to a core, a hardware thread typically refers to any logic located on an integrated circuit that is capable of maintaining an independent architectural state, where the independently maintained architectural states share access to execution resources. As can be seen, the boundary between the nomenclature of hardware thread and core overlaps when some resources are shared and other resources are dedicated to a certain architectural state. However, cores and hardware threads are often viewed by the operating system as separate logical processors, where the operating system can schedule operations on each logical processor separately.

[0024] like Figure 1 As shown in , physical processor 100 includes two cores—core 101 and 102. Here, cores 101 and 102 are considered to be symmetric cores, i.e., cores having the same configuration, functional units, and / or logic. In another embodiment, core 101 includes an out-of-order processor core, while core 102 includes an in-order processor core. However, cores 101 and 102 can be individually selected from any type of core, such as a native core, a software-managed core, a core adapted to execute a native instruction set architecture (ISA), a core adapted to execute a converted instruction set architecture (ISA), a co-designed core, or other known cores. In a heterogeneous core environment (i.e., an asymmetric core), some form of conversion (such as binary conversion) can be used to schedule or execute code on one or both cores. Also for further discussion, the functional units illustrated in core 101 are described in further detail below, as the units in core 102 operate in a similar manner in the depicted embodiment.

[0025] As depicted, core 101 includes two hardware threads 101a and 101b, which may also be referred to as hardware thread slots 101a and 101b. Therefore, in one embodiment, a software entity (such as an operating system) potentially views processor 100 as four separate processors, i.e., four logical processors or processing elements, capable of concurrently executing four software threads. As alluded to above, a first thread is associated with architecture state registers 101a, a second thread is associated with architecture state registers 101b, a third thread may be associated with architecture state registers 102a, and a fourth thread may be associated with architecture state registers 102b. Each of the architecture state registers (101a, 101b, 102a, and 102b) may be referred to herein as a processing element, thread slot, or thread unit, as described above. As illustrated, architecture state register 101a is replicated in architecture state register 101b, so that separate architecture states / contexts can be stored for logical processors 101a and 101b. In core 101, other smaller resources, such as the instruction pointer and renaming logic in allocator and rename block 130, can also be replicated for threads 101a and 101b. Some resources, such as the reorder buffers, ILTB 120, load / store buffers, and queues in reorder / retirement unit 135, can be shared through partitioning. Other resources, such as general internal registers, page table base registers, low-level data cache and data TLB 115, execution units 140, and portions of out-of-order unit 135, are potentially fully shared.

[0026] Processor 100 often includes other resources that may be fully shared, shared through partitioning, or dedicated by / to processing elements. Figure 1 , an embodiment of a purely exemplary processor (with illustrative logic units / resources of the processor) is illustrated. Note that the processor may include or omit any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core 101 comprises a simplified, representative out-of-order (OOO) processor core. However, in-order processors may be utilized in different embodiments. The OOO core includes a branch target buffer 120 to predict branches to be executed / taken and an instruction translation buffer (I-TLB) 120 to store address translation entries for instructions.

[0027] Core 101 further includes a decode module 125 coupled to fetch unit 120 to decode fetched elements. In one embodiment, the fetch logic includes separate sequencers associated with thread slots 101a and 101b, respectively. Core 101 is typically associated with a first ISA, which defines / specifies the instructions executable on processor 100. Machine code instructions that are part of the first ISA often include a portion of the instruction (called an opcode) that references / specifies the instruction or operation to be performed. Decode logic 125 includes circuitry that identifies these instructions by their opcodes and passes the decoded instructions through the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below, in one embodiment, decoder 125 includes logic designed or adapted to recognize specific instructions, such as transactional instructions. As a result of the recognition performed by decoder 125, the architecture or core 101 takes specific, predefined actions to perform the task associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein can be executed in response to a single or multiple instructions; some of these instructions may be new or legacy instructions. Note that in one embodiment, decoders 126 recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 126 recognize a second ISA (a subset of the first ISA or an entirely different ISA).

[0028] In one example, allocator and renamer block 130 includes an allocator to reserve resources, such as a register file, for storing instruction processing results. However, threads 101a and 101b are potentially capable of out-of-order execution, with allocator and renamer block 130 also reserving other resources, such as a reorder buffer to track instruction results. Unit 130 may also include a register renamer to rename program / instruction reference registers to other registers within processor 100. Reorder / retirement unit 135 includes components (such as the reorder buffer, load buffer, and store buffer mentioned above) to support out-of-order execution and the later in-order retirement of instructions executed out-of-order.

[0029] In one embodiment, scheduler and execution unit block 140 includes a scheduler unit to schedule instructions / operations on the execution units. For example, floating-point instructions are scheduled on the port of the execution unit that has an available floating-point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating-point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

[0030] A lower-level data cache and data translation buffer (D-TLB) 150 are coupled to the execution unit 140. The data cache is to store recently used / operated on elements, such as data operands, which are potentially retained in a memory consistency state. The D-TLB is to store the most recent virtual / linear to physical address translations. As a specific example, the processor may include a page table structure to decompose physical memory into multiple virtual pages.

[0031] Here, cores 101 and 102 share access to a higher level or further-out cache, such as a second level cache associated with on-chip interface 110. Note that higher level or further refers to cache levels that increase or become further away from the execution units. In one embodiment, the higher level cache is a last level data cache—the last level cache in the memory hierarchy on processor 100—such as a second or third level data cache. However, the higher level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache—a type of instruction cache—in turn may be coupled after decoder 125 to store recently decoded traces. Here, instruction potentially refers to a macroinstruction (i.e., a general instruction recognized by the decoder) that may be decoded into multiple microinstructions (macro-operations).

[0032] In the depicted configuration, processor 100 also includes an on-chip interface module 110. Historically, a memory controller, described in more detail below, has been included in a computing system external to processor 100. In this case, on-chip interface 110 is to communicate with devices external to processor 100, such as system memory 175, a chipset (often including a memory controller hub connected to memory 175 and an I / O controller hub connected to peripheral devices), a memory controller hub, a north bridge, or other integrated circuit. Also in this case, bus 105 may include any known interconnect, such as a multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

[0033] Memory 175 may be dedicated to processor 100 or shared with other devices in the system. Common examples of types of memory 175 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device 180 may include a graphics accelerator, a processor or card coupled to a memory controller hub, a data storage device coupled to an I / O controller hub, a wireless transceiver, a flash memory device, an audio controller, a network controller, or other known devices.

[0034] Recently, however, as more logic and devices are being integrated onto a single die (such as an SOC), each of these devices may be combined onto the processor 100. For example, in one embodiment, a memory controller hub is on the same package and / or die as the processor 100. Here, a portion of the core 110 (the on-core portion) includes one or more controllers for interfacing with other devices such as memory 175 or graphics 180. A configuration that includes interconnects and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, the on-chip interface 110 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 105 for off-chip communication. However, in an SOC environment, even more devices (such as a network interface, coprocessor, memory 175, graphics processor 180, and any other known computer devices / interfaces) may be integrated onto a single die or integrated circuit to provide high functionality and low power consumption in a small form factor.

[0035] In one embodiment, the processor 100 is capable of executing a compiler, optimizer and / or converter code 177 that compiles, converts and / or optimizes application code 176 to support or interface with the devices and methods described herein. A compiler typically includes a program or set of programs to convert source text / code into target text / code. Typically, compilation of program / application code using a compiler is performed in multiple stages and passes to transform high-level programming language code into low-level machine or assembly language code. However, a single-pass compiler may still be used for simple compilation. The compiler may utilize any known compilation technology and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

[0036] Larger compilers often include multiple phases, but most commonly, these phases are included within two general phases: (1) the front end, which is typically where syntactic processing, semantic processing, and some transformation / optimization can occur, and (2) the back end, which is typically where analysis, transformation, optimization, and code generation can occur. Some compilers refer to the middle end, which illustrates the ambiguity of the delineation between the front end and the back end of the compiler. Therefore, references to insertion, association, generation, or other operations of the compiler can occur in any of the above phases or passes, as well as in any other known phases or passes of the compiler. As an illustrative example, the compiler potentially inserts operations, calls, functions, etc. in one or more phases of compilation, such as inserting the call / operation in the front end phase of compilation and then transforming the call / operation to lower-level code during the transformation phase. Note that during dynamic compilation, compiler code or dynamic optimization code can insert such operations / calls and optimize code for execution during runtime. As a specific illustrative example, binary code (already compiled code) can be dynamically optimized during runtime. Here, program code can include dynamic optimization code, binary code, or a combination thereof.

[0037] The following detailed description refers to the accompanying drawings. The same reference numerals may be used to identify the same or similar elements in different figures. In the following description, for the purpose of explanation rather than limitation, specific details are set forth, such as specific structures, architectures, interfaces, technologies, etc., in order to provide a thorough understanding of the various aspects of the various embodiments. However, it will be apparent to those skilled in the art who benefit from this disclosure that the various aspects of the various embodiments may be practiced in other examples that deviate from these specific details. In some instances, descriptions of well-known devices, circuits, and methods are omitted to avoid unnecessary details that obscure the description of the various embodiments.

[0038] Current software and hardware interface overhead prohibits efficient utilization of improved storage capabilities, such as storage as memory. The present disclosure is directed to exposing storage as coherent memory directly accessible from the core using hardware capabilities. This disclosure includes using a processor-integrated field programmable gate array (FPGA) to leverage programmable logic in the FPGA to create a system agent in a coherency domain to extend memory semantics to storage via PCIe.

[0039] Today, storage devices are high-latency devices that are programmed and accessed using a device model from the core. This means long-latency IO interfaces (doorbells, interrupts) and many layers of the storage SW stack. The present disclosure exposes storage devices (particularly low-latency NVM technology with low device access latency) as coherent memory. This allows for the exposure of massive memory sizes to the system, which benefits many applications like in-memory databases and provides low-latency storage for many big data applications.

[0040] Figure 2 Schematic diagram 200 of an example multi-chip platform (MCP) 202 including a field programmable gate array (FPGA) 204 and a system agent 206 according to an embodiment of the present disclosure. MCP 202 includes a processor 212. Processor 212 can be a hardware processor, such as a microprocessor. Processor 212 includes a system agent 214 configured to execute memory access instructions from, for example, an application 228. Application 228 can make storage device access requests 232 and memory access requests 230, each of which can be processed by processor 212 (or specifically by system agent 214). The system agent can access storage device 226 via PCIe interface 224 or via other interfaces, such as a Serial Advanced Technology Attachment (SATA)-compliant link. Memory accesses are routed through system agent 214 to DDR interface 234, through system agent 214 and memory controller 207, or to other home agents in a coherency domain.

[0041] MCP 202 also includes FPGA 204. FPGA 204 includes a system agent 206, implemented in hardware, such as through digital design. System agent 206 is configured to execute memory access instructions. System agent 206 can identify the physical address for its channel in order to execute the memory access request via QPI or UPI compliant link 216. System agent 206 converts the physical address into a channel address and passes it to memory controller 207. The system agent is responsible for mapping memory into the processor system address space. System agent 206 may also be responsible for managing cache coherency across the system. Each memory controller 207 has a table to look up what to do for each range of channel addresses it is passing. System agent 206 can advertise address spaces to system agent 214. System agent 214 can direct memory access requests for the advertised address spaces to system agent 206.

[0042] Aspects of the present disclosure are directed to a system agent 206 built into the FPGA 204. The system agent 206 is configured to conform to a processor Quick Path Interconnect (QPI) or Ultra Path Interconnect (UPI) coherency domain and participates in memory transactions on behalf of memory devices 210 connected via HSSI (High Speed ​​Serial Interface) 208. The system agent 206 exposes and manages the memory devices 210 connected to it via HSSI 208 as memory. The system agent 206 participates in memory transactions via the QPI / UPI protocol 216 and responds to messages related to the memory behind it.

[0043] The system agent 206 also manages the directory structure stored in its own memory or in DRAM connected to the processor, and optionally caches it in the FPGA block RAM 234.

[0044] The system agent 206 is configured to operate as a hardware design that couples a storage device as memory to a processor through a hardware-based coherence protocol.

[0045] When a memory request reaches system agent 214, system agent 214 can identify system agent 206 as the responsible entity for processing the memory access request. For example, system agent 214 can identify system agent 206 as part of FPGA 204 for processing the memory access request. System agent 206 can process the memory access request by accessing the appropriate address from storage device element 210 acting as memory through HSSI 208.

[0046] Although shown as an MCP, a single-chip platform can also be used, such as an ASIC. Embodiments can be extended beyond FPGA implementations to include any accelerator that can be connected to a processor and storage devices, and can include hardware system agents. Other examples of such accelerators can include dedicated accelerator chips or general-purpose computing on a graphics processing unit (GPGPU).

[0047] Figure 3 FIG3 is a schematic diagram 300 of another example multi-chip platform 302 including a field programmable gate array 304 and a system agent 306 according to an embodiment of the present disclosure. In some embodiments, the FPGA 304 supports direct mapping 314 of memory RD / WR 328 transactions through the system agent 306 to a memory controller 316, which provides additional flow control. The FPGA 304 also includes one or more accelerator circuits 308 for performing in-line processing (reading or writing data) of data.

[0048] FPGA 304 can include a 4KB row cache 312. 4KB row cache 312 can cache data blocks from storage device 210. In some embodiments, memory reads and writes can account for long latencies by using asynchronous read / write instructions. System agent 214 can send a read acknowledgment to processor system agent 214. The read acknowledgment can be sent during the latency of the read execution, allowing processor 212 to move to the next processing step. System agent 306 can cache data blocks retrieved from storage device 210 in row cache 312. Similarly, system agent 306 can provide write acknowledgments and cache the write data in row cache 312, and then store the write data in memory within storage device 210 as memory.

[0049] The system agent 306 can cache data fed from the storage device 210 in higher block sizes as well (in 4KB blocks in the 4KB line cache 312 as opposed to 64B requests on a cache line).

[0050] Directory cache 310 can provide additional performance by retaining a portion or subset of the memory directory. Directory cache 310 can be part of FPGA 304 that caches a portion of the memory directory—memory represented by potentially several terabytes of available storage (or more).

[0051] In an embodiment, FPGA 304 can emulate a PCIe root complex. By emulating the PCIe root complex and the PCIe interface, system agent 306 can directly expose memory in storage device 210 as memory.

[0052] In some implementations, the existing PCIe IP in FPGA 304 connects to an existing PCIe-based storage solution. To extend consistent memory to the device side, QPI messages are tunneled through the PCIe protocol. Instead of handling the Non-Volatile Memory Express (NVMe) protocol 326 over PCIe, the controller needs to handle RD / WR transactions over PCIe.

[0053] Figure 4Schematic diagram 400 of an example multi-chip platform 402 including a field programmable gate array 404 and a system agent 406 illustrating online accelerator circuitry according to an embodiment of the present disclosure. The embodiment includes online accelerators 414 a and 414 b built into FPGA 404 to perform memory-side streaming acceleration (e.g., encryption / decryption, compression / decompression, Structured Query Language (SQL) acceleration, extract-transform-load (ETL) functions, etc.). Accelerators 414 a and 414 b can utilize an optional cache 412 and cache controller 410 built into the FPGA logic to improve performance.

[0054] Figure 4 Also illustrated is how certain memory controller components can be moved to FPGA 404 to expose the storage device as memory 210. FPGA 404 can include memory controller 416, which includes a 4KB cache 418. FPGA 404 can also include NVMe driver 420 as a hardware circuit design that emulates NVMe driver functionality.

[0055] Similar to those embodiments shown above, processor 212 can include a system agent 214 that can interface with FPGA 404 across a QPI-compliant link, such as UPI link 218. FPGA 404 is shown as including a UPI interface 408 that can facilitate a QPI-compliant (or UPI-specific) protocol between system agent 406 or cache agent 410 and system agent 214. It is understood that FPGAs generally described herein will include a protocol interface, such as UPI interface 408, to facilitate communications between system agent 214 and FPGA components, such as system agent 406.

[0056] Figure 5A is a diagram 500 of an example multi-chip platform 502 including a field programmable gate array 504 and a system agent 506 for connecting to a fabric-connected storage device as memory according to an embodiment of the present disclosure. Figure 5B 550 is a diagram of an example fabric-attached storage device as memory according to an embodiment of the present disclosure. In an embodiment of the present disclosure, a fabric-attached storage device (or traditional DRAM memory) can be exposed as memory. In this scenario, HSSI 208 is connected to an external fabric that drives memory transactions via a fabric protocol. Memory extensions can be used to expose disaggregated storage device as memory 516 or disaggregated memory 518 via fabric.

[0057] FPGA 504 can include a fabric interface 514 that can provide hardware steps to emulate the fabric interface. FPGA 504 can also include an NVMe driver 512 to provide memory access across HSSI 208. In an embodiment, NVMe driver 512 or fabric 514 can include circuitry that emulates a PCIe interface, allowing NVMe driver 512 to perform memory RD / WR across HSSI 208. FPGA 504 can also include a cache 510 and a memory controller 508 coupled to a system agent 506.

[0058] Figure 5B Illustrated are example disaggregated storage as memory 516 and disaggregated memory 518. Disaggregated storage as memory 516 can include multiple networked storage devices 520. Disaggregated memory 518 can include multiple networked memory elements 522.

[0059] Even though the fabric shown here has a 2D mesh topology, it can be replaced with any topology based on scaling requirements. HSSI 208 can also be expanded to support higher bandwidth, especially if DRAM 522 is attached to the fabric. Components shown as implemented in FPGAs can ultimately be integrated into a processor as hardened logic for power / performance reasons.

[0060] To address performance and potential functional issues surrounding long-latency memory reads, asynchronous support can be used. That is, instead of a synchronous read that returns with a data response, the system agent can issue and complete the instruction with a non-data response to the processor. The data is then received via user-level MWAIT, triggered by the arrival of data in the 4KB line cache in the FPGA.

[0061] Figure 6A 600 is a process flow diagram for processing a memory access request according to an embodiment of the present disclosure. The process can be performed by a field programmable gate array (FPGA) or one or more components of the FPGA, such as a hardware implementation of a system agent. The system agent can receive a memory access request (602) from another system agent coupled to a processor of the FPGA via a link compliant with a Quick Path Interconnect (QPI), such as a link compliant with a Super Path Interconnect (UPI). The system agent can identify a memory location in a connected storage device as memory across a high-speed serial interconnect (HSSI) (604) and execute the memory access request (606).

[0062] Figure 6B610 is a process flow diagram for asynchronous memory access execution according to an embodiment of the present disclosure. The process can be executed by a field programmable gate array (FPGA) or one or more components of the FPGA, such as a hardware implementation of a system agent. The system agent can receive a memory access request (612) from another system agent coupled to a processor of the FPGA via a link compliant with a Quick Path Interconnect (QPI), such as a link compliant with a Super Path Interconnect (UPI). The system agent can identify a memory location (614) in a connected storage device as memory across a high-speed serial interconnect (HSSI) to execute the memory access request (616).

[0063] The system agent can then provide confirmation of the execution of the memory access request to the requesting system agent (618). In an embodiment, the confirmation can include a read confirmation. The system agent can cache the read data in a row cache in the FPGA (620) and transmit the read data from the FPGA row cache at a later time (622).

[0064] In an embodiment, the system agent can provide write acknowledgement and can cache the write data in a line cache in the FPGA and store the write data in the cache at a later time.

[0065] Figure 6C 630 is a process flow diagram for performing online data processing according to an embodiment of the present disclosure. The process can be performed by a field programmable gate array (FPGA) or one or more components of the FPGA (such as a hardware implementation of a system agent). The system agent can receive a memory access request (632) from another system agent coupled to a processor of the FPGA via a link compliant with a Quick Path Interconnect (QPI), such as a link compliant with a Super Path Interconnect (UPI) . The system agent can identify a memory location in a connected storage device as memory (634). The system agent can direct data (read or write data) to one or more accelerator circuits (636) that are part of the FPGA. The one or more accelerator circuits can process the data (638). The system agent can then provide the data to the processor (for a read instruction) or can store the processed data in memory (for a write instruction) (640).

[0066] Aspects of the present disclosure expose large-capacity, low-latency (storage) devices as memory through a non-DDR interface, with advantages including access to high-capacity memory through traditional memory RD / WR semantics without sacrificing a high-performance DDR interface. This has the potential to improve application performance when using large amounts of in-memory computing.

[0067] One interconnect fabric architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. The primary purpose of PCIe is to enable components and devices from different vendors to interoperate in an open architecture across multiple market segments: clients (desktop and mobile), servers (standard and enterprise), and embedded and communications devices. PCI Express is a high-performance, general-purpose I / O interconnect defined for a wide variety of future computing and communications platforms. Some PCI attributes, such as its usage model, load-store architecture, and software interface, have been maintained through its revisions, while the previous parallel bus implementation has been replaced with a highly scalable, fully serial interface. More recent versions of PCI Express leverage advances in point-to-point interconnects, switch-based technologies, and packetized protocols to deliver new levels of performance and features. Power management, quality of service (QoS), hot-plug / hot-swap support, data integrity, and error handling are among the advanced features supported by PCI Express.

[0068] See also Figure 7 , an embodiment of a configuration consisting of point-to-point links interconnecting a set of components is illustrated. System 700 includes a processor 705 and system memory 710 coupled to a controller hub 715. Processor 705 includes any processing element such as a microprocessor, a host processor, an embedded processor, a coprocessor, or other processor. Processor 705 is coupled to controller hub 715 via a front side bus (FSB) 706. In one embodiment, FSB 706 is a serial point-to-point interconnect as described below. In another embodiment, link 706 includes a serial differential interconnect architecture that conforms to a different interconnect standard.

[0069] System memory 710 includes any memory device, such as random access memory (RAM), nonvolatile (NV) memory, or other memory accessible by devices in system 700. System memory 710 is coupled to controller hub 715 through a memory interface 716. Examples of a memory interface include a double data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

[0070] In one embodiment, the controller hub 715 is a root hub, root complex, or root controller in the Peripheral Component Interconnect Express (PCIe or PCIE) interconnect hierarchy. Examples of controller hubs 715 include chipsets, memory controller hubs (MCHs), north bridges, interconnect controller hubs (ICHs), south bridges, and root controller / hubs. The term chipset often refers to two physically separate controller hubs, namely, a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include an MCH integrated with the processor 705, while the controller 715 communicates with I / O devices in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported through the root complex 715.

[0071] Here, controller hub 715 is coupled to switch / bridge 720 via serial link 719. Input / output modules 717 and 721, which may also be referred to as interfaces / ports 717 and 721, include / implement a layered protocol stack to provide communication between controller hub 715 and switch 720. In one embodiment, multiple devices can be coupled to switch 720.

[0072] Switch / bridge 720 routes packets / messages from devices 725 upstream (i.e., up the hierarchy toward the root complex) to controller hub 715, and downstream (i.e., down the hierarchy away from the root controller) from processor 705 or system memory 710 to devices 725. In one embodiment, switch 720 refers to a logical assembly of multiple virtual PCI-to-PCI bridge devices. Devices 725 include any internal or external device or component to be coupled to an electronic system, such as I / O devices, network interface controllers (NICs), add-in cards, audio processors, network processors, hard drives, storage devices, CD / DVD ROMs, monitors, printers, mice, keyboards, routers, portable storage devices, FireWire devices, Universal Serial Bus (USB) devices, scanners, and other input / output devices. In PCIe terminology, such devices are often referred to as endpoints. Although not explicitly shown, devices 725 may include PCIe-to-PCI / PCI-X bridges to support legacy or other versions of PCI devices. Endpoint devices in PCIe are often categorized as either legacy PCIe or root complex integrated endpoints.

[0073] Graphics accelerator 730 is also coupled to controller hub 715 via serial link 732. In one embodiment, graphics accelerator 730 is coupled to the MCH, which is coupled to the ICH. Switch 720 and, accordingly, I / O device 725 are thus coupled to the ICH. I / O modules 731 and 718 also implement a layered protocol stack for communication between graphics accelerator 730 and controller hub 715. Similar to the MCH discussion above, the graphics controller or graphics accelerator 730 itself may be integrated into processor 705.

[0074] Go to Figure 8 , an embodiment of a layered protocol stack is illustrated. The layered protocol stack 800 includes any form of layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or other layered stack. Although immediately below see Figure 7-10 The discussion is related to the PCIe stack, but the same concepts can be applied to other interconnect stacks. In one embodiment, the protocol stack 800 is a PCIe protocol stack, including a transaction layer 805, a link layer 810, and a physical layer 820. Figure 7 The interfaces 717, 718, 721, 722, 726, and 731 in may be represented as a communication protocol stack 800. Representation as a communication protocol stack may also refer to modules or interfaces that implement / include the protocol stack.

[0075] PCI Express uses packets to transfer information between components. Packets are formed in the Transaction Layer 805 and Data Link Layer 810 to carry information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are expanded with additional information required to process the packets at those layers. The reverse process occurs on the receiving side, and the packet is converted from its Physical Layer 820 representation to the Data Link Layer 810 representation, and finally (for transaction layer packets) to a form that can be processed by the Transaction Layer 805 of the receiving device.

[0076] Transaction Layer

[0077] In one embodiment, the transaction layer 805 provides an interface between a device's processing core and the interconnect architecture (such as the data link layer 810 and the physical layer 820). In this regard, the primary responsibility of the transaction layer 805 is the assembly and disassembly of packets (i.e., transaction layer packets, or TLPs). The transaction layer 805 typically manages credit-based flow control for TLPs. PCIe implements split transactions (i.e., transactions with request and response separated by time) to allow the link to carry other traffic while the target device gathers data for the response.

[0078] Additionally, PCIe utilizes credit-based flow control. In this scheme, a device advertises an initial amount of credits for each receive buffer in the transaction layer 805. Figure 7 An external device at the opposite end of the link from the controller hub 715 counts the number of credits consumed by each TLP. If the transaction does not exceed the credit limit, the transaction is forwarded. Upon receiving a response, the amount of credit is restored. The advantage of the credit scheme is that, assuming the credit limit is not encountered, the latency for credit return does not impact performance.

[0079] In one embodiment, the four transaction address spaces include a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to / from a memory-mapped location. In one embodiment, memory space transactions can use two different address formats, for example, a short address format such as a 32-bit address or a long address format such as a 64-bit address. Configuration space transactions are used to access the configuration space of a PCIe device. Transactions to the configuration space include read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

[0080] Thus, in one embodiment, transaction layer 805 assembles packet header / payload 806. The format for the current packet header / payload can be found in the PCIe specifications at the PCIe specifications website.

[0081] Quick Reference Figure 9 , an embodiment of a PCIe transaction descriptor is illustrated. In one embodiment, transaction descriptor 900 is a mechanism for carrying transaction information. In this regard, transaction descriptor 900 supports the identification of transactions in the system. Other potential uses include tracking modifications to default transaction ordering and associating transactions with channels.

[0082] Transaction descriptor 900 includes a global identifier field 902, an attribute field 904, and a channel identifier field 906. In the illustrated example, global identifier field 902 is depicted as including a local transaction identifier field 908 and a source identifier field 910. In one embodiment, global transaction identifier 902 is unique for all outstanding requests.

[0083] According to one implementation, the local transaction identifier field 908 is a field generated by the requesting agent and is unique for all outstanding requests that require completion for that requesting agent. Furthermore, in this example, the source identifier 910 uniquely identifies the requester agent within the PCIe hierarchy. Accordingly, together with the source ID 910, the local transaction identifier 908 field provides a global identification of transactions within the hierarchy domain.

[0084] Attribute field 904 specifies the characteristics and relationships of the transaction. In this regard, attribute field 904 is potentially used to provide additional information that allows modification of the default handling of the transaction. In one embodiment, attribute field 904 includes a priority field 912, a reserved field 914, a sort field 916, and a no-listen field 918. Here, priority subfield 912 can be modified by the initiator to assign a priority to the transaction. Reserved attribute field 914 is held reserved for future or vendor-defined use. Reserved attribute fields can be used to implement possible usage models that use priority or security attributes.

[0085] In this example, the ordering attribute field 916 is used to supply optional information that conveys the type of ordering that can modify the default ordering rules. According to one example implementation, an ordering attribute of "0" indicates that the default ordering rules are to be applied, wherein an ordering attribute of "1" indicates relaxed ordering, wherein writes can be delivered in the same direction as writes, and read completions can be delivered in the same direction as writes. The snoop attribute field 918 is used to determine whether the transaction is snooped. As shown, the channel ID field 906 identifies the channel associated with the transaction.

[0086] Link Layer

[0087] Now return to Figure 8 The link layer 810, also known as the data link layer 810, acts as an intermediate level between the transaction layer 805 and the physical layer 820. In one embodiment, the data link layer 810 is responsible for providing a reliable mechanism for exchanging transaction layer packets (TLPs) between the two components of the link. One side of the data link layer 810 accepts the TLPs assembled by the transaction layer 805 and applies a packet sequence identifier 811, i.e., an identification number or packet number, calculates and applies an error detection code, i.e., a CRC 812, and submits the modified TLP to the physical layer 820 for transmission across the physical layer to an external device.

[0088] Physical layer

[0089] In one embodiment, the physical layer 820 includes a logical sub-block 821 and an electrical sub-block 822 to physically transmit packets to external devices. Here, the logical sub-block 821 is responsible for the "digital" functions of the physical layer 821. In this regard, the logical sub-block includes a transmit section that prepares outgoing information for transmission by the physical sub-block 822 and a receiver section that identifies and prepares received information before passing it to the link layer 810.

[0090] Physical block 822 includes a transmitter and a receiver. The transmitter is supplied with symbols by logic sub-block 821, and the transmitter serializes the symbols and transmits them to an external device. The receiver is supplied with serialized symbols from the external device and converts the received signal into a bit stream. The bit stream is deserialized and supplied to logic sub-block 821. In one embodiment, 8b / 10b transmission code is adopted, in which 10-bit symbols are transmitted / received. Here, special symbols are used to form packets through frames 823. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

[0091] As described above, even though the transaction layer 805, link layer 810, and physical layer 820 are discussed with reference to a specific embodiment of the PCIe protocol stack, the layered protocol stack is not so limited. In fact, layered protocols may be included / implemented. As an example, a port / interface represented as a layered protocol includes: (1) a first layer, i.e., a transaction layer, for assembling packets; a second layer, i.e., a link layer, for sequencing packets; and a third layer, i.e., a physical layer, for transmitting packets. As a specific example, the Common Standard Interface (CSI) layered protocol is utilized.

[0092] See next Figure 10 , an embodiment of a PCIe serial point-to-point architecture is illustrated. Although an embodiment of a PCIe serial point-to-point link is illustrated, a serial point-to-point link is not so limited, as it includes any transmission path for transmitting serial data. In the illustrated embodiment, a basic PCIe link includes two low-voltage differential drive signal pairs: transmit pair 1006 / 1011 and receive pair 1012 / 1007. Accordingly, device 1005 includes transmit logic 1006 for transmitting data to device 1010 and receive logic 1007 for receiving data from device 1010. In other words, the PCIe link includes two transmit paths (i.e., paths 1016 and 1017) and two receive paths (i.e., paths 1018 and 1019).

[0093] A transmission path refers to any path for transmitting data, such as a transmission line, copper wire, optical line, wireless communication channel, infrared communication link, or other communication path. A connection between two devices, such as device 1005 and device 1010, is called a link, such as link 415. A link can support one lane—each lane represents a set of differential signal pairs (one pair for transmit and one pair for receive). To scale bandwidth, a link can aggregate multiple lanes, represented as xN, where N is any supported link width, such as 1, 2, 4, 8, 16, 32, 64, or wider.

[0094] A differential pair refers to two transmission paths, such as lines 416 and 417, that carry differential signals. For example, when line 416 switches from a low voltage level to a high voltage level (i.e., a rising edge), line 417 drives from a high logic level to a low logic level (i.e., a falling edge). Differential signals potentially exhibit better electrical characteristics, such as improved signal integrity, i.e., cross-coupling, voltage overshoot / undershoot, and ringing. This allows for better timing windows, which enables faster transmission frequencies.

[0095] Go to Figure 11 A block diagram of an exemplary computer system formed using a processor including execution units that execute instructions is illustrated, wherein one or more interconnected components implement one or more features according to one embodiment of the present disclosure. According to the present disclosure, such as in the embodiments described herein, system 1100 includes components, such as processor 1102, to employ execution units including logic to execute algorithms for process data. System 1100 represents a processing system based on a PENTIUM III™, PENTIUM4™, Xeon™, Itanium, XScale™, and / or StrongARM™ microprocessor available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In one embodiment, sample system 1100 may execute a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used. Thus, embodiments of the present disclosure are not limited to any specific combination of hardware circuitry and software.

[0096] The embodiments are not limited to computer systems. Alternative embodiments of the present disclosure can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications can include microcontrollers, digital signal processors (DSPs), systems on a chip, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0097] In the illustrated embodiment, processor 1102 includes one or more execution units 1108 to implement an algorithm to execute at least one instruction. One embodiment may be described in the context of a single-processor desktop or server system, but alternative embodiments may be included in a multi-processor system. System 1100 is an example of a "hub" system architecture. Computer system 1100 includes processor 1102 to process data signals. As an illustrative example, processor 1102 includes, for example, a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor that implements a combination of instruction sets, or any other processor device such as a digital signal processor. Processor 1102 is coupled to a processor bus 1110, which transmits data signals between processor 1102 and other components in system 1100. The elements of system 1100 (e.g., graphics accelerator 1112, memory controller hub 1116, memory 1120, I / O controller hub 1124, wireless transceiver 1126, flash BIOS 1128, network controller 1134, audio controller 1136, serial expansion port 1138, I / O controller 1140, etc.) perform their conventional functions well known to those skilled in the art.

[0098] In one embodiment, processor 1102 includes a level 1 (L1) internal cache memory 1104. Depending on the architecture, processor 1102 may have a single internal cache or multiple levels of internal cache. Other embodiments include a combination of internal and external caches, depending on the specific implementation and needs. Register file 1106 stores different types of data in various registers, including integer registers, floating-point registers, vector registers, banked registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers.

[0099] Execution unit 1108, which includes logic for performing integer and floating-point operations, also resides in processor 1102. In one embodiment, processor 1102 includes a microcode (ucode) ROM to store microcode, which, when executed, performs algorithms for certain macroinstructions or handles complex scenarios. The microcode is potentially updateable to handle logic errors / fixes for processor 1102. In one embodiment, execution unit 1108 includes logic for processing a packed instruction set 1109. By including a packed instruction set 1109 in the general-purpose processor 1102's instruction set, along with associated circuitry for executing the instructions, operations used by many multimedia applications can be performed in the general-purpose processor 1102 using packed data. Consequently, by using the full width of the processor's data bus to perform operations on packed data, many multimedia applications are executed more efficiently and accelerated. This potentially eliminates the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0100] Alternative embodiments of execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System 1100 includes memory 1120. Memory 1120 may include dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, or other memory devices. Memory 1120 stores instructions and / or data represented by data signals to be executed by processor 1102.

[0101] Note that you can Figure 11Any of the previously mentioned features or aspects of the present disclosure may be utilized on one or more interconnects illustrated in FIG. For example, an on-die interconnect (ODI) not shown for coupling internal elements of processor 1102 implements one or more of the aforementioned aspects of the present disclosure. Alternatively, the present disclosure may be associated with a processor bus 1110 (e.g., Intel Quick Path Interconnect (QPI) or other known high-performance computing interconnect), a high-bandwidth memory path 1118 to memory 1120, a point-to-point link to a graphics accelerator 1112 (e.g., a Peripheral Component Interconnect Express (PCIe)-compatible fabric), a controller hub interconnect 1122, an I / O or other interconnect (e.g., USB, PCI, PCIe) for coupling other illustrated components. Some examples of such components include an audio controller 1136, a firmware hub (Flash BIOS) 1128, a wireless transceiver 1126, a data storage device 1124, a legacy I / O controller 1110 including a user input and keyboard interface 1142, a serial expansion port 1138 such as a Universal Serial Bus (USB), and a network controller 1134. The data storage device 1124 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0102] Now see Figure 12 , which shows a block diagram of a second system 1200 according to an embodiment of the present disclosure. Figure 12 As shown in FIG, multiprocessor system 1200 is a point-to-point interconnect system and includes a first processor 1270 and a second processor 1280 coupled via a point-to-point interconnect 1250. Each of processors 1270 and 1280 may be a certain version of a processor. In one embodiment, processors 1252 and 1254 are part of a serial, point-to-point coherent interconnect fabric, such as Intel's Quick Path Interconnect (QPI) architecture. As a result, the present disclosure may be implemented within the QPI architecture.

[0103] Although shown with only two processors 1270, 1280, it is to be understood that the scope of the present disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

[0104] Processors 1270 and 1280 are shown as including integrated memory controller units 1272 and 1282, respectively. Processor 1270 also includes point-to-point (PP) interfaces 1276 and 1278 as part of its bus controller unit; similarly, second processor 1280 includes PP interfaces 1286 and 1288. Processors 1270, 1280 can exchange information via point-to-point (PP) interface 1250 using PP interface circuits 1278, 1288. Figure 12As shown in FIG, IMCs 1272 and 1282 couple the processors to respective memories, namely, memory 1232 and memory 1234, which may be portions of main memory locally attached to the respective processors.

[0105] Processors 1270, 1280 each exchange information with chipset 1290 via separate PP interfaces 1252, 1254 using point-to-point interface circuits 1276, 1294, 1286, 1298. Chipset 1290 also exchanges information with high-performance graphics circuitry 1238 via graphics interface circuitry 1292 along a high-performance graphics interconnect 1239.

[0106] A shared cache (not shown) may be included in the processor or external to both processors but connected to the processors via the PP interconnect so that if the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0107] Chipset 1290 may be coupled to first bus 1216 via interface 1296. In one embodiment, first bus 1216 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as PCI Express or another third generation I / O interconnect bus, but the scope of the present disclosure is not so limited.

[0108] like Figure 12 As shown in , various I / O devices 1214 may be coupled to first bus 1216, along with a bus bridge 1218 that couples first bus 1216 to a second bus 1220. In one embodiment, second bus 1220 comprises a low pin count (LPC) bus. In one embodiment, various devices are coupled to second bus 1220 including, for example, a keyboard and / or mouse 1222, communication devices 1227, and a storage unit 1228 such as a disk drive or other mass storage device that often includes instructions / code and data 1230. Additionally, audio I / O 1224 is shown coupled to second bus 1220. Note that other architectures are possible that include different components and interconnect architectures. For example, a system may implement a multi-drop bus or other such architecture instead of Figure 12 Point-to-point architecture.

[0109] The present disclosure also shows a set of technical solutions, as follows:

[0110] 1. A processor device, comprising:

[0111] microprocessors, including microprocessor system agents; and

[0112] A field programmable gate array (FPGA), the FPGA comprising:

[0113] an FPGA system agent, configured to process memory access requests received from the microprocessor system agent across a communication link;

[0114] a memory controller communicatively coupled to the system agent;

[0115] A high-speed serial interface is used to link the system agent and the storage system.

[0116] 2. The processor device according to technical solution 1, wherein the communication link is configured to carry protocol semantics for the system agent.

[0117] 3. A processor device according to technical solution 1, wherein the FPGA further includes hardware logic to emulate a root complex compliant with Peripheral Component Interconnect Express (PCIe), the hardware logic emulating the PCIe protocol through one or more hardware operations, and wherein the system agent is configured to process memory access requests across the high-speed serial interface using a protocol compliant with PCIe.

[0118] 4. The processor device according to technical solution 1, wherein the FPGA includes one or more accelerator circuits to perform processing on data transmitted between the microprocessor and the storage system.

[0119] 5. The processor device according to technical solution 4, wherein the one or more accelerator circuits are configured to perform one or more of compression and / or decompression, encryption and / or decryption, structured query language (SQL) acceleration, or extract transform load (ETL) operations.

[0120] 6. The processor device according to technical solution 4, wherein the FPGA further includes a cache agent and a memory cache to cache data for the one or more accelerator circuits.

[0121] 7. A processor device according to technical solution 1, wherein the FPGA includes a directory cache to store a subset of the storage directory within the FPGA.

[0122] 8. A processor device according to technical solution 1, wherein the FPGA includes a cache line to temporarily store data in the FPGA before storing the data in the processor.

[0123] 9. The processor device according to technical solution 1, wherein the FPGA includes a fabric interface for interfacing to a disaggregated storage system supported by a network fabric.

[0124] 10. The processor device of claim 1 , wherein the FPGA includes a non-volatile memory express (NVMe) memory controller to interface with an NVMe controller on a connected storage device across a high-speed serial interface (HSSI).

[0125] 11. A method performed by a hardware element of a processor, the method comprising:

[0126] A system agent implemented in a field programmable gate array (FPGA) receives memory instructions from a hardware processor;

[0127] identifying a memory location managed by the system agent, the memory location portion of a storage device being communicatively coupled to the FPGA;

[0128] executing the memory instruction; and

[0129] Providing confirmation of execution of the memory instruction to the hardware processor.

[0130] 12. The method according to technical solution 11 further includes retrieving the data stored in the memory from the high-speed serial interface.

[0131] 13. The method according to technical solution 12 further includes transmitting data from the FPGA from the memory to the hardware processor across a communication link.

[0132] 14. A method according to technical solution 11, wherein the confirmation of the execution of the memory instruction includes an asynchronous confirmation response.

[0133] 15. The method according to technical solution 14 further comprises:

[0134] retrieving data from the storage device acting as memory;

[0135] transmitting a read response to the hardware processor;

[0136] caching the data in a cache memory; and

[0137] After transmitting the read response to the hardware processor, the data is transmitted from the cache memory to the hardware processor.

[0138] 16. The method according to technical solution 11 further includes caching the data retrieved from the memory location in a cache in the FPGA.

[0139] 17. The method according to technical solution 11 further includes notifying the system agent of the hardware processor of the memory address space managed by the system agent implemented in the FPGA.

[0140] 18. The method according to technical solution 11 further includes performing data processing on one or both of the incoming data to the FPGA or the outgoing data from the FPGA by one or more accelerator circuits.

[0141] 19. The method according to technical solution 18, wherein the data processing includes performing one or more of compression and / or decompression, encryption and / or decryption, structured query language (SQL) acceleration, or extract transform load (ETL) operations.

[0142] 20. The method according to technical solution 11 further comprises:

[0143] receiving, at the FPGA system agent, a memory access request from a system agent associated with the hardware processor;

[0144] determining memory locations of the decomposed memory elements for construction of the memory elements; and

[0145] Based on the determined memory location, the memory access request is processed.

[0146] 21. A system comprising:

[0147] microprocessors, including microprocessor system agents;

[0148] Accelerator system, including:

[0149] a system agent for processing memory access requests received from the microprocessor system agent across a communication link;

[0150] a memory controller communicatively coupled to the system agent; and

[0151] a high-speed serial interface for linking the system agent with a storage system; and

[0152] A storage device is connected to the accelerator system through the high-speed serial interface.

[0153] 22. The system according to technical solution 21, wherein the storage device includes a solid-state drive (SSD) non-volatile memory element.

[0154] 23. The system of claim 21, wherein the accelerator system comprises a fabric interconnect; and

[0155] wherein the storage means comprises a disaggregated storage as memory device comprising a plurality of solid state drive non-volatile memory elements managed by a network fabric coupled to the accelerator system by the fabric interconnect.

[0156] 24. The system according to technical solution 21, wherein the accelerator system includes one or more accelerator circuits to perform processing on data transmitted between the microprocessor and the storage system.

[0157] 25. A system according to technical solution 24, wherein the one or more accelerator circuits are configured to perform one or more of compression and / or decompression, encryption and / or decryption, structured query language (SQL) acceleration, or extract transform load (ETL) operations.

[0158] Example 1 is a processor device including a microprocessor, the microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA includes the FPGA system agent that processes memory access requests received from the microprocessor system agent across a communication link; a memory controller communicatively coupled to the system agent; and a high-speed serial interface that links the system agent with a memory system.

[0159] Example 2 may include the subject matter of Example 1, wherein the communication link complies with a Quick Path Interconnect protocol.

[0160] Example 3 may include the subject matter of Example 1, wherein the FPGA further includes hardware logic to emulate a Peripheral Component Interconnect Express (PCIe) compliant root complex, the hardware logic emulating a PCIe protocol through one or more hardware operations, and wherein the system agent is configured to process memory access requests across the high-speed serial interface using the PCIe compliant protocol.

[0161] Example 4 may include the subject matter of any of Examples 1-3, wherein the FPGA includes one or more accelerator circuits to perform processing on data transferred between the microprocessor and the memory system.

[0162] Example 5 may include the subject matter of Example 4, wherein the one or more accelerator circuits are configured to perform one or more of compression and / or decompression, encryption and / or decryption, structured query language (SQL) acceleration, or extract transform load (ETL) operations.

[0163] Example 6 may include the subject matter of Example 4, wherein the FPGA further comprises a cache agent and a memory cache to cache data for the one or more accelerator circuits.

[0164] Example 7 may include the subject matter of any of Examples 1-6, wherein the FPGA includes a directory cache to store a subset of the storage directory within the FPGA.

[0165] Example 8 may include the subject matter of any of Examples 1-7, wherein the FPGA includes a cache line to cache data stored in the memory device.

[0166] Example 9 may include the subject matter of any of Examples 1-8, wherein the FPGA includes a fabric interface for interfacing to a disaggregated storage system supported by a network fabric.

[0167] Example 10 may include the subject matter of any of Examples 1-9, wherein the FPGA includes a non-volatile memory express (NVMe) memory controller to interface with an NVMe controller on a connected storage device across a high-speed serial interface (HSSI).

[0168] Example 11 is a method performed by a hardware element of a processor, the method comprising receiving, by a system agent implemented in a field programmable gate array (FPGA), a memory instruction from the hardware processor; identifying a memory location managed by the system agent, the memory location portion of a storage device being communicatively coupled to the FPGA; executing the memory instruction; and providing confirmation of execution of the memory instruction to the hardware processor.

[0169] Example 12 may include the subject matter of Example 11, and can also include retrieving data stored in the memory from the high-speed serial interface.

[0170] Example 13 may include the subject matter of Example 12, and can also include transferring data from the FPGA from the memory to the hardware processor across the communication link.

[0171] Example 14 may include the subject matter of Example 11, wherein the confirmation of the memory instruction execution comprises an asynchronous confirmation response.

[0172] Example 15 includes the subject matter of Example 14, and can also include retrieving data from the storage device as memory; transmitting the read response to the hardware processor; caching the data in a cache memory; and after transmitting the read response to the hardware processor, transmitting the data from the cache memory to the hardware processor.

[0173] Example 16 may include the subject matter of Example 11, and can also include caching data retrieved from the memory location in a cache in the FPGA.

[0174] Example 17 may include the subject matter of Example 11, and can also include advertising a memory address space managed by a system agent implemented in an FPGA to a system agent of a hardware processor.

[0175] Example 18 may include the subject matter of Example 11, and can also include performing data processing, by one or more accelerator circuits, on one or both of incoming data to the FPGA or outgoing data from the FPGA.

[0176] Example 19 may include the subject matter of Example 18, wherein the data processing comprises performing one or more of compression and / or decompression, encryption and / or decryption, structured query language (SQL) acceleration, or extract transform load (ETL) operations.

[0177] Example 20 may include the subject matter of Example 11 and may also include receiving, at the FPGA system agent, a memory access request from a system agent associated with the hardware processor; determining a memory location of a decomposed memory element for construction of the memory element; and processing the memory access request based on the determined memory location.

[0178] Example 21 is a system including a microprocessor, the microprocessor including a microprocessor system agent and an accelerator system. The accelerator system includes a system agent to process memory access requests received from the microprocessor system agent across a communication link. The accelerator system also includes a memory controller communicatively coupled to the system agent. The accelerator system also includes a high-speed serial interface to link the system agent with the memory system. The system also includes a memory device connected to the accelerator system via the high-speed serial interface.

[0179] Example 22 may include the subject matter of Example 21, wherein the storage device comprises a solid state drive (SSD) non-volatile memory element.

[0180] Example 23 may include the subject matter of Example 21, wherein the accelerator system includes a fabric interconnect, and wherein the storage device includes a disaggregated storage device as memory, the disaggregated storage device as memory including a plurality of solid-state drive non-volatile memory elements managed by a network fabric, the fabric coupled to the accelerator system by the fabric interconnect.

[0181] Example 24 may include the subject matter of Example 21, wherein the accelerator system includes one or more accelerator circuits to perform processing on data transferred between the microprocessor and the memory system.

[0182] Example 25 may include the subject matter of Example 24, wherein the one or more accelerator circuits are configured to perform one or more of compression and / or decompression, encryption and / or decryption, structured query language (SQL) acceleration, or extract transform load (ETL) operations.

[0183] The foregoing description of one or more implementations provides illustration and description, but is not intended to be exhaustive or to limit the scope of the embodiments to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practice of various embodiments.

Claims

1. A processor device, comprising: microprocessors, including microprocessor home agents; as well as A field programmable gate array, comprising: a field programmable gate array home agent to process a memory access request received from the microprocessor home agent across a communication link, wherein the field programmable gate array home agent and the communication link are in a coherency domain of the microprocessor; a memory controller communicatively coupled to the field programmable gate array home agent; A high-speed serial interface is used to connect the field programmable gate array home agent and the storage system.

2. The processor device of claim 1, wherein the communication link complies with a Quick Path Interconnect protocol.

3. The processor device of claim 1 , wherein the field programmable gate array further comprises hardware logic to emulate a Peripheral Component Interconnect Express (PCI-Express) compliant root complex, the hardware logic emulating a PCI-Express protocol through one or more hardware operations, and wherein the field programmable gate array home agent is configured to process memory access requests across the high-speed serial interface using the PCI-Express protocol. 4 . The processor device of claim 1 , wherein the field programmable gate array includes one or more accelerator circuits to perform processing on data transferred between the microprocessor and the memory system.

5. The processor device of claim 4, wherein the one or more accelerator circuits are configured to perform one or more of compression and / or decompression, encryption and / or decryption, structured query language acceleration, or extract transform load operations. 6 . The processor device of claim 4 , wherein the field programmable gate array further comprises a cache agent and a memory cache to cache data for the one or more accelerator circuits.

7. The processor device of claim 1, wherein the field programmable gate array comprises a directory cache to store a subset of a storage directory within the field programmable gate array.

8. The processor device of claim 1, wherein the field programmable gate array comprises a cache line to cache data stored in a memory device.

9. The processor device of claim 1, wherein the field programmable gate array includes a fabric interface for interfacing to a disaggregated storage system supported by a network fabric.

10. The processor apparatus of claim 1, wherein the field programmable gate array includes a non-volatile memory high-speed memory controller to interface with a non-volatile memory high-speed controller on a connected memory device across a high-speed serial interface.

11. A method performed by a hardware element of a processor, the method comprising: A home agent implemented in a field programmable gate array receives memory instructions from a hardware processor via a coherent interconnect link; identifying a memory location managed by the home agent, the memory location portion of a storage device being communicatively coupled to the field programmable gate array; executing the memory instruction; as well as Providing confirmation of execution of the memory instruction to the hardware processor.

12. The method of claim 11, further comprising retrieving data stored in the memory from a high-speed serial interface.

13. The method of claim 12, further comprising transferring data from the field programmable gate array from the memory to the hardware processor across a communication link.

14. The method of claim 11, wherein the acknowledgment of the memory instruction execution comprises an asynchronous acknowledgment response.

15. The method according to claim 14, further comprising: retrieving data from a storage device acting as a memory; transmitting a read response to the hardware processor; caching the data in a cache memory; as well as After transmitting the read response to the hardware processor, the data is transmitted from the cache memory to the hardware processor.

16. The method of claim 11, further comprising caching data retrieved from the memory location in a cache in the field programmable gate array.

17. The method of claim 11, further comprising advertising to a home agent of the hardware processor a memory address space managed by the home agent implemented in the field programmable gate array.

18. The method of claim 11, further comprising performing data processing by one or more accelerator circuits on one or both of inbound data to the field programmable gate array or outbound data from the field programmable gate array.

19. The method of claim 18, wherein the data processing comprises performing one or more of compression and / or decompression, encryption and / or decryption, structured query language acceleration, or extract-transform-load operations.

20. The method of claim 11, further comprising: receiving, at the field programmable gate array home agent, a memory access request from a home agent associated with the hardware processor; determining memory locations of the exploded memory elements for configuration of the memory elements; as well as Based on the determined memory location, the memory access request is processed.

21. A processor system comprising: microprocessors, including microprocessor home agents; A field programmable gate array, comprising: a field programmable gate array home agent to process a memory access request received from the microprocessor home agent across a communication link, wherein the field programmable gate array home agent and the communication link are in a coherency domain of the microprocessor; a memory controller communicatively coupled to the field programmable gate array home agent; and a high-speed serial interface for linking the FPGA home agent with a storage system; and A storage device is connected to the field programmable gate array through the high-speed serial interface.

22. The system of claim 21, wherein the storage device comprises a solid state drive non-volatile memory element.

23. The system of claim 21, wherein the field programmable gate array includes a fabric interconnect; and wherein the storage means comprises a disaggregated storage device as memory comprising a plurality of solid state drive non-volatile memory elements managed by a network fabric coupled to the field programmable gate array by the fabric interconnect.

24. The system of claim 21, wherein the field programmable gate array includes one or more accelerator circuits to perform processing on data transferred between the microprocessor and the memory system.

25. The system of claim 24, wherein the one or more accelerator circuits are configured to perform one or more of compression and / or decompression, encryption and / or decryption, structured query language acceleration, or extract transform load operations.

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