Flash memory on-chip network architecture based on multi-path reservation
By adopting a multi-path pre-determined flash memory on-chip network architecture in solid-state drives, using 2D-Mesh topology and multi-path pre-determined routing algorithms, the problem of SSD channel conflict is solved, and higher path diversity and performance improvement is achieved, especially The performance of SSD is significantly improved under fine-grained read loads.
Patent Information
- Application Number
- CN202411401081.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-01-07
AI Technical Summary
Existing solid-state drives (SSDs) have channel conflicts that lead to performance bottlenecks when handling large numbers of random IO requests, and the existing technology increases the number of channels or uses 2D-Mesh topology but is costly and performs poorly under fine-grained read loads.
Using a flash memory on-chip network architecture based on multi-path reservation, path reservation is performed before data transmission through 2D-Mesh topology and multi-path reservation routing algorithm, and using the strategy of separation between router chips and flash chips, reduce path conflicts and optimize path reservation success Rate.
It effectively reduces the number of path conflicts and the overall transmission time of fine-grained reading, improves the path predetermined success rate and performance, especially significantly improves the performance of SSD under dense fine-grained reading loads.
Smart Images
Figure CN119271145A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of solid state hard disks, and in particular to a flash memory chip network architecture based on multi-path reservation. Background Art
[0002] To meet the growing demands of modern data-intensive applications, the performance and capacity of solid-state drives (SSDs) continue to improve. However, communication within the SSD (i.e., communication between the SSD controller and the NAND flash chips) remains a key performance bottleneck for many applications, especially workloads with a large number of random IO requests. SSDs use a multi-channel shared bus architecture, with multiple flash chips sharing the same path, which may result in multiple IO requests accessing the NAND flash chips on the same channel. These IO requests are transmitted serially on the same channel, greatly limiting the parallelism of the SSD. Therefore, handling path conflicts properly is key to improving SSD parallelism and performance.
[0003] SSD vendors mainly reduce path conflicts by increasing the number of channels in the SSD. However, this is not a scalable solution because increasing the number of channels makes the SSD controller more complex, for example, the SSD controller requires more IO pins to serve more parallel channels, thus increasing the overall cost of the SSD.
[0004] At present, the existing technology solves the path conflict problem by increasing the bandwidth of each SSD channel and adding vertical channels based on the traditional bus topology. However, this technology requires relatively large modifications to the SSD, is expensive to implement, and does not make good use of path diversity during data transmission.
[0005] Another technology increases path diversity by using a 2D-Mesh topology, and alleviates the path conflict problem by pre-registering paths and using a non-minimal fully adaptive routing algorithm. However, the reservation success rate of the routing algorithm used in this technology needs to be improved, and when path reservation fails, it is necessary to wait for the busy path to be released before re-reserving, and the time overhead of path reservation failure is comparable to the path conflict problem in traditional bus-type SSDs. In addition, the performance of this technology will significantly decrease under loads with a large number of fine-grained reads (such as the size of an embedded vector of 128B), because the design does not take into account the significant impact of the number of hops on the path reservation time, which results in the path reservation time being comparable to the data transmission time, seriously affecting the performance under fine-grained read loads.
[0006] Therefore, there is an urgent need for a mechanism to expand the traditional topology structure, reduce path conflicts through a path reservation mechanism, and improve the performance of SSDs under intensive and fine-grained read loads. Summary of the invention
[0007] The purpose of the present invention is to provide a flash memory chip network architecture based on multi-path reservation, which performs multi-path reservation before data transmission, reduces the number of data transmission path conflicts, reduces the overall transmission time of fine-grained reads, and improves the path reservation success rate.
[0008] To achieve the above-mentioned object, the present invention provides a flash memory chip network architecture based on multi-path reservation, including building modules as nodes, and each node is connected by a two-dimensional grid topology structure; based on a multi-path reservation routing algorithm, the building modules are used to allocate a flash memory controller to each IO request in the queue, and path reservation is performed until all IO requests are completed and the reserved path is released; The building module is composed of a flash memory chip and a router chip. The flash memory chip in each building module communicates with the router chip through an injection and ejection port, and the router chips between the building modules are connected through a bidirectional link.
[0009] Preferably, path reservation includes identifying and reserving the path by sending a scout packet, and determining, based on a pattern of the scout packet, a behavior of a routing chip on the target building module after receiving the scout packet.
[0010] Preferably, the modes of the scout packet include a retain mode and a cancel mode: When the mode of the reconnaissance packet is the reservation mode, the router chip calculates the sending port of the reconnaissance packet through the multi-path reservation routing algorithm, and records the code, entry port and sending port of the reconnaissance packet in the path reservation table of the routing chip; When the mode of the scout packet is the cancel mode, the path reservation of the scout packet fails, the table entry is deleted from the path reservation table, and the previous building module is traced back according to the information in the path reservation table.
[0011] Preferably, reserving a conflict-free path for each IO request in the queue includes checking the flash controllers in order from small to large according to the distance between the target building module and the flash controller, allocating a flash controller for a given IO request, and sending a reconnaissance packet to the target building module through the flash controller.
[0012] Preferably, the multi-path reservation routing algorithm comprises: Get the number N of idle flash controllers in the flash on-chip network architecture; Take N requests in the request queue in order and obtain the data transmission size of the corresponding requests, and divide the N requests into a first priority queue and a second priority queue according to the data volume threshold M; According to the horizontal distance between the target building block and the flash controller, the flash controller is allocated to the requests of the first priority queue and the second priority queue in turn until all the requests complete the path reservation.
[0013] Therefore, the present invention adopts the above-mentioned flash memory chip network architecture based on multi-path reservation, which has the following technical effects: (1) The 2D-Mesh topology structure effectively enriches the path diversity of data transmission. The strategy of separating the routing chip from the flash chip avoids additional processing of the flash chip and makes full use of the path diversity to identify and reserve conflict-free paths for IO requests.
[0014] (2) The path reservation technology is used to fundamentally solve the problem of path conflicts. In addition, a multi-path reservation routing algorithm is used to give priority to reducing the number of path reservation hops for fine-grained requests, effectively reducing the total path reservation time and improving the problem of poor performance of existing technologies under loads dominated by fine-grained requests.
[0015] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 Schematic diagram of MrNode structure in the embodiment; Figure 2 Schematic diagram of the overall architecture of MRSSD in the embodiment; Figure 3 1 is a schematic diagram showing the structure of a reconnaissance package in an embodiment; Figure 4 is a schematic diagram of allocating a flash memory controller in an embodiment; Figure 5 is a flow chart of the existing routing algorithm allocation path in the embodiment; Figure 6 4 is a flow chart of the multi-path routing algorithm allocating paths in the embodiment.
[0017] Reference numerals
[0018] 1. Building blocks; 2. Flash memory chip; 3. IO data pins; 4. Bidirectional link connection; 5. Router chip; 6. Flash memory controller; 7. Header flit; 8. Tail flit. DETAILED DESCRIPTION
[0019] The present invention can be explained in more detail by the following examples. The purpose of disclosing the present invention is to protect all changes and improvements within the scope of the present invention. The present invention is not limited to the following examples.
[0020] A fundamental problem of path conflict is that there are few paths for data transmission. The lack of transmission paths leads to a high probability that the transmission paths will be repeated, resulting in path conflicts. Therefore, in order to solve the path conflict problem, more paths need to be introduced. Based on this, this embodiment adopts a two-dimensional grid topology structure to provide rich path diversity. Another problem is cost. Some existing technologies do improve path diversity, but they introduce high costs.
[0021] To this end, this embodiment provides a flash memory chip network architecture MRSSD based on multi-path reservation. The key design decision of this architecture with low cost is to separate the router from the flash memory chip, so that there is no need to modify the flash memory chip to avoid incurring additional expenses. Figure 1 As shown, MRSSD uses a new building block 1 (MrNode), which consists of a flash memory chip 2 and an independent router chip 5. In each MrNode, the flash memory chip uses its IO data pin 3 (i.e., the injection ejection port) to communicate with the router chip. In this embodiment, in MRSSD, MrNode is used as a node, and MrNodes are connected using a two-dimensional grid topology structure, i.e., a low-cost network interconnection technology. In addition, the router chip in each MrNode is connected to the router chip in the adjacent MrNode via a bidirectional link 4, as shown in FIG. Figure 2 shown.
[0022] On the other hand, in order to solve the frequent path conflict problem in the flash memory, this embodiment adopts the path reservation technology, that is, before the data starts to be transmitted, MrNode will reserve a non-conflicting path for each IO request, and this path can only be used for this IO request, and will not release this reserved path until the request is completed. Since the path has been determined before the data is transmitted, there will be no path conflict problem. More importantly, the MRSSD using the path reservation technology does not need to use a large cache area in the router chip, which further reduces the MRSSD overhead.
[0023] The entire process of route reservation is as follows: MRSSD identifies and reserves paths by sending a special packet called a reconnaissance packet, such as Figure 3As shown. Assume that the current MRSSD has 8 flash controllers 6 and 64 flash chips 2. At this time, the reconnaissance packet consists of two 8-bit flits, namely the head flit 7 and the tail flit 8. The most significant bit (first significant bit) of the two flits is used to indicate the type of the flit. Since there are only two types, 1 bit can be used to represent it; the second most significant bit (second significant bit) indicates the mode of the current reconnaissance packet. There are two modes, namely the reserve mode and the cancel mode. The type of mode will determine the behavior of the router chip after receiving the reconnaissance packet. If it is the reserve mode, the router chip 5 will use the routing algorithm to calculate which port the reconnaissance packet will be sent from, and record the ID, entry port and sending port of the reconnaissance packet in the path reservation table of the router chip; if it is the cancel mode, it means that the last reconnaissance packet path reservation failed, and the table entry of the reconnaissance packet will be deleted from the path reservation table, and the information in the path reservation table will be used to trace back to the previous MrNode. The target MrNode ID is stored in the last six bits of the head flit 7, because six bits can represent 64 MrNodes; in the tail flit, the source flash controller ID is used to store the flash controller ID responsible for this transmission.
[0024] For a given IO request, MRSSD will first check whether the nearest flash controller of the target MrNode is available. If the nearest flash controller is available, MRSSD will select this flash controller to process the IO request. If the nearest flash controller is not available, it will search in order until an available flash controller is found. After that, the found flash controller is used as the source flash controller, and the reconnaissance packet is sent to the target MrNode through the Reserve mode. The process is as follows: First, the router chip prioritizes the reconnaissance packet to try the two ports closest to the target MrNode path. If the two closest ports are occupied, it will try the other two ports in the opposite direction of the target MrNode path. When the four ports of the router chip cannot find an available port, the upstream router chip of this request is searched according to the path reservation table of the router chip, and the reconnaissance packet is changed to Cancel mode and sent to the previous router chip. When the router chip receives the reconnaissance packet in Cancel mode, it deletes the relevant information in the path reservation table and continues to try other ports that have not been tried in sequence. Repeat the above process. If the reconnaissance packet reaches the target MrNode in Reserve mode, the path reservation is successful, and a response message is sent to the source flash memory controller to prepare for data transmission; if the reconnaissance packet traces back to the source flash memory controller in Cancel mode, it means that the path reservation has failed, and the path reservation will be retried immediately, and a new reconnaissance message will be sent.
[0025] Because the routing algorithms in the prior art either fail to utilize path diversity or cause the number of hops to be too large when reserving a path, the time taken for path reservation is relatively long when the data transmission volume is small, which seriously affects the performance of the system. In addition, the existing routing algorithms consider read and write requests separately, which results in the reserved path being only a local optimum. When the data transmission volume is small, the number of hops for this request will be an important factor affecting the entire IO request. Based on this, the multi-path reservation routing algorithm adopted in this implementation will give priority to reducing the number of hops for fine-grained data transmission, as follows: First, the number N of idle flash controllers in the MRSSD at this time is obtained, where N is the number of paths reserved this time. At the same time, a data volume threshold M is maintained in the system.
[0026] Afterwards, MRSSD retrieves N requests from the request queue in order and obtains the corresponding request sizes, adds requests with data transfer sizes smaller than M to the maintained first priority queue, and puts the remaining requests into the second priority queue.
[0027] Then, the path reservation is performed for the requests in the first priority queue. The important factor affecting the total number of hops in the path reservation is the order in which the flash controllers are assigned to the requests. The process of MRSSD assigning flash controllers is as follows: Figure 4 As shown in the figure, MRSSD will assign priorities to requests in the queue according to the horizontal distance from the controller. The closer the horizontal distance to the flash controller, the higher the priority will be. The nearest flash controller will be assigned to high-priority requests first. Follow this process until all request paths in the first priority queue are assigned, and then process the requests in the second priority queue in order. Among them, giving priority to assigning flash controllers to requests that are closer to the flash controller will better avoid path conflicts and reduce the total number of hops in the scheduled path.
[0028] In addition, to verify the effectiveness of MRSSD in this embodiment, a comparative analysis is also conducted with the existing path reservation, such as Figure 5 and Figure 6 As shown, it can be seen that the total number of hops in the previous solution is 19, while after adopting the multi-path scheduled routing algorithm proposed by MRSSD, the total number of hops is only 15.
[0029] Therefore, the present invention adopts the above-mentioned flash memory chip network architecture based on multi-path reservation, which effectively enriches the path diversity of data transmission and avoids additional processing of the flash memory chip. At the same time, it adopts path reservation technology to fundamentally solve the problem of path conflict.
[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.
Claims
1. A flash memory chip network architecture based on multi-path reservation, characterized in that: The method includes using building modules as nodes, and connecting each node with a two-dimensional grid topology structure; using the building modules to allocate a flash controller to each IO request in the queue based on a multi-path scheduled routing algorithm, and performing path reservation until all IO requests are completed and the reserved path is released; The building module is composed of a flash memory chip and a router chip. The flash memory chip in each building module communicates with the router chip through an injection and ejection port, and the router chips between the building modules are connected through a bidirectional link.
2. A flash memory chip network architecture based on multi-path reservation according to claim 1, characterized in that: Path reservation includes identifying and reserving a path by sending a scout packet, and determining the behavior of the routing chip on the target building block after receiving the scout packet based on the pattern of the scout packet.
3. A flash memory chip network architecture based on multi-path reservation according to claim 2, characterized in that: The modes of reconnaissance packets include retain mode and cancel mode: When the mode of the reconnaissance packet is the reservation mode, the router chip calculates the sending port of the reconnaissance packet through the multi-path reservation routing algorithm, and records the ID, entry port and sending port of the reconnaissance packet in the path reservation table of the routing chip; When the mode of the scout packet is the cancel mode, the path reservation of the scout packet fails, the table entry is deleted from the path reservation table, and the previous building module is traced back according to the information in the path reservation table.
4. The flash memory chip network architecture based on multi-path reservation according to claim 1, characterized in that: Reserving a conflict-free path for each IO request in the queue includes checking the flash controllers in order from the smallest to the largest distance between the target building block and the flash controller, allocating a flash controller for a given IO request, and sending a reconnaissance packet to the target building block through the flash controller.
5. The flash memory chip network architecture based on multi-path reservation according to claim 1, characterized in that: Multipath reservation routing algorithm, including: Get the number N of idle flash controllers in the flash on-chip network architecture; Take N requests in the request queue in order and obtain the data transmission size of the corresponding requests, and divide the N requests into a first priority queue and a second priority queue according to the data volume threshold M; According to the horizontal distance between the target building block and the flash controller, the flash controller is allocated to the requests of the first priority queue and the second priority queue in turn until all the requests complete the path reservation.