A joint test workgroup microcode update module, method and system

Abstract

The present invention discloses a joint test workgroup microcode update module, method and system. The joint test workgroup microcode update module includes a JTAG interface, a buffer and drive unit, a security and protection unit, a test access port controller, an instruction register, a data register and a microcode interface logic unit; external microcode data is loaded through the JTAG interface, and the buffer and drive unit performs signal enhancement processing on the output signal of the JTAG interface; the security and protection unit receives and verifies the security and correctness of the microcode data loaded through the JTAG interface, and controls the further transmission of the verified microcode data and intercepts the microcode data that fails the verification; the test access port controller is electrically connected to the instruction register and the data register respectively to control the transmission of data and instructions; and the microcode interface logic unit transmits the microcode data to the system interface unit. The present invention can safely and reliably update the external microcode to the processor system.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a joint test working group microcode update module, method and system. Background Art

[0002] A conventional processor distributes, calculates and processes various information through a core inside the processor and various levels of cache, a control unit and an interface electrically connected / coupled to the core.

[0003] Microcode is a series of relatively simple instructions that are decomposed when executing some complex instructions under the CISC structure. The role of microcode is to separate machine instructions from related circuit implementations, so that machine instructions can be designed and modified more freely without considering the actual circuit architecture. Microcode is usually written by CPU engineers during design and stored in read-only memory (ROM) or programmable logic array (PLA). Microcode is also stored in static random access memory (SRAM) or flash memory. For ordinary programmers or assembler programmers, microcode is invisible and cannot be modified.

[0004] The function of the processor can be changed by updating the microcode, or the error of the processor can be corrected by updating the microcode. For updating or patching the microcode routine in the core of the processor, data and programs can generally be input into the core of the processor through the network. In the prior art, upgrading the microcode means that the manufacturer sends a data update package (referred to as the update package) of the microcode change to the customer according to the specific device requirements, and the customer upgrades the microcode of the device according to these data update packages. When users need to perform batch upgrades on the devices in use, they often choose to set the microcode version based on experience, and upgrade different devices to the set version uniformly. However, the method of inputting data or programs in a network connection also relatively increases the risk of the processor being maliciously invaded or loaded with backdoor programs.

[0005] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0006] The object of the present invention is to provide a joint test workgroup microcode update module, method and system, which can safely and reliably update external microcode to a processor system.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A joint test workgroup microcode update module is used to load microcode data outside a processor system into a core of the processor system, the processor system is configured with a system interface unit electrically connected to the core, and the joint test workgroup microcode update module is electrically connected to the system interface unit;

[0009] The joint test working group microcode update module includes a JTAG interface, a buffer and drive unit, a security and protection unit, a test access port controller, an instruction register, a data register and a microcode interface logic unit;

[0010] The JTAG interface is configured to be electrically connected to a JTAG connector of a storage device, the storage device is configured to store microcode data, and the JTAG interface is configured to load the microcode data stored in the storage device into the joint test working group microcode update module;

[0011] The buffer and drive unit is electrically connected to the JTAG interface, and the buffer and drive unit is configured to perform signal enhancement processing on an output signal of the JTAG interface;

[0012] The security and protection unit is configured to receive and verify the security and correctness of the microcode data loaded through the JTAG interface, and control the further transmission of the verified microcode data and intercept the microcode data that fails the verification;

[0013] The input end of the test access port controller is electrically connected to the output end of the security and protection unit, and the output end of the test access port controller is electrically connected to the instruction register and the data register respectively;

[0014] The microcode interface logic unit is electrically connected to the output end of the instruction register and the output end of the data register respectively, and the microcode interface logic unit is configured to transmit the microcode data to the system interface unit.

[0015] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the security and protection unit includes an encryptor, a comparison logic, a control logic and a reference memory;

[0016] Wherein, the reference memory has a plurality of reference encrypted values ​​pre-stored therein;

[0017] The encryptor is configured to generate a corresponding first encrypted value for the microcode data;

[0018] The comparison logic is configured to compare the first encrypted value with the reference encrypted value to obtain a comparison result, and transmit the comparison result to the control logic, wherein the comparison result includes consistency and inconsistency;

[0019] If the comparison result is consistent, the control logic is configured to control the further transmission of the microcode data; if the comparison result is inconsistent, the control logic is configured to intercept the microcode data.

[0020] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, if the comparison result is consistent, the security and correctness verification of the microcode data loaded through the JTAG interface is passed; if the comparison result is inconsistent, the security and correctness verification of the microcode data loaded through the JTAG interface fails.

[0021] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the comparison logic is configured to compare the first encrypted value with the reference encrypted value to obtain a comparison result, including:

[0022] The first encrypted value is compared with the multiple reference encrypted values ​​one by one. If the first encrypted value is the same as any one of the reference encrypted values, the comparison result is consistent; if the first encrypted value is different from any one of the reference encrypted values, the comparison result is inconsistent.

[0023] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the processor system includes multiple cores, and the reference encryption value has a corresponding relationship with the core;

[0024] The comparison logic is configured to compare the first encrypted value with the reference encrypted value to obtain a comparison result, including:

[0025] Determine that the core into which the microcode data is targeted is a target core, wherein the target core is one of the plurality of cores;

[0026] According to the correspondence between the reference encrypted value and the core, determine a reference encrypted value having a corresponding relationship with the target core as a target reference encrypted value;

[0027] The first encrypted value is compared with the target reference encrypted value. If the first encrypted value is the same as the target reference encrypted value, the comparison result is consistent; if the first encrypted value is different from the target reference encrypted value, the comparison result is inconsistent.

[0028] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the encryptor adopts a hash calculator, and the hash calculator is configured to generate a corresponding first hash value for the microcode data, the first hash value is configured as the first encryption value, and the reference encryption value is a pre-stored reference hash value.

[0029] Further, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further comprises a core selection unit, which is arranged between the buffer and drive unit and the safety and protection unit, and is electrically connected to the buffer and drive unit and the safety and protection unit respectively;

[0030] The core selection unit is configured to determine a target core microcode unit into which the microcode data is expected to be loaded according to an output signal of the buffer and drive unit, wherein the target core microcode unit is one of the core microcode units corresponding to each core.

[0031] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, it also includes a level converter, which is arranged between the core selection unit and the safety and protection unit, and is electrically connected to the core selection unit and the safety and protection unit respectively;

[0032] The level converter is configured to receive the JTAG signal output by the core selection unit and control the level of the JTAG signal to match the working level of the target core microcode unit.

[0033] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the processor system further includes a peripheral controller, and the peripheral controller is electrically connected to the system interface unit;

[0034] The joint test working group microcode update module is also configured to load external microcode data into the peripheral controller through the system interface unit. The peripheral controller also has a corresponding core. Loading external microcode data into the peripheral controller means loading it into the core of the peripheral controller.

[0035] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the test access port controller includes a state machine whose state transition is controlled by a mode selection pin (Test Mode Select, TMS), and the state machine is configured to control JTAG operations, including inputting corresponding data into the data register according to the microcode data, and inputting corresponding instructions into the instruction register;

[0036] The data register is configured to transmit the microcode data;

[0037] The instruction register is configured to receive and store JTAG instructions.

[0038] According to another aspect of the present invention, a joint test workgroup microcode update method is provided, which uses the joint test workgroup microcode update module as described in any one of the above technical solutions or a combination of multiple technical solutions to update external microcode data into the core of the processor system.

[0039] According to another aspect of the present invention, the present invention provides a processor system, comprising one or more cores, a system interface unit, and a joint test workgroup microcode update module as described in any one of the above technical solutions or a combination of multiple technical solutions, wherein each of the cores is electrically connected to the system interface unit;

[0040] The joint test workgroup microcode update module is electrically connected to the system interface unit, and the joint test workgroup microcode update module is configured to load microcode data outside the processor system into one or more of the multiple cores through the system interface unit.

[0041] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, it also includes a peripheral controller, and the peripheral controller is electrically connected to the system interface unit;

[0042] The joint test working group microcode update module is configured to load microcode data outside the processor system into one or more of the plurality of peripheral controllers through the system interface unit.

[0043] According to another aspect of the present invention, the present invention provides a computer system, comprising a joint test working group microcode update module as described in any one of the above technical solutions or a combination of multiple technical solutions.

[0044] The beneficial effects brought by the technical solution provided by the present invention are as follows:

[0045] a. The joint test working group microcode update module provided by the present invention can transmit external microcode data to the core of the processor by means of a proximal physical connection, and can verify and protect the microcode data through a security and protection unit, thereby reducing the risk of malicious intrusion and loading of backdoor programs on the processor, and can safely and reliably update the external microcode to the processor system;

[0046] b. The present invention utilizes the encryption form and comparison verification provided by the security and protection unit to further enhance the effect of preventing malicious modification of the processor core, and provides two verification methods: one-to-one comparison and layer-by-layer comparison. Among them, the one-to-one comparison verification method is easy to implement and is suitable for a processor system with a single core or a small number of cores. The layer-by-layer comparison verification method can improve the verification efficiency for a processor system with a large number of cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 A schematic diagram of the architecture of a JTAG microcode update module provided for an exemplary embodiment of the present invention;

[0049] Figure 2 A schematic diagram of the connection between a processor and a JTAG microcode update module provided for an exemplary embodiment of the present invention;

[0050] Figure 3 A schematic diagram of the architecture of a processor system provided for an exemplary embodiment of the present invention;

[0051] Figure 4 A schematic diagram of the core architecture provided for an exemplary embodiment of the present invention;

[0052] Figure 5 A schematic diagram of the architecture of a safety and protection unit provided for an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0054] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0055] In one embodiment of the present invention, a Joint Test Group (JTAG) microcode update module is provided, which is used to load microcode data outside a processor system into a core of the processor system, the processor system is configured with a system interface unit electrically connected to the core, and the Joint Test Group microcode update module is electrically connected to the system interface unit;

[0056] See also Figure 1 and Figure 2 , the joint test working group microcode update module includes a JTAG interface, a buffer and drive unit, a security and protection unit, a test access port controller, an instruction register, a data register and a microcode interface logic unit;

[0057] The JTAG interface is configured to be electrically connected to a JTAG connector of a storage device, the storage device is configured to store microcode data, and the JTAG interface is configured to load the microcode data stored in the storage device into the joint test working group microcode update module;

[0058] The buffer and drive unit is electrically connected to the JTAG interface, and the buffer and drive unit is configured to perform signal enhancement processing on the output signal of the JTAG interface to prevent / offset signal attenuation;

[0059] The security and protection unit is configured to receive and verify the security and correctness of the microcode data loaded through the JTAG interface, and control the further transmission of the verified microcode data and intercept the microcode data that fails the verification;

[0060] The input end of the test access port controller is electrically connected to the output end of the security and protection unit, and the output end of the test access port controller is electrically connected to the instruction register and the data register respectively;

[0061] The microcode interface logic unit is electrically connected to the output end of the instruction register and the output end of the data register respectively, and the microcode interface logic unit is configured to transmit the microcode data to the system interface unit.

[0062] In one embodiment of the present invention, the architecture of the processor system to which the joint test working group microcode update module is applicable is as follows: Figure 3 As shown, the processor system includes at least one core, and a core microcode unit is configured inside the core, and the core microcode unit is used to store the microcode data of the core. Generally speaking, the core is directly or indirectly coupled to a system memory, and the core can be configured to execute instructions that can be stored in the system memory. The definition of the instructions can be based on a specific instruction set architecture. For example, the core can be configured as a version of the x86 ISA (instruction set architecture), so the core is configured to independently execute instructions defined by the instruction set architecture. In other specific embodiments, the core can be a combination of different ISA versions or several ISAs.

[0063] like Figure 3 As shown, the core of the processor system is used to electrically connect / couple the system interface unit; the memory and peripheral controller and the third-level cache (L3 cache) are electrically connected / coupled to the system interface unit 14, wherein the memory and peripheral controller can be electrically connected / coupled to a peripheral device. In the processor system, the core can be configured with a first-level cache (L1 cache) and a second-level cache (L2 cache), and the electrical connection / coupling includes but is not limited to connection using appropriate metal conductors.

[0064] The core of the processor system has a core microcode unit that supports microcoded operations. Generally speaking, microcode can include an implementation technology derived from the processor system control and data storage and given individual operations performed by the core 12. For example, the core of the x86 ISA version can include the execution of instructions, as well as reset functions, interrupt / trap / exception functions, etc.

[0065] Second, some instructions in the ISA can be mapped directly to individual corresponding operations. In some embodiments, microcode can be used to convert a given complex instruction into a sequence of simpler operations that can be dispatched for execution, so that the operations that can be used by the microcode include operations that correspond to directly executable ISA instructions. However, in some embodiments, microcode operations can also include operations that can be performed by the execution unit but are invisible to the programmer.

[0066] Additionally, microcode may be used to include a sequence of operations that put the core in a consistent operating state after a software or hardware reset event, for example, by initializing caches, storing specific values ​​in specific architectural and non-architectural registers, causing instruction fetches to begin at a predetermined address, etc. Microcode may also be used to implement hardware testing or debugging routines for use during product manufacturing, field analysis, power-on self-test, or for other suitable applications.

[0067] In one embodiment of the present invention, the architecture of the core is as follows Figure 4 As shown, it includes a cache module, an instruction decoding unit, a cluster (integer execution cluster), a floating point unit (floating point unit), a core interface unit, a first-level cache and a second-level cache. Among them, the cache module is electrically connected / coupled to the instruction decoding unit. The instruction decoding unit is electrically connected / coupled to at least one cluster and a floating point unit. The core interface unit is electrically connected / coupled to the cluster and the floating point unit. In addition, the core interface unit is electrically connected / coupled to a first-level cache and a second-level cache to meet different storage speed requirements. The core interface unit is electrically connected / coupled to the system interface unit.

[0068] The cache module may include an instruction cache and be coupled to provide instructions to an instruction fetch unit. The designated fetch unit may be coupled to a branch prediction unit, wherein the instruction cache unit of the cache module may be electrically connected / coupled to the instruction decoding unit.

[0069] The instruction decoding unit may provide a plurality of operations to the cluster and the floating point operation unit. The cluster may include a coupled cluster scheduler and an execution unit. The floating point operation unit may include a coupled floating point scheduler and a floating point execution unit.

[0070] Based on the above-mentioned processor system, the joint test working group microcode update module is not only used to update the core microcode unit in the core, but is also configured to load external microcode data into the peripheral controller through the system interface unit to update the microcode data in the peripheral controller.

[0071] like Figure 1 and Figure 2As shown, the JTAG microcode update module is used to receive external data and programs. In particular, the JTAG microcode update module can receive external microcoded data and programs and transmit them to the core through the system interface unit.

[0072] In one embodiment of the present invention, Figure 1 As shown, the JTAG microcode update module also includes a core selection unit and a level converter. The core selection unit is arranged between the buffer and drive unit and the security and protection unit, and is electrically connected to the buffer and drive unit and the security and protection unit respectively. The core selection unit is configured to determine the target core microcode unit into which the microcode data is expected to be loaded according to the output signal of the buffer and drive unit, and the target core microcode unit is one of the core microcode units corresponding to each core. It should be noted that when there is only one core, the core selection unit may not be configured, and the core selection unit may also be set to be inactive or the core selection unit may be set to always select the core microcode unit corresponding to the only core of the processor system as the target core microcode unit.

[0073] The level converter is arranged between the core selection unit and the security and protection unit, and is electrically connected to the core selection unit and the security and protection unit respectively. The level converter is used to perform level conversion when the level of the JTAG signal received and output from the core selection unit does not match the designated core microcode unit. Specifically, the level converter is configured to receive the JTAG signal output by the core selection unit, and control the level of the JTAG signal to match the working level of the target core microcode unit.

[0074] The test access port controller includes a state machine whose state transition is controlled by TMS, and the state machine is configured to control JTAG operations, including inputting corresponding data into the data register according to the microcode data, and inputting corresponding instructions into the instruction register; the data register is configured to transmit the microcode data; and the instruction register is configured to receive and store JTAG instructions.

[0075] In one embodiment of the present invention, see Figure 5 , the security and protection unit includes an encryptor, a comparison logic, a control logic and a reference memory. The reference memory is pre-stored with a plurality of reference encryption values; the encryptor is configured to generate a corresponding first encryption value for the microcode data; the comparison logic is configured to compare the first encryption value with the reference encryption value to obtain a comparison result, and transmit the comparison result to the control logic, wherein the comparison result includes consistency and inconsistency.

[0076] Preferably, the encryptor adopts a hash calculator, and the hash calculator is configured to generate a corresponding first hash value for the microcode data, the first hash value is configured as the first encryption value, and the reference encryption value is a pre-stored reference hash value.

[0077] The present invention provides two methods for comparing the first hash value with the reference hash value:

[0078] The first method is to compare the first hash value with the multiple reference hash values ​​one by one without distinguishing the number and classification of cores of the processor system. If the first hash value is the same as any of the reference hash values, the comparison result is consistent; if the first hash value is different from any of the reference hash values, the comparison result is inconsistent. This method is easy to implement and is more suitable for single-core processor systems or processor systems with a small number of cores.

[0079] The second method is to compare layer by layer, first matching the corresponding core and then comparing the first hash value with the reference hash value corresponding to the matching core. This method is suitable for a processor system including multiple cores, and the reference hash value is pre-configured to have a corresponding relationship with the core.

[0080] In the method, the comparison logic is configured to compare the first hash value with the reference hash value to obtain a comparison result, including:

[0081] Determine that the core into which the microcode data is targeted is a target core, wherein the target core is one of the plurality of cores;

[0082] Determine, according to the correspondence between the reference hash value and the core, a reference hash value having a correspondence with the target core as a target reference hash value;

[0083] The first Hash value is compared with the target reference Hash value. If the first Hash value is the same as the target reference Hash value, the comparison result is consistent; if the first Hash value is different from the target reference Hash value, the comparison result is inconsistent.

[0084] If the comparison result is consistent, the security and correctness verification of the microcode data loaded through the JTAG interface is passed, and the control logic is configured to control the further transmission of the microcode data.

[0085] If the comparison result is inconsistent, the security and correctness verification of the microcode data loaded through the JTAG interface fails, and the control logic is configured to intercept the microcode data.

[0086] In actual applications, the external microcode data is preloaded into a storage device, and then the external microcode is input into the processor from the storage device. Specifically, the storage device has a JTAG connector, or can be connected to a connection line with a JTAG connector, and then the JTAG connector and the JTAG interface are connected to each other, so that the external microcode can be input into the processor, thus eliminating the use of a network connection to transmit the microcode. In addition, in order to facilitate the connection between the JTAG connector and the JTAG interface, the JTAG interface can be designed to extend to the surface of the device having the processor system.

[0087] In one embodiment of the present invention, a joint test workgroup microcode update method is provided, which uses the joint test workgroup microcode update module described in any one of the above embodiments or a combination of multiple embodiments to update external microcode data into the core of the processor system.

[0088] In one embodiment of the present invention, a processor system is provided, comprising one or more cores, a system interface unit, a peripheral controller, and a joint test workgroup microcode update module as described in any one of the above embodiments or a combination of multiple embodiments, wherein each of the cores is electrically connected to the system interface unit;

[0089] The joint test workgroup microcode update module is electrically connected to the system interface unit, and the joint test workgroup microcode update module is configured to load microcode data outside the processor system into one or more of the plurality of cores through the system interface unit;

[0090] The peripheral controller is electrically connected to the system interface unit; the joint test working group microcode update module is configured to load microcode data outside the processor system into one or more of the plurality of peripheral controllers through the system interface unit.

[0091] It should be noted that the joint test working group microcode update method and processor system provided by the present invention have the same inventive concept as the above-mentioned joint test working group microcode update module embodiment, and all the contents of the joint test working group microcode update module embodiment are incorporated into the joint test working group microcode update method and processor system embodiment by introduction.

[0092] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0093] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A joint test working group microcode update module, characterized in that: Used to load microcode data outside a processor system into a core of the processor system, the processor system is configured with a system interface unit electrically connected to the core, and a joint test working group microcode update module is electrically connected to the system interface unit; The joint test working group microcode update module includes a JTAG interface, a buffer and drive unit, a security and protection unit, a test access port controller, an instruction register, a data register and a microcode interface logic unit; The JTAG interface is configured to be electrically connected to a JTAG connector of a storage device, the storage device is configured to store microcode data, and the JTAG interface is configured to load the microcode data stored in the storage device into the joint test working group microcode update module; The buffer and drive unit is electrically connected to the JTAG interface, and the buffer and drive unit is configured to perform signal enhancement processing on an output signal of the JTAG interface; The security and protection unit is configured to receive and verify the security and correctness of the microcode data loaded through the JTAG interface, and control the further transmission of the verified microcode data and intercept the microcode data that fails the verification; The input end of the test access port controller is electrically connected to the output end of the security and protection unit, and the output end of the test access port controller is electrically connected to the instruction register and the data register respectively; The microcode interface logic unit is electrically connected to the output end of the instruction register and the output end of the data register respectively, and the microcode interface logic unit is configured to transmit the microcode data to the system interface unit.

2. The joint test working group microcode update module according to claim 1, characterized in that: The security and protection unit includes an encryptor, a comparison logic, a control logic and a reference memory; Wherein, the reference memory has a plurality of reference encrypted values ​​pre-stored therein; The encryptor is configured to generate a corresponding first encrypted value for the microcode data; The comparison logic is configured to compare the first encrypted value with the reference encrypted value to obtain a comparison result, and transmit the comparison result to the control logic, wherein the comparison result includes consistency and inconsistency; If the comparison result is consistent, the control logic is configured to control the further transmission of the microcode data; if the comparison result is inconsistent, the control logic is configured to intercept the microcode data.

3. The joint test working group microcode update module according to claim 2, characterized in that: If the comparison result is consistent, the security and correctness verification of the microcode data loaded through the JTAG interface passes; if the comparison result is inconsistent, the security and correctness verification of the microcode data loaded through the JTAG interface fails.

4. The joint test working group microcode update module according to claim 2, characterized in that: The comparison logic is configured to compare the first encrypted value with the reference encrypted value to obtain a comparison result, including: The first encrypted value is compared with the multiple reference encrypted values ​​one by one. If the first encrypted value is the same as any one of the reference encrypted values, the comparison result is consistent; if the first encrypted value is different from any one of the reference encrypted values, the comparison result is inconsistent.

5. The joint test working group microcode update module according to claim 2, characterized in that: The processor system includes a plurality of cores, and the reference encryption value has a corresponding relationship with the cores; The comparison logic is configured to compare the first encrypted value with the reference encrypted value to obtain a comparison result, including: Determine that the core into which the microcode data is targeted is a target core, wherein the target core is one of the plurality of cores; According to the correspondence between the reference encrypted value and the core, determine a reference encrypted value having a corresponding relationship with the target core as a target reference encrypted value; The first encrypted value is compared with the target reference encrypted value. If the first encrypted value is the same as the target reference encrypted value, the comparison result is consistent; if the first encrypted value is different from the target reference encrypted value, the comparison result is inconsistent.

6. The joint test working group microcode update module according to claim 2, characterized in that: The encryptor adopts a hash calculator, and the hash calculator is configured to generate a corresponding first hash value for the microcode data, the first hash value is configured as the first encryption value, and the reference encryption value is a pre-stored reference hash value.

7. The joint test working group microcode update module according to claim 1, characterized in that: Also included is a core selection unit, which is disposed between the buffer and drive unit and the safety and protection unit, and is electrically connected to the buffer and drive unit and the safety and protection unit respectively; The core selection unit is configured to determine a target core microcode unit into which the microcode data is expected to be loaded according to an output signal of the buffer and drive unit, wherein the target core microcode unit is one of the core microcode units corresponding to each core.

8. The joint test working group microcode update module according to claim 7, characterized in that: Also included is a level converter, which is disposed between the core selection unit and the safety and protection unit and is electrically connected to the core selection unit and the safety and protection unit respectively; The level converter is configured to receive the JTAG signal output by the core selection unit and control the level of the JTAG signal to match the working level of the target core microcode unit.

9. The joint test working group microcode update module according to claim 1, characterized in that: The processor system further includes a peripheral controller, wherein the peripheral controller is electrically connected to the system interface unit; The joint test working group microcode update module is also configured to load external microcode data into the peripheral controller through the system interface unit.

10. The joint test working group microcode update module according to claim 1, characterized in that: The test access port controller includes a state machine configured to control JTAG operations, including inputting corresponding data into the data register according to the microcode data, and inputting corresponding instructions into the instruction register; The data register is configured to transmit the microcode data; The instruction register is configured to receive and store JTAG instructions.

11. A joint test working group microcode update method, characterized in that: The external microcode data is updated into the core of the processor system using the joint test working group microcode update module as described in any one of claims 1-10.

12. A processor system, characterized in that: The device comprises one or more cores, a system interface unit and a joint test working group microcode update module as claimed in any one of claims 1 to 10, wherein each of the cores is electrically connected to the system interface unit respectively; The joint test workgroup microcode update module is electrically connected to the system interface unit, and the joint test workgroup microcode update module is configured to load microcode data outside the processor system into one or more of the multiple cores through the system interface unit.

13. The processor system according to claim 12, characterized in that Also included is a peripheral controller, the peripheral controller being electrically connected to the system interface unit; The joint test working group microcode update module is configured to load microcode data outside the processor system into one or more of the plurality of peripheral controllers through the system interface unit.

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