Data transmission circuits and electronic devices

Abstract

This application provides a data transmission circuit and an electronic device. The data transmission circuit is used to connect a microprocessor and multiple flip-flops of a function register. The microprocessor includes a read / write bus. The data transmission circuit includes a conversion circuit and a data transmission circuit. The input terminal of the conversion circuit is connected to the read / write bus and is used to generate a bit enable signal according to the address enable signal sent by the microprocessor. The first input terminal of the data transmission circuit is connected to the output terminal of the conversion circuit to receive the bit enable signal. The second input terminal of the data transmission circuit is connected to the read / write bus. Each output terminal of the read / write circuit is connected to a flip-flop to store the read / write data sent by the microprocessor to a target flip-flop. The target flip-flop is determined according to the bit enable signal and is selected from multiple flip-flops according to the bit enable signal. Only one target flip-flop exists at any given time.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a data transmission circuit and electronic equipment. Background Art

[0002] At present, in the assembly instruction set of the microprocessor (Reduced Instruction Set Computer, RISC), the assembly instructions that can perform bit operations include: bit segment clearing, bit segment insertion and bit segment extension. The bit segment clearing instruction can clear a certain segment of a general register. The bit segment insertion instruction can insert a certain segment of a general register into a specific position of another register. The bit segment extension instruction extracts a certain segment of a general register and extends it with a sign / unsigned extension. The above assembly instructions are more cumbersome when performing bit operations on the byte data in the function register of an external device. First, the byte data of the function register needs to be read out to the general register, and then the assembly instructions are used to clear / insert certain bits or bit segments of the byte data written to the general register to obtain the rewritten byte data, and then the rewritten byte data is written back to the function register of the external device. The entire process takes a long time to complete, which limits the speed of bit operations on the function register of the external device. Summary of the invention

[0003] The present application provides a data transmission circuit and an electronic device for improving the speed of performing bit operations on a function register of an external device.

[0004] In a first aspect, an embodiment of the present application provides a data transmission circuit, the data transmission circuit is used to connect a microprocessor and a plurality of triggers of a function register, the microprocessor includes: a read-write bus, the data transmission circuit includes: a conversion circuit and a read-write circuit;

[0005] The input end of the conversion circuit is connected to the read-write bus and is used to generate a bit enable signal according to the address enable signal sent by the microprocessor;

[0006] The first input end of the read-write circuit is connected to the output end of the conversion circuit to receive the bit enable signal, the second input end of the read-write circuit is connected to the data signal line, and each output end of the read-write circuit is respectively connected to one of the triggers. The read-write circuit is used to store the read-write data sent by the microprocessor to a target trigger. The target trigger is determined from multiple triggers according to the bit enable signal, and there is only one target trigger at the same time.

[0007] In some embodiments, the read / write bus includes: a type I address line, a type II address line, and a data signal line, and the conversion circuit includes:

[0008] A first decoder, the first decoder is connected to the first type of address lines, the first decoder comprises: 4 byte control terminals;

[0009] A second decoder, the second decoder is connected to the second type of address lines, the second decoder comprises: 8 bit control terminals;

[0010] Each of the byte control terminals and each of the bit control terminals respectively form a bit enable control terminal, and one of the address enable signals only controls a corresponding one of the enable control terminals to be in a working state.

[0011] In some embodiments, the conversion circuit comprises:

[0012] A plurality of first logic elements, wherein two input terminals of the first logic element are respectively used to connect the byte control terminal and the bit control terminal, and the output terminal of the first logic element is the bit enable control terminal.

[0013] In some embodiments, the read / write circuit includes: a second logic element and a plurality of third logic elements, the second logic element includes: an OR gate element, the third logic element includes: an AND gate element, and the third logic element corresponds to the first logic element one by one;

[0014] The input terminal of the second logic element is connected to the data signal line, and is used to generate a data write signal according to the read / write data;

[0015] The first input terminal of each of the third logic components is connected to the output terminal of the corresponding first logic component, the second input terminal of each of the third logic components is connected to the output terminal of the second logic component, and the output terminal of each of the third logic components is respectively connected to the data input terminal of one of the triggers, and the third logic components are used to modify the value stored in the target trigger according to the data write signal and the bit enable signal.

[0016] In some embodiments, the microprocessor further comprises: a start signal line, and the conversion circuit comprises:

[0017] A comparator, wherein the input end of the comparator is respectively connected to the start signal line and a preset start judgment signal line;

[0018] A plurality of fourth logic elements, wherein a first input terminal of each of the fourth logic elements is connected to an output terminal of the comparator, a second input terminal of each of the fourth logic elements is respectively connected to a byte control terminal or a bit control terminal, an output terminal of each of the fourth logic elements is respectively connected to an input terminal of the first logic element, and the fourth logic elements include: an AND gate element and an XNOR gate element.

[0019] In a second aspect, an embodiment of the present application provides an electronic device, wherein the electronic device includes a data transmission circuit as described in any one of the embodiments of the present application.

[0020] The embodiment of the present application provides a data transmission circuit, which is used to connect a microprocessor and multiple triggers of a function register. The microprocessor includes: a read-write bus and a data signal line, and the data transmission circuit includes: a conversion circuit and a read-write circuit. The input end of the conversion circuit is connected to the read-write bus, and is used to generate a bit enable signal according to the address enable signal sent by the microprocessor; the first input end of the read-write circuit is connected to the output end of the conversion circuit to receive the bit enable signal, the second input end of the read-write circuit is connected to the data signal line, and each output end of the read-write circuit is connected to a trigger respectively. The read-write circuit is used to store the read-write data sent by the microprocessor to the target trigger. The target trigger is determined from multiple triggers according to the bit enable signal. At the same time, there is only one target trigger. In the above data transmission circuit, by converting the address enable signal into a bit enable signal, and then using the bit enable signal to put the output end of the read-write circuit corresponding to the target trigger into a working state, each bit enable signal corresponds to only one target trigger, so that the read-write data is only written to one target trigger at a time, thereby realizing direct bit operations on the function registers of the external device through assembly instructions, and at the same time, there is no need to use general registers for data transfer, thereby improving the speed of bit operations on the function registers of the external device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0022] Figure 1 A schematic block diagram of a data transmission circuit provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of a first conversion circuit provided in an embodiment of the present application;

[0024] Figure 3 A schematic diagram of a conversion circuit provided in an embodiment of the present application

[0025] Figure 4 A schematic diagram of a second conversion circuit provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of the composition of an assembly instruction provided in an embodiment of the present application.

[0027] Description of reference numerals:

[0028] 200, microprocessor; 201, read-write bus; L1, type I address line; L2, type II address line; L3, data signal line; L4, start signal line; L5, start judgment signal line; 300, function register; 301, trigger; 100, data transmission circuit; 11, conversion circuit; Y1, first logic element; Y4, fourth logic element; 111, first decoder; 112, second decoder; 12, read-write circuit; Y2, second logic element; Y3, third logic element. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0031] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0032] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0033] It should be noted that external devices refer to devices connected outside the computer host. They are generally divided into input devices, output devices and external storage devices. External devices are an important component of the computer system and play the role of information transmission, transfer and storage.

[0034] See also Figure 1 , Figure 1 The embodiment of the present application also provides a schematic block diagram of a data transmission circuit. Figure 1As shown, the data transmission circuit 100 is used to connect the microprocessor 200 and multiple triggers 301 of the function register 300. The microprocessor 200 includes: a read-write bus 201, and the data transmission circuit 100 includes: a conversion circuit 11 and a read-write circuit 12.

[0035] Exemplarily, the microprocessor 200 is a RISC processor, and the microprocessor 200 is connected to the data transmission circuit 100 via a read / write bus 201 .

[0036] The input end of the conversion circuit 11 is connected to the read / write bus 201, and is used to generate a bit enable signal according to the address enable signal sent by the microprocessor 200. Since the address intelligent signal is generated according to the assembly instruction, the bit selection of the function register is realized based on the assembly instruction.

[0037] Exemplarily, the microprocessor 200 is used to generate an address enable signal according to the addressing information in the input assembly instruction, and send the address enable signal to the conversion circuit 11 through the read-write bus 201. The address enable signal complies with the communication protocol standard of the data bus. The bit enable signal is used to complete the read and write enable of a single register.

[0038] The first input end of the read-write circuit 12 is connected to the output end of the conversion circuit 11 to receive a bit enable signal. The second input end of the read-write circuit 12 is connected to the read-write bus 201. Each output end of the read-write circuit 12 is respectively connected to a trigger 301. The read-write circuit 12 is used to store the read-write data sent by the microprocessor 200 to the target trigger 301. The target trigger 301 is determined from multiple triggers 301 according to the bit enable signal. At the same time, there is only one target trigger 301.

[0039] Exemplarily, through the converted bit enable signal, at any time, there is only one output end of the data output circuit that can read and write data to the trigger 301, and the trigger 301 corresponding to the output end is the target trigger 301. In this way, the risk of data string writing is avoided. Then, a read and write pulse is generated according to the read and write data and the bit enable signal, and transmitted to the target trigger 301. In this way, fixed-point reading and writing of the target register is realized, thereby realizing bit operation of the function register 300.

[0040] The embodiment of the present application provides a data transmission circuit, which is used to connect a microprocessor and multiple triggers of a function register. The microprocessor includes a read-write bus, and the data transmission circuit includes a conversion circuit and a read-write circuit. The input end of the conversion circuit is connected to the read-write bus, and is used to generate a bit enable signal according to the address enable signal sent by the microprocessor; the first input end of the read-write circuit is connected to the output end of the conversion circuit to receive the bit enable signal, the second input end of the read-write circuit is connected to the read-write bus, and each output end of the read-write circuit is connected to a trigger respectively. The read-write circuit is used to store the read-write data sent by the microprocessor to a target trigger, and the target trigger is determined from multiple triggers according to the bit enable signal. At the same time, there is only one target trigger. In the above data transmission circuit, by converting the address enable signal into a bit enable signal, and then using the bit enable signal to put the output end of the read-write circuit corresponding to the target trigger into a working state, each bit enable signal corresponds to only one target trigger, so that the read-write data is only written to one target trigger at a time, thereby realizing direct bit operations on the function registers of the external device through assembly instructions, and at the same time, there is no need to use general registers for data transfer, thereby improving the speed of bit operations on the function registers of the external device.

[0041] In order to more clearly introduce the technical solution of the present application, the technical solution of the present application will be introduced through specific embodiments below. It should be noted that the specific embodiments are used to expand the technical solution of the present application, but are not intended to limit the present application.

[0042] In some embodiments, see Figure 2 , Figure 2 The schematic diagram of the first conversion circuit provided by the embodiment of the present application is shown. Figure 2 As shown, the read / write bus 201 includes: a first type of address line L1, a second type of address line L2 and a data signal line L3, and the conversion circuit 11 includes: a first decoder 111 and a second decoder 112.

[0043] The first decoder 111 is connected to a type of address line L1, and the first decoder 111 includes: 4 byte control terminals (Z0-Z3).

[0044] Exemplarily, the first decoder 111 is a 2-4 line decoder, and the 2-4 line decoder includes 4 output terminals, that is, the 2-4 line decoder includes 4 byte control terminals. The first type of address line L1 is the address line numbered 3 and 4 in the read-write bus 201. The first decoder 111 generates a 4-bit byte selection signal according to the address enable signal transmitted by the 2-bit first type of address line L1.

[0045] In such Figure 1The functional register 300 shown generally includes 32 flip-flops 301. The values ​​stored in every eight flip-flops 301 constitute a byte. The first decoder 111 generates a byte selection signal to determine the selection range of the target flip-flop 301.

[0046] In some embodiments, a 2-bit type I address line L1 corresponds to a 32-bit function register, and so on, when the function register is 64 bits, it is only necessary to expand L1 to 3 bits. That is, the function registers that can be controlled by a type I address line L1 include 8 bits, 32 bits, and 64 bits.

[0047] The second decoder 112 is connected to the second type address line L2, and the second decoder 112 includes: 8 bit control terminals (W0-W7).

[0048] Exemplarily, the second decoder 112 is a 3-8 line decoder, and the 3-8 line decoder includes 8 output terminals, that is, the 3-8 line decoder includes 8 bit control terminals. The second type address line L2 is the address line numbered 0, 1 and 2 in the read-write bus 201. The second decoder 112 generates an 8-bit bit selection signal according to the address enable signal transmitted by the 3-bit second type address line L2. In the previous step, the selection range of the target trigger 301 determined by the byte selection signal includes 8 triggers 301, and the target trigger 301 is accurately selected from the 8 triggers 301 in the selection range through the bit selection signal.

[0049] Each byte control terminal and each bit control terminal form a bit enable control terminal (ZW0-ZW31), and an address enable signal only controls a corresponding enable control terminal to be in a working state.

[0050] It should be noted that both the bit selection signal and the byte selection signal are binary sequences, and there is a value of "1" in each bit selection signal or byte selection signal. For example, the byte selection signals include: 0001, 0010, 0100 and 1000.

[0051] In some embodiments, the conversion circuit 11 includes: a plurality of first logic elements Y1. Two input terminals of the first logic element Y1 are respectively used to connect to a byte control terminal and a bit control terminal, and an output terminal of the first logic element Y1 is a bit enable control terminal.

[0052] Exemplarily, each byte control terminal is combined with each bit control terminal, for example, one byte control terminal is connected to the first input terminals of eight AND gates, and the second input terminals of the eight AND gates are connected to each bit control terminal. The output terminal of each AND gate is a bit enable control terminal. Through the above circuit relationship, each address enable signal can only make one AND gate in working state, even if the output terminal of the AND gate outputs a high level.

[0053] In this way, under the premise of complying with the communication standard protocol of the data bus, the target trigger 301 can be accurately identified through assembly instructions.

[0054] In some embodiments, see Figure 3 , Figure 3 The embodiment of the present application also provides a schematic diagram of a read / write circuit. The read / write circuit 12 includes: a second logic element Y2 and a plurality of third logic elements Y3, the second logic element Y2 includes: an OR gate element, the third logic element Y3 includes: an AND gate element, and the third logic element Y3 corresponds to the first logic element Y1 one by one.

[0055] The input end of the second logic element Y2 is connected to the data signal line L3, and is used to generate a data write signal according to the read and write data. The second logic element Y2 is used to filter out valid data in the read and write data according to the protocol corresponding to the assembly instruction, and generate a data write signal.

[0056] Since the bit enable signal is used to ensure that there is only one target trigger 301 at any time, the read and write data transmitted by multiple data signal lines L3 can be collected by the second logic element Y2 before use.

[0057] The first input terminal of each third logic element Y3 is connected to the output terminal of the corresponding first logic element Y1, the second input terminal of each third logic element Y3 is connected to the output terminal of the second logic element Y2, and the output terminal of each third logic element Y3 is respectively connected to the data input terminal of a trigger 301, and the third logic element Y3 is used to modify the value stored in the target trigger 301 according to the data write signal and the bit enable signal.

[0058] Exemplarily, the number of first logic elements Y1 and third logic elements Y3 is the same, and the first logic elements Y1 and the third logic elements Y3 correspond one to one, and the output end of each third logic element Y3 is respectively connected to the data input end (D end) of a trigger 301. When the byte selection signal and the bit selection signal input to the first logic element Y1 are both "1", the first logic element Y1 outputs a bit enable signal (value is "1"). Since there is only one value of 1 in the byte selection signal or the bit selection signal, then at the same time, only one first logic element Y1 can output a bit enable signal. In this way, the third logic element Y3 (AND gate element) corresponding to the first logic element Y1 can modify the value stored in the target trigger 301 according to the bit enable signal and the data write signal.

[0059] Through the above circuit, it is possible to directly perform bit operations on the function register 300 of the external device through assembly instructions, that is, to read and write data on the target trigger 301, without the need for data transfer via a general register, thereby improving the speed of performing bit operations on the function register 300 of the external device.

[0060] In some embodiments, see Figure 4 , Figure 4 The embodiment of the present application also provides a schematic diagram of a second conversion circuit. Figure 4 As shown, the microprocessor 200 further includes: a start signal line L4, and the conversion circuit 11 includes: a comparator and a plurality of fourth logic elements Y4.

[0061] The input end of the comparator is connected to the start signal line L4 and the preset start judgment signal line L5 respectively. The first input end of each fourth logic element Y4 is connected to the output end of the comparator, the second input end of each fourth logic element Y4 is connected to a byte control end or a bit control end respectively, the output end of each fourth logic element Y4 is connected to an input end of the first logic element Y1 respectively, and the fourth logic element Y4 includes: an AND gate element and an XNOR gate element.

[0062] Exemplarily, the start signal line L4 is a byte size control line on the data bus, and the byte size control line is a 2-bit data line. The first input terminal of the comparator is connected to the start signal line L4, and the second input terminal of the comparator is connected to the preset start judgment signal line L5. In the embodiment of the present application, the signal on the preset start judgment signal line L5 is "00". If the output terminal of the comparator is required to output a high level (value "1"), the byte size control signal input to the start signal line L4 is also required to be "00".

[0063] It should be noted that the signal on the start judgment signal line L5 also includes: "01" and "10". According to different signals on the start judgment signal line L5, the assembly instructions for calling other functions need to be adaptively modified.

[0064] Through the above mechanism, it is achieved that the conversion circuit 11 is turned on or off through the byte size control line, representing the bit read and write operation of the function register 300.

[0065] In some embodiments, see Figure 5 , Figure 5 The embodiment of the present application also provides a schematic diagram of the composition of an assembly instruction. Figure 5 As shown, "STRB R n ,[R d , #bit]" indicates an assembly instruction example. Among them, "R n " is a register in the general register (R0-R7), which is used to store the read and write data to be written, and can only be 0 or 1. "R d " is the same as "R n" is another register that is different from the base address of the function register. "#bit" corresponds to the output segment of the first logic element Y1, indicating a bit enable signal. Each function bit of the register corresponds to an offset address; when writing 1 to the 29th bit of the register, that is, address = base address + 29, R n =0x01, R d =base address, "bit" = 29.

[0066] Through the data transmission circuit provided in the present application, bit operations can be performed more accurately and quickly on the functional registers of peripherals in the fields of industrial control and automobile control.

[0067] An embodiment of the present application provides an electronic device, wherein the electronic device includes a data transmission circuit as described in any one of the embodiments of the present application.

[0068] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A data transmission circuit, characterized in that: The data transmission circuit is used to connect a microprocessor and a plurality of triggers of a function register. The microprocessor includes a read-write bus, and the read-write bus includes a first-class address line, a second-class address line and a data signal line. The data transmission circuit includes: A conversion circuit, the input end of which is connected to the read-write bus, and is used to generate a bit enable signal according to the address enable signal sent by the microprocessor; A read-write circuit, wherein a first input end of the read-write circuit is connected to an output end of the conversion circuit to receive the bit enable signal, a second input end of the read-write circuit is connected to the read-write bus, and each output end of the read-write circuit is respectively connected to one of the triggers, and the read-write circuit is used to store the read-write data sent by the microprocessor into a target trigger, wherein the target trigger is determined from a plurality of the triggers according to the bit enable signal, and at the same time, there is only one target trigger; The conversion circuit includes: a first decoder and a second decoder; The first decoder is connected to the first type of address lines, and the first decoder includes: a plurality of byte control terminals; The second decoder is connected to the second type of address lines, and the second decoder includes: a plurality of bit control terminals; Each of the byte control terminals and each of the bit control terminals respectively form a bit enable control terminal, and one of the address enable signals only controls a corresponding one of the enable control terminals to be in a working state; The conversion circuit comprises: a plurality of first logic elements, wherein two input terminals of the first logic element are respectively used to connect the byte control terminal and the bit control terminal, and the output terminal of the first logic element is the bit enable control terminal; The read-write circuit includes: a second logic element and a plurality of third logic elements, the second logic element includes: an OR gate element, the third logic element includes: an AND gate element, and the third logic element corresponds to the first logic element one by one; The input terminal of the second logic element is connected to the data signal line, and is used to generate a data write signal according to the read / write data; The first input terminal of each of the third logic components is connected to the output terminal of the corresponding first logic component, the second input terminal of each of the third logic components is connected to the output terminal of the second logic component, and the output terminal of each of the third logic components is respectively connected to the data input terminal of one of the triggers, and the third logic components are used to modify the value stored in the target trigger according to the data write signal and the bit enable signal.

2. The data transmission circuit according to claim 1, characterized in that: The microprocessor further comprises: a start signal line, and the conversion circuit comprises: A comparator, wherein the input end of the comparator is respectively connected to the start signal line and a preset start judgment signal line; A plurality of fourth logic elements, wherein a first input terminal of each of the fourth logic elements is connected to an output terminal of the comparator, a second input terminal of each of the fourth logic elements is respectively connected to a byte control terminal or a bit control terminal, an output terminal of each of the fourth logic elements is respectively connected to an input terminal of the first logic element, and the fourth logic elements include: an AND gate element and an XNOR gate element.

3. An electronic device, characterized in that: The electronic device comprises the data transmission circuit as claimed in any one of claims 1 to 2.

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