Instruction acquisition method, processor, system on chip and computing equipment

Abstract

The embodiment of the invention provides an instruction obtaining method, a processor, a system on chip and computing equipment, the instruction obtaining method is applied to an instruction fetching unit of the processor, the processor further comprises a cache unit, a tight coupling storage unit and a program counter, and the instruction obtaining method comprises the steps that branch prediction information for a current jump instruction is received; based on the branch prediction information, determining a current storage unit where the current jump instruction is located from a cache unit and a tight coupling storage unit; based on the offset of the current program count value recorded by the program counter, the current jump instruction is taken out from the current storage unit, so that the time sequence pressure is reduced, the dominant frequency of the processor is improved, and meanwhile, the additional dynamic power consumption caused by simultaneously acquiring the jump instruction by double branches is effectively avoided; according to the method, the performance and the product endurance of the processor in processing discontinuous instructions are improved, more efficient and energy-saving instruction acquisition is realized on the premise of not sacrificing the processing speed, and the method is suitable for application scenes with higher requirements on the real-time performance and the product endurance.

Description

Technical Field

[0001] The embodiments of this specification relate to the technical field of electronic hardware, and more particularly to an instruction acquisition method, a processor, a system on chip, and a computing device. Background Art

[0002] With the development of semiconductor technology and processor architecture technology, modern processors not only pursue higher performance, but also need to meet the real-time and energy efficiency requirements of specific application fields.

[0003] At present, for high real-time scenarios, the processor needs to ensure that the processing delay of key instructions is within a certain range. If the processor obtains key instructions from the cache unit, when the key instructions are not in the cache unit, the key instructions cannot be pulled from the memory outside the processor through the bus interface unit (BIU) to ensure stable delay. To address this problem, by adding an independent tightly coupled storage unit in the processor, which is independent of the cache unit but exists at the same time, the key instructions can be placed in it, and the key instruction acquisition with stable delay can be achieved.

[0004] However, if the key instruction is a non-continuous instruction such as a jump instruction, it may cause a sudden change in the direction of the instruction flow. It is necessary to compare the addresses in advance to determine whether the key instruction is stored in the cache unit or the tightly coupled storage unit at the current jump, and then obtain the key instruction from the corresponding storage unit. This method of comparing the addresses in advance and then obtaining the corresponding instructions will produce a large delay, reduce the processor's main frequency, and affect the processor's processing performance. Summary of the invention

[0005] In view of this, an embodiment of this specification provides an instruction acquisition method. One or more embodiments of this specification also relate to a processor, a system on a chip, a computing device, a computer-readable storage medium and a computer program product to solve the technical defects existing in the prior art.

[0006] According to a first aspect of an embodiment of this specification, there is provided an instruction acquisition method, which is applied to an instruction fetch unit of a processor, wherein the processor further includes a cache unit, a tightly coupled storage unit, and a program counter, including: receiving branch prediction information for the current jump instruction; Based on the branch prediction information, determine the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit; Based on the offset of the current program count value recorded by the program counter, the current jump instruction is fetched from the current storage unit.

[0007] According to a second aspect of an embodiment of this specification, a processor is provided, the processor comprising an instruction fetch unit, a cache unit, a tightly coupled storage unit and a program counter; The instruction fetch unit is used to receive branch prediction information for the current jump instruction, determine the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit based on the branch prediction information, and fetch the current jump instruction from the current storage unit based on the offset of the current program count value recorded by the program counter.

[0008] According to a third aspect of an embodiment of this specification, a system on chip is provided, including: a control unit and a plurality of on-chip components, the plurality of on-chip components including a processor; The control unit is used to control and manage multiple on-chip components, and the processor is used to execute computer programs / instructions. When the computer programs / instructions are executed by the processor, the steps of the above-mentioned instruction acquisition method are implemented.

[0009] According to a fourth aspect of an embodiment of this specification, a computing device is provided, including: Memory and System-on-Chip; The memory is used to store computer programs / instructions, and the system on chip is used to execute the computer programs / instructions. When the computer program / instructions are executed by the system on chip, the steps of the above-mentioned instruction acquisition method are implemented.

[0010] According to a fifth aspect of the embodiments of this specification, a computer-readable storage medium is provided, which stores a computer program / instruction, and the computer program / instruction implements the steps of the above-mentioned instruction acquisition method when executed by a processor.

[0011] According to a sixth aspect of the embodiments of this specification, a computer program product is provided, including a computer program / instruction, which implements the steps of the above-mentioned instruction acquisition method when executed by a processor.

[0012] In one embodiment of the present specification, in the instruction fetch stage, based on the branch prediction information for the current jump instruction, one of the cache units and the tightly coupled storage units is directly determined as the current storage unit where the current jump instruction is located, and based on the offset of the current program count value recorded by the program counter, the current jump instruction is taken out from the current storage unit, and address comparison and instruction acquisition are no longer performed sequentially, thereby reducing timing pressure and increasing the main frequency of the processor. At the same time, it also effectively avoids the additional dynamic power consumption caused by the simultaneous acquisition of jump instructions by two branches, improves the performance of the processor when processing non-continuous instructions and the product endurance, and achieves more efficient and energy-saving instruction acquisition without sacrificing processing speed. It is suitable for application scenarios with high requirements for real-time performance and product endurance. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a pipeline diagram of the instruction fetch stage; Figure 2 is a flowchart diagram of an instruction acquisition method; Figure 3 is a flowchart of another instruction acquisition method; Figure 4 is a flow chart of an instruction acquisition method provided by an embodiment of this specification; Figure 5 This is one of the flowcharts of an instruction acquisition method provided by an embodiment of this specification; Figure 6 This is a second flow chart of an instruction acquisition method provided by an embodiment of this specification; Figure 7 is a comparative schematic diagram of an instruction acquisition method provided by an embodiment of this specification; Figure 8 is a schematic diagram of the structure of a processor provided by an embodiment of this specification; Fig. 9 is a structural block diagram of a system on a chip provided by an embodiment of this specification; Fig.10 It is a structural block diagram of a computing device provided by an embodiment of this specification. DETAILED DESCRIPTION

[0014] Many specific details are described in the following description to facilitate a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of this specification, so this specification is not limited to the specific implementation disclosed below.

[0015] The terms used in one or more embodiments of this specification are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of this specification. The singular forms of "a", "said" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0016] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of this specification, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0017] In addition, it should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in one or more embodiments of this specification are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0018] First, the terms involved in one or more embodiments of this specification are explained.

[0019] Reduced Instruction Set Computing (RISC) is a processor architecture design concept that emphasizes the use of a smaller number of simple instructions to build a processor in order to improve the execution efficiency and speed of the processor.

[0020] Reduced Instruction Set Processor (RISC Processor): A processor designed based on the RISC concept, characterized by a shorter instruction pipeline, a fixed instruction format and a simple addressing mode, which can achieve high-speed processing.

[0021] Complex Instruction Set Computing (CISC) is a processor architecture design concept that emphasizes the use of a larger number of complex instructions to build processors in order to improve the functionality and flexibility of the processor.

[0022] Complex Instruction Set Processor (CISC Processor): A processor designed based on the CISC concept, characterized by a large number of complex instructions, each of which can complete multiple operations.

[0023] Cache unit: A high-speed, small-capacity random storage unit located between the processor and the main memory, used to temporarily store recently frequently accessed data and instructions to reduce the time to access the main memory and improve the work efficiency of the processor. The cache unit is divided into instruction cache (ICache for short) and data cache (DCache for short) to optimize the instruction flow and data flow respectively.

[0024] Tightly Coupled Memory (TCM): A random access memory unit directly connected to the processor, used to store key data or instructions that need to be accessed quickly, with lower access latency than ordinary cache. TCMs are divided into instruction tightly coupled memory units (ITCMs) and data tightly coupled memory units (DTCMs) to optimize instruction flow and data flow respectively.

[0025] Static Random Access Memory (SRAM) is a random access memory cell that can maintain stable data storage without the need for a refresh circuit. It has a faster access speed and is often used to make cache.

[0026] Instruction Fetch Unit (IFU): The part of the processor that is responsible for fetching the next instruction to be executed from the storage unit and sending it to the subsequent processing stage.

[0027] Program Counter (PC): A register that stores the address of the next instruction and instructs the instruction fetch unit where to get the next instruction.

[0028] Load Store Unit (LSU): responsible for processing data loading and storage operations, that is, reading data from the memory or writing data back to the memory.

[0029] Execution Unit (EXU): The execution unit is responsible for executing instructions, including arithmetic and logical operations.

[0030] Arithmetic Logic Unit (ALU) is the part of the processor that performs basic arithmetic operations (addition, subtraction, etc.) and logical operations (AND, OR, NOT, etc.).

[0031] Bus Interface Unit (BIU): Responsible for the communication between the processor and external devices, including data transmission and address sending.

[0032] Branch Unit (BJU): A component unit used to process branch instructions. It is responsible for analyzing branch conditions and predicting the direction of the branch to reduce pipeline stalls caused by waiting for the results of branch instructions, thereby improving the execution efficiency of the processor.

[0033] Predictor: A component unit used to predict the address of the next instruction. It predicts whether a branch instruction will jump and its target address by analyzing historical data and current conditions, thereby reducing pipeline stalls caused by waiting for branch instruction results, thereby improving the execution efficiency of the processor.

[0034] Figure 1 FIG. 4 shows a pipeline diagram of the instruction fetch stage, such as Figure 1 As shown: The entire process from instruction fetch to execution completion, the instruction life cycle usually includes five stages: instruction fetch (Instruction Fetch, referred to as IF), decoding stage (Instruction Decode, referred to as ID), execution stage (Instruction Execute, referred to as EX), memory access stage (Memory Access, referred to as MEM) and memory access stage (Memory Access, referred to as MEM).

[0035] Instruction fetch phase: The first phase of the instruction cycle, the process of reading instructions from memory into the processor.

[0036] Decoding stage: The process of converting the fetched instructions into control signals to determine the specific operation of the instruction and the required operands.

[0037] Execution phase: perform specific operations such as calculation and comparison based on the decoding results.

[0038] Memory access phase: The process that occurs when an instruction needs to access memory (read or write data).

[0039] Write back stage: write the execution result back to the register or memory to complete the execution of the instruction.

[0040] In the instruction fetch stage of the instruction fetch unit, it is usually divided into the following four stages: Program Counter GENeration (PCGEN), instruction fetch, pre-decode (IP) and cache (IB).

[0041] The programmer generation stage contains combinational logic that determines the current memory location where the current jump instruction is located.

[0042] The instruction fetch stage is responsible for accessing the first-level cache (L1) instruction cache and predictor records, and completing the conversion of virtual addresses to physical addresses.

[0043] The pre-decoding stage is responsible for instruction preprocessing and initiating branch jump requests recorded by the predictor.

[0044] The cache stage initiates branch jump requests recorded by the miss predictor, and initiates jump requests for indirect branches and function call returns, and encapsulates and caches the instructions preprocessed in the pre-decoding stage. At the same time, after the instruction fusion operation, it sends at most two instructions to the decoding stage.

[0045] Since the programmer generation stage is logically coupled with other modules, it does not go through the register cache and is sometimes not a pipeline stage in the instruction fetch stage.

[0046] at present, Figure 2 A flow chart of an instruction acquisition method is shown, as shown in Figure 2 As shown: Critical instructions are non-continuous instructions such as jump instructions, which may cause a sudden change in the direction of the instruction flow.

[0047] In the program counter generation stage: after receiving the combinational logic of the branch prediction information for the current jump instruction (instruction retirement unit jump, branch unit jump, pre-decoding predictor jump, cache predictor jump and program counter value increment), perform address comparison and judgment in advance, and choose to initiate an access request to the cache unit or the tightly coupled storage unit based on whether the tightly coupled storage unit is hit and the current program count value.

[0048] In the instruction fetch stage: fetch the current jump instruction from the cache unit or tightly coupled storage unit.

[0049] Figure 2 In the illustrated advance address determination scheme, the address is compared in advance and then the instruction is obtained accordingly, which will cause a large delay in the processing timing, reduce the main frequency of the processor, and affect the processing performance of the processor.

[0050] In response to the above timing delay problem, Figure 3 A flow chart of another instruction acquisition method is shown. Figure 3 As shown: Critical instructions are non-continuous instructions such as jump instructions, which may cause a sudden change in the direction of the instruction flow.

[0051] In the program counter generation stage: after receiving the combinational logic of the branch prediction information for the current jump instruction (instruction retirement unit jump, branch unit jump, pre-decoding predictor jump, cache predictor jump and program counter value increment), according to the current program counter value of the program counter, the current instruction is sequentially executed from the cache unit and the tightly coupled storage unit respectively, and at the same time, the target address is calculated, and the target address is compared with the address range of the cache unit or the tightly coupled storage unit respectively, to determine that the cache unit or the tightly coupled storage unit is the valid current storage unit.

[0052] During the instruction fetch stage: retain the current jump instruction from the valid current memory location.

[0053] Figure 3 In the post-issuance selection scheme shown, although the timing pressure is small, since another branch is executed additionally, even if the capacity of the tightly coupled storage unit is large, if instructions are obtained at the same time, it will generate large dynamic power consumption, affecting the processor's battery life and heat dissipation.

[0054] It can be seen that Figure 2 The solution shown chooses to compare the address first and then obtain the instruction. Figure 3 The solution shown chooses to compare addresses while fetching instructions, and then retains one and discards the other based on the address comparison results. This cannot effectively reduce the delay caused by address comparison while ensuring the stability of instruction fetching, avoid additional dynamic power consumption, and reduce the processing performance of the processor and product life.

[0055] In response to the above problems, an instruction acquisition method is provided in this specification. This specification also involves a processor, a system on a chip, a computing device, a computer-readable storage medium and a computer program product, which are described in detail one by one in the following embodiments.

[0056] See also Figure 4 , Figure 4 A flowchart of an instruction acquisition method provided by an embodiment of the present specification is shown. The method is applied to an instruction fetch unit of a processor. The processor also includes a cache unit, a tightly coupled storage unit and a program counter, and includes the following specific steps: Step 402: Receive branch prediction information for the current jump instruction.

[0057] The processor is the core component of the computer system, responsible for executing instructions and processing data, and controlling other parts of the computer system, such as input / output devices, memory, and network interfaces. The processor completes specific processing tasks by performing a series of complex operations, including fetching instructions from storage media, decoding instructions, executing instructions, accessing memory, and writing back results. Processors include but are not limited to: reduced instruction set processors and complex instruction set processors.

[0058] The instruction fetch unit is a component unit in the processor that is responsible for fetching the next instruction to be executed from the storage unit. The instruction fetch unit is used to fetch instructions from the storage unit during the instruction fetch phase and pass them to subsequent processing phases, such as the decoding phase of the decoding unit and the execution phase of the execution unit.

[0059] The cache unit is a storage unit in the processor for temporarily storing data and instructions. The cache unit stores the most recently frequently accessed data and instructions to reduce the number of times the processor accesses the external memory, reduce the data access latency, and improve the work efficiency of the processor. The cache unit is usually divided into multiple levels, and the speed and capacity of each level are different. In the embodiment of this specification, the cache unit can be an instruction cache unit. For example, among the three levels of cache (L1, L2, L3), the L1 cache has the fastest speed but the smallest capacity, and the L3 cache has the slowest speed but the largest capacity.

[0060] The tightly coupled storage unit is a storage unit in the processor for temporarily storing key instructions. The tightly coupled storage unit and the cache unit are storage units of the same level. Compared with the cache unit, the instructions and data stored in the tightly coupled storage unit are generally different: such as interrupt processing instructions, real-time operating system kernel instructions, communication protocol stack instructions, etc. These key instructions and data are very sensitive to delays and require fast responses. In the embodiments of this specification, the tightly coupled storage unit can be an instruction tightly coupled storage unit.

[0061] The program counter is a register in the processor that stores the instruction address of the next instruction, and is used to instruct the instruction fetch unit to fetch the next instruction from the instruction address. The instruction address is the program counter value, and the program counter value is a storage unit address, pointing to the storage unit where the next instruction is fetched.

[0062] The jump instruction is a non-continuous instruction used to change the execution order of the program. The jump instruction enables the processor to skip certain instructions or jump to another location in the program to continue execution. Jump instructions are often used to implement logic such as conditional branches, loops, subroutine calls, and returns. For example, unconditional jump: JMP label, regardless of the conditions, jump to label label to continue execution. Conditional jump: JZ label, if the zero flag (Z) is 1, jump to label label to continue execution. Subroutine call: CALL function, jump to function function and save the return address. Subroutine return: RET, return from the subroutine and restore to the instruction address before the call.

[0063] The current jump instruction is the jump instruction currently being executed by the processor. The processor needs to parse and execute this instruction and update the program counter value recorded by the program counter to point to the new instruction address. The execution of the current jump instruction may affect the control flow of the program and lead to different execution paths.

[0064] The branch prediction information for the current jump instruction is information that predicts whether the current instruction is a jump instruction. The branch prediction information is the prediction for the current jump instruction output by the branch prediction unit, including the prediction result (jump or not jump), and may also include the source branch prediction unit. The branch prediction information is generally expressed as an electrical signal transmitted between component units in the processor. The purpose of branch prediction is to reduce pipeline stalls caused by waiting for instruction branch jumps, thereby improving the execution efficiency of the processor.

[0065] Receiving branch prediction information for the current jump instruction, an optional way is: receiving branch prediction information for the current jump instruction output by a branch prediction unit. The branch prediction unit is a component unit in the processor for predicting the behavior of jump instructions, including but not limited to: an instruction retirement unit, a branch unit, an instruction fetch predictor, and a cache predictor.

[0066] Exemplarily, in a RISC-V processor, there are an instruction fetch unit, an instruction cache unit, an instruction tightly coupled storage unit, and a program counter. In the RISC-V processor, n instructions are executed in a pipeline manner. In the instruction fetch stage of the i-th instruction: the instruction fetch unit receives the branch prediction information JumpSignal_i for the current jump instruction Instruction_i output by the branch prediction unit: prediction result: jump occurs; source: branch unit.

[0067] In step 402, branch prediction information for the current jump instruction is received, which provides an information basis for subsequently determining the current storage unit where the current jump instruction is located.

[0068] Step 404: Based on the branch prediction information, determine the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit.

[0069] The current storage unit where the current jump instruction is located is the storage unit that stores the current jump instruction predicted according to the branch prediction information. It is the instruction fetching object in the instruction fetching stage of the current jump instruction. The current storage unit is either a cache unit or a tightly coupled storage unit, but not both at the same time. The current storage unit may store a valid current jump instruction or an invalid current jump instruction.

[0070] Based on the branch prediction information, the current storage unit where the current jump instruction is located is determined from the cache unit and the tightly coupled storage unit. An optional method is: when the prediction result of the branch prediction information is that a jump occurs, the current storage unit where the current jump instruction is located is determined from the cache unit and the tightly coupled storage unit.

[0071] Exemplarily, when the prediction result of the branch prediction information JumpSignal_i is that a jump occurs, the current storage unit Storage Unit_i where the current jump instruction Instruction_i is located is determined to be an instruction tightly coupled storage unit from the instruction cache unit and the instruction tightly coupled storage unit.

[0072] Based on the branch prediction information, the current storage unit where the current jump instruction is located is determined from the cache unit and the tightly coupled storage unit, which provides a basis for fetching the instruction object for the subsequent acquisition of the current jump instruction.

[0073] Step 406: Based on the offset of the current program count value recorded by the program counter, fetch the current jump instruction from the current storage unit.

[0074] The current program counter value is the instruction address of the next instruction (the current jump instruction in the embodiment of this specification) updated by the program counter after the previous instruction is executed. For example, the current program counter value is 0x1000, indicating that the next instruction to be executed is located at address 0x1000. If the processor executes a jump instruction JMP 0x1010, the program counter will be updated to 0x1010, indicating that the next instruction to be executed is located at address 0x1010.

[0075] The current program counter value is offset from the instruction address of the previous instruction to the instruction address of the next instruction. This offset is usually fixed and depends on the processor architecture. In most processors, the length of instructions is fixed, so the offset is also a fixed value. For example, for a 32-bit processor, each instruction is 4 bytes long, so the offset is 4 bytes. For a 64-bit processor, the length of each instruction may be 8 bytes or more.

[0076] Based on the offset of the current program count value recorded by the program counter, the current jump instruction is taken out from the current storage unit. An optional method is: based on the offset of the current program count value recorded by the program counter, the instruction address is determined, and the instruction corresponding to the instruction address is taken out from the current storage unit as the current jump instruction.

[0077] Exemplarily, based on the offset of the current program count value 0x1000 recorded by the program counter, the instruction address is determined as 0x1000+ 4=0x1004, and the instruction corresponding to the instruction address (0x1004) is taken out from the instruction tightly coupled storage unit, the current storage unit Storage Unit_i, as the current jump instruction Instruction_i.

[0078] In the embodiments of the present specification, in the instruction fetch stage, based on the branch prediction information for the current jump instruction, one of the cache units and the tightly coupled storage units is directly determined as the current storage unit where the current jump instruction is located, and based on the offset of the current program count value recorded by the program counter, the current jump instruction is taken out from the current storage unit, and address comparison and instruction acquisition are no longer performed sequentially, thereby reducing timing pressure and increasing the main frequency of the processor. At the same time, it also effectively avoids the additional dynamic power consumption caused by the simultaneous acquisition of jump instructions by two branches, improves the performance of the processor when processing non-continuous instructions and the product endurance, and achieves more efficient and energy-saving instruction acquisition without sacrificing processing speed. It is suitable for application scenarios with high requirements for real-time performance and product endurance.

[0079] against Figure 3 The post-issuance selection scheme shown causes large dynamic power consumption when instructions are obtained simultaneously, affecting the battery life and heat dissipation of the processor. Targeted optimization can be performed based on Scheme 3, and one cache unit or a tightly coupled storage unit can be directly selected as the current storage unit to avoid obtaining instructions from two storage units at the same time, thereby reducing dynamic power consumption.

[0080] Correspondingly, in an optional embodiment of the present specification, step 404 includes the following specific steps: When the prediction result of the branch prediction information is that a jump occurs, the last storage unit where the last jump instruction is located is determined from the cache unit and the tightly coupled storage unit as the current storage unit where the current jump instruction is located.

[0081] The previous jump instruction is the jump instruction that was executed most recently before the current jump instruction.

[0082] The last storage unit where the last jump instruction is located is the storage unit that stores the last jump instruction and is the instruction fetch object of the instruction fetch stage of the last jump instruction. The last storage unit is either a cache unit or a tightly coupled storage unit, but not both. The last storage unit stores a valid last jump instruction.

[0083] Exemplarily, when the prediction result of the branch prediction information JumpSignal_i is that a jump occurs, the previous storage unit Storage Unit_(i-1) where the previous jump instruction Instruction_(i-1) is located is determined from the instruction cache unit and the instruction tightly coupled storage unit: the instruction tightly coupled storage unit is the current storage unit Storage Unit_i where the current jump instruction Instruction_i is located.

[0084] In the embodiments of this specification, a retransmission scheme is adopted to directly determine the previous storage unit where the previous jump instruction is located as the current storage unit where the current jump instruction is located, thereby avoiding obtaining instructions from two storage units at the same time, reducing timing pressure, increasing the main frequency of the processor, and improving the performance of the processor when processing non-continuous instructions and product endurance.

[0085] In an optional embodiment of the present specification, when the prediction result of the branch prediction information is that a jump occurs, before determining from the cache unit and the tightly coupled storage unit that the previous storage unit where the previous jump instruction is located is the current storage unit where the current jump instruction is located, the following specific steps are also included: receiving branch prediction information for an initial jump instruction; In the case where the branch prediction information records that the first jump instruction has jumped, determining that both the cache unit and the tightly coupled storage unit are first storage units; Based on the offset of the current program counter value recorded by the program counter, a first initial jump instruction is fetched from the cache unit, and based on the offset of the current program counter value recorded by the program counter, a second initial jump instruction is fetched from the tightly coupled storage unit; Compare the current program count value recorded by the program counter with the address range of the cache unit and the tightly coupled storage unit, and determine the valid initial storage unit from the cache unit and the tightly coupled storage unit; The first primary jump instruction or the second primary jump instruction from the valid primary storage unit is retained as the initial jump instruction.

[0086] The first jump instruction is the first jump instruction executed by the processor.

[0087] The branch prediction information for the first jump instruction is information predicting whether the first instruction is a jump instruction. The branch prediction information is the prediction for the first jump instruction output by the branch prediction unit, including the prediction result (jump or not jump), and may also include the source branch prediction unit. The branch prediction information is generally expressed as an electrical signal transmitted between component units in the processor.

[0088] The first storage unit is a storage unit that may store the first jump instruction. The first storage unit is a cache unit and a tightly coupled storage unit. When the jump instruction is executed for the first time, since there is no historical data (the last storage unit) to refer to, the processor needs to obtain the instruction from the cache unit and the tightly coupled storage unit at the same time to ensure integrity.

[0089] The first initial jump instruction is the initial jump instruction taken from the cache unit. The first initial jump instruction may be a valid initial jump instruction or an invalid initial jump instruction, which needs to be verified in a subsequent comparison address.

[0090] The second initial jump instruction is an initial jump instruction taken from the tightly coupled storage unit. The second initial jump instruction may be a valid initial jump instruction or an invalid initial jump instruction, which needs to be verified in a subsequent address comparison.

[0091] The address range of the cache unit is the address interval of the data and instructions stored in the cache unit. The address range of the cache unit is usually fixed and determined by the hardware design. The processor determines whether the first initial jump instruction obtained from the cache unit is a valid initial jump instruction by comparing the current program count value recorded by the program counter with the address range of the cache unit. The address range of the cache unit is 0x1000 to 0x1FFF.

[0092] The address range of the tightly coupled storage unit is the address interval of the data and instructions stored in the tightly coupled storage unit. The address range of the tightly coupled storage unit is usually fixed and determined by the hardware design. The processor determines whether the second initial jump instruction obtained from the tightly coupled storage unit is a valid initial jump instruction by comparing the current program count value recorded by the program counter with the address range of the tightly coupled storage unit. For example, the address range of the tightly coupled storage unit is 0x2000 to 0x2FFF.

[0093] The effective first storage unit is the first storage unit that is determined to store the first jump instruction. When executing the jump instruction for the first time, the processor needs to fetch the instructions from the cache unit and the tightly coupled storage unit respectively, and then compare the current program count value recorded by the program counter with the address range of the two storage units to determine which storage unit stores the first jump instruction is valid. The first jump instruction in the effective first storage unit will be retained and executed later.

[0094] Based on the offset of the current program count value recorded by the program counter, the first initial jump instruction is taken out from the cache unit. An optional method is: based on the offset of the current program count value recorded by the program counter, the instruction address is determined, and the instruction corresponding to the instruction address is taken out from the cache unit as the first initial jump instruction.

[0095] Based on the offset of the current program count value recorded by the program counter, a second initial jump instruction is taken out from the tightly coupled storage unit. An optional method is: based on the offset of the current program count value recorded by the program counter, an instruction address is determined, and the instruction corresponding to the instruction address is taken out from the tightly coupled storage unit as the second initial jump instruction.

[0096] Exemplarily, in the instruction fetch stage of the first instruction: the instruction fetch unit receives the branch prediction information JumpSignal_1 for the first jump instruction Instruction_1 output by the branch prediction unit: prediction result: jump occurs; source: branch unit. In the case where the branch prediction information JumpSignal_1 records that the first jump instruction jumps, it is determined that the instruction cache unit and the instruction tightly coupled storage unit are both the first storage unit Storage Unit_1. Based on the current program count value 0x0000 and offset 4 recorded by the program counter, the instruction address is determined: 0x0000+4=0x0004. The instruction corresponding to the instruction address (0x0004) is taken out from the instruction cache unit as the first first jump instruction Instruction_1.1, and the instruction corresponding to the instruction address (0x0004) is taken out from the instruction tightly coupled storage unit as the second first jump instruction Instruction_1.2. The address range of the instruction cache unit is 0x0000 to 0x0FFF. The address range of the instruction tightly coupled storage unit is 0x1000 to 0x1FFF. Comparing the target address 0x0004 with the address range of the instruction cache unit 0x0000 to 0x0FFF, it is found that the target address is within the address range of the instruction cache unit. Comparing the target address 0x0004 with the address range of the instruction tightly coupled storage unit 0x1000 to 0x1FFF, it is found that the target address is not within the address range of the instruction tightly coupled storage unit. Determine that the instruction cache unit is a valid primary storage unit. Keep the first primary jump instruction Instruction_1.1 from the valid primary storage unit as the initial jump instruction Instruction_1.

[0097] In the embodiments of the present specification, when a jump instruction is executed for the first time, instructions are taken out from the cache unit and the tightly coupled storage unit respectively, and the current program count value recorded by the program counter is compared with the address range of the two storage units to determine the effective initial storage unit. This ensures that the effective initial jump instruction is taken out from the correct storage unit, avoids the additional dynamic power consumption caused by obtaining instructions from two storage units at the same time, reduces timing pressure, improves the main frequency and energy efficiency of the processor, and improves the performance of the processor when processing non-continuous instructions and product endurance.

[0098] Although targeted optimization can be performed based on Solution 3, by directly selecting one of the cache units or the tightly coupled storage units as the current storage unit to avoid fetching instructions from two storage units at the same time and reduce dynamic power consumption, the instantaneous power consumption of the processor will still increase during the jump. If the source type of the branch prediction information is relatively stable, a speculative approach can be used to complete instruction fetching.

[0099] Correspondingly, in an optional embodiment of the present specification, step 404 includes the following specific steps: When the prediction result of the branch prediction information is that a jump occurs, a current storage unit where the current jump instruction is located is determined from the cache unit and the tightly coupled storage unit based on the source type of the branch prediction information.

[0100] The source type of branch prediction information is the output source of the branch prediction information, that is, which component unit generates the information that predicts whether the current instruction is a jump instruction. Different source types reflect different prediction mechanisms and prediction accuracies, and have different effects on the performance and power consumption of the processor. The source types of branch prediction information include but are not limited to: instruction retirement unit, branch unit, predictor (instruction fetch predictor and cache predictor), and program counter value increment.

[0101] It should be noted that according to the habit of using tightly coupled storage units, in common usage scenarios, key instructions, such as exception vector tables and exception handling functions, are stored in tightly coupled storage units. Jumps to such scenarios are usually triggered by instruction retirement units. Using this method can reduce the time to enter the exception and speed up the processing flow. Normally executed code generally enters from sources such as branch units and predictors, and does not require high latency, so the default cache unit is the current storage unit.

[0102] Exemplarily, when the prediction result of the branch prediction information JumpSignal_i is a jump, based on the source type of the branch prediction information JumpSignal_i: instruction retirement unit, from the instruction cache unit and the instruction tightly coupled storage unit, it is determined that the current storage unit Storage Unit_i where the current jump instruction Instruction_i is located is an instruction tightly coupled storage unit.

[0103] In the embodiments of the present specification, when the prediction result of the branch prediction information is a jump, based on the source type of the branch prediction information, the current storage unit where the current jump instruction is located is directly determined from the cache unit and the tightly coupled storage unit, which can effectively reduce the instantaneous power consumption of the processor, improve the prediction accuracy and processing performance, and effectively avoid the additional dynamic power consumption caused by the simultaneous acquisition of jump instructions by two branches while ensuring performance, thereby improving the performance of the processor when processing non-continuous instructions and product endurance.

[0104] In an optional embodiment of the present specification, when the prediction result of the branch prediction information is that a jump occurs, based on the source type of the branch prediction information, determining the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit includes the following specific steps: When the prediction result of the branch prediction information is that a jump occurs and the source type of the branch prediction information is a branch unit, the cache unit is determined to be a current storage unit where the current jump instruction is located.

[0105] The branch unit is a component unit in the processor used to predict jump instructions. It is responsible for analyzing branch conditions and predicting the direction of branches to reduce pipeline stalls caused by waiting for the results of jump instructions, thereby improving the execution efficiency of the processor. The main functions of the branch unit include: Branch condition analysis: Analyze the conditional flags of the jump instruction (such as zero flag Z, negative flag N, overflow flag V, etc.) to determine whether the branch condition is met. Branch prediction: Predict whether the instruction will jump based on historical data and current conditions. Common prediction algorithms include static prediction and dynamic prediction. Branch instruction address calculation: Calculate the instruction address of the jump instruction so that the instruction fetch unit can get the next instruction from the correct address. Branch history record: Maintain the branch history table (Branch History Table, referred to as BHT), record the behavior of past jump instructions, and use it for dynamic prediction.

[0106] Exemplarily, when the prediction result of the branch prediction information JumpSignal_i is a jump, based on the source type of the branch prediction information JumpSignal_i: branch unit, from the instruction cache unit and the instruction tightly coupled storage unit, it is determined that the current storage unit Storage Unit_i where the current jump instruction Instruction_i is located is the instruction cache unit.

[0107] In the embodiments of the present specification, when the prediction result of the branch prediction information is a jump and the source type of the branch prediction information is a branch unit, the cache unit is directly determined to be the current storage unit where the current jump instruction is located. This does not require high latency and can effectively reduce the instantaneous power consumption of the processor and improve prediction accuracy and processing performance.

[0108] In an optional embodiment of the present specification, when the prediction result of the branch prediction information is that a jump occurs, based on the source type of the branch prediction information, determining the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit includes the following specific steps: When the prediction result of the branch prediction information is that a jump occurs and the source type of the branch prediction information is an instruction retirement unit, the tightly coupled storage unit is determined to be the current storage unit where the current jump instruction is located.

[0109] The instruction retirement unit is a component unit in the processor responsible for confirming the execution results of instructions and updating the status. The instruction retirement unit ensures that the execution results of instructions are correctly submitted to the status of the processor, including updating the register and memory status. After confirming that the instruction is executed correctly, the instruction retirement unit will generate branch prediction information, especially for jump instructions, indicating whether the jump occurs. The main functions of the instruction retirement unit include: Confirm the execution results of instructions: Ensure that the instruction has been executed correctly and no exceptions or errors have occurred. Update status: Update the register and memory status to reflect the execution results of the instruction. Generate branch prediction information: For jump instructions, the instruction retirement unit will generate branch prediction information to indicate whether the jump occurs. Exception handling: Handle abnormal situations that may occur during the execution of instructions.

[0110] Exemplarily, when the prediction result of the branch prediction information JumpSignal_i is a jump, based on the source type of the branch prediction information JumpSignal_i: retired instruction unit, from the instruction cache unit and the instruction tightly coupled storage unit, it is determined that the current storage unit Storage Unit_i where the current jump instruction Instruction_i is located is an instruction tightly coupled storage unit.

[0111] In the embodiments of the present specification, when the prediction result of the branch prediction information is a jump and the source type of the branch prediction information is an instruction retirement unit, directly determining the tightly coupled storage unit as the current storage unit where the current jump instruction is located can reduce the time to enter the exception, speed up the processing flow, effectively reduce the instantaneous power consumption of the processor, and improve the prediction accuracy and processing performance.

[0112] In an optional embodiment of the present specification, when the prediction result of the branch prediction information is that a jump occurs, based on the source type of the branch prediction information, determining the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit includes the following specific steps: When the prediction result of the branch prediction information is a jump, and the source type of the branch prediction information is a predictor, the previous storage unit where the previous jump instruction is located is determined from the cache unit and the tightly coupled storage unit as the current storage unit where the current jump instruction is located.

[0113] The predictor is a component unit in the processor used to predict the address of the next instruction. The predictor predicts whether the jump instruction will jump and its target address by analyzing historical data and current conditions, so as to reduce the pipeline stall caused by waiting for the result of the jump instruction, thereby improving the execution efficiency of the processor. The main functions of the predictor include: Static prediction: prediction based on fixed rules, such as always predicting whether the jump instruction will jump or not. Dynamic prediction: prediction based on historical data, common dynamic prediction algorithms include: Local prediction: only consider the historical behavior of the current branch. Global prediction: consider the historical behavior of all branches. Hybrid prediction: combine local prediction and global prediction. Branch target buffer (Branch Target Buffer, referred to as BTB): used to store the target address of known jump instructions to speed up the calculation of branch target addresses. Branch history table: used to record the behavior of past jump instructions and support dynamic prediction.

[0114] In an optional embodiment of the present specification, the predictor is at least one of a pre-decoding predictor and a cache predictor.

[0115] The Instruction Pre-decode Predictor is a component unit in the processor that predicts the address of the next instruction during the instruction pre-decoding stage. It predicts whether a jump instruction will jump and its target address by analyzing historical data and current conditions, thereby reducing pipeline stalls caused by waiting for the jump instruction result, thereby improving the execution efficiency of the processor.

[0116] The Instruction Cache Predictor is a component unit in the processor used to predict cache access patterns. It predicts whether the next instruction or data will hit the cache by analyzing historical data and current conditions, so as to optimize the cache usage efficiency, reduce cache misses, and improve the execution efficiency of the processor.

[0117] Exemplarily, when the prediction result of the branch prediction information JumpSignal_i is that a jump occurs, based on the source type of the branch prediction information JumpSignal_i: pre-decoding predictor, it is determined from the cache unit and the tightly coupled storage unit that the previous storage unit Storage Unit_(i-1) where the previous jump instruction Instruction_(i-1) is located is the current storage unit Storage Unit_i where the current jump instruction Instruction_i is located.

[0118] In the embodiments of the present specification, when the prediction result of the branch prediction information is a jump and the source type of the branch prediction information is a predictor, the previous storage unit where the previous jump instruction is located is directly determined from the cache unit and the tightly coupled storage unit as the current storage unit where the current jump instruction is located. The latency requirement is not high, and the instantaneous power consumption of the processor can be effectively reduced, thereby improving the prediction accuracy and processing performance.

[0119] Since no address comparison is performed in steps 402 to 406, an erroneous current storage unit may be determined, resulting in an invalid instruction being obtained. Therefore, a check and correction can be performed in the instruction fetch stage. If an error occurs, the offset of the current program count value is resent, the current storage unit is updated, and the current jump instruction is re-obtained.

[0120] In an optional embodiment of the present specification, after step 406, the following specific steps are further included: Compare the current program count value recorded by the program counter with the address range of the current storage unit to determine whether it falls within the address range; If not, update another storage unit from the cache unit and the tightly coupled storage unit to be the current storage unit where the current jump instruction is located; Based on the offset of the current program counter value, the current jump instruction is fetched from the updated current storage unit.

[0121] The updated current storage unit is another storage unit updated after address comparison in the instruction fetch stage. This update process ensures the correctness and stability of instruction fetching and avoids instruction fetching failure caused by misprediction.

[0122] Exemplarily, the instruction fetch unit determines that the current storage unit is an instruction tightly coupled storage unit. Compare the current program counter value recorded by the program counter and the address range of the current storage unit: the current program counter value is 0x2000, and the address range of the instruction tightly coupled storage unit is 0x1000 to 0x1FFF. The comparison result shows that the current program counter value 0x2000 is not within the address range of the instruction tightly coupled storage unit, and the previous prediction is wrong. The instruction cache unit is updated to the current storage unit Storage Unit_i. Based on the offset of the current program counter value 0x2000, the current jump instruction is re-fetched from the instruction cache unit. Instruction_i.

[0123] In the embodiments of the present specification, after address comparison is performed in the instruction fetch stage, another storage unit is updated to be the current storage unit where the current jump instruction is located, thereby ensuring the correctness and stability of instruction fetching, avoiding instruction fetching failure due to incorrect prediction, and ensuring high efficiency and stability in application scenarios with high real-time and energy efficiency requirements.

[0124] Referring to the above embodiment, Figure 5 FIG. 1 shows one of the flow charts of an instruction acquisition method provided by an embodiment of the present specification, such as Figure 5 As shown: Critical instructions are non-continuous instructions such as jump instructions, which may cause a sudden change in the direction of the instruction flow.

[0125] In the program counter generation stage: after receiving the combinational logic of the branch prediction information for the initial jump instruction (instruction retirement unit jump, branch unit jump, pre-decoding predictor jump, cache predictor jump and program counter value increment), according to the current program counter value, the current instruction is sequentially executed from the cache unit and the tightly coupled storage unit respectively, and the address comparison is performed. According to whether the tightly coupled storage unit is hit, according to the current program count value, an access request is initiated to the cache unit or the tightly coupled storage unit.

[0126] In the instruction fetch stage: the initial jump instruction is taken from the cache unit or tightly coupled storage unit.

[0127] After that, in the program counter generation stage: after receiving the combinational logic of the branch prediction information for the current jump instruction (instruction retirement unit jump, branch unit jump, pre-decoding predictor jump, cache predictor jump and program counter value increment), when the prediction result of the branch prediction information is that a jump occurs, the previous storage unit where the previous jump instruction is located is determined from the cache unit and the tightly coupled storage unit to be the current storage unit where the current jump instruction is located, and it is determined that the tightly coupled storage unit is hit, and according to the current program count value, an access request is initiated to the cache unit or the tightly coupled storage unit.

[0128] In the instruction fetch stage: fetch the current jump instruction from the cache unit or tightly coupled storage unit, and determine whether an error occurs through address comparison. If an error occurs, feedback the result.

[0129] Figure 5 In the retransmission scheme shown, the address comparison is bypassed to reduce the timing pressure of the program counter generation stage, which can lead to an increase in the processor main frequency.

[0130] Referring to the above embodiment, Figure 6 FIG. 2 shows a flow chart of a method for acquiring instructions provided by an embodiment of the present specification. Figure 6 As shown: Critical instructions are non-continuous instructions such as jump instructions, which may cause a sudden change in the direction of the instruction flow.

[0131] In the program counter generation stage: after receiving the combinational logic of the branch prediction information for the current jump instruction (instruction retirement unit jump, branch unit jump, pre-decode predictor jump, cache predictor jump and program counter value increment), when the prediction result of the branch prediction information is that a jump occurs, based on the source type of the branch prediction information (instruction retirement unit, branch unit, pre-decode predictor, cache predictor), determine the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit, determine whether the tightly coupled storage unit is hit, and choose to initiate an access request to the cache unit or the tightly coupled storage unit.

[0132] In the instruction fetch stage: fetch the current jump instruction from the cache unit or tightly coupled storage unit, and determine whether an error occurs through address comparison. If an error occurs, resend it.

[0133] Figure 6 In the speculative scheme shown, the recording / inference selection branch path is selected, which greatly reduces dynamic power consumption and improves product endurance without reducing / slightly reducing performance. It is the preferred scheme when the speculation success rate is high.

[0134] against Figure 2 , Figure 3 , Figure 5 and Figure 6 Four options, Figure 7 A comparative schematic diagram of an instruction acquisition method provided by an embodiment of this specification is shown: Figure 2 The advance address determination scheme shown in , at the program counter generation stage: Select jump target; compare addresses; select current storage unit; send access request.

[0135] In the instruction fetch phase: Get the current jump instruction.

[0136] Among them, address comparison is the source of timing pressure. This part of the logic is more complex than other parts, and too many levels of superposition with other logic will affect the processor's main frequency.

[0137] Figure 3 The post-issuance selection scheme shown in , at the program counter generation stage: Select the jump target; compare the address and send the request as the current storage unit; send the access request.

[0138] In the instruction fetch phase: Get the current jump instruction; select the source based on the address comparison result.

[0139] Among them, address comparison is the source of timing pressure. This part of the logic is more complex than other parts, and too many levels of superposition with other logic will affect the processor frequency. At the same time, as the current storage unit sends a request, it is the source of increased power consumption. At the same time, the tightly coupled storage unit and cache unit are accessed, but only the instruction data of one of them is used, and the other is discarded, which will lead to power consumption waste.

[0140] Figure 5 The retransmission scheme shown in , during the program counter generation phase: Select the jump target; compare the addresses and send a request as the current storage unit; after the first time, send an access request based on the comparison result.

[0141] In the instruction fetch phase: Get the current jump instruction; record the comparison result; select the source according to the address comparison result.

[0142] Among them, address comparison is the source of timing pressure. This part of the logic is more complex than other parts, and too many levels of superposition with other logic will affect the processor frequency. At the same time, as the current storage unit sends a request, it is a source of increased power consumption. At the same time, the tightly coupled storage unit and cache unit are accessed, but only the instruction data of one of them is used, and the other is discarded, which will cause power consumption waste. The record comparison result depends on the principle of locality. The instruction source after the jump will not switch, but if it switches, it will not cause an error. The instruction will be resent to select another branch path.

[0143] Figure 6 The speculative scheme shown in , during the program counter generation phase: Select the jump target; compare the addresses and determine the current storage unit based on the source; after the first time, issue an access request based on the comparison result.

[0144] In the instruction fetch phase: Get the current jump instruction; record the comparison result; select the source according to the address comparison result.

[0145] Among them, the current storage unit is determined according to the source, and the tightly coupled storage unit or cache unit is selected for access, which saves power consumption. At the same time, the current storage unit sends a request, which is a source of increased power consumption. At the same time, the tightly coupled storage unit and the cache unit are accessed at the same time, but only the instruction data of one of them is used, and the other is discarded, which will cause power consumption waste. The record comparison result depends on the principle of locality. The instruction source after the jump will not switch, but if it switches, it will not cause an error. The instruction will be resent to select another branch path.

[0146] In summary, Figure 5 and Figure 6 The solution combines retransmission and speculation strategies to ensure that the performance does not decrease or decreases slightly, while significantly reducing the dynamic power consumption of the processor, enabling it to have higher performance, longer product life and lower heat dissipation requirements on embedded devices and edge computing devices.

[0147] Corresponding to the above method embodiment, this specification also provides a processor embodiment, Figure 8 FIG. 1 shows a schematic diagram of a processor structure provided by an embodiment of the present specification. Figure 8 As shown, the processor 800 includes an instruction fetch unit 810, a cache unit 820, a tightly coupled storage unit 830 and a program counter 840; The instruction fetch unit 810 is used to receive branch prediction information for the current jump instruction, determine the current storage unit where the current jump instruction is located from the cache unit 820 and the tightly coupled storage unit 830 based on the branch prediction information, and fetch the current jump instruction from the current storage unit based on the offset of the current program count value recorded by the program counter 840.

[0148] In the embodiments of the present specification, in the processor, the instruction fetch unit directly determines one of the cache units and the tightly coupled storage units as the current storage unit where the current jump instruction is located based on the branch prediction information for the current jump instruction during the instruction fetch stage, and fetches the current jump instruction from the current storage unit based on the offset of the current program count value recorded by the program counter. Address comparison and instruction acquisition are no longer performed sequentially, which reduces timing pressure and increases the main frequency of the processor. At the same time, it effectively avoids the additional dynamic power consumption caused by the simultaneous acquisition of jump instructions by two branches, improves the performance and product endurance of the processor when processing non-continuous instructions, and achieves more efficient and energy-saving instruction acquisition without sacrificing processing speed. It is suitable for application scenarios with high requirements for real-time performance and product endurance.

[0149] The above is a schematic solution of a processor of this embodiment. It should be noted that the technical solution of the processor and the technical solution of the above instruction acquisition method belong to the same concept, and the details not described in detail in the technical solution of the processor can be referred to the description of the technical solution of the above instruction acquisition method.

[0150] Corresponding to the above-mentioned embodiment of the instruction acquisition method, this specification also provides an embodiment of the system on chip, Fig. 9 A schematic diagram of the structure of a system on chip provided by an embodiment of the present specification is shown. The system on chip 900 includes but is not limited to a control unit 910 and multiple on-chip components 920 . The multiple on-chip components 920 include a processor 9210 .

[0151] The control unit 910 is used to control and manage multiple on-chip components 920 .

[0152] The processor 9210 is used to execute a computer program / instruction, which implements the steps of the above-mentioned instruction acquisition method when executed by the processor 9210.

[0153] The system on chip 900 is a chip system-level hardware device that integrates a control unit 910 and multiple on-chip components 920. It usually integrates a control unit 910, a central processor, a digital signal processor, a processor, and multiple on-chip components 920 such as an input / output interface (I / O). The system on chip 900 can improve performance, reduce power consumption, and reduce physical size, and can be applied to a variety of scenarios such as mobile devices, Internet of Things devices, embedded systems, and edge computing devices. The specific embodiments of this application do not limit the specific implementation of the system on chip.

[0154] The control unit 910 is a core component of the system on chip 900, responsible for decoding instructions, controlling the execution process, and coordinating with multiple on-chip components 920. The control unit 910 controls and manages the workflow of multiple on-chip components 920 by sending control signals to ensure that each on-chip component can correctly complete the task according to the predetermined order and logic.

[0155] The plurality of on-chip components 920 are various functional hardware components in the system on chip 900, which work together to complete specific tasks or functions. The plurality of on-chip components 920 may include, but are not limited to, a central processing unit, a digital signal processor, a processor, and an input-output interface.

[0156] The above is a schematic scheme of a system on chip of this embodiment. It should be noted that the technical scheme of the system on chip and the technical scheme of the above instruction acquisition method belong to the same concept, and the details not described in detail in the technical scheme of the system on chip can be referred to the description of the technical scheme of the above instruction acquisition method.

[0157] Corresponding to the above-mentioned instruction acquisition method and the embodiment of the system on chip, this specification also provides an embodiment of a computing device, Fig.10 The schematic diagram of the structure of a computing device provided by an embodiment of the present specification is shown. The computing device 1000 includes but is not limited to a memory 1010 and a system on chip 1020 .

[0158] The memory 1010 is used to store computer programs / instructions.

[0159] The system on chip 1020 is used to execute the following computer program / instruction, which implements the steps of the above instruction acquisition method when executed by the system on chip 1020.

[0160] The computing device 1000 is an electronic device with computing capabilities, capable of running various software programs to complete specific functions or tasks. The computing device 1000 generally includes a memory 1010 and a hardware device for performing tasks. In the embodiments of this specification, the computing device 1000 includes but is not limited to a system on chip 1020 and a memory 1010. The specific embodiments of this application do not limit the specific implementation of the computing device.

[0161] The memory 1010 is a component in the computing device 1000 for storing data and computer programs / instructions, and is generally divided into two types: volatile and non-volatile. Volatile memory (such as RAM) will lose data after power failure and is mainly used to temporarily store running programs and data; non-volatile memory (such as ROM, flash memory) can still retain data after power failure and is used to store firmware and persistent data.

[0162] The above is a schematic scheme of a computing device of this embodiment. It should be noted that the technical scheme of the computing device and the technical scheme of the above instruction acquisition method belong to the same concept, and the details not described in detail in the technical scheme of the computing device can be referred to the description of the technical scheme of the above instruction acquisition method.

[0163] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0164] The computer program / instructions include computer program code, which may be in source code form, object code form, executable file, or some intermediate form.

[0165] It should be noted that, for the convenience of description, the aforementioned method embodiments are all described as a series of action combinations, but those skilled in the art should be aware that the embodiments of this specification are not limited by the order of the actions described, because according to the embodiments of this specification, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the embodiments of this specification.

[0166] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0167] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The optional embodiments do not describe all the details in detail, nor do they limit the invention to only the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of the embodiments of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of this specification, so that technicians in the relevant technical field can well understand and use this specification. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. An instruction acquisition method, applied to an instruction fetch unit of a processor, wherein the processor further includes a cache unit, a tightly coupled storage unit and a program counter, comprising: receiving branch prediction information for the current jump instruction; Based on the branch prediction information, determining a current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit; The current jump instruction is fetched from the current storage unit based on the offset of the current program count value recorded by the program counter.

2. The method according to claim 1, wherein determining the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit based on the branch prediction information comprises: When the prediction result of the branch prediction information is that a jump occurs, the previous storage unit where the previous jump instruction is located is determined from the cache unit and the tightly coupled storage unit as the current storage unit where the current jump instruction is located.

3. The method according to claim 2, when the prediction result of the branch prediction information is that a jump occurs, before determining from the cache unit and the tightly coupled storage unit that the previous storage unit where the previous jump instruction is located is the current storage unit where the current jump instruction is located, further comprises: receiving branch prediction information for an initial jump instruction; In a case where the branch prediction information records that the first jump instruction has jumped, determining that both the cache unit and the tightly coupled storage unit are first storage units; fetching a first initial jump instruction from the cache unit based on an offset of a current program count value recorded by the program counter, and fetching a second initial jump instruction from the tightly coupled storage unit based on an offset of a current program count value recorded by the program counter; Comparing the current program count value recorded by the program counter with the address range of the cache unit and the tightly coupled storage unit, and determining a valid initial storage unit from the cache unit and the tightly coupled storage unit; The first initial jump instruction or the second initial jump instruction from the effective initial storage unit is retained as an initial jump instruction.

4. The method according to claim 1, wherein determining the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit based on the branch prediction information comprises: When the prediction result of the branch prediction information is that a jump occurs, a current storage unit where the current jump instruction is located is determined from the cache unit and the tightly coupled storage unit based on the source type of the branch prediction information.

5. The method according to claim 4, wherein when the prediction result of the branch prediction information is that a jump occurs, determining the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit based on the source type of the branch prediction information comprises: When the prediction result of the branch prediction information is that a jump occurs and the source type of the branch prediction information is a branch unit, the cache unit is determined to be a current storage unit where the current jump instruction is located.

6. The method according to claim 4, wherein when the prediction result of the branch prediction information is that a jump occurs, determining the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit based on the source type of the branch prediction information comprises: When the prediction result of the branch prediction information is that a jump occurs and the source type of the branch prediction information is an instruction retirement unit, the tightly coupled storage unit is determined to be the current storage unit where the current jump instruction is located.

7. The method according to claim 4, wherein when the prediction result of the branch prediction information is that a jump occurs, determining the current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit based on the source type of the branch prediction information comprises: When the prediction result of the branch prediction information is a jump and the source type of the branch prediction information is a predictor, the previous storage unit where the previous jump instruction is located is determined from the cache unit and the tightly coupled storage unit as the current storage unit where the current jump instruction is located.

8. The method of claim 7, wherein the predictor is at least one of a pre-decoding predictor and a cache predictor.

9. The method according to any one of claims 1 to 8, after fetching the current jump instruction from the current storage unit based on the offset of the current program count value recorded by the program counter, further comprising: Comparing the current program count value recorded by the program counter with the address range of the current storage unit to determine whether it falls within the address range; If not, updating another storage unit from the cache unit and the tightly coupled storage unit to be the current storage unit where the current jump instruction is located; The current jump instruction is fetched from the updated current storage unit based on the offset of the current program counter value.

10. A processor comprising an instruction fetch unit, a cache unit, a tightly coupled storage unit and a program counter; The instruction fetch unit is used to receive branch prediction information for a current jump instruction, determine a current storage unit where the current jump instruction is located from the cache unit and the tightly coupled storage unit based on the branch prediction information, and fetch the current jump instruction from the current storage unit based on an offset of a current program count value recorded by the program counter.

11. A system on chip, comprising: a control unit and a plurality of on-chip components, the plurality of on-chip components including a processor; The control unit is used to control and manage the multiple on-chip components, and the processor is used to execute computer programs / instructions. When the computer programs / instructions are executed by the processor, the steps of the method according to claims 1 to 9 are implemented.

12. A computing device comprising: Memory and System-on-Chip; The memory is used to store computer programs / instructions, and the system on chip is used to execute the computer programs / instructions. When the computer program / instructions are executed by the system on chip, the steps of the method according to claims 1 to 9 are implemented.

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