Dynamically composable computing system, data center and method for dynamically composing computing system

Abstract

The present disclosure relates to a dynamically composable computing system comprising a computing fabric comprising a plurality of different deaggregated computing hardware resources having respective hardware characteristics. The resource manager has access to respective hardware characteristics of the different deaggregated computing hardware resources and is configured to assemble the composite computing node by selecting one or more deaggregated computing hardware resources having respective hardware characteristics that meet requirements of an application to be executed on the composite computing node. The orchestrator is configured to schedule applications using the assembled composite computing nodes.

Description

[0001] This application is a divisional application of the patent application with the same name as application number 201810218398.4 filed on March 16, 2018. Technical Field

[0002] The present disclosure relates generally to configurable or composable computing resources. Background Art

[0003] Software Defined Infrastructure (SDI) is a technological advancement that enables new ways to operate a shared pool of configurable computing resources deployed in a data center or as part of a cloud infrastructure. SDI can allow individual elements of a configurable computing resource system to be composed with software. These elements can include depolymerized physical elements (hardware), such as CPUs, memory, network input / output devices, or storage devices. Elements can also include constituent elements, which can include various numbers of physical elements or combinations of physical elements composed to form logical servers, which can support virtual elements arranged to implement service / workload elements.

[0004] The virtual elements of SDI can be ordered to form a service chain. Generally, each virtual element of the service chain will have different performance limitations. As a result, the virtual element will become a bottleneck in the overall performance of the service chain. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Some examples of apparatus and / or methods will be described below, by way of example only, and with reference to the accompanying drawings, in which

[0006] Figure 1A and Figure 1B Combined to form FIG1 , which shows an example first system;

[0007] Figure 2A and Figure 2B Combined to form Figure 2, showing an example of assembling a composite node;

[0008] Figure 3A and Figure 3B Combine to form Figure 3 , shows an example of assembling a composite node based on the hardware requirements of an application;

[0009] Figure 4 A resource manager is shown that includes a storage device that stores metadata indicative of hardware characteristics associated with a plurality of different distributed disaggregated hardware resources;

[0010] Figure 5 A block diagram of an example computing sled is shown;

[0011] Figure 6A flow chart showing a method for dynamically composing a computing system is shown;

[0012] Figure 7 An example of a storage medium is shown; and

[0013] Figure 8 An example of a computing platform is shown. DETAILED DESCRIPTION

[0014] Various examples will now be described more fully with reference to the accompanying drawings, in which some examples are shown. In the accompanying drawings, the thickness of lines, layers and / or regions may be exaggerated for clarity.

[0015] Therefore, although other examples are capable of various modifications and alternative forms, some specific examples thereof will be shown in the figures and will be described in detail later. However, this detailed description does not limit other examples to the specific forms described. Other examples will cover all modifications, equivalents and alternatives that fall within the scope of the present disclosure. Throughout the description of the drawings, like numbers represent the same or similar elements, which can be implemented in an equivalent or modified form when compared to each other while providing the same or similar functions.

[0016] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled or connected or coupled via one or more intermediate elements. If two elements A and B are combined using "or", this should be understood to disclose all possible combinations, i.e., only A, only B, and A and B. An alternative term for the same combination is "at least one of A and B". The same applies to combinations of more than two elements.

[0017] The terminology used herein for describing a particular example is not intended to limit other examples. Whenever singular forms such as "one", "an" and "the" are used and only a single element is neither explicitly nor implicitly defined as mandatory, other examples can also use multiple elements to implement the same function. Similarly, when the function is subsequently described as being implemented using multiple elements, other examples can use a single element or processing entity to implement the same function. It will be further understood that the terms "include", "include", "include" and / or "include" specify the presence of the features, integers, steps, operations, processes, actions, elements and / or components when used, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, actions, elements, components and / or any group thereof.

[0018] Unless otherwise defined, all terms (including technical and scientific terms) are used herein according to the common meaning of the art to which they belong.

[0019] Over the past decade, the tremendous growth in demand for Internet and mobile services has driven a rapid transformation of digital business. This growth has been extremely disruptive; it has created new business opportunities and challenged the status quo. In the data center, two forces have produced many of these changes: the evolution of virtualization and the rise of cloud computing. However, these forces represent only two of three key elements that will drive competitive advantage moving forward. The third element and the missing piece is the flexible compute, storage, and network fabrics that will usher in the era of truly agile digital infrastructure. Virtualization has set the stage for agile infrastructure. It enables elastic horizontal scaling, seeding cloud computing, and creating new standard computing units, such as virtual machines, which can be installed on one server or across multiple servers. The growth of virtualization has been complemented by the expansion of various types of cloud computing infrastructure services: infrastructure as a service, platform as a service, and the most popular form, software as a service. By creating the potential for massive scalability, cloud computing has created new business models and changed the context for existing business models. Businesses are increasingly relying on the cloud, not only for lower total cost of ownership, but also for greater return on investment as they increasingly seek to use the cloud's flexibility to realize business benefits, reach their customers anywhere in the world, and accelerate their ability to evolve to meet customer needs.

[0020] However, today's infrastructure cannot effectively handle the complexity of managing an increasing number of computing resources that may exist anywhere in the world, nor can it help address the need for rapid changes and the introduction of new product features and capabilities. This creates the need to add a software abstraction layer on top of the architecture in order to scale and adapt it to the needs of the time. Traditional data center architectures include a set of different heterogeneous or homogeneous platforms (also known as computing nodes or servers), which are statically composed of a set of local resources (such as computing, memory, storage devices, computing structures or accelerators) and can have access to disaggregated resources (such as storage devices or accelerators) through computing structures. One of the main advantages provided by these architectures is the ease and manageability of maintenance. However, they lack adaptability, configurability and scalability. As previously mentioned, most data center requirements and workloads have evolved over the past few decades, with a greater number of needs, characteristics and dynamics. In order to meet these new needs, the SDI architecture is promoted to provide a mechanism that allows the dynamic creation of platforms in which applications are executed.

[0021] As contemplated by the present disclosure, each workload can be performed using a shared pool of configurable resources, such as computing hardware resources in a data center. These workloads can be implemented using software-defined architecture (SDI), software-defined network (SDN) or other virtualization technologies. Generally, the present disclosure provides a process and device for managing the allocation of computing hardware resources for these various workloads. For example, the present disclosure provides a controller that is configured to allocate computing hardware resources with corresponding hardware characteristics that meet the predefined (hardware) requirements of the workload to be executed on the assembled composite computing node. The examples of the present disclosure can allocate cache space (e.g., L3 cache, etc.), memory bandwidth and / or input and output (I / O) bandwidth to various workloads. In some examples, the controller can allocate such resources based on performance requirements and / or the relative priority of the workload. Such performance targets and / or workload priorities can be specified by, for example, service level agreements (SLAs), etc.

[0022] Examples of the present disclosure provide management and allocation of shared computing resources at a "fine-grained" level compared to current technologies. Therefore, examples of the present disclosure can achieve higher binding density of workloads, better management of resources to meet performance goals, and better management on a per-workload basis (e.g., process flow, virtual machine (VM), virtual network function (VNF), container, etc.). In particular, the present disclosure provides management or resource allocation on a per-workload basis, which is different from limiting the number of workloads per platform or limiting resource usage per workload.

[0023] In some examples, the controller can be configured to allocate resources, adjust resource allocation, rebalance resource allocation, and / or migrate a service chain to another server or portion of a configurable computing resource. The controller can be configured to receive a policy including an indication of hardware requirements for a plurality of service chains. The controller can also be configured to receive performance information including an indication of performance of the service chains and adjust resource allocation based on the received policy, hardware requirements, and relative priorities between the service chains.

[0024] 1 illustrates an example first dynamically configurable computing system 100. Computer system 100 and associated components may be housed in a data center.

[0025] In some examples, the system 100 may include a plurality of different disaggregated computing hardware resources 110, composite computing nodes 120, virtualization elements 130, workload elements 140, and resource balancers or managers 150. Here, disaggregated computing hardware resources may also be understood as separate or distributed computing hardware resources that may be located in different rack drawers or racks, respectively. Each disaggregated computing hardware resource 110 has corresponding hardware characteristics associated therewith, such as, for example, processing performance (e.g., clock rate), power consumption, bandwidth (e.g., memory and / or storage device bandwidth), latency, capacity (e.g., memory and / or storage device capacity), underlying technology (e.g., volatile versus non-volatile memory, DRAM versus 3-dimensional (3D) crosspoint memory versus storage device, NAND storage device versus hard disk storage, etc.), and cost. The resource manager 150 has access to information about the respective hardware characteristics of the different disaggregated computing hardware resources 110, and is configured to assemble a composite computing node 120 by selecting or allocating one or more disaggregated computing hardware resources 110 having respective hardware characteristics that meet the requirements of an application (e.g., a service chain 142) to be executed on the assembled composite computing node 120. Once all of the disaggregated computing hardware resources 110 are assembled to create a composite node 120 or virtualization element 130, an operating system (OS) may be booted and a service chain or application 140 may be instantiated.

[0026] According to an example of the present disclosure, the resource manager 150 may include a data structure 155 storing hardware characteristics of individual disaggregated computing hardware resources 110, such as performance, capacity, technical characteristics, and cost of each different disaggregated computing hardware resource 110. For example, the resource manager 150 may include a data structure 155 that may be configured to store metadata indicating hardware characteristics associated with a plurality of different distributed disaggregated hardware resources 110. The resource manager 150 may also provide a mechanism that can be used by the disaggregated computing hardware resources 110 to register their corresponding hardware characteristics, such as performance, capacity, and technical characteristics, with the resource manager 150, for example, at the time of data center boot. For example, when a new hardware resource is added to the disaggregated hardware resource pool, the newly added hardware resource may send a registration request message including information about its hardware characteristics to the resource manager 150. The newly added hardware resource, along with its hardware characteristic information, may then be registered or stored in the resource manager 150. Instead of this automated process, it may also be that a human system administrator may input the hardware characteristic information of the newly added hardware into the resource manager 150. In this manner, resource manager 150 may expose new resource selection policies to an orchestrator for scheduling service chains or applications that allows for specification of requirements for computing hardware resources associated with composite compute nodes 120 .

[0027] According to some examples, as shown in FIG. 1 , the disaggregated computing hardware resources 110 may include CPUs 112-1 to 112-n, where “n” is any positive integer greater than 1. CPUs 112-1 to 112-n may individually represent a single microprocessor or may represent individual cores of a multi-core microprocessor. The disaggregated computing hardware resources 110 may also include memories 114-1 to 114-n. Memories 114-1 to 114-n may represent various types of memory devices, such as but not limited to dynamic random access memory (DRAM) devices that may be included in dual in-line memory modules (DIMMs) or may also include other configurations of non-volatile memory such as but not limited to non-volatile memory such as 3D cross-point memory using chalcogenide phase change materials (e.g., chalcogenide glass). A person skilled in the art who benefits from the present disclosure will appreciate that the term memory refers to a component that allows short-term data access (volatile memory). The disaggregated computing hardware resources 110 may also include storage devices 116-1 to 116-n. Storage devices 116-1 to 116-n may represent various types of storage devices such as hard disk drives (HDDs) or solid-state drives (SSDs). A person skilled in the art who will benefit from this disclosure will appreciate that the term storage device refers to a component (non-volatile storage device) that allows long-term data access. The disaggregated computing hardware resources 110 may also include so-called computing modules, which include a configuration of local computing hardware resources such as a set of CPUs and a certain amount of computer memory. In some examples, a computing module may include a static predetermined configuration of local computing hardware resources such as a fixed set of CPUs and a fixed amount of memory. The disaggregated computing hardware resources 110 may also include network (NW) input / output (I / O) 118-1 to 118-n. NW I / O 118-1 to 118-n may include a network interface card (NIC) having one or more NW ports w / associated media access control (MAC) functions for network connections within or outside the system 100. The disaggregated computing hardware resources 110 may also include NW switches 119-1 to 119-n. The NW switches 119 - 1 to 119 - n may be capable of routing data via internal or external network links for elements of the system 100 .

[0028] In some examples, as shown in FIG. 1 , the composite computing node 120 may include one or more logical servers 122-1 to 122-n. In other words, the logical server 122 may be considered as a composite computing node assembled or composed of disaggregated computing hardware resources 110. As described above, the logical server 122 may be composed according to the (hardware) requirements of one or more applications (e.g., service chain 142) to be executed on the logical server 122. For these examples, groups of CPUs, memories, storage devices, NW I / Os, or NW switching elements from the disaggregated computing hardware resources 110 may be composed to form logical servers 122-1 to 122-n. Each logical server 122-1 to 122-n may include any number of CPUs, memories, storage devices, NW I / Os, or NW switching elements, or a combination thereof. Unlike conventional mechanisms, the disaggregated computing hardware resources 110 that form the composite computing node 120 are exposed as local resources to the software stack or application running on the composite node. Hence, while they may be distributed across multiple pools of hardware resources across data centers, the proposed SDI architecture provides the illusion of executing applications on a traditional platform with the exact requirements provided by the application / user. Once the application completes its execution, the composite nodes can be decomposed.

[0029] According to some examples, as shown in FIG. 1, the virtualization element 130 may include a plurality of virtual machines (VMs) 132-1 to 132-n, virtual switches (vSwitches) 134-1 to 134-n, virtual network functions (VNFs) 136-1 to 136-n, or containers 138-1 to 138-n. It should be appreciated that the virtual element 130 may be configured to implement a variety of different functions and / or execute a variety of different applications. For example, VM 132-a may be any of a variety of virtual machines configured to operate or behave as a specific machine and may execute a separate operating system as part of the VM. VNF 136-a may be any of a variety of network functions, such as packet inspection, intrusion detection, accelerators, etc. Container 138-a may be configured to execute or perform a variety of applications or operations, such as, for example, email processing, web services, application processing, data processing, etc.

[0030] In some examples, the virtualized elements 130 may be arranged to form service chains 142, also referred to as workloads, process flows, or applications. For example, service chains 142-1 and 142-2 may include VNFs 136-1 to 136-3 and 136-4 to 136-6, respectively. In addition, the individual virtual elements of the service chains may be connected via a vSwitch 134. Furthermore, in some examples, each virtualized element 130 for any number of service chains 142 may be supported by a given logical server in the logical servers 122-1 to 122-n of the composite computing node 120. For example, the logical server 122-1 may be formed by a disaggregated physical element of a CPU 112-1 with a cache, a memory 114-1, and a NW I / O 118-1. Thus, each service chain supported by the logical server 122-1 may be configured to operate using a portion of the computing resources of the logical server 122-1 (e.g., CPU 112-1, memory 114-1, NW I / O 118-1, etc.). In other words, a portion of the computing resources of the logical server 122-1 may be allocated to each service chain 142 supported by the logical server 122-1. According to an example of the present disclosure, the disaggregated computing hardware resources 110 are allocated to the logical servers 122 based on the respective hardware requirements of the service chains 142 to be executed by the logical servers 122. To this end, the resource manager 150 has stored information about the hardware characteristics of the respective disaggregated computing hardware resources 110.

[0031] In some examples, the resource manager 150 may be arranged to manage or control at least some aspects of the deaggregated computing hardware resources 110, the composite computing nodes 120, the virtualization elements 130, and the service chains 140. The resource balancer or manager 150, which may also be referred to as an SDI-manager, may be implemented by software, hardware, or some combination of the two. In some examples, it may be a hardware component of a data center. Therefore, it may include computer hardware components such as CPUs, memory devices, storage devices, I / O devices, display devices, etc. In some examples, the resource manager 150 is configured as a programmable hardware device, such as a digital signal processor (DSP) or a field programmable gate array (FPGA). The resource manager 150 may provide for sharing the deaggregated computing hardware resources 110 and the composite computing nodes 120 by the virtualization elements 130 and the service chains 140 based on the relative priorities of the virtualization elements 130 and the service chains 140. For example, resource manager 150 may be configured to coordinate the sharing of hardware resources (e.g., cache space, memory bandwidth, I / O bandwidth, etc.) in system 100 between virtualization elements 130 and / or various ones of service chains 140 based on the relative priorities of these elements.

[0032] Resource manager 150 may be configured to coordinate the sharing of resources between any workloads supported by the configurable resource pool represented by system 100. For example, resource manager 150 may coordinate the sharing of resources between virtualization elements 130, service chains 140, or any combination of these "workload elements." Although many of the examples provided herein use service chains 140, and in particular network virtualization functions (NVFs), as examples, this is not limiting.

[0033] The resource manager 150 can be configured to receive workload requirements for the workload elements 140 supported by the system 100 and coordinate the sharing of hardware resources between the workload elements 140 based on these workload requirements. The workload requirements can be provided by an orchestrator that aligns business requests with applications, data, and infrastructure. The orchestrator defines policies and service levels through automated workflows, provisioning, and change management. This creates an application-aligned infrastructure that can be scaled up or down based on the needs of each application. For example, the resource manager 150 can be configured to allocate a portion of a shared configurable resource pool (e.g., disaggregated computing hardware resources 110) to any number of workload elements 140 (or adjust its allocation). In addition, the resource manager 150 can be configured to relocate the workload element 140 from one logical server 122 to another logical server if the workload hardware requirements change.

[0034] The resource manager 150 may be configured to coordinate the resource sharing based on the workload requirements (e.g., hardware requirements) of the workload elements 140 and, alternatively or additionally, indications of relative priority between the workload elements 140. Examples of such situations are provided in more detail below. However, it is worth noting that the resource manager 150 may also be configured to coordinate sharing based on increasing throughput, decreasing latency, etc. Thus, the coordination of resource sharing described herein may result in improved data center performance and, in addition, increased density of workload elements 140 without sacrificing performance.

[0035] FIG. 2 illustrates an example of assembling a composite node 120 from disaggregated computing hardware resources 110 according to the present disclosure. In FIG. 2 , a resource manager 150 is operably coupled to an orchestrator 160, which is configured to schedule service chains or applications 142 running on the assembled composite computing nodes. In general, the orchestrator 160 is configured to implement policies and manage the entire system 200, in particular the cloud infrastructure in which the composite computing nodes (e.g., logical servers 122) are implemented. The orchestrator 160 may include or be configured with information including policies and indications of relative priorities or priority categories for each of the service chains 142-1 and 142-2. The policy may correspond to a workload element of the system 200 and / or a service level agreement (SLA) of a customer, etc. Thus, the policy may include hardware requirements for one or more service chains or applications 142 to be executed on the composite computing node or logical server 122. In some examples, the orchestrator 160 is configured to provide the hardware requirements of the application to the resource manager 150 for assembling the composite computing node of the application. Thus, orchestrator 160 may be viewed as a service chain or scheduler for application 142. Information including indications of policies and priorities may be communicated to resource manager 150 in order to select or compose sufficient logical servers 122 for application 142.

[0036] In the example of FIG. 2 , the resource manager 150 creates an example composite node 120 by connecting a computing module 210 including a certain amount of local CPUs 112-1, local memories 114-1, and local storage devices 116-1 to three units of disaggregated resources of type 1 provided by resource pool A, four units of resource type 2 provided by resource pool B, and five units of resource type n provided by resource pool M. In the example shown, different computing hardware resource pools include corresponding different types of disaggregated computer memories or storage devices. In addition, different computing hardware resource pools can be located, for example, in different rack drawers or in different racks in a data center. Different disaggregated memory or storage device hardware resources 110 can be connected to the computing module 210 via a computing structure 220.

[0037] In this particular example, it is assumed that the local processor 112-1 is hosted in a minimal platform form factor with a local resource called a compute module. Thus, in the example shown, the composite node 120 includes at least one compute module 210, which includes a (minimal) set of local computing hardware resources 112-1, 114-1, 116-1. The resource manager 150 is configured to connect the compute module 210 to the selected disaggregated memory or storage device hardware resources 110 via a compute structure 220. The local computing hardware resources of the compute module may include one or more local CPUs and one or more local memory modules. However, in another example, the CPU 112-1 may be pooled, as well as part of another hardware resource pool.

[0038] exist Figure 3 1 shows another example of using disaggregated memory or storage hardware resources 110 to assemble one or more composite nodes 120 according to predefined hardware requirements of application A. Those skilled in the art having benefit of this disclosure will appreciate that the hardware attributes of the disaggregated memory or storage hardware resources 110 shown are merely examples and may differ in other implementations.

[0039] The orchestrator 160 may be configured to determine the number of memory levels or storage tiers of the composite computing node to be equipped for the application based on the hardware requirements of the application. Figure 3In the example shown, for application A, there are two memory levels and two storage tiers, and application A also requires a total hardware cost of no more than 1200 cost units. Examples of cost units are financial cost units (e.g., dollars, euros, etc.) or energy cost units (e.g., kWh). Different memory levels or storage tiers can be associated with correspondingly different memory or storage device hardware resource characteristics. Here, it is assumed that storage tier 1 has a performance of 200 performance units, while storage tier 2 is assumed to have a lower performance of only 100 performance units. Examples of performance units are floating point operations per second (FLOPS), instructions per second (IPS), response time, etc. It is assumed that storage tier 1 has a capacity of 75 capacity units, while storage tier 2 is assumed to have a higher capacity of 200 capacity units. Examples of capacity units are bits or bytes, words, etc. It is assumed that storage tier 1 has a distance from the CPU corresponding to a waiting time of 400ns, while storage tier 2 is assumed to have a distance from the CPU corresponding to a higher waiting time of 2000ns. Assume that memory rank 1 has a performance of 100 performance units, while memory rank 2 is assumed to have a lower performance of only 80 performance units. Assume that memory rank 1 has a capacity of 10 capacity units, while memory rank 2 is assumed to have a higher capacity of 20 capacity units. Assume that memory rank 1 has a distance from the CPU corresponding to a latency of 300ns, while memory rank 2 is assumed to have a distance from the CPU corresponding to a higher latency of 800ns.

[0040] The list of different memory classes and storage tier requirements may be provided from orchestrator 160 to resource manager 150 to select appropriate memory or storage hardware resources for the corresponding composite node. For this purpose, resource manager 150 may be configured to associate one or more memory or storage hardware resources that meet the hardware resource characteristics of the corresponding requirements with the corresponding memory class or storage tier. For example, a specified memory or storage tier (e.g., Figure 3 The first of the memory levels 1) of the application A in the computing module may be associated with a local memory or storage device hardware resource of the computing module, and the memory or storage device layer (e.g., Figure 3 At least a second one of the memory levels 2) of the application A in the embodiment of the present invention may be associated with a dynamically configured disaggregated computing memory or storage device hardware resource. In addition, the corresponding memory / storage address range may be mapped to a corresponding memory level or storage layer.

[0041] Figure 4An example of a resource manager 150 having a storage device 155 for storing metadata indicating hardware characteristics associated with a plurality of different distributed disaggregated hardware resources is shown. In the example shown, the resource manager 150 includes: a first storage device 155-1 for storing metadata indicating hardware characteristics associated with a plurality of different disaggregated memory resources; and a second storage device 155-2 for storing metadata indicating hardware characteristics associated with a plurality of different disaggregated storage resources. It can be seen that the first storage device 155-1 can include entries regarding pool ID, resource ID, technical metadata (e.g., DRAM, 3D cross point memory, reliability, etc.), performance metadata (e.g., bandwidth, latency, etc.), and economic cost of the disaggregated memory hardware resources. Similarly, the second storage device 155-2 can include entries regarding pool ID, resource ID, technical metadata (e.g., NVM, reliability, etc.), performance data (e.g., bandwidth, latency, etc.), and economic cost of the disaggregated storage hardware resources. Thus, the first and second storage devices 155-1, 155-2 can be used to store data about different disaggregated memory and storage device resources available in a data center. These structures can save technical and performance data as well as economic costs.

[0042] The resource manager 150 may also include logic circuitry 156 that implements corresponding resource selection policies for memory and storage devices, which select different memory or storage device hardware resources for each specified layer based on the orchestrator request. For example, the resource manager 150 can be configured to associate a memory or storage device hardware resource with one of the specified memory or storage device tiers only when the associated hardware resource characteristics of the memory or storage device hardware resource fall within a predefined range of the corresponding memory or storage device tier. For example, the resource manager 150 can be configured to associate a memory or storage device hardware resource with one of the memory or storage device tiers only when the associated processing performance (e.g., cache, speed, clock rate, etc.) of the memory or storage device hardware resource falls within a predefined performance range of the corresponding tier. Figure 3 In the example of , only memories with a performance of at least 100 performance units should be associated with memory level 1. Additionally or alternatively, the resource manager 150 can be configured to associate a memory or storage hardware resource with one of the memory or storage tiers only when the underlying technology of the memory or storage hardware resource meets the predefined technical requirements of the corresponding tier. Additionally or alternatively, the resource manager 150 can be configured to associate a memory or storage hardware resource with one of the memory or storage tiers only when the associated cost of the memory or storage hardware resource falls below a predefined cost level for the corresponding tier.

[0043] As previously discussed, the resource manager 150 may include a resource selection strategy that can be used to select memory and storage devices for each level and layer using the provided requirements. For example, given a set of different memory or storage device levels {1,..,N} with a set of requirements iReq = {[PerfLowThr,PerfHighThr], [LatLowThr,LatHighThr]}, TechReqi = [Tech1,..,TechN]} and a maximum cost MAX_COST or MAX_COST_PER_LEVELi, the resource manager 150 can select a resource Resi (which is a resource memory or storage device) applicable to the memory or storage device level i that satisfies Perf(Resi) within [PerfLowThr,PerfHighThr], Lat(Resi) within [LatLowThr,LatHighThr], the technical requirements provided by the resource satisfy TechReqi, and the associated cost is less than or equal to MAX_COST / NumLevels or MAX_COST_PER_LEVELi (depending on how the resource is provided).

[0044] Additionally or alternatively, the selection of hardware resources may also take into account other types of resource selection strategies. For example, the resource manager 150 may also select hardware resources to reduce data center fragmentation using the unique restriction that the hardware resources will not violate the actual restrictions specified for each memory and storage device policy. The selection strategy may assume that the cost associated with local resources within a composite node (e.g., DDR or high bandwidth memory (HBM) within a computing module) is calculated by dividing the cost of a particular node by the memory / storage level that will be mapped from the computing module to the composite node. The resource manager 150 may allocate an SLA for disaggregated resources that share certain portions of an end-to-end path with other composite nodes. In this case, if there is any actual cost associated with the SLA for that particular resource, the cost will be added to the actual cost of the resource.

[0045] like Figure 5, the compute module 210 may include system address decoding programming logic 510 that can be used by the resource manager 150 to program the system address decoder 515 to map different memory and storage layers to corresponding SDI fabric interfaces 520 of the compute module 210. Thus, a caching agent (CA) 525 may be configured to redirect I / O and memory requests for each memory or storage layer to a remote disaggregated memory or storage device 110 or a local memory or storage device 530. In addition, the compute module 210 may include a set of control registers (e.g., model specific registers, MSRs) 535 that are configured by the resource manager 150 when the composite node 120 is composed to specify how many memory and storage layers are available, their characteristics, and the memory ranges mapped to them. Thus, the resource manager 150 may be configured to specify the selected disaggregated computing hardware by writing to the control registers 535 of the compute module 210. Thus, the set of control registers 535 indicates at least one of the number of memory or storage layers, the corresponding hardware characteristics, and the group of corresponding memory / storage address ranges.

[0046] This can be used by the operating system to correctly display each memory and storage device layer to the application. The application can use those control registers 535 to understand the performance implications of each layer. In some examples, the platform can expose the following control registers 535-1 for k memory levels:

[0047] {MSR_MEM_1LM_BW, MSR_MEM_1LM_LAT, MSR_MEM_1LM_TECHOLOGY}

[0048] …

[0049] {MSR_MEM_kLM_BW, MSR_MEM_kLM_LAT, MSR_MEM_kLM_TECHOLOGY}

[0050] Here, register MSR_MEM_kLM_BW is used to indicate the memory bandwidth of memory rank k. Register MSR_MEM_kLM_LAT is used to indicate the latency of memory rank k. Register MSR_MEM_kLM_LAT is used to indicate the memory technology of memory rank k.

[0051] In some examples, the platform may expose the following control registers 535 - 2 for k storage tiers: {MSR_STO_1TIER_BW, MSR_STO_1TIER_LAT, MSR_STO_1TIER_TECHOLOGY}

[0052] …

[0053] {MSR_STO_kTIER_BW, MSR_STO_kTIER_LAT, MSR_STO_kTIER_TECHOLOGY}

[0054] Here, MSR_STO_kTIER_BW is used to indicate the bandwidth of storage tier k. Register MSR_STO_kTIER_LAT is used to indicate the latency of storage tier k. Register MSR_STO_kTIER_TECHOLOGY is used to indicate the memory technology of storage tier k. A person skilled in the art who has benefited from this disclosure will appreciate that register 535 is one of various alternatives for the OS or application to discover how the tiering is accomplished. However, other methods such as discovering or querying the orchestrator through the resource manager (SDI manager) 159 are also contemplated.

[0055] Those skilled in the art who have benefited from the present disclosure will appreciate that the apparatus described above is configured to implement a method for dynamically composing a computing system based on a plurality of different disaggregated computing hardware resources 110 having corresponding hardware characteristics. Figure 6 An example of this method 600 is shown in FIG.

[0056] The method 600 includes storing 610 information about respective hardware characteristics of different disaggregated computing hardware resources 110, and assembling 620 a composite computing node 120 by selecting, based on the stored information, one or more disaggregated computing hardware resources 110 having respective hardware characteristics that meet the requirements of an application to be executed on the composite computing node. As previously described, the information about the respective hardware characteristics may be stored in the resource manager 150. In this manner, the resource manager 150 may assemble the composite computing node 120 according to the hardware requirements of the application assumed to be executed on the composite computing node.

[0057] In summary, the present disclosure provides functions to alleviate the complexity under SDI storage devices and memory architectures. Some examples relate to adaptive memory and storage device composition based on performance and cost for composable architectures. The architecture provides access to various types of memory and storage device disaggregation and local resources, each of which has different characteristics from the perspective of performance, capacity, cost and technology (such as reliability, volatility, etc.). The amount of data layers considered from an application perspective is much larger than that of traditional architectures. The possibility of creating composite nodes that meet the requirements of memory and storage device users will be very large (multiple ways to create composite nodes). In order to address the previous three areas, the present invention proposes to expand the existing resource manager, so that common features and methods can be provided for the software stack, so as to efficiently utilize and map the storage devices and memory layers and technologies provided by the SDI architecture while considering the cost implications.

[0058] This disclosure proposes a new data hierarchical model that allows orchestrators to:

[0059] (1) Dynamically define how many memory and storage tiers a given composite node will have;

[0060] (2) Associating each tier with a specific memory or storage device (local or disaggregated); (3) Mapping to each tier a given memory or storage address range that an application can use to access that specific tier.

[0061] (2) A resource selection algorithm implemented in the resource manager that allows for the selection of memory or storage based on performance, cost, capacity, and technology. This algorithm is used to select specific resources to be associated with each tier.

[0062] Figure 7 An example storage medium 700 is shown. Figure 7 As shown, the storage medium includes storage medium 700. Storage medium 700 may include an article of manufacture. In some examples, storage medium 700 may include any non-transitory computer-readable medium or machine-readable medium, such as an optical, magnetic or semiconductor storage device. Storage medium 700 may store various types of computer-executable instructions, such as instructions that implement logic flow 600. Examples of computer-readable or machine-readable storage media may include any tangible medium capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. Examples of computer-executable instructions may include any appropriate type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, etc. Examples are not limited in this context.

[0063] Figure 8 An example computing platform 800 is shown. In some examples, such as Figure 8 As shown, computing platform 800 may include processing components 840, other platform components 850, or communication interfaces 860. According to some examples, computing platform 800 may host a management element (e.g., a cloud infrastructure orchestrator, a network data center service chaining orchestrator, etc.) that provides management functions for a system with a configurable computing resource sharing pool, such as, for example, system 100 of FIG. 1. Computing platform 800 may be a single physical server or composed of logical servers that include a combination of disaggregated components or elements composed of a configurable computing resource sharing pool.

[0064] According to some examples, the processing component 840 can perform processing operations or logic of the resource manager 150 and / or the storage medium 700. The processing component 840 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software elements may include software components, programs, applications, computer programs, applications, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, software interfaces, application program interfaces (APIs), instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and / or software elements can vary depending on any number of factors such as desired computational rates, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints required for a given example.

[0065] In some examples, other platform components 850 may include shared computing elements such as one or more processors, multi-core processors, coprocessors, memory units, chipsets, controllers, peripherals, interfaces, orchestrators, timing devices, video cards, audio cards, multimedia input / output (I / O) components (e.g., digital displays), power supplies, etc. Examples of memory units may include, but are not limited to, various types of computer-readable and machine-readable storage media in the form of one or more higher-speed memory units, such as read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), double data rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, polymer memory such as ferroelectric polymer memory, bidirectional memory, phase change or ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic or optical cards, device arrays such as redundant array of independent disks (RAID) drives, solid-state memory devices (e.g., USB memory), solid-state drives (SSDs), and any other type of storage medium suitable for storing information.

[0066] In some examples, the communication interface 860 may include logic and / or features that support the communication interface. For these examples, the communication interface 860 may include one or more communication interfaces that operate according to various communication protocols or standards to communicate through direct or network communication links. Direct communication may occur through the use of communication protocols or standards (such as those associated with the PCIe specification) described in one or more industrial standards (including descendants and variants). Network communication may occur via the use of communication protocols or standards such as those described in one or more Ethernet standards promulgated by IEEE. For example, one such Ethernet standard may include IEEE 802.3. Network communication may also occur according to one or more open flow specifications such as the open flow hardware abstraction API specification. Network communication may also occur according to the Infiniband architecture specification or the TCP / IP protocol.

[0067] As described above, computing platform 800 can be implemented in a single server or a logical server composed of constituent disaggregated components or elements for a shared pool of configurable computing resources. Therefore, the functionality and / or specific configuration of computing platform 800 described herein may be included or omitted in various embodiments of computing platform 800 as appropriate for the physical or logical server.

[0068] The components and features of computing platform 800 may be implemented using any combination of discrete circuits, application specific integrated circuits (ASICs), logic gates, and / or single chip architectures. In addition, the features of computing platform 1000 may be implemented using microcontrollers, programmable logic arrays, and / or microprocessors, or any combination of the above, where appropriate. Note that hardware, firmware, and / or software elements may be collectively or individually referred to herein as "logic" or "circuitry."

[0069] It should be realized that Figure 8 The exemplary computing platform 800 shown in the block diagram of can represent a functional descriptive example of many possible implementations. Therefore, the division, omission or inclusion of block functions depicted in the drawings should not be inferred that the hardware components, circuits, software and / or elements used to implement these functions must be divided, omitted or included in the embodiments.

[0070] One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium, which represents various logic within the processor, which when read by a machine, computing device or system causes the machine, computing device or system to make logic to implement the techniques described herein. Such representations, known as "IP cores", may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

[0071] Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, programs, software interfaces, application program interfaces (APIs), instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and / or software elements can vary depending on any number of factors such as the desired computational rate, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints required for a given implementation.

[0072] Some examples may include an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium that stores logic. In some examples, a non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. In some examples, logic may include various software elements, such as software components, programs, applications, computer programs, applications, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, programs, software interfaces, APIs, instruction sets, computing codes, computer nodes, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0073] According to some examples, a computer-readable medium may include a non-transitory storage medium that stores or maintains instructions, which, when executed by a machine, a computing device, or a system, causes the machine, the computing device, or the system to perform methods and / or operations according to the examples. The instructions may include any appropriate type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. The instructions may be implemented according to a predefined computer language, manner, or syntax to instruct a machine, a computing device, or a system to perform a function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0074] Some examples may be described using the expression "in one example" or "example" and its derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The phrase "in one example" appearing in various places in the specification does not necessarily refer to the same example.

[0075] Some examples may be described using the expressions "coupled" and "connected" and their derivatives. These terms are not necessarily synonymous with each other. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0076] It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that, for the purpose of simplifying the present disclosure, various features are grouped together in a single embodiment. This method of the present disclosure is not to be interpreted as reflecting the intention that the examples claimed for protection require more features than those explicitly stated in each claim. On the contrary, as reflected in the following claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are thus incorporated into the detailed description, with each claim itself as a separate example. In the appended claims, the terms "including" and "in which" are used as the simple English equivalents of the corresponding terms "comprising" and "wherein", respectively. In addition, the terms "first", "second", "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0077] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

[0078] The following examples relate to further embodiments.

[0079] Example 1 is a dynamically composable computing system, including a computing structure that interconnects a plurality of different disaggregated computing hardware resources having corresponding hardware characteristics. The dynamically composable computing system includes a resource manager that has access to the corresponding hardware characteristics of the different disaggregated computing hardware resources and is configured to assemble a composite computing node by selecting one or more disaggregated computing hardware resources having corresponding hardware characteristics that meet the requirements of an application to be executed on the composite computing node. An orchestrator is configured to schedule an application using the assembled composite computing node.

[0080] In Example 2, the corresponding hardware characteristics may be from the group of processing performance, power consumption, bandwidth, latency, capacity, underlying technology, and cost.

[0081] In Example 3, the resource manager may include a storage device configured to store metadata indicating hardware characteristics associated with a plurality of different distributed disaggregated hardware resources.

[0082] In Example 4, different distributed computing hardware resources may include different types of computer memory or storage.

[0083] In Example 5, the dynamically composable computing system of any of the foregoing examples may further optionally include at least one computing module including a set of local computing hardware resources. The resource manager may be configured to connect the computing module to the selected disaggregated computing hardware resources through the computing fabric.

[0084] In Example 6, the local computing hardware resources of the computing module of Example 5 may include one or more local CPUs and one or more local memory modules.

[0085] In Example 7, the computing module of any one of Examples 5 or 6 may include a set of control registers. The resource manager may be configured to specify the selected disaggregated computing hardware by writing to the control registers.

[0086] In Example 8, the set of control registers of Example 7 may indicate at least one of a number of memory or storage layers, corresponding characteristics, and a group of corresponding address ranges.

[0087] In Example 9, the orchestrator of any of the preceding examples may be configured to provide the requirements of the application to the resource manager for assembling the composite computing node.

[0088] In Example 10, the orchestrator of any of the foregoing examples may be configured to determine the number of memory and / or storage tiers of the composite computing node according to the requirements of the application, wherein different memory and / or storage tiers are associated with corresponding different hardware resource characteristics. The resource manager may be configured to associate one or more memory or storage hardware resources that conform to the corresponding hardware resource characteristics with the corresponding memory or storage tier and map the corresponding address range to the corresponding memory or storage tier.

[0089] In Example 11, the resource manager of Example 10 may be configured to associate a memory or storage hardware resource with one of the memory or storage tiers only when an associated hardware resource characteristic of the memory or storage hardware resource falls within a predefined range of the corresponding tier.

[0090] In Example 12, the resource manager of Example 11 can be configured to associate a memory or storage device hardware resource with one of the memory or storage device tiers only when the associated processing performance, power consumption, bandwidth, latency, capacity, underlying technology, or cost of the memory or storage device hardware resource falls within a predefined range of the corresponding tier.

[0091] In Example 13, a first of the memory or storage tiers of any of Examples 10 to 12 may be associated with a local memory or storage hardware resource of a computing module, and at least a second of the memory or storage tiers may be associated with a dynamically configured disaggregated computing memory or storage hardware resource.

[0092] In Example 14, the composite computing node may be configured to redirect storage or memory requests for one or more of the determined memory or storage tiers of any of Examples 10 to 13 to one or more corresponding memory or storage hardware resources associated with the corresponding memory or storage tiers.

[0093] Example 15 is a data center comprising: at least one computing module, which includes a set of local computing hardware resources; a computing structure, including multiple different disaggregated memory and storage device hardware resources with corresponding hardware characteristics; an orchestrator, which is configured to schedule applications with application-specific hardware requirements; and a data center resource management hardware component, which has access to the corresponding hardware characteristics of different disaggregated memory and storage device hardware resources and is configured to assemble a composite computing node by selecting one or more disaggregated memory and storage device hardware resources with corresponding hardware characteristics that meet the hardware requirements of the application and connecting the statically configured computing modules with the selected disaggregated memory and storage device hardware resources through the computing structure.

[0094] In Example 16, the data center resource management hardware component of Example 15 may include a storage device accessible to the orchestrator for storing metadata indicating respective hardware characteristics associated with a plurality of different disaggregated memory and storage device hardware resources available in the data center.

[0095] In Example 17, the computing module of any one of Examples 15 or 16 may include a set of control registers. The data center resource management hardware component may be configured to specify the selected disaggregated memory and storage hardware resources by writing to the control registers.

[0096] Example 17 is a method for dynamically composing a computing system based on a plurality of different disaggregated computing hardware resources having corresponding hardware characteristics. The method includes storing information about the corresponding hardware characteristics of the different disaggregated computing hardware resources, and assembling a composite computing node by selecting one or more disaggregated computing hardware resources having corresponding hardware characteristics that meet the requirements of an application to be executed on the composite computing node based on the stored information.

[0097] In Example 19, the corresponding hardware characteristics of Example 18 may be from the group of processing performance, power, bandwidth, latency, capacity, underlying technology, and cost.

[0098] In Example 20, the different distributed computing hardware resources of any of Examples 18 or 19 may include different types of computer memory or storage.

[0099] In Example 21, assembling the composite computing node may further include connecting a computing module having a set of local computing hardware resources with the selected disaggregated computing hardware resources through a computing fabric.

[0100] In Example 22, the local computing hardware resources of the computing module of Example 21 may include one or more local CPUs and one or more local memory modules.

[0101] In Example 23, assembling the composite computing node may also include writing corresponding hardware characteristics of the selected disaggregated computing hardware to one or more control registers of the computing module of any one of Examples 21 or 22.

[0102] In Example 24, the one or more control registers of Example 23 may indicate at least one of a number of memory or storage layers, corresponding characteristics, and a group of corresponding address ranges.

[0103] In Example 25, the method of any one of Examples 18 to 24 may optionally further include providing the requirements of the application from an orchestrator that schedules the application to a resource manager for assembling the composite computing node.

[0104] In Example 26, the method of any one of Examples 18 to 25 may optionally further include determining the number of memory or storage device layers of the composite computing node based on application requirements, wherein different memory or storage device layers are associated with corresponding different hardware resource characteristics, associating one or more memory or storage device hardware resources that conform to the corresponding hardware resource characteristics with the corresponding memory or storage device layers, and mapping the corresponding address ranges to the corresponding memory or storage device layers.

[0105] In Example 27, a memory or storage hardware resource is associated with one of the memory or storage tiers of Example 26 only if an associated hardware resource characteristic of the memory or storage hardware resource falls within a predefined range of the corresponding tier.

[0106] In Example 28, a memory or storage device hardware resource is associated with one of the memory or storage device tiers of Example 26 or 27 only if at least one of the associated power consumption, bandwidth, latency, capacity, underlying technology, or cost of the memory or storage device hardware resource falls within a predefined range for the corresponding tier.

[0107] In Example 29, a first of the memory or storage tiers of any one of Examples 26 to 28 may be associated with a local memory or storage hardware resource of a computing module, and at least a second of the memory or storage tiers may be associated with a disaggregated computing memory or storage hardware resource.

[0108] In Example 30, the method of any one of Examples 26 to 29 may optionally further include redirecting storage or memory requests for one or more of the determined memory or storage tiers to one or more corresponding memory or storage hardware resources associated with the corresponding memory or storage tiers.

[0109] Example 31 is a computer program product comprising a non-transitory computer-readable medium having computer-readable program code implemented therein, wherein the computer-readable program code, when loaded onto a computer, a processor, or a programmable hardware component, is configured to implement a method for dynamically composing a computing system based on a plurality of different disaggregated computing hardware resources having corresponding hardware characteristics, the method comprising: storing information about corresponding hardware characteristics of different disaggregated computing hardware resources, and assembling a composite computing node by selecting one or more disaggregated computing hardware resources having corresponding hardware characteristics that meet requirements of an application to be executed on the composite computing node based on the stored information.

Claims

1. A method for accessing any one of a plurality of different disaggregated memory resources, the method comprising: mapping a first address range to the first memory resource within the plurality of different disaggregated memory resources and mapping a second address range to the second memory resource within the plurality of different disaggregated memory resources based at least on available memory bandwidth from the first memory resource and the second memory resource within the plurality of different disaggregated memory resources; issuing access requests to the first memory resource and the second memory resource in response to access requests including addresses in the first address range and the second address range; responsive to an access request including an address in the first address range, issuing the access request to the first memory resource; and In response to an access request including an address in the second address range, the access request is issued to the second memory resource.

2. The method according to claim 1, wherein: The plurality of different disaggregated memory resources include one or more of volatile memory devices and non-volatile memory devices.

3. The method according to claim 1, wherein: The first memory resource has an associated memory bandwidth and the second memory resource has an associated memory bandwidth, and a first address range is mapped to the first memory resource within the plurality of different disaggregated memory resources and a second address range is mapped to the second memory resource within the plurality of different disaggregated memory resources based at least on available memory bandwidth from the first memory resource and the second memory resource within the plurality of different disaggregated memory resources.

4. The method according to claim 1, wherein: The first memory resource and the second memory resource include one or more of: a dynamic random access memory (DRAM) and a solid state drive (SSD).

5. The method according to claim 1, wherein: The first memory resource and the second memory resource include volatile memory or persistent memory.

6. The method according to claim 1, wherein: The first memory resource and the second memory resource comprise byte-addressable memory.

7. The method of claim 1, comprising generating a communication with an issued access request, wherein: The communication complies with one or more of the following: PCIe, IEEE 802.3, InfiniBand or TCP / IP protocols.

8. A system comprising: At least one processor configured to: mapping a first address range to a first memory resource within a plurality of different disaggregated memory resources and a second address range to a second memory resource within the plurality of different disaggregated memory resources based at least on available memory bandwidth from the first memory resource and the second memory resource; issuing access requests to the first memory resource and the second memory resource in response to access requests referencing addresses in the first address range and the second address range; In response to an access request referencing an address within the first address range, issuing the access request to the first memory resource; responsive to an access request referencing an address within the second address range, issuing the access request to the second memory resource; and A communication interface is used to transmit commands, wherein the commands include at least one access request to access a specific memory resource.

9. The system according to claim 8, wherein: The first memory resource and the second memory resource comprise byte-addressable memory.

10. The system according to claim 8, wherein: The first memory resource and the second memory resource include volatile memory or persistent memory.

11. The system according to claim 8, wherein: The first memory resource and the second memory resource include one or more of: a dynamic random access memory (DRAM) and a solid state drive (SSD).

12. The system according to claim 8, wherein: The first memory resource has an associated memory bandwidth and the second memory resource has an associated memory bandwidth, and based at least on available memory bandwidths from the first memory resource and the second memory resource within the plurality of different disaggregated memory resources, the at least one processor is configured to: mapping a first address range to the first memory resource within the plurality of different disaggregated memory resources, and A second address range is mapped to a second memory resource within the plurality of different disaggregated memory resources.

13. The system according to claim 8, wherein: The at least one processor includes one or more of: a central processing unit (CPU) or an accelerator, and includes one or more local memory devices.

14. The system according to claim 8, wherein: The communication interface is used to transmit commands according to one or more of the following: PCIe, IEEE 802.3, InfiniBand or TCP / IP protocols.

15. The system according to claim 8, wherein: The communication interface is for receiving communications from the disaggregated memory resource.

16. A non-transitory computer-readable medium comprising instructions stored thereon, the instructions, if executed by one or more processors, causing the one or more processors to: mapping a first address range to a first memory resource within a plurality of different disaggregated memory resources and mapping a second address range to a second memory resource within the plurality of different disaggregated memory resources based at least on available memory bandwidth from the first memory resource and the second memory resource within the plurality of different disaggregated memory resources; issuing access requests to the first memory resource and the second memory resource in response to access requests referencing addresses in the first address range and the second address range; In response to an access request referencing an address within the first address range, issuing the access request to the first memory resource; responsive to an access request referencing an address within the second address range, issuing the access request to the second memory resource; and A command is caused to be transmitted, the command comprising at least one access request to access a specific memory resource.

17. The non-transitory computer readable medium of claim 16, wherein: The first memory resource and the second memory resource include one or more of: a dynamic random access memory (DRAM) and a solid state drive (SSD).

18. The non-transitory computer readable medium of claim 16, wherein: The first memory resource and the second memory resource include volatile memory or persistent memory.

19. The non-transitory computer readable medium of claim 16, wherein: The first memory resource and the second memory resource comprise byte-addressable memory.

20. The non-transitory computer readable medium of claim 16, wherein: The commands include communications conforming to one or more of: PCIe, IEEE 802.3, InfiniBand, or TCP / IP protocols.

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