Load balancing method, chip and storage medium for low-power AI processor

Abstract

The present invention relates to the technical field of low-power AI processors, and discloses a load balancing method, chip and storage medium of a low-power AI processor, the method comprising: partitioning cache resources for multiple neuromorphic cores in a low-power AI processor to obtain a double-layer cache structure; performing characteristic analysis on a target computing task, and constructing a directed acyclic graph of computing tasks and a dependency strength matrix; performing task segmentation to obtain a subtask partitioning scheme; creating a task-core mapping table; based on the task-core mapping table, organizing the neuromorphic core into multiple concentric ring layers to obtain a multi-layer ring collaborative computing network; based on the multi-layer ring collaborative computing network, calculating multiple performance indicators of each neuromorphic core, and performing dynamic load optimization to obtain a dynamic load optimization strategy. The present invention realizes load balancing of a low-power AI processor, and improves computing efficiency and energy utilization.

Description

Technical Field

[0001] The present invention relates to the technical field of low-power AI processors, and in particular to a load balancing method, chip and storage medium for a low-power AI processor. Background Art

[0002] Neuromorphic processors demonstrate unique advantages in processing neural network computing tasks by simulating the working mode of biological nervous systems. However, when executing large-scale neural network computing tasks, current neuromorphic processors are prone to problems such as uneven load distribution between processor cores, low cache resource utilization, and high data transmission overhead due to the lack of effective resource management and load balancing mechanisms. Especially in the process of multi-core collaborative computing, it is difficult to achieve efficient scheduling and optimal allocation of computing resources due to the lack of in-depth analysis of computing task characteristics and resource dependencies.

[0003] Existing neuromorphic processors generally lack dynamic energy efficiency management mechanisms and cannot flexibly adjust system resources according to the actual computing load. This results in both inability to guarantee computing performance and unnecessary energy waste when processing dynamically changing neural network computing tasks. Especially in terms of cache resource management, the traditional multi-level cache structure is difficult to adapt to the special needs of neuromorphic computing, affecting the overall computing efficiency and energy utilization of the system. Summary of the invention

[0004] The present invention provides a load balancing method, chip and storage medium for a low-power AI processor. The present invention realizes load balancing of a low-power AI processor and improves computing efficiency and energy utilization.

[0005] In a first aspect, the present invention provides a load balancing method for a low-power AI processor, the load balancing method for the low-power AI processor comprising:

[0006] Divide cache resources of multiple neuromorphic cores in low-power AI processors to obtain a two-layer cache structure;

[0007] Performing characteristic analysis on the target computing task according to the double-layer cache structure, and constructing a directed acyclic graph and a dependency strength matrix of the computing task;

[0008] Based on the computing task directed acyclic graph and the dependency strength matrix, task segmentation is performed to obtain a subtask division scheme;

[0009] Generate a resource requirement vector for each subtask according to the task division scheme, establish a core state matrix for each neuromorphic core, and create a task-core mapping table;

[0010] Based on the task-core mapping table, the neuromorphic core is organized into multiple concentric ring layers to obtain a multi-layer ring collaborative computing network;

[0011] Based on the multi-layer ring collaborative computing network, multiple performance indicators of each neuromorphic core are calculated, and dynamic load optimization is performed to obtain a dynamic load optimization strategy.

[0012] In a second aspect, the present invention provides a load balancing device for a low-power AI processor, the load balancing device for the low-power AI processor comprising:

[0013] A partitioning module is used to partition cache resources of multiple neuromorphic cores in a low-power AI processor to obtain a two-layer cache structure;

[0014] An analysis module, used to perform characteristic analysis on a target computing task according to the double-layer cache structure, and to construct a directed acyclic graph and a dependency strength matrix of the computing task;

[0015] A partitioning module, used to partition tasks based on the computing task directed acyclic graph and the dependency intensity matrix to obtain a subtask partitioning scheme;

[0016] A creation module is used to generate a resource requirement vector for each subtask according to the task division scheme, establish a core state matrix for each neuromorphic core, and create a task-core mapping table;

[0017] A processing module, configured to organize the neuromorphic core into a plurality of concentric ring layers based on the task-core mapping table to obtain a multi-layer ring collaborative computing network;

[0018] The optimization module is used to calculate multiple performance indicators of each neuromorphic core based on the multi-layer ring collaborative computing network, and perform dynamic load optimization to obtain a dynamic load optimization strategy.

[0019] A third aspect of the present invention provides a chip for executing the load balancing method of the above-mentioned low-power AI processor.

[0020] A fourth aspect of the present invention provides a computer-readable storage medium, which stores instructions that, when executed on a computer, enable the computer to execute the above-mentioned load balancing method for the low-power AI processor.

[0021] In the technical solution provided by the present invention, the access efficiency of cache resources is improved by dividing the instruction cache area, the data cache area and the synaptic weight cache area; the dynamic power management mechanism is adopted to power off the cache units with low frequency access, thereby reducing the static power consumption of the system; the refined management of cache resources is realized, and the cache space utilization rate is improved. The task segmentation scheme based on the directed acyclic graph of computing tasks and the dependency strength matrix reduces the data dependency overhead between tasks; the balanced distribution of computing load is achieved through the dynamic programming algorithm; the task priority mechanism considering the synaptic computing characteristics improves the execution efficiency of critical path tasks. The multi-layer ring collaborative computing network architecture reduces the communication delay between cores; the point-to-point link mechanism reduces the intermediate links of data transmission; the inter-layer bridging strategy optimizes the efficiency of cross-layer data transmission. Real-time monitoring and evaluation of system performance indicators realizes dynamic adjustment of resource allocation; the task migration mechanism based on load balancing avoids local resource overload; and the multi-dimensional performance evaluation system ensures the stable operation of the system. The cache management strategy based on access frequency reduces the overall power consumption of the system; the dynamic resource configuration mechanism improves the hardware utilization rate; and the task locality optimization reduces the data movement overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0023] Figure 1 Schematic diagram of the steps of a load balancing method for a low-power AI processor in an embodiment of the present invention;

[0024] Figure 2 Schematic diagram of the structure of the load balancing device of the low-power AI processor in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Embodiments of the present invention provide a load balancing method, chip and storage medium for a low-power AI processor. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] For ease of understanding, the specific process of the embodiment of the present invention is described below. Figure 1 , an embodiment of the load balancing method of the low-power AI processor in the embodiment of the present invention includes:

[0027] Step S1, dividing cache resources of multiple neuromorphic cores in a low-power AI processor to obtain a double-layer cache structure;

[0028] It is understandable that the execution subject of the present invention can be a load balancing device of a low-power AI processor, or a terminal or a server, which is not limited here. The embodiment of the present invention is described by taking the server as the execution subject as an example.

[0029] Specifically, processor core numbers are assigned to multiple neuromorphic cores in a low-power AI processor to obtain a core number assignment sequence, and the specific location and number of each neuromorphic core in the processor are clarified. The first-level cache is configured for each neuromorphic core, and the 192KB cache space is divided into an instruction cache area, a data cache area, and a synaptic weight cache area according to the computing task characteristics of each core, and appropriate read and write priorities are set for each cache area to ensure that cache resources can be reasonably utilized during the execution of different computing tasks. In this way, an allocation table of the first-level cache space is obtained, so that the division and use of cache resources are effectively managed to ensure that different types of data (such as instructions, data, and synaptic weights) can be stored and accessed in the best way. Based on the first-level cache space allocation table, a data path inside the neuromorphic core is constructed. Direct data links are established between the instruction cache area, the data cache area, and the synaptic weight cache area and the computing unit of the neuromorphic core, respectively, to form an access path for the first-level cache, to ensure that the transmission delay of data between the cache area and the computing unit is minimized, and to improve the availability of data and the response speed of the system. The total cache space of the processor is calculated, the total capacity of the first-level cache of multiple neuromorphic cores is deducted from the total cache space, and then the remaining cache space is planned as a shared storage area to obtain the total capacity value of the second-level cache. When the cache demand changes dynamically, the problem of insufficient cache resources of some cores is alleviated by shared cache. According to the total capacity value of the second-level cache, the storage unit is divided, and the second-level cache is divided into 256 independent cache units of equal size. Each cache unit is configured with an independent power control circuit and access counter, so that each cache unit is independently controlled and managed to form a distribution map of the second-level cache unit. The access frequency of each cache unit in the second-level cache unit distribution map is monitored. Through the access counter, the number of read and write operations of the cache unit is recorded in each 100 millisecond sampling period, and when the average access frequency of 10 consecutive sampling periods is less than 100 times per second, a low-frequency access mark is generated to obtain dynamic monitoring data of the cache unit. Based on the dynamic monitoring data of the cache unit, a cache status management database is established, and the database is used to update the allocation of cache resources in real time, so as to maintain an accurate record of the current cache resource usage status. In this way, a dynamic management strategy for cache resources is obtained, so that resource allocation can be quickly adjusted when cache demand changes, cache utilization can be improved, and overall system energy consumption can be reduced. According to the dynamic management strategy for cache resources, the independent power control circuit of each cache unit is used to power off the cache units marked as low-frequency access to reduce system power consumption. At the same time, the management authority of the low-frequency access cache units is transferred from the current neuromorphic core to the system resource pool so that they can be quickly reallocated when new tasks are required.Relevant parameters are updated in real time in the cache status management database to ensure that the entire system manages the cache status dynamically, in real time and efficiently, and ultimately a double-layer cache structure is obtained.

[0030] Step S2: Analyze the characteristics of the target computing task according to the double-layer cache structure, and construct a directed acyclic graph of the computing task and a dependency strength matrix;

[0031] Specifically, the target computing task is subjected to hierarchical processing of the neural network model. The number of neurons, the distribution of synaptic weights and the data transmission requirements of each layer are extracted through the synaptic connection analyzer, and these requirements are matched based on the dynamic management strategy of cache resources in the double-layer cache structure to obtain a hierarchical feature data table. The computing mode is classified based on the hierarchical feature data table, and the computing operations of each layer are marked as different types such as synaptic weight calculation, neuron activation calculation, pulse signal transmission calculation and synaptic plasticity calculation. According to the cache area type in the first-level cache space allocation table, different types of data are mapped to generate a computing feature classification table. Through classification, the types of calculations required for each layer and their corresponding data storage requirements are clarified. According to the computing feature classification table, the computing density analysis is performed on each computing type, and the unit data processing volume of each type is matched with the data throughput capacity of the second-level cache unit. At the same time, the access frequency factor in the dynamic monitoring data of the cache unit is taken into account to ensure that the allocation of computing tasks can make full use of cache resources and avoid resource waste, and a computing load density map is obtained to reflect the specific requirements of different types of computing tasks for system resources. The synaptic connection strength is calculated for the inter-layer data flow in the hierarchical feature data table. The synaptic weight matrix between adjacent layers is multiplied by the data transmission frequency, and combined with the bandwidth limit of the first-level cache access path, the dependency strength of the data between layers is calculated to obtain the inter-layer data dependency strength table. Through calculation, the data transmission relationship between layers and its impact on the system bandwidth are accurately described to ensure that the data flow between layers will not cause performance bottlenecks due to insufficient bandwidth. Based on the inter-layer data dependency strength table, a neural computation graph is constructed. In the neural computation graph, each synaptic computation operation is regarded as an independent node, the data transmission path is regarded as a directed edge, and the corresponding synaptic weight and transmission delay are marked on each edge. At the same time, the cache unit allocation information in the cache resource dynamic management strategy is associated with the computation graph to obtain the initial computation dependency graph. In order to eliminate potential cyclic dependencies in the computation tasks, loop detection is performed on the initial computation dependency graph. The cyclic dependencies in the data flow path are identified by the topological sorting algorithm, and the detected cyclic paths are decoupled by parallel branch reconstruction. The decoupling operation can reorganize the computation tasks in the loop, making the dependency relationship between tasks more linear, eliminating potential resource conflicts and performance bottlenecks caused by the loop. After decoupling is completed, the relevant parameters in the cache state management database are updated to reflect the latest resource allocation and computing path relationship, and the directed acyclic graph of the computing task is obtained. Based on the directed acyclic graph of the computing task, a quantitative model of the dependency is established. Through this model, the data transmission volume, memory access dependency, and computing resource competition between any two computing nodes are calculated. These calculation results are filled into a dependency matrix of size N×N, where N is the total number of synaptic computing nodes, to obtain a dependency strength matrix. This matrix describes the dependency relationship between each node in the entire computing task and the competition for resources.

[0032] Step S3: based on the directed acyclic graph of computing tasks and the dependency strength matrix, perform task segmentation to obtain a subtask division scheme;

[0033] Specifically, the synaptic computing nodes in the directed acyclic graph of the computing task are topologically sorted, and the execution priority order of the nodes is established through the inter-layer data dependency strength table. At the same time, a one-to-one correspondence is established between the corresponding row and column relationships in the dependency strength matrix and the node number to obtain the execution sequence of the computing node. The execution sequence of the computing node is input into the state transition model, a dynamic programming state equation is constructed, and the state space is constrained by the dynamic management strategy of the cache resource to obtain the task segmentation state space. In this way, the search range of the state space can be effectively narrowed, the computational complexity can be reduced, and the task segmentation can be made more efficient and meet the constraint requirements of the cache resource. Dynamic programming can help find the optimal task segmentation scheme that meets various constraints. A three-dimensional cost calculation model is constructed based on the task segmentation state space, in which the load balance of synaptic computing, the overhead of data transmission and the utilization rate of cache resources are used as calculation dimensions. The cost function of task segmentation is obtained by quantitative calculation based on the computational load density map, the inter-layer data dependency strength table and the dynamic monitoring data of the cache unit. The optimal solution search is performed for the task segmentation cost function, and the cost value of all states in the task segmentation state space is calculated recursively. Through recursive calculation, the segmentation state with the lowest cost is effectively found, so that the entire calculation process tends to be optimal. At the same time, the cache access efficiency of the segmentation scheme is verified through the access counter of the second-level cache unit to ensure that the segmented tasks can effectively utilize cache resources in actual execution and obtain the state transition path table. According to the state transition path table, the optimal path backtracking is performed to determine the set of synaptic computing nodes contained in each subtask in turn, and the corresponding cache resource requirements are written into the cache state management database to obtain the partition table of the basic task. The basic partition table is evaluated for balance, and the variance coefficient of the synaptic computing amount, the variance coefficient of the cache access amount, and the variance coefficient of the data transmission amount of each subtask are calculated respectively. If any coefficient exceeds 0.2, it means that the current subtask division is not balanced enough, and the load adjustment operation needs to be triggered according to the weight relationship in the dependency strength matrix to obtain the task balance adjustment rule. The purpose of balance evaluation and adjustment is to eliminate the imbalance in task division so that the computational amount and resource consumption of each subtask can reach a reasonable balance. Under the guidance of the task balance adjustment rules, the boundaries of the subtasks are reconstructed, and the three variance coefficients of each subtask are adjusted to be less than 0.2 by adjusting the allocation scheme of the synaptic computing nodes, thereby ensuring that the load between subtasks is more balanced. At the same time, the corresponding cache unit allocation relationship is updated in the cache state management database to ensure that the system can correctly identify and manage the new task division state after the adjustment, and obtain an optimized task allocation scheme. The subtasks in the optimized task allocation scheme are prioritized, and the critical path weight of each subtask in the directed acyclic graph of the computing task is calculated.Based on the critical path weight, the importance of the subtask in the entire computing process is judged, and the execution priority is assigned to it according to the cache resource dynamic management strategy, and the priority information is written into the cache status management database. Through priority calibration, it is ensured that the critical tasks are executed first, the computing efficiency and response speed of the entire system are improved, and finally the subtask division scheme is obtained.

[0034] Step S4: Generate a resource requirement vector for each subtask according to the task division scheme, establish a core state matrix for each neuromorphic core, and create a task-core mapping table;

[0035] Specifically, a neural network resource demand analysis is performed for each subtask in the task division scheme. Based on the calculation feature classification table and the first-level cache space allocation table, the synaptic weight space, neuron activation space, and pulse signal transmission space required for each subtask are calculated, and the resource demand is compared with the dynamic monitoring data of the cache unit to obtain the resource occupancy distribution table of the subtask. A resource demand vector is constructed according to the subtask resource occupancy distribution table, and the synaptic computing resource demand, storage space demand, and data transmission bandwidth demand are organized into a vector to obtain the resource demand vector of each subtask. The resource demand vector uniformly expresses the various requirements of the task in a mathematical form, which facilitates the subsequent calculation and task allocation process, so that the requirements of each subtask can be matched with the core capabilities in a vectorized manner. At the same time, performance parameters of multiple neuromorphic cores are collected, and the current synaptic computing capacity, cache space margin, and communication bandwidth margin of each core are recorded according to the core number allocation sequence. At the same time, the core working status mark in the cache resource dynamic management strategy is read to obtain the state data set of the neuromorphic core. Through these data, the current state of each neuromorphic core, including its available resources and workload, is understood so that the appropriate core can be selected for load balancing during the task allocation process. The state data set of the neuromorphic core is converted into a core state matrix, and the core state matrix is ​​screened to obtain a valid core list. Cores in a high-load state or with insufficient resources are eliminated to ensure that the cores to which the task is assigned can effectively undertake the computing task and avoid performance bottlenecks caused by core overload. The cores in the valid core list will be used as candidate resources for subsequent task allocation decisions. A resource matching calculation model is constructed based on the valid core list and the resource demand vector. By using the vector inner product operation, the resource matching between each subtask and the candidate core is calculated, and the calculation results are combined with the data dependency constraints in the dependency strength matrix to obtain a comprehensive matching score table. Based on the comprehensive matching score table, task allocation optimization is performed, and the bipartite graph maximum weight matching algorithm is used to pair subtasks and neuromorphic cores one by one to obtain a core allocation plan. The bipartite graph maximum weight matching algorithm is an algorithm that can maximize the overall matching degree during the pairing process, ensuring that each subtask is assigned to the most suitable core, thereby achieving the optimal computing allocation plan under the overall resource constraints of the system. Optimize the spatial location of the core allocation scheme. Based on the physical layout of the first-level cache access path, assign subtasks with frequent data interactions to the neuromorphic core group with the closest physical distance, reduce the delay of data transmission between different cores, and thus improve the overall response speed and performance of the system. Through this step, the data transmission path is ensured to be the shortest, the computing efficiency of the system is improved, and the power consumption is reduced, and finally the task-core mapping table is obtained.

[0036] Step S5: Based on the task-core mapping table, the neuromorphic core is organized into multiple concentric ring layers to obtain a multi-layer ring collaborative computing network;

[0037] Specifically, the connection strength of the neuromorphic cores in the task-core mapping table is analyzed to obtain a distribution map of the core connection strength. Through the analysis of the connection strength, the frequency of interaction between each neuromorphic core and other cores is quantified, and based on this, multiple cores are hierarchically organized to obtain a distribution table of ring layer cores. The hierarchical organization enables the system to place closely related cores in the same ring layer as much as possible according to the connection strength, thereby reducing the data transmission delay and communication overhead between the cores and ensuring the optimization of system performance. According to the ring layer core distribution table, the communication link within the ring is constructed. A direct data channel is established for the adjacent neuromorphic cores in each ring layer, and the data interaction between these cores is connected into a ring structure. At the same time, the data throughput capacity of the second-level cache unit is used as the bandwidth upper limit of the communication link, and the physical delay parameters of each link and the cache access overhead are recorded to obtain the communication link table within the ring. Ensure that the communication channel within the ring layer has sufficient bandwidth to support frequent data exchange during task execution, and quantify the link delay and cache overhead to provide basic data for subsequent link optimization. The bandwidth of each link in the intra-ring communication link is configured to obtain a reasonable link bandwidth configuration scheme to ensure the efficiency of data transmission in the ring. Based on the bandwidth configuration scheme, bridge points for inter-layer communication are designed between different ring layers to obtain an inter-layer bridging scheme, thereby establishing a data exchange channel between different ring layers, so that computing tasks can not only be effectively coordinated within the same ring layer, but also realize data transmission between different ring layers, enhancing the synergy of the entire network. For the communication channel in the inter-layer bridging scheme, priority is configured to obtain the control strategy of the bridge channel. Transmission priorities are set for different communication channels to ensure that important data or high-priority tasks can be transmitted through the bridge channel first, thereby improving the response speed of the system. Based on the intra-ring communication link table and the control strategy of the bridge channel, a global routing table is established, and the physical constraints of the first-level cache access path are used as the routing cost factor to obtain the network routing scheme of the entire system. In this way, the transmission paths of various types of data between different cores are determined, and the physical overhead of cache access is considered when selecting the path, ensuring that the cost of data transmission is reduced as much as possible while meeting performance requirements. Link reliability verification of the network routing scheme is performed. Combining the dynamic monitoring data of the cache unit and the state matrix of the neuromorphic core, the load of the link is evaluated to ensure that the load of all communication links is balanced and does not exceed their maximum carrying capacity, thus obtaining a multi-layer ring collaborative computing network.

[0038] Step S6: Calculate multiple performance indicators of each neuromorphic core based on the multi-layer ring collaborative computing network, perform dynamic load optimization, and obtain a dynamic load optimization strategy.

[0039] Specifically, the running status of each neuromorphic core in the multi-layer ring collaborative computing network is sampled and analyzed to obtain the core performance monitoring table. By real-time monitoring of the workload, computing power, energy consumption and other parameters of each core, the state performance of each core in the actual working process can be fully understood. Based on the monitoring data, a multi-dimensional performance evaluation system is constructed to obtain a performance index evaluation system. The evaluation system covers multiple performance indicators, such as computing efficiency, energy consumption ratio, communication bandwidth usage, cache hit rate, etc., to comprehensively evaluate the performance of each neuromorphic core. Multiple performance indicators in the performance index evaluation system are weighted and calculated to obtain a comprehensive performance score table. In the process of weighted calculation, different performance indicators have different importance, and weights are set according to the system optimization goal. Through the comprehensive performance score table, the overall performance of each neuromorphic core is compared, and then the performance of multiple neuromorphic cores is graded to obtain a core load classification table. Based on the core load classification table, the load balance degree is calculated to obtain the load balance degree evaluation result, quantify the load distribution of each core in the entire system, and judge whether the load of each core is uniform and reasonable. If there is a significant load imbalance in the system, the performance of some cores will be degraded due to excessive load, affecting the computing efficiency of the entire system. According to the evaluation results of the load balance, it is optimized and planned to generate a task balancing plan. Through reasonable task migration and resource reconfiguration, the load distribution of all cores is more even, improving the overall performance and energy efficiency of the system. According to the task balancing plan, resources are reconfigured to migrate some synaptic computing tasks on the high-load core to the low-load core to achieve load rebalancing. During the task migration process, it is necessary to ensure the integrity and consistency of the data, while minimizing the additional overhead caused by task migration. In order to adapt to the new task allocation plan, the bandwidth allocation parameters in the intra-ring communication link table and the inter-layer bridge channel control strategy are adjusted accordingly to ensure that the migrated core can obtain sufficient bandwidth support and maintain the normal execution of the task. The adjusted resource configuration information is updated to the cache status management database to ensure that each module of the system can obtain the latest resource configuration in time and maintain the stable operation of the system. Through the above steps, the dynamic load optimization strategy is finally obtained. This strategy is a solution that can be adjusted at any time according to the system status, ensuring that under different workload conditions, the system can automatically adjust the task allocation and resource configuration of each neuromorphic core to achieve the best computing performance and the lowest energy consumption.

[0040] In the embodiment of the present invention, the access efficiency of cache resources is improved by dividing the instruction cache area, the data cache area and the synaptic weight cache area; the dynamic power management mechanism is adopted to power off the cache units with low frequency access, thereby reducing the static power consumption of the system; the refined management of cache resources is realized, and the cache space utilization rate is improved. The task partitioning scheme based on the directed acyclic graph of computing tasks and the dependency strength matrix reduces the data dependency overhead between tasks; the balanced distribution of computing load is realized through the dynamic programming algorithm; the task priority mechanism considering the synaptic computing characteristics improves the execution efficiency of critical path tasks. The multi-layer ring collaborative computing network architecture reduces the communication delay between cores; the point-to-point link mechanism reduces the intermediate links of data transmission; the inter-layer bridging strategy optimizes the efficiency of cross-layer data transmission. Real-time monitoring and evaluation of system performance indicators realizes dynamic adjustment of resource allocation; the task migration mechanism based on load balancing avoids local resource overload; and the multi-dimensional performance evaluation system ensures the stable operation of the system. The cache management strategy based on access frequency reduces the overall power consumption of the system; the dynamic resource configuration mechanism improves the hardware utilization rate; and the task locality optimization reduces the data movement overhead.

[0041] In a specific embodiment, the process of executing step S1 may specifically include the following steps:

[0042] Assign processor core numbers to multiple neuromorphic cores in a low-power AI processor to obtain a core number assignment sequence;

[0043] Perform first-level cache configuration for each neuromorphic core, divide the 192KB cache space into instruction cache, data cache, and synaptic weight cache according to the computing task characteristics of each neuromorphic core, set the read and write priority of each cache area, and obtain the first-level cache space allocation table;

[0044] Based on the first-level cache space allocation table, the internal data path of the neuromorphic core is constructed, and the instruction cache, data cache, and synaptic weight cache are respectively connected to the computing unit of the neuromorphic core to establish direct data links, thereby obtaining the first-level cache access path.

[0045] Calculate the capacity of the total cache space of the processor, deduct the total capacity of the first-level cache of multiple neuromorphic cores from the total cache space, plan the remaining cache space as a shared storage area, and obtain the total capacity value of the second-level cache;

[0046] The storage unit is divided according to the total capacity value of the second-level cache, and the second-level cache is divided into 256 independent cache units of equal size. Each cache unit is configured with an independent power control circuit and an access counter, and a distribution map of the second-level cache units is obtained;

[0047] The access frequency of each cache unit in the second-level cache unit distribution map is monitored, and the number of read and write operations of the cache unit is recorded in each 100 millisecond sampling period through the access counter. When the average access frequency of 10 consecutive sampling periods is less than 100 times per second, a low-frequency access mark is generated to obtain the dynamic monitoring data of the cache unit;

[0048] Based on the dynamic monitoring data of the cache unit, a cache status management database is established, and the cache resource allocation status is maintained by updating parameters in real time to obtain a dynamic cache resource management strategy;

[0049] According to the dynamic management strategy of cache resources, the power control circuit is used to power off the cache unit marked as low-frequency access. At the same time, the management authority of the cache unit is transferred from the current neuromorphic core to the system resource pool, and the relevant parameters are updated in the cache status management database to obtain a double-layer cache structure.

[0050] Specifically, multiple neuromorphic cores in a low-power AI processor are assigned processor core numbers. The numbers are usually consecutive integer numbers, such as ,in Represents the total number of neuromorphic cores in the processor. Perform first-level cache configuration for each neuromorphic core. According to the specific computing task characteristics of each neuromorphic core, the 192KB cache space is divided into instruction cache area, data cache area and synaptic weight cache area. Assume that the size of the instruction cache area is , the data buffer size is , the synaptic weight buffer size is , then the following relationship holds:

[0051] ;

[0052] For example, for a specific core, assuming that its computing task is mainly neuron activation calculation, a larger instruction cache and synaptic weight cache are allocated, while the size of the data cache is reduced, so that KB 32KB KB. At the same time, in order to optimize data access efficiency, the read and write priority of each cache area is set according to the priority of the task. For example, the instruction cache has the highest priority, followed by the synaptic weight cache area, and finally the data cache area, to obtain the first-level cache space allocation table. Based on the first-level cache space allocation table, the internal data path of the neuromorphic core is constructed. By establishing direct data links between the instruction cache area, the data cache area, and the synaptic weight cache area and the computing unit of the neuromorphic core respectively, the access path of the first-level cache is obtained. The instruction cache area is directly connected to the control unit of the core to ensure that the calculation instructions can be obtained quickly; the data cache area is connected to the data processing unit to facilitate efficient data processing; the synaptic weight cache area is connected to the synaptic computing unit to ensure that the weight data can be quickly used for neural network calculations. This data link design enables the calculation process of each core to maintain low latency and high efficiency, forming a complete first-level cache access path. The capacity of the total cache space of the processor is calculated, and the total capacity of the first-level cache of multiple neuromorphic cores is deducted from it. Assume that the total capacity of the first-level cache is , then: Assuming the processor has 16 cores, then KB. Total cache capacity of the slave processor Deduction , plan the remaining cache space as a shared storage area, and get the total capacity of the second-level cache

[0053] ;

[0054] ;

[0055] If the total cache capacity of the processor is 8192KB, then KB. According to the total capacity of the second-level cache, it is divided into 256 independent cache units of equal size, and the size of each cache unit is . Therefore, the size of each cache unit is:

[0056] ;

[0057] Each cache unit is equipped with an independent power control circuit and access counter to obtain a distribution map of the second-level cache unit. These independent cache units are flexibly allocated to different neuromorphic cores to improve the utilization efficiency of cache resources. In order to monitor the usage of the cache, the access frequency of each cache unit in the second-level cache unit distribution map is monitored. Through the access counter, the number of read and write operations of the cache unit is recorded in each 100-ms sampling period. When the average access frequency of 10 consecutive sampling periods is less than 100 times per second, a low-frequency access mark is generated to obtain the dynamic monitoring data of the cache unit. Based on the dynamic monitoring data of the cache unit, a cache status management database is established, and the allocation status of cache resources is maintained by updating parameters in real time to obtain a dynamic management strategy for cache resources. The dynamic management strategy is used to optimize the power consumption of the system and the utilization efficiency of cache resources. For example, when a cache unit is marked as a low-frequency access, the power control circuit is used to power off the cache unit to reduce the overall power consumption of the system. At the same time, the management authority of the cache unit marked as a low-frequency access is transferred from the current neuromorphic core to the system resource pool so that these cache units can be reallocated and utilized when there are new computing tasks. Update relevant parameters in the cache status management database to ensure that the entire system maintains consistency and real-time status of cache resources, forming a two-layer cache structure. The two-layer cache structure contains both the first-level cache of each neuromorphic core, which is used to store high-priority, low-latency data, and a shared second-level cache, which is used to improve the utilization of cache resources and the overall performance of the system.

[0058] In a specific embodiment, the process of executing step S2 may specifically include the following steps:

[0059] The target computing task is processed by the neural network model in layers. The number of neurons, synaptic weight distribution and data transmission requirements of each layer are extracted through the synaptic connection analyzer. The cache requirements are matched based on the dynamic management strategy of cache resources in the double-layer cache structure to obtain a hierarchical feature data table.

[0060] Based on the hierarchical feature data table, the calculation mode is classified, and the calculation operation of each layer is marked as synaptic weight calculation, neuron activation calculation, pulse signal transmission calculation and synaptic plasticity calculation. The data is mapped according to the cache area type in the first-level cache space allocation table to obtain a calculation feature classification table;

[0061] Perform computational density analysis based on the computational feature classification table, match the unit data processing volume of each computational type with the data throughput capacity of the second-level cache unit, and consider the access frequency factor in the dynamic monitoring data of the cache unit to obtain a computational load density diagram;

[0062] Calculate the synaptic connection strength of the inter-layer data flow in the hierarchical feature data table, multiply the synaptic weight matrix between adjacent layers by the data transmission frequency, and combine it with the bandwidth limit of the first-level cache access path to obtain the inter-layer data dependency strength table;

[0063] Based on the inter-layer data dependency strength table, a neural computation graph is constructed. Each synaptic computation operation is taken as an independent node, and the data transmission path is taken as a directed edge. The synaptic weight and transmission delay of each edge are marked. At the same time, the cache unit allocation information in the cache resource dynamic management strategy is associated to obtain the initial computation dependency graph.

[0064] Perform loop detection on the initial computational dependency graph, identify the cyclic dependencies in the data flow path through a topological sorting algorithm, decouple the detected cyclic paths through parallel branch reconstruction, and update the relevant parameters in the cache state management database to obtain a directed acyclic graph of computational tasks;

[0065] A dependency quantification model is established based on the directed acyclic graph of computing tasks. The data transmission volume, memory access dependency and computing resource competition between any two computing nodes are calculated. The calculation results are filled into a dependency matrix of size N×N, where N is the total number of synaptic computing nodes, to obtain a dependency strength matrix.

[0066] Specifically, the target computing task is processed by layering the neural network model, and the number of neurons, synaptic weight distribution, and data transmission requirements of each layer are extracted through the synaptic connection analyzer. The synaptic connection analyzer can analyze the neuron structure characteristics of each layer, including the number of neurons, the connection relationship between neurons, and the corresponding synaptic weights. Suppose the number of neurons in a certain layer is , the synaptic weight matrix is , the data transmission requirement is . represents the total number of neurons in the current layer, represents the connection weight between each neuron, and It reflects the demand for data transmission when the layer performs calculations. Based on this information and the dynamic management strategy of cache resources in the two-layer cache structure, the cache requirements of each layer are matched to obtain the hierarchical feature data table of each layer. Based on the hierarchical feature data table, the calculation mode is classified, and the calculation operation of each layer is marked as synaptic weight calculation, neuron activation calculation, pulse signal transmission calculation and synaptic plasticity calculation. Synaptic weight calculation mainly involves the weight product between neurons in each layer; neuron activation calculation is the application of activation function to each neuron; pulse signal transmission calculation is related to signal transmission between neurons, and synaptic plasticity calculation is used to simulate the learning process in neural networks. Based on the cache area type in the first-level cache space allocation table, these calculation operations are mapped to the corresponding cache area, such as instruction cache area, data cache area or synaptic weight cache area, to obtain a calculation feature classification table. For example, if a layer mainly involves synaptic weight calculation, then this part of the data should be stored in the synaptic weight cache area first. According to the calculation feature classification table, the calculation density analysis is performed to obtain the matching between the unit data processing volume of each calculation type and the data throughput capacity of the second-level cache unit. Assume that the unit data processing volume is , the data throughput capacity of the second-level cache unit is , the matching operation is performed using the following formula:

[0067] ;

[0068] in, Indicates the calculation density matching degree, is the unit data processing capacity of a specific computing type, is the throughput of the second-level cache unit. , determine whether the cache unit is sufficient to meet the data requirements of the computing task. Consider the access frequency factor in the dynamic monitoring data of the cache unit. If the access frequency of a cache unit is low, relocate some computing tasks to the cache unit to achieve better load balancing, and obtain a computing load density map to describe the occupancy of cache resources by different computing tasks. Calculate the synaptic connection strength of the inter-layer data flow in the hierarchical feature data table. By combining the synaptic weight matrix between adjacent layers Data transmission frequency Multiply them together to calculate the connection strength between layers

[0069] ;

[0070] in, Indicates Layer and The synaptic weight matrix between layers, Indicates the frequency of data transmission between these two layers, Then it is the data dependency strength between layers. At the same time, combined with the bandwidth limit of the first-level cache access path, to ensure that data transmission does not exceed the capacity of the cache path, the inter-layer data dependency strength table is obtained. Based on the inter-layer data dependency strength table, a neural computation graph is constructed. In the neural computation graph, each synaptic computation operation is regarded as an independent node, and the data transmission path is represented as a directed edge. The corresponding synaptic weight and transmission delay are marked on each edge to accurately describe the data dependency relationship between different computing nodes. Assume that the node and There is a data transmission path between them, then the weight of the edge is , the transmission delay is , and associated with the cache unit allocation information in the cache resource dynamic management strategy, to obtain the initial computing dependency graph, which represents the dependency relationship and data flow path between each computing node. In order to ensure the correct execution of the computing task, loop detection is performed on the initial computing dependency graph. Through the topological sorting algorithm, the circular dependency in the data flow path is effectively identified, so that the detected circular path is processed. The circular path is decoupled by parallel branch reconstruction to avoid deadlock problems during the calculation process. After the decoupling is completed, the relevant parameters in the cache status management database are updated to reflect the latest allocation status of the task, and the directed acyclic graph of the computing task is obtained. Based on the directed acyclic graph of the computing task, a dependency quantification model is established. Through this model, the data transmission volume, memory access dependency and computing resource competition between any two computing nodes are calculated. For example, suppose two computing nodes and The amount of data transferred between , the memory access dependency is , the computing resource competition is Fill these calculation results into the size of The dependency matrix ,in Represents the total number of synaptic computing nodes, and obtains the dependency strength matrix:

[0071] ;

[0072] Each matrix element Contains nodes and There are three dependencies between them.

[0073] In a specific embodiment, the process of executing step S3 may specifically include the following steps:

[0074] The synaptic computing nodes in the directed acyclic graph of computing tasks are topologically sorted, and the node execution priority order is established according to the inter-layer data dependency strength table. At the same time, the corresponding row and column relationships in the dependency strength matrix are established in a one-to-one correspondence with the node numbers to obtain the computing node execution sequence;

[0075] The computing node execution sequence is input into the state transfer model, the dynamic programming state equation is constructed, and the state space is constrained through the cache resource dynamic management strategy to obtain the task segmentation state space;

[0076] A three-dimensional cost calculation model is constructed based on the task segmentation state space. The synaptic computing load balance, data transmission overhead and cache resource utilization are used as calculation dimensions. The task segmentation cost function is obtained by performing quantitative calculations based on the computing load density map, the inter-layer data dependency intensity table and the cache unit dynamic monitoring data.

[0077] The optimal solution of the task partitioning cost function is searched, and the cost values ​​of all states in the task partitioning state space are calculated recursively. The cache access efficiency of the partitioning scheme is verified through the access counter of the second-level cache unit to obtain the state transition path table.

[0078] Perform optimal path backtracking according to the state transfer path table, determine the set of synaptic computing nodes included in each subtask in turn, and write the corresponding cache resource requirements into the cache state management database to obtain the basic task division table;

[0079] The basic task partitioning table is evaluated for balance, and the variance coefficients of synaptic computation, cache access, and data transmission for each subtask are calculated. When any coefficient exceeds 0.2, the load adjustment operation is triggered according to the weight relationship in the dependency strength matrix to obtain the task balance adjustment rule.

[0080] Based on the task balance adjustment rule, the subtask boundaries are reconstructed, and the three variance coefficients of each subtask are adjusted to be less than 0.2 by adjusting the allocation scheme of the synaptic computing nodes. At the same time, the corresponding cache unit allocation relationship is updated in the cache state management database to obtain the optimized task allocation scheme.

[0081] The subtasks in the optimization task allocation scheme are prioritized, the critical path weight of each subtask in the directed acyclic graph of computing tasks is calculated, the execution priority is assigned according to the dynamic management strategy of cache resources, and the priority information is written into the cache status management database to obtain the subtask division scheme.

[0082] Specifically, the synaptic computing nodes in the directed acyclic graph of computing tasks are topologically sorted to ensure that the predecessor task of each node is completed before it. This is achieved through a standard topological sorting algorithm, such as depth-first search (DFS) or Kahn algorithm. Based on the inter-layer data dependency strength table, the priority order of node execution is established. Let the dependency strength between layers in the dependency strength table be the matrix ,in Representation Node For Node The strength of dependence. The size of the node is used to determine the execution priority of the node, and the nodes with greater dependency strength are processed first to ensure that the order of data transmission and processing is optimal. At the same time, a one-to-one correspondence is established between the corresponding row and column relationship in the dependency strength matrix and the node number to obtain the execution sequence of the computing node, which is recorded as ,in Indicates Executed nodes, is the total number of nodes. Input the computing node execution sequence into the state transfer model and construct the state equation of dynamic programming. Suppose the state transfer function is , indicating execution to the nodes and the status is The optimal solution for each state is obtained by recursively calculating the optimal path cost for each state. In the process of state transfer, the state space is constrained by the dynamic management strategy of cache resources to reduce unnecessary state space searches and obtain the state space of task segmentation. Based on the task segmentation state space, a three-dimensional cost calculation model is constructed. The load balance of synaptic computing, the overhead of data transmission and the utilization of cache resources are used as three calculation dimensions. The quantitative calculation is performed based on the calculation load density diagram, the inter-layer data dependency intensity table and the dynamic monitoring data of the cache unit to obtain the cost function of task segmentation. , which has the following form:

[0083] ;

[0084] in, Indicates The cost of a state, is the load balance degree, which indicates the difference between the computing loads of each core. is the data transmission overhead, which represents the data transmission cost between computing nodes. is the utilization rate of cache resources, indicating the usage of the current cache unit. is the corresponding weight factor, which is used to adjust the importance of different calculation dimensions. The optimal solution of all states in the task partition state space is found by recursive calculation. The optimal solution of the task partition cost function is searched, and the cost value of all states in the task partition state space is calculated recursively. In order to verify the cache access efficiency of the partition scheme, the access counter of the second-level cache unit is used to monitor the access of the cache under each partition scheme, record the number of accesses and access efficiency, and obtain the state transition path table. The state transition path table records all state transition information from the initial state to the optimal state. Based on the state transition path table, the optimal path backtracking is performed, starting from the final state and gradually backtracking to the initial state, and the set of synaptic computing nodes contained in each subtask is determined in turn. During the backtracking process, the corresponding cache resource demand is written into the cache state management database to ensure that the system can timely understand the cache resource demand of each subtask and obtain the partition table of the basic task. The basic task partition table is evaluated for balance. The variance coefficient of the synaptic computing amount, the variance coefficient of the cache access amount, and the variance coefficient of the data transmission amount of each subtask are calculated respectively. If any coefficient exceeds the set threshold, such as 0.2, it means that the current task division is significantly unbalanced and needs to be adjusted. Based on the weight relationship in the dependency intensity matrix, the load adjustment operation is triggered to obtain the task balance adjustment rule. Based on the task balance adjustment rule, the boundaries of the subtasks are reconstructed, and the three variance coefficients of each subtask are all less than 0.2 by adjusting the allocation scheme of the synaptic computing nodes. During the adjustment process, the computing nodes are reallocated to balance the computing amount, cache access amount and data transmission amount of each subtask as much as possible. After the adjustment is completed, the corresponding cache unit allocation relationship is updated in the cache state management database to ensure that the resource allocation information of the system remains consistent and timely, and an optimized task allocation scheme is obtained. The priority of the subtasks in the optimized task allocation scheme is calibrated. The critical path weight of each subtask in the directed acyclic graph of the computing task is calculated to indicate the degree of influence of the task on the final result in the entire computing process. According to the critical path weight and the dynamic management strategy of the cache resources, the execution priority is assigned to each subtask, and the priority information is written into the cache state management database so that the system can give priority to important tasks during the execution process, and finally the subtask division scheme is obtained.

[0085] In a specific embodiment, the process of executing step S4 may specifically include the following steps:

[0086] Perform neural network resource demand analysis on each subtask in the subtask division scheme. Based on the calculation feature classification table and the first-level cache space allocation table, calculate the synaptic weight space, neuron activation space, and pulse signal transmission space required for each subtask. Compare the space requirements with the dynamic monitoring data of the cache unit to obtain the subtask resource occupancy distribution table.

[0087] Construct a resource requirement vector based on the subtask resource occupancy distribution table, organize the synaptic computing resource requirements, storage space requirements, and data transmission bandwidth requirements into vectors, and obtain the resource requirement vector of each subtask;

[0088] Collect performance parameters of multiple neuromorphic cores, assign sequences according to core numbers, record the current synaptic computing capacity, cache space margin, and communication bandwidth margin of each core, and read the core working status mark in the cache resource dynamic management strategy to obtain the neuromorphic core status data set;

[0089] Convert the neuromorphic core state data set into a core state matrix, and perform core screening on the core state matrix to obtain a valid core list;

[0090] A resource matching calculation model is constructed based on the effective core list and resource demand vector. The resource matching degree between each subtask and the candidate core is calculated using vector inner product operation. The calculation results are combined with the data dependency constraints in the dependency strength matrix to obtain a comprehensive matching score table.

[0091] According to the comprehensive matching score table, task allocation optimization is performed, and the bipartite graph maximum weight matching algorithm is used to pair subtasks and neuromorphic cores one by one to obtain the core allocation plan;

[0092] The core allocation scheme is spatially optimized. Based on the physical layout of the first-level cache access path, subtasks with frequent data interactions are assigned to the neuromorphic core group with the closest physical distance to obtain a task-core mapping table.

[0093] Specifically, based on the computational feature classification table and the first-level cache space allocation table, the various resources required by each subtask in the computation process are determined, including synaptic weight space, neuron activation space, and pulse signal transmission space. For each subtask, let its synaptic weight requirement be , the neuron activation requirement is , the pulse signal transmission requirement is , then the calculation of these requirements is based on the information in the calculation characteristic classification table. represents the storage requirements of all synaptic connections in the subtask, represents the number of neurons that need to be activated and their state storage requirements, and It represents the demand for cache and bandwidth during the transmission of pulse signals between neurons. Compare the space demand of each subtask with the dynamic monitoring data of the cache unit to ensure that the current cache resources of the system can meet the needs of the subtask. By reading the current state of the cache unit, including its usage frequency, free space and other information, the subtask resource occupancy distribution table is obtained, which lists the specific requirements of each subtask for cache and other resources. According to the subtask resource occupancy distribution table, the resource demand vector of each subtask is constructed. Let the resource demand vector be ,in represents the synaptic computing resource demand, Indicates the storage space requirement. Represents the data transmission bandwidth requirement. Collect performance parameters of multiple neuromorphic cores. According to the core number allocation sequence, record the current synaptic computing capacity, cache space margin, and communication bandwidth margin of each core, and read the core working status mark in the cache resource dynamic management strategy to understand the workload status of each core. Suppose the current synaptic computing capacity of a core is , the cache space margin is , the bandwidth margin is , these parameters constitute a core state vector By summarizing the state vectors of all cores, we get the neuromorphic core state dataset. Convert the neuromorphic core state dataset into the core state matrix , each row of the matrix represents the state vector of a core. Perform core screening on the core state matrix, remove cores that are already in a high load state or have insufficient resources, and obtain a list of valid cores. The cores in the valid core list are used as candidate resources for subsequent task allocation to ensure that each subtask can be allocated sufficient computing and storage resources. Based on the valid core list and the resource requirement vector of each subtask, a resource matching calculation model is constructed. The calculation of resource matching is achieved through vector inner product operation. Let the resource requirement vector of the subtask be , the state vector of the candidate core is , then the matching degree Calculated by the following formula:

[0094] ;

[0095] in, Represents a subtask With candidate core The resource matching degree between them. The higher the matching degree, the more suitable the core is for executing the subtask. In order to make the matching result more reasonable, the matching degree calculation result is combined with the data dependency constraints in the dependency strength matrix to ensure that the data transmission requirements between tasks are taken into account, and a comprehensive matching degree score table is obtained. Based on the comprehensive matching degree score table, task allocation optimization is performed, and the bipartite graph maximum weight matching algorithm is used to pair subtasks and neuromorphic cores one by one to obtain a core allocation scheme. Among all possible allocation schemes, the scheme with the largest comprehensive matching degree is found to ensure that each subtask is assigned to the most suitable core and maximize resource utilization efficiency. The spatial position of the preliminary core allocation scheme is optimized. Based on the physical layout of the first-level cache access path, subtasks with frequent data interactions are assigned to the neuromorphic core group with the closest physical distance as much as possible to reduce the delay and overhead of data transmission. For example, based on the objective function of minimizing data transmission delay, a task-core mapping table is obtained.

[0096] In a specific embodiment, the process of executing step S5 may specifically include the following steps:

[0097] Performing connection strength analysis on the neuromorphic cores in the task-core mapping table to obtain a core connection strength distribution map, and organizing multiple neuromorphic cores in layers based on the core connection strength distribution map to obtain a ring-layer core distribution table;

[0098] According to the ring layer core distribution table, the intra-ring communication link is constructed, and a direct data channel is established for the adjacent neuromorphic cores in each ring layer. The data throughput capacity of the second-level cache unit is used as the link bandwidth upper limit, and the physical delay parameters and cache access overhead of the link are recorded to obtain the intra-ring communication link table;

[0099] The bandwidth of each link in the intra-ring communication link table is configured to obtain a link bandwidth configuration plan, and the inter-layer communication bridge point is designed based on the ring layer core distribution table to obtain an inter-layer bridging plan;

[0100] Prioritize the communication channels in the inter-layer bridging scheme to obtain the bridging channel control strategy, and establish a global routing table based on the intra-ring communication link table and the bridging channel control strategy. At the same time, the physical constraints of the first-level cache access path are used as routing cost factors to obtain the network routing solution.

[0101] The link reliability of the network routing scheme is verified, and the link load is evaluated by combining the dynamic monitoring data of the cache unit and the core state matrix to obtain a multi-layer ring collaborative computing network.

[0102] Specifically, the communication and data interaction frequencies between each neuromorphic core are counted to obtain the connection strength between the cores. With the core The connection strength between ,in Represents the frequency of data exchange or the demand for communication bandwidth between two cores. Based on these connection strengths, a core connection strength distribution graph is constructed to describe the mutual communication dependency and data interaction relationship between all cores. By analyzing the connection strength distribution graph, multiple neuromorphic cores are organized in layers according to their connection strengths, so that cores with frequent communication are assigned to the same layer to reduce data transmission delays and communication overhead, and a distribution table of ring layer cores is obtained. An intra-ring communication link is constructed based on the ring layer core distribution table. According to the ring layer core distribution table, a direct data channel is established for adjacent neuromorphic cores in each ring layer, so that these cores can efficiently exchange data. In order to ensure that the bandwidth of the link can meet the communication requirements, the data throughput capacity of the second-level cache unit is used as the bandwidth upper limit of the communication link. Assume that the bandwidth of the link is , the data throughput capacity of the second-level cache unit is , then:

[0103] ;

[0104] in, Indicates the maximum bandwidth of the link, Represents the maximum data transmission capacity of the second-level cache unit. By limiting the bandwidth of the link to the throughput capacity of the cache unit, link overload is avoided and the reliability of data transmission is improved. The physical delay parameters and cache access overhead of each link are recorded to obtain the intra-ring communication link table, which records the communication link information between cores in each ring layer, including bandwidth, delay, and access overhead. Based on the intra-ring communication link table, bandwidth is configured for each link to ensure that data transmission between cores can be carried out within the bandwidth allowed. For each link, let its required bandwidth be , the following conditions should be met:

[0105] ;

[0106] By properly configuring the bandwidth of each link, data transmission within the entire ring layer is made more efficient. At the same time, based on the ring layer core distribution table, inter-layer communication bridge points are designed to establish communication channels between different ring layers and obtain an inter-layer bridging solution. The role of the bridge point is to achieve cross-layer data transmission, so that data flows between different ring layers can be transmitted smoothly and improve the coordination of the system. For the communication channel in the inter-layer bridging solution, priority is configured to obtain the bridge channel control strategy. Assume that the priority of the bridge channel is , then for important data, a higher priority is given to ensure that it can be transmitted first. Based on the intra-ring communication link table and the bridge channel control strategy, a global routing table is established, and the physical constraints of the first-level cache access path are used as the routing cost factor to obtain the final network routing solution. Let the routing cost be , the physical constraints are , then:

[0107] ;

[0108] in, represents the cost of the route, is the physical constraint of the first-level cache access path, is the link bandwidth, is the priority of the bridge channel. By comprehensively considering these factors, an optimal network routing solution is constructed to ensure the efficiency and reliability of data transmission. The reliability of the link of the network routing solution is verified. Combined with the dynamic monitoring data of the cache unit and the core status matrix, the load of each link is evaluated to determine whether there is a link overload. Assume that the link load is , the dynamic monitoring data of the cache unit is , the core state matrix is , then the link load evaluation is expressed as:

[0109] ;

[0110] Through evaluation , determine whether the link is in a high-load state, and further optimize and adjust the network based on the evaluation results, and finally obtain a multi-layer ring collaborative computing network.

[0111] In a specific embodiment, the process of executing step S6 may specifically include the following steps:

[0112] The running status of each neuromorphic core in the multi-layer ring collaborative computing network is sampled and analyzed to obtain a core performance monitoring table. Based on the core performance monitoring table, a multi-dimensional performance evaluation system is constructed to obtain a performance indicator evaluation system.

[0113] Perform weighted calculation on multiple performance indicators in the performance indicator evaluation system to obtain a comprehensive performance score table, and perform performance grading on multiple neuromorphic cores based on the comprehensive performance score table to obtain a core load grading table;

[0114] Calculate the load balance based on the core load classification table to obtain the load balance evaluation result, optimize the load balance evaluation result and generate a task balancing plan;

[0115] According to the task balancing scheme, resources are reconfigured to partially migrate the synaptic computing tasks on the high-load core to the low-load core. At the same time, the bandwidth allocation parameters in the intra-ring communication link table and the bridge channel control strategy are adjusted, and the resource configuration information in the cache state management database is updated to obtain a dynamic load optimization strategy.

[0116] Specifically, the computing status of each core is monitored in real time, including its computing load, cache utilization, data transmission bandwidth and other performance indicators. By periodically sampling these status parameters, a core performance monitoring table is constructed. The sampling index is ,in represents the computational load of the core, Indicates cache utilization, Represents the data transmission bandwidth. Based on the core performance monitoring table, a multi-dimensional performance evaluation system is constructed to classify and quantify different performance indicators. Suppose the indicator set in the multi-dimensional performance evaluation system is , where each Indicates the core A performance indicator of the core, such as computing load, cache access efficiency, or data transmission latency. In order to comprehensively evaluate the performance of each core, these indicators are weighted and the weight of each indicator is set to , then the core Overall performance rating It is expressed as:

[0117] ;

[0118] in, Indicates the core The overall performance score of Indicates performance indicators The weight of each core is determined by the system's evaluation of the importance of each indicator. By calculating the comprehensive performance scores of all cores, a comprehensive performance score table is obtained to quantify the overall performance of each core. The performance of multiple neuromorphic cores is graded according to the comprehensive performance score table. Assume that the core score level is , according to a certain scoring range, each core is divided into different levels, such as high performance, medium performance and low performance, to obtain a core load classification table. Based on the core load classification table, the load balance degree is calculated to evaluate the load distribution of each core in the system. The load balance degree is measured by calculating the variance of the load of each core. Suppose there are a total of cores, whose load is , then the load balancing degree It is expressed as:

[0119] ;

[0120] in, Represents the average load of all cores, calculated as:

[0121] ;

[0122] By calculating the load balance , to understand the uniformity of the system load. If the value is large, it indicates that there is a significant load imbalance in the system, some cores are overloaded, and the resources of other cores are not fully utilized. According to the evaluation results of the load balance, the task allocation of the system is optimized and planned, and a task balancing plan is generated. Resources are reconfigured according to the task balancing plan. Some synaptic computing tasks on the high-load core are migrated to the low-load core to balance the computing load of each core. For example, suppose the core is a high-load core, and its synaptic computing task is , part of which Migrate to a less loaded core , so that the new task volume is , ,in Indicates the core The original task volume. Task migration effectively reduces the pressure on high-load cores, improves the utilization of low-load cores, and achieves load balancing of the system. While performing task migration, adjust the bandwidth allocation parameters in the intra-ring communication link table and the inter-layer bridging channel control strategy to adapt to the new task allocation situation. If the task volume of a core decreases, the corresponding communication link bandwidth demand will also decrease. Therefore, the bandwidth allocation of the link is appropriately reduced, and the excess bandwidth is reallocated to other required links to improve the overall bandwidth utilization. At the same time, update the resource configuration information in the cache status management database to reflect the latest resource allocation situation, ensure that each module in the system can obtain the latest configuration, thereby maintaining the consistency and stability of the system and obtaining a dynamic load optimization strategy.

[0123] The above describes the load balancing method of the low-power AI processor in the embodiment of the present invention. The following describes the load balancing device of the low-power AI processor in the embodiment of the present invention. Figure 2 , an embodiment of a load balancing device for a low-power AI processor in an embodiment of the present invention includes:

[0124] A partitioning module is used to partition cache resources of multiple neuromorphic cores in a low-power AI processor to obtain a two-layer cache structure;

[0125] An analysis module, used to analyze the characteristics of the target computing task according to the double-layer cache structure, and to construct a directed acyclic graph of the computing task and a dependency strength matrix;

[0126] The partitioning module is used to partition tasks based on the directed acyclic graph of computing tasks and the dependency strength matrix to obtain a subtask partitioning scheme;

[0127] Create a module to generate the resource requirement vector of each subtask according to the task division scheme, establish the core state matrix of each neuromorphic core, and create a task-core mapping table;

[0128] A processing module, for organizing the neuromorphic core into multiple concentric ring layers based on a task-core mapping table to obtain a multi-layer ring collaborative computing network;

[0129] The optimization module is used to calculate multiple performance indicators of each neuromorphic core based on a multi-layer ring collaborative computing network, and perform dynamic load optimization to obtain a dynamic load optimization strategy.

[0130] Through the cooperation of the above components, the access efficiency of cache resources is improved by dividing the instruction cache area, data cache area and synaptic weight cache area; the dynamic power management mechanism is adopted to power off the cache units with low frequency of access, reducing the static power consumption of the system; the refined management of cache resources is realized, and the cache space utilization rate is improved. The task segmentation scheme based on the directed acyclic graph of computing tasks and the dependency strength matrix reduces the data dependency overhead between tasks; the balanced distribution of computing load is achieved through the dynamic programming algorithm; the task priority mechanism considering the synaptic computing characteristics improves the execution efficiency of critical path tasks. The multi-layer ring collaborative computing network architecture reduces the communication delay between cores; the point-to-point link mechanism reduces the intermediate links of data transmission; the inter-layer bridging strategy optimizes the efficiency of cross-layer data transmission. Real-time monitoring and evaluation of system performance indicators realizes dynamic adjustment of resource allocation; the task migration mechanism based on load balancing avoids local resource overload; and the multi-dimensional performance evaluation system ensures the stable operation of the system. The cache management strategy based on access frequency reduces the overall power consumption of the system; the dynamic resource configuration mechanism improves hardware utilization; and the task locality optimization reduces the data movement overhead.

[0131] An embodiment of the present invention further provides a chip for implementing the above method.

[0132] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0133] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0134] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0135] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0136] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A load balancing method for a low-power AI processor, characterized in that: The method comprises: Divide cache resources of multiple neuromorphic cores in low-power AI processors to obtain a two-layer cache structure; Performing characteristic analysis on the target computing task according to the double-layer cache structure, and constructing a directed acyclic graph and a dependency strength matrix of the computing task; Based on the computing task directed acyclic graph and the dependency strength matrix, task segmentation is performed to obtain a subtask division scheme; Generate a resource requirement vector for each subtask according to the task division scheme, establish a core state matrix for each neuromorphic core, and create a task-core mapping table; Based on the task-core mapping table, the neuromorphic cores are organized into multiple concentric ring layers to obtain a multi-layer ring collaborative computing network; specifically, the method includes: performing connection strength analysis on the neuromorphic cores in the task-core mapping table to obtain a core connection strength distribution map, and hierarchically organizing the multiple neuromorphic cores based on the core connection strength distribution map to obtain a ring layer core distribution table; constructing an intra-ring communication link according to the ring layer core distribution table, establishing a direct data channel for adjacent neuromorphic cores in each ring layer, using the data throughput capacity of the second-level cache unit as the link bandwidth upper limit, and recording the physical delay parameters and cache access overhead of the link to obtain an intra-ring communication link table ; Perform bandwidth configuration on each link in the intra-ring communication link table to obtain a link bandwidth configuration plan, and design inter-layer communication bridge points based on the ring layer core distribution table to obtain an inter-layer bridging plan; Perform priority configuration on the communication channels in the inter-layer bridging plan to obtain a bridging channel control strategy, and establish a global routing table based on the intra-ring communication link table and the bridging channel control strategy, and use the physical constraints of the first-level cache access path as a routing cost factor to obtain a network routing plan; Perform link reliability verification on the network routing plan, combine the cache unit dynamic monitoring data and the core state matrix to perform link load evaluation, and obtain a multi-layer ring collaborative computing network; Based on the multi-layer ring collaborative computing network, multiple performance indicators of each neuromorphic core are calculated, and dynamic load optimization is performed to obtain a dynamic load optimization strategy.

2. The load balancing method for a low-power AI processor according to claim 1, characterized in that: The cache resources of multiple neuromorphic cores in the low-power AI processor are divided to obtain a double-layer cache structure, including: Assign processor core numbers to multiple neuromorphic cores in a low-power AI processor to obtain a core number assignment sequence; Performing first-level cache configuration on each of the neuromorphic cores, dividing the 192KB cache space into an instruction cache area, a data cache area, and a synaptic weight cache area according to the computing task characteristics of each neuromorphic core, and setting the read and write priority of each cache area to obtain a first-level cache space allocation table; Based on the first-level cache space allocation table, an internal data path of the neuromorphic core is constructed, and direct data links are established between the instruction cache area, the data cache area, and the synaptic weight cache area and the computing unit of the neuromorphic core respectively to obtain a first-level cache access path; Calculate the capacity of the total cache space of the processor, deduct the total capacity of the first-level cache of multiple neuromorphic cores from the total cache space, plan the remaining cache space as a shared storage area, and obtain the total capacity value of the second-level cache; Divide the storage unit according to the total capacity value of the second-level cache, divide the second-level cache into 256 independent cache units of equal size, configure each cache unit with an independent power control circuit and an access counter, and obtain a second-level cache unit distribution map; The access frequency of each cache unit in the second-level cache unit distribution map is monitored, and the number of read and write operations of the cache unit is recorded in each 100 millisecond sampling period by the access counter. When the average access frequency of 10 consecutive sampling periods is less than 100 times per second, a low-frequency access mark is generated to obtain dynamic monitoring data of the cache unit; Establishing a cache status management database based on the dynamic monitoring data of the cache unit, maintaining the cache resource allocation status by updating parameters in real time, and obtaining a cache resource dynamic management strategy; According to the cache resource dynamic management strategy, the power control circuit is used to perform power-off processing on the cache unit marked as low-frequency access. At the same time, the management authority of the cache unit is transferred from the current neuromorphic core to the system resource pool, and the relevant parameters are updated in the cache status management database to obtain a double-layer cache structure.

3. The load balancing method for a low-power AI processor according to claim 2, characterized in that: The characteristic analysis of the target computing task is performed according to the double-layer cache structure, and a directed acyclic graph of the computing task and a dependency strength matrix are constructed, including: Performing layered processing of the neural network model on the target computing task, extracting the number of neurons, synaptic weight distribution and data transmission requirements of each layer through a synaptic connection analyzer, and matching cache requirements based on the cache resource dynamic management strategy of the double-layer cache structure to obtain a hierarchical feature data table; Based on the hierarchical feature data table, computing modes are classified, and the computing operations of each layer are marked as synaptic weight calculation, neuron activation calculation, pulse signal transmission calculation, and synaptic plasticity calculation, and data mapping is performed according to the cache area type in the first-level cache space allocation table to obtain a computing feature classification table; Performing calculation density analysis according to the calculation feature classification table, matching the unit data processing amount of each calculation type with the data throughput capacity of the second-level cache unit, and taking into account the access frequency factor in the dynamic monitoring data of the cache unit, to obtain a calculation load density map; Calculating the synaptic connection strength of the inter-layer data flow in the hierarchical feature data table, multiplying the synaptic weight matrix between adjacent layers by the data transmission frequency, and combining the bandwidth limit of the first-level cache access path to obtain an inter-layer data dependency strength table; Constructing a neural computation graph based on the inter-layer data dependency strength table, taking each synaptic computation operation as an independent node, the data transmission path as a directed edge, marking the synaptic weight and transmission delay of each edge, and associating the cache unit allocation information in the cache resource dynamic management strategy, to obtain an initial computation dependency graph; Performing loop detection on the initial computation dependency graph, identifying loop dependencies in the data flow path through a topological sorting algorithm, decoupling the detected loop path through a parallel branch reconstruction method, and updating relevant parameters in the cache state management database to obtain a directed acyclic graph of computation tasks; A dependency quantification model is established according to the directed acyclic graph of the computing task, and the data transmission volume, memory access dependency and computing resource competition between any two computing nodes are calculated. The calculation results are filled into a dependency matrix of size N×N, where N is the total number of synaptic computing nodes, to obtain a dependency strength matrix.

4. The load balancing method for a low-power AI processor according to claim 3, characterized in that: The step of performing task segmentation based on the computing task directed acyclic graph and the dependency intensity matrix to obtain a subtask division scheme includes: Topologically sorting the synaptic computing nodes in the directed acyclic graph of the computing task, establishing a node execution priority order according to the inter-layer data dependency strength table, and establishing a one-to-one correspondence between the corresponding row and column relationships in the dependency strength matrix and the node numbers to obtain a computing node execution sequence; Inputting the computing node execution sequence into a state transfer model, constructing a dynamic programming state equation, and constraining the state space through the cache resource dynamic management strategy to obtain a task segmentation state space; A three-dimensional cost calculation model is constructed based on the task segmentation state space, and the synaptic computing load balance, data transmission overhead and cache resource utilization are used as calculation dimensions. Quantitative calculations are performed according to the computing load density map, the inter-layer data dependency intensity table and the cache unit dynamic monitoring data to obtain a task segmentation cost function; Searching for the optimal solution of the task partitioning cost function, calculating the cost values ​​of all states in the task partitioning state space by recursion, and verifying the cache access efficiency of the partitioning scheme by the access counter of the second-level cache unit, and obtaining a state transition path table; Perform optimal path backtracking according to the state transition path table, determine the set of synaptic computing nodes included in each subtask in turn, and write the corresponding cache resource demand into the cache state management database to obtain a basic task division table; Performing a balance evaluation on the basic task partitioning table, respectively calculating the variance coefficient of synaptic computation, the variance coefficient of cache access, and the variance coefficient of data transmission for each subtask, and when any coefficient exceeds 0.2, triggering a load adjustment operation according to the weight relationship in the dependency strength matrix, and obtaining a task balance adjustment rule; Reconstructing the subtask boundaries based on the task balance adjustment rule, adjusting the allocation scheme of the synaptic computing nodes so that the three variance coefficients of each subtask are all less than 0.2, and updating the corresponding cache unit allocation relationship in the cache state management database to obtain an optimized task allocation scheme; Priority calibration is performed on the subtasks in the optimization task allocation scheme, the critical path weight of each subtask in the directed acyclic graph of the computing task is calculated, execution priority is assigned according to the cache resource dynamic management strategy, and the priority information is written into the cache status management database to obtain a subtask division scheme.

5. The load balancing method for a low-power AI processor according to claim 4, characterized in that: Generating a resource requirement vector for each subtask according to the task division scheme, establishing a core state matrix for each neuromorphic core, and creating a task-core mapping table include: Performing a neural network resource demand analysis on each subtask in the subtask division scheme, calculating the synaptic weight space, neuron activation space, and pulse signal transmission space required for each subtask based on the calculation feature classification table and the first-level cache space allocation table, and comparing each space requirement with the cache unit dynamic monitoring data to obtain a subtask resource occupancy distribution table; Constructing a resource requirement vector according to the subtask resource occupancy distribution table, organizing the synaptic computing resource requirement, storage space requirement and data transmission bandwidth requirement into a vector, and obtaining a resource requirement vector for each subtask; Collecting performance parameters of the multiple neuromorphic cores, recording the current synaptic computing capacity, cache space margin, and communication bandwidth margin of each core according to the core number allocation sequence, and reading the core working status flag in the cache resource dynamic management strategy to obtain a neuromorphic core status data set; Converting the neuromorphic core state data set into a core state matrix, and performing core screening on the core state matrix to obtain a valid core list; Building a resource matching degree calculation model based on the effective core list and the resource demand vector, calculating the resource matching degree between each subtask and the candidate core by using a vector inner product operation, and combining the calculation result with the data dependency constraints in the dependency strength matrix to obtain a comprehensive matching degree score table; Perform task allocation optimization according to the comprehensive matching score table, use a bipartite graph maximum weight matching algorithm to pair subtasks and neuromorphic cores one by one, and obtain a core allocation plan; The core allocation scheme is spatially optimized, and based on the physical layout of the first-level cache access path, subtasks with frequent data interactions are allocated to the neuromorphic core group with the closest physical distance to obtain a task-core mapping table.

6. The load balancing method for a low-power AI processor according to claim 5, characterized in that: The method of calculating multiple performance indicators of each neuromorphic core based on the multi-layer ring collaborative computing network and performing dynamic load optimization to obtain a dynamic load optimization strategy includes: Sampling and analyzing the operating status of each neuromorphic core in the multi-layer ring collaborative computing network to obtain a core performance monitoring table, and constructing a multidimensional performance evaluation system based on the core performance monitoring table to obtain a performance indicator evaluation system; Performing weighted calculation on multiple performance indicators in the performance indicator evaluation system to obtain a comprehensive performance score table, and performing performance grading on the multiple neuromorphic cores according to the comprehensive performance score table to obtain a core load grading table; Calculating the load balance based on the core load classification table to obtain a load balance evaluation result, optimizing the load balance evaluation result, and generating a task balancing plan; According to the task balancing scheme, resources are reconfigured, and part of the synaptic computing tasks on the high-load core are migrated to the low-load core. At the same time, the bandwidth allocation parameters in the intra-ring communication link table and the bridge channel control strategy are adjusted, and the resource configuration information in the cache status management database is updated to obtain a dynamic load optimization strategy.

7. A load balancing device for a low-power AI processor, characterized in that: A method for performing a load balancing method for a low-power AI processor according to any one of claims 1 to 6, wherein the load balancing device for the low-power AI processor comprises: A partitioning module is used to partition cache resources of multiple neuromorphic cores in a low-power AI processor to obtain a two-layer cache structure; An analysis module, used to perform characteristic analysis on a target computing task according to the double-layer cache structure, and to construct a directed acyclic graph and a dependency strength matrix of the computing task; A partitioning module, used to partition tasks based on the computing task directed acyclic graph and the dependency intensity matrix to obtain a subtask partitioning scheme; A creation module is used to generate a resource requirement vector for each subtask according to the task division scheme, establish a core state matrix for each neuromorphic core, and create a task-core mapping table; A processing module, configured to organize the neuromorphic core into a plurality of concentric ring layers based on the task-core mapping table to obtain a multi-layer ring collaborative computing network; The optimization module is used to calculate multiple performance indicators of each neuromorphic core based on the multi-layer ring collaborative computing network, and perform dynamic load optimization to obtain a dynamic load optimization strategy.

8. A chip, characterized in that: A load balancing method for implementing a low-power AI processor as described in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the processor executes the load balancing method for a low-power AI processor as described in any one of claims 1 to 6.

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