Processor, single board, equipment and method for obtaining information

Abstract

The invention discloses a processor, a single board, equipment and a method for obtaining information, when the processor is suspended, a processor core cannot exchange information with other modules in the processor through a system bus, and when a monitoring module senses that the processor is suspended, field information of the processor can be obtained through a diagnosis bus, the field information is information which can be used for analyzing the hanging reason of the processor when the processor is hung. Thus, by deploying the monitoring module and the diagnosis bus in the processor, when the processor is suspended, the processor can obtain the field information when the processor is suspended without the help of other equipment externally connected with the processor, so that it is possible to obtain the field information more simply and safely when the processor is suspended; therefore, the performance of the processor is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a processor, a single board, a device, and a method for obtaining information. Background Art

[0002] As the core component of various devices, the quality of the processor is related to the performance of the device. If the processor hangs due to various software and hardware anomalies, it will affect the operation of the system where the processor is located. If it is possible to obtain key information when the processor hangs after it hangs, and analyze the key information to determine the cause of the processor hang, in the subsequent work of the processor, it will be possible to avoid the processor from repeatedly hanging due to the same reason and improve the performance of the processor. Therefore, how to simply and safely obtain key information when the processor hangs after it hangs is a technical problem that urgently needs a solution. Summary of the invention

[0003] Based on this, the present application provides a processor, a single board, a device and a method for obtaining information, which can simply and conveniently obtain the key information of the processor when the processor hangs, providing a basis for analyzing the cause of the processor hang.

[0004] In the first aspect, the present application provides a processor, which may include a monitoring module and a diagnostic bus. The monitoring module is used to obtain field information of the processor through the diagnostic bus when it is determined that the processor is hung, and the field information is used to determine the cause of the processor hanging, and the processor hanging is a state in which the processor stops running. In this way, by deploying the monitoring module and the diagnostic bus inside the processor, when the processor hangs, the processor itself can obtain the field information when the processor hangs without the help of other devices external to the processor, making it possible to obtain field information more simply and safely when the processor hangs.

[0005] In a possible implementation, the monitoring module is further used to save the on-site information to a memory connected to the processor. In this way, if it is necessary to analyze the cause of the processor hang, the on-site information when the processor hangs can be read from the memory, providing a basis for analyzing the cause of the processor hang.

[0006] In a possible implementation, the monitoring module is specifically used to determine that the processor is hung when no message from the processor core is received within a preset period of time. In this way, during the normal monitoring message interaction between the monitoring module and the processor core, the operating state of the processor can be sensed, making it possible to obtain on-site information when the processor is hung.

[0007] In a possible implementation, the processor also includes a processor core, and the processor core is used to send an abnormal indication to the monitoring module through the diagnostic bus when determining that the processor is dead; the monitoring module is specifically used to determine that the processor is dead based on the abnormal indication. In this way, when the processor core determines that the processor is dead, it believes that it cannot collect "last words" and informs the monitoring module that the processor is dead, triggering the monitoring module to execute an action to obtain on-site information when the processor is dead. For example, the processor core can have an out-of-band interface. For example, when the processor core is not dead, the out-of-band interface is at a low level. When the processor core is dead, the out-of-band interface can send a high level to the monitoring module through the diagnostic bus, and the high level can be understood as the above-mentioned abnormal indication; for another example, when the processor core is not dead, the out-of-band interface is at a high level. When the processor core is dead, the out-of-band interface can send a low level to the monitoring module through the diagnostic bus, and the low level can be understood as the above-mentioned abnormal indication.

[0008] As an example, the field information may include a processor core and other modules, and the field information may include relevant information of the processor and relevant information of the other modules, and the other modules include at least one of the following modules: a power processing unit (power processor element, PPE), a network processor (network processor, NP) or a double data rate controller (double data rate controller, DDRC).

[0009] As an example, the processor may be any one of the following types: a central processing unit (CPU) or a graphics processing unit (GPU).

[0010] As an example, the diagnostic bus may be any one of the following buses: a data joint test action group (DJTAG) bus, a joint test action group (JTAG) bus, or an out-of-band bus.

[0011] As an example, the monitoring module may be, for example, an internal monitor unit (IMU).

[0012] In a second aspect, the present application further provides a single board, which may include at least a first memory and the processor provided in the first aspect, wherein the first memory is used to store the field information.

[0013] In a possible implementation, the single board may be a main control board. As an example, the first memory is a power-off non-volatile storage unit in the main control board, which is used to save the field information acquired by the monitoring module. As another example, the first memory is a power-off volatile storage unit in the single board, and the single board may also include a second memory, and the second memory is a power-off non-volatile storage unit. Then, the first memory is also used to save the field information to the second memory; thus, the second memory is used to save the field information.

[0014] Among them, the power-off volatile storage unit has a faster storage speed than the power-off non-volatile storage unit, so the processor can first store the field information in the power-off volatile storage unit, and then transfer the field information from the power-off volatile storage unit to the power-off non-volatile storage unit when idle. In addition, the single board can also include a power-off non-volatile storage unit, then the memory can save the field information in the power-off volatile storage unit, and read it from the power-off volatile storage unit when needed, or transfer the field information from the power-off volatile storage unit of the single board to the power-off non-volatile storage unit external to the single board when idle.

[0015] In another possible implementation, the single board may be a business board or a network board. As an example, the first memory is a power-off non-volatile storage unit included in the main control board of the device where the single board is located, and is used to save the field information acquired by the monitoring module. As another example, the first memory is a power-off volatile storage unit in the single board, and the device where the single board is located also includes a main control board, and the main control board includes a second memory, and the second memory is a power-off non-volatile storage unit. The first memory is also used to save the field information to the second memory through the main control board; the second memory is used to save the field information.

[0016] In a third aspect, the present application further provides a device, which may include the single board provided in the above second aspect.

[0017] In the fourth aspect, the present application also provides a method for obtaining information, which method may include, for example: when the monitoring module of the processor determines that the processor is hung, the monitoring module obtains the field information of the processor through the diagnostic bus, and the field information is used to determine the cause of the processor hanging. The processor hanging is a state in which the processor stops running. The monitoring module is a module in the processor that monitors the processor through the diagnostic bus. It can be seen that under the condition that the present application provides a processor including a monitoring module and a diagnostic bus, through this method, the monitoring module of the processor not only senses that the processor is hung, but also can obtain the field information of the processor through the diagnostic bus when the processor is sensed to be hung, and the "last words" of the processor when it is hung can be recorded without the help of other devices external to the processor. The processor can obtain field information more simply and safely, making it possible to conveniently and safely analyze the cause of the processor hanging.

[0018] In one possible implementation, the monitoring module determines that the processor is hung, including: the monitoring module does not receive a message from the processor core for a preset period of time; or, the monitoring module receives an abnormal indication sent by the processor core through the diagnostic bus, and the abnormal indication is generated by the processor core when determining that the processor is hung.

[0019] In a possible implementation, when the monitoring module saves the field information to a first memory connected to the processor, a collection success flag of the first memory is set, and the processor is restarted.

[0020] In a possible implementation, the first memory is a power-off volatile storage unit connected to the processor, and the processor is also connected to a second memory, and the second memory is a power-off non-volatile storage unit. The method also includes: after the processor is restarted, the processor determines that the collection success flag is in position, then transfers the field information to the second memory, and deletes the field information from the first memory.

[0021] In one possible implementation, the method also includes: after the processor is restarted, the processor obtains the top address information of the call stack, the top address information of the call stack is used to determine the complete information of the call stack in combination with the field information, and the complete information of the call stack is used to indicate the function call relationship of the processor core.

[0022] In one possible implementation, the field information includes exception stack information and register status information. The exception stack information is used to determine the complete information of the call stack. The complete information of the call stack is used to indicate the function call relationship of the processor core. The register status information is used to determine the cause of the processor hang in combination with the complete information of the call stack.

[0023] In a fifth aspect, the present application provides a computer-readable storage medium, in which instructions are stored, and when the computer-readable storage medium is executed on a processor, the computer executes the operation steps of the method in the fourth aspect.

[0024] In a sixth aspect, the present application provides a computer program product comprising instructions, which, when executed on a processor, enables the computer to execute the operating steps of the method in the fourth aspect.

[0025] Based on the implementations provided in the above aspects, the present application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0027] Figure 1 A schematic diagram of a scenario for obtaining key information when a processor hangs;

[0028] Figure 2 A schematic diagram of another scenario for obtaining key information when a processor hangs;

[0029] Figure 3 A schematic diagram of the structure of a CPU 300 in an embodiment of the present application;

[0030] Figure 4 This is a schematic diagram of the structure of a single board 400 in an embodiment of the present application;

[0031] Figure 5 This is a flow chart of recording on-site information by a single board 400 when a CPU 300 hangs up in an embodiment of the present application;

[0032] Figure 6 This is a schematic diagram of the structure of a device 600 in an embodiment of the present application;

[0033] Figure 7 This is a flow chart of recording on-site information by the board 620 when the CPU 621 is hung up in an embodiment of the present application;

[0034] Figure 8 A schematic diagram of a flow chart of a method 100 for obtaining information in an embodiment of the present application;

[0035] Fig. 9 Schematic diagram of the structure of a device 900 for obtaining information in an embodiment of the present application. DETAILED DESCRIPTION

[0036] Nowadays, electronic devices are widely used in all walks of life, and processors are the core components of electronic devices. The stable operation of processors is one of the manifestations of the reliability and safety of electronic devices. However, due to various software and hardware reasons, the processor may hang. At this time, it is necessary to record some key information on the processor when the processor hangs. This key information can be used to analyze the cause of the processor hang, which can be figuratively understood as the "last words" of the processor when it hangs. Only by determining the cause of the processor hang can the processor be prevented from hanging again due to the cause during subsequent processor operation, so as to improve the reliability of the processor and the electronic device where the processor is located.

[0037] The situation such as the system bus in the processor being hung, the processor core interrupt nesting being hung or the double data rate controller (DDRC) being abnormal in the processor will cause the processor to be unable to record any information and the processor core will not respond to external interrupts, resulting in the "processor hanging" referred to in the embodiments of the present application. For example, a software access exception causes an abnormality in the system bus in the processor, causing the processor to hang. In this case, the processor core cannot access the storage unit under the system bus. Even if the processor core obtains key information that can be used to analyze the cause of the processor hanging, it cannot store this key information in the storage unit, that is, the processor cannot record any information. For another example, the processor's cache is abnormal, triggering the processor core to enter the exception handler, causing the processor to hang. In this case, the processor is also unable to record any information.

[0038] Combine the following Figure 1 and Figure 2 This article introduces two current methods for obtaining key information when a processor hangs.

[0039] One of the current ways to obtain key information when a processor hangs can be understood as a monitoring solution of "host computer + joint test action group (JTAG)". Figure 1As shown, the scenario may include: a processor 1, a device 2 and a personal computer (PC) 3. The processor 1 may include but is not limited to: at least one processor core 11, a network processor (NP) 12, a power processor element (PPE) 13, a system bus 14, a JTAG bus 15 and a JTAG interface 16. The device 2 may include a JTAG emulator 21, and the PC 3 includes a superior software 31 corresponding to the JTAG emulator 21. When the processor 1 is hung, the processor 1 loses the ability to record information. Then, the user can initiate access to the processor core 11, NP 12 and PPE 13 modules on the processor 1 through the JTAG emulator 21, the JTAG interface 16 and the JTAG bus 15 on the device 2 by operating the software 31 on the PC 3, so as to obtain key information on the processor 1 when the processor 1 is hung, and provide data basis for analyzing the cause of the processor 1 hanging. However, this solution requires external devices 2 and PC 3 to be connected to processor 1, which is an offline solution. It has the following shortcomings: on the one hand, it cannot be deployed in the current network operation scenario; on the other hand, for security reasons, the device integrating the processor usually shields the JTAG interface on the processor, resulting in the solution being unable to achieve the purpose of obtaining key information when the processor hangs. Moreover, for the situation where the processor hangs due to a problem with a small probability of recurrence, this offline solution often takes a long time to reproduce the situation when the processor hangs.

[0040] Another current way to obtain key information when a processor hangs can be understood as an "external coprocessor" monitoring solution. Figure 2 As shown, the scenario may include: a processor 1 and a baseboard management controller (BMC) 2, and the processor 1 may include but is not limited to: at least one processor core 11, NP 12, PPE 13, system bus 14, outband bus 15 and outband interface 16. When the processor 1 is hung, the processor 1 loses the ability to record information. Then, when the BMC 2 senses that the processor 1 is hung, it can access the processor core 11, NP 12 and PPE 13 on the processor 1 through the outband interface 16 and the outband bus 15 to obtain the key information on the processor 1 when the processor 1 is hung, which provides data basis for analyzing the cause of the processor 1 hanging. However, the shortcomings of this solution include: on the one hand, it is necessary to add a BMC outside the processor, which increases the cost of chip design, single board design and product design, and increases the complexity of the solution; on the other hand, adding a BMC connected to the processor outside the processor increases the hardware security risk.

[0041] Based on this, an embodiment of the present application provides a processor, which includes, in addition to at least one processor core and a system bus, a monitoring module and a diagnostic bus, and at least one processor core and the monitoring module are connected both through the system bus and through the diagnostic bus. When the processor is working normally, the processor core exchanges information with other modules (including the monitoring module) in the processor through the system bus, and the monitoring module monitors the working status of the processor core. When the monitoring module senses that the processor is dead, it can obtain the on-site information of the processor (i.e., the above-mentioned key information or "last words") through the diagnostic bus. The on-site information is information that can be used to analyze the cause of the processor dead when the processor is dead. In this way, by deploying a monitoring module and a diagnostic bus inside the processor, when the processor is dead, the processor itself can obtain the on-site information when the processor is dead, without the help of other devices external to the processor, making it possible to obtain on-site information more simply and safely when the processor is dead.

[0042] In the embodiment of the present application, a processor hang can be understood as one or more processor cores in the processor being unable to respond to any external interrupt, especially unable to respond to the highest level interrupt, which can be, for example, a "last words" interrupt. A processor hang, for a target processor core that is unable to respond to the highest level interrupt, means that the target processor core is unable to record the processor's field information and is unable to respond to other interrupts. The processor core hereinafter can be understood as the above-mentioned target processor core.

[0043] In the embodiment of the present application, the processor may include but is not limited to any of the following types: a central processing unit (CPU) or a graphics processing unit (GPU). As long as the processor has a processor core and a system bus, and a monitoring module and a diagnostic bus can be added internally, it belongs to the processor mentioned in the embodiment of the present application. The following description takes the processor as an example of a CPU.

[0044] In the embodiment of the present application, the diagnostic bus may include but is not limited to any one of the following buses: a JTAG bus, a Data Joint Test Action Group (DJTAG) bus, or an out-of-band bus. As long as the bus type (except the system bus) can connect the modules in the processor, it can be used as the diagnostic bus mentioned in the embodiment of the present application. The diagnostic bus is described below as an example of a DJTAG bus.

[0045] In the embodiment of the present application, the monitoring module can be implemented by a coprocessor such as an internal monitoring unit (IMU) that has a monitoring function and can communicate with other modules in the processor through a diagnostic bus. As long as the module can be used to monitor the operating status of the processor core and obtain information on each module of the processor (including the processor core), it can be used as the monitoring module mentioned in the embodiment of the present application. The monitoring module only reflects the monitoring function of each module in the processor. Whether it can control each module in the processor does not belong to the scope of the embodiment of the present application. The following description takes the monitoring module as an IMU as an example.

[0046] In an embodiment of the present application, the field information obtained by the monitoring module may include relevant information of the processor core, and may also include relevant information of other modules in the processor. Other modules may include, but are not limited to, at least one of the following modules: PPE, NP, or DDRC. If the cause of the processor hang can be determined by analyzing only the relevant information of the processor core, then the monitoring module can only obtain relevant information of the processor core; if the cause of the processor hang needs to be determined only by comprehensively analyzing the relevant information of each module in the processor, then the monitoring module can obtain relevant information of each module in the processor. As long as the field information of the cause of the processor hang can be determined by analysis, the field information specifically obtained by the monitoring module can be used. The following is an example of the monitoring module obtaining the field information of the processor core and other modules in the processor.

[0047] In the embodiment of the present application, for a processor including multiple processor cores, if the failure of some processor cores causes the processor to hang, then, in one case, the monitoring module can only obtain the field information of the failed processor core, or the monitoring module can also obtain the field information of the failed processor core and other modules, without obtaining the field information of other processor cores that have not failed; in another case, the monitoring module can obtain the field information of all processor cores, or the monitoring module can also obtain the field information of all processor cores and other modules without distinguishing which of the field information comes from the failed processor core. Regardless of what the obtained field information includes, as long as the cause of the processor hang can be analyzed based on the field information, it can belong to the field information to be obtained in the embodiment of the present application.

[0048] For greater clarity, the technical solution provided in the embodiments of the present application is introduced below in conjunction with the accompanying drawings.

[0049] Figure 3 A schematic diagram of the structure of a CPU 300 provided in an embodiment of the present application is shown. Figure 3As shown, the CPU 300 includes: a CPU core 311, a CPU core 312, ..., a CPU core 31N, a system bus 320, a DJTAG bus 330, an IMU 340, an NP 350, a PPE 360, and a DDRC 370. N is an integer greater than 1.

[0050] In CPU 300, CPU core 311, CPU core 312, ..., CPU core 31N, IMU 340, NP 350, PPE 360 and DDRC 370 are connected through system bus 320 and DJTAG bus 330. System bus 320 can be understood as a bus belonging to each CPU core, that is, when each CPU core works normally, the CPU core interacts with other modules in CPU 300 through system bus 320; DJTAG bus 330 can be understood as a bus belonging to IMU 340, that is, when IMU 340 senses that CPU 300 is hung, the IMU 340 interacts with other modules in CPU 300 through DJTAG bus 330 to obtain field information.

[0051] After the single board where the CPU 300 is located is started, the IMU 340 is also started normally, and the IMU 340 begins to monitor each module in the CPU 300. For example, the IMU 340 is used to monitor each CPU core.

[0052] The strategy for recording on-site information when the CPU 300 hangs up may include, for example, the following two possible implementations.

[0053] In one implementation, the strategy of the CPU 300 for recording the on-site information may be: the CPU core in the CPU 300 cooperates with the IMU 340 to implement the recording of the on-site information. As an example, the process of recording the field information of CPU 300 may include: S11, CPU core attempts to obtain the field information of each module in CPU 300 through system bus 320, if successful, execute S12 to S13, otherwise execute S14; S12, CPU core records the obtained field information 1 into memory 1 in the single board where CPU 300 is located; S13, IMU 340 senses that CPU core has obtained the field information of each module in CPU 300, and IMU 340 resets CPU 300; S14, IMU 340 senses that CPU 300 is hung, IMU 340 obtains field information 2 of each module in CPU 300 through DJTAG bus 330, records the obtained field information 2 into memory 1 in the single board where CPU 300 is located, and IMU 340 resets CPU 300; S15, CPU After the memory 1 in the single board where CPU 300 is located records the field information 1 or the field information 2, the collection success flag is set; S16, after CPU 300 is reset, if the collection success flag in the memory 1 is set, the field information 1 or the field information 2 in the memory 1 is transferred to the memory 2, and the stack top address information of the call stack is saved in the memory 2, so that the complete information of the call stack when CPU 300 is hung this time can be determined based on the stack top address information of the call stack in the memory 2 and the exception stack information in the field information 1 or the field information 2. The complete information of the call stack is used to indicate the function call relationship of the CPU core when CPU 300 is hung, so that the reason for the hang of CPU 300 is determined based on the register status information included in the field information 1 or the field information 2 in the memory 2 and the complete information of the call stack.

[0054] The way in which IMU 340 senses that CPU 300 is hung may include but is not limited to: way 1, if IMU 340 does not receive a response message from CPU core to a monitoring message sent by IMU 340 within a preset time, IMU 340 determines that CPU 300 is hung; way 2, IMU 340 receives an abnormal indication sent by CPU core via DJTAG bus 330. Generally, if CPU core fails to obtain the on-site information of each module in CPU 300 via system bus 320, CPU core will send an abnormal indication to IMU 340 via DJTAG bus 330.

[0055] If the way in which IMU 340 senses that CPU 300 is hung is the above-mentioned way one, the way in which IMU 340 senses whether CPU core has successfully acquired the on-site information of each module in CPU 300 may be: IMU 340 receives a record indication sent by CPU core through DJTAG bus 330, and the record indication is used to indicate whether CPU core has successfully acquired the on-site information of each module in CPU 300. For example, when the record indication is a first value (such as 1), it indicates that CPU core has successfully acquired the on-site information of each module in CPU 300; and when the record indication is a second value (such as 0), it indicates that CPU core has failed to acquire the on-site information of each module in CPU 300. If the way in which IMU 340 senses that CPU 300 is hung is the above-mentioned way 2, the way in which IMU 340 senses whether CPU core has successfully obtained the on-site information of each module in CPU 300 may include: in one case, IMU 340 receives an abnormal indication sent by CPU core through DJTAG bus 330, and the abnormal indication is also used to indicate whether CPU core has successfully obtained the on-site information of each module in CPU 300; in another case, the information sent by CPU core through DJTAG bus 330 received by IMU 340 includes not only the abnormal indication but also the record indication, and the record indication is used to indicate whether CPU core has successfully obtained the on-site information of each module in CPU 300.

[0056] It should be noted that the above-mentioned methods of recording the on-site information of the CPU 300 in S11 to S16 are only exemplary, and other possible recording methods may also be adopted based on requirements.

[0057] In another implementation, the strategy of CPU 300 for recording field information may be: the CPU core and IMU 340 in CPU 300 each independently implement the recording of field information. As an example, the process of recording the field information of CPU 300 may include: S21, the CPU core attempts to obtain the field information of each module in CPU 300 through the system bus 320, and if successful, executes S22; S22, the CPU core records the obtained field information 1 into the memory 1 in the single board where CPU 300 is located; S23, IMU 340 senses that CPU 300 is hung, IMU 340 obtains the field information 2 of each module in CPU 300 through DJTAG bus 330, and records the obtained field information 2 into the memory 1 in the single board where CPU 300 is located; S24, IMU340 resets CPU 300; S25, after the memory 1 in the single board where CPU 300 is located records the field information 1 or field information 2, the collection success flag is set; S26, CPU After 300 is reset, if the collection success flag in memory 1 is set, the field information 1 or field information 2 in memory 1 is transferred to memory 2, and the stack top address information of the call stack is saved in memory 2, so that the complete information of the call stack when CPU 300 is hung this time can be determined based on the stack top address information of the call stack in memory 2 and the exception stack information in field information 1 or field information 2. The complete information of the call stack is used to indicate the function call relationship of the CPU core when CPU 300 is hung, so that the cause of the CPU 300 hanging can be determined based on the register state information included in the field information 1 or field information 2 in memory 2 and the complete information of the call stack. It should be noted that there is no order limit for the execution of S21-S22 and S23. S21-S22 can be executed first and then S23, or S23 can be executed first and then S21-S22, or S21-S22 and S23 can be executed at the same time.

[0058] In the above two implementations, the CPU core attempts to obtain the field information of each module in the CPU 300 through the system bus 320. Regardless of whether the CPU core successfully obtains the field information, as long as the IMU 340 senses that the CPU 300 is hung, the field information 2 of each module in the CPU 300 is obtained through the DJTAG bus 330. If the CPU core also obtains the field information 1, then when the field information 2 is saved in the memory 1, if the field information 2 has been saved in the memory 1, then, in one case, when it is determined by comparison that the field information 2 is the same as the field information 1, only the field information 1 (or the field information 2) is saved in the memory 1; in another case, the field information 1 and the field information 2 can be saved in the memory 1 at the same time, and the comparative analysis is performed when analyzing the cause of the CPU 300 hanging.

[0059] In the above two implementations, memory 1 and memory 2 both refer to non-volatile storage units connected to CPU 300. Memory 1 may be a storage unit that is non-volatile upon reset but volatile upon power failure, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). Memory 2 may be a storage unit that is non-volatile upon reset and non-volatile upon power failure, such as a flash memory or a serial advanced technology attachment (SATA) memory. Both memory 1 and memory 2 can be deployed on the single board where CPU 300 is located. Then, the device where the single board is located can be, for example, a box-type device. A box-type device can be understood as a device that only includes one single board. Alternatively, the single board can also be, for example, a main control board in a frame-type device. A frame-type device can be understood as a device that includes multiple types of single boards. The multiple types of single boards can include, for example: a main control board, a service board, or a network board. Alternatively, memory 1 is deployed on single board 1 where CPU 300 is located, and memory 2 can be deployed on single board 2 that belongs to the same device as single board 1. Single board 1 can be, for example, a service board or a network board in a frame-type device, and single board 2 can be, for example, a main control board of the device. Single board 1 and single board 2 can interact using an inter-board management channel.

[0060] visible, Figure 3In the CPU 300 shown, by internally deploying the IMU 340 and the DJTAG bus 330, when the CPU 300 hangs, the CPU 300 itself can obtain the on-site information when the CPU 300 hangs, without the need to rely on other devices external to the CPU 300, so that when the CPU 300 hangs, it is easier and safer to obtain on-site information, which provides an analysis basis for analyzing the cause of the CPU 300 hanging, makes the reliable operation of the CPU 300 possible, and improves the performance of the CPU 300.

[0061] It should be noted that, if “the CPU core attempts to obtain the on-site information of each module within the CPU 300 through the system bus 320” is successful, it can be considered that the CPU 300 has an exception but the CPU 300 is not hung. When the CPU 300 is not hung but an exception occurs, the “CPU core attempts to obtain the on-site information of each module within the CPU 300 through the system bus 320” can be executed and there is a possibility that the “CPU core attempts to obtain the on-site information of each module within the CPU 300 through the system bus 320” is successful.

[0062] Figure 4 FIG. 4 shows a schematic diagram of the structure of a single board 400 provided in an embodiment of the present application. Figure 4 As shown, the single board 400 may include Figure 3 The CPU 300 shown, the single board 400 may also include: a memory 1 and a memory 2.

[0063] Among them, both memory 1 and memory 2 may refer to non-volatile storage units connected to CPU 300. Memory 1 may be a storage unit that is non-volatile upon reset but volatile upon power failure, such as DRAM or SRAM. Memory 2 may be a storage unit that is non-volatile upon reset and non-volatile upon power failure, such as Flash memory or SATA memory.

[0064] Single board 400 can be, for example, a single board in a device such as a box-type device that only includes one single board, or single board 400 can be, for example, a main control board in a device such as a frame-type device that includes multiple types of single boards. The multiple types of single boards in the device can include, for example: a main control board, a business board or a network board.

[0065] As an example, when CPU 300 hangs, Figure 5 As shown, the process of recording the on-site information by the single board 400 may include:

[0066] S31, the CPU core attempts to obtain the field information of each module in the CPU 300 through the system bus 320. If successful, S32 to S33 are executed, otherwise S34 is executed.

[0067] S32, the CPU core records the acquired field information 1 into the memory 1.

[0068] S33 , the IMU 340 senses that the CPU 300 is hung, and the IMU 340 resets the CPU 300 .

[0069] S34, IMU 340 senses that CPU 300 is hung, IMU 340 obtains field information 2 of each module in CPU 300 through DJTAG bus 330, records the obtained field information 2 into memory 1, and IMU 340 resets CPU 300.

[0070] S35, after the memory 1 records the scene information 1 or the scene information 2, the collection success flag is set.

[0071] S36, after the CPU 300 is reset, if the collection success flag in the memory 1 is set, the scene information 1 or the scene information 2 in the memory 1 is transferred to the memory 2, and the stack top address information of the call stack is saved in the memory 2.

[0072] It is understandable that when the single board 400 is started, it is first necessary to check whether the collection success flag in the memory 1 is set. If it is set, the program counter (PC) pointer is deduced according to the field information 1 or field information 2 stored in the memory 1. The previous and subsequent preset number (such as 10) instructions are derived to obtain the exception stack information before the CPU 300 is reset. Then, the register state information, the exception stack information and the stack top address information of the call stack (also called the head address information of the call stack) are transferred to the memory 2, and the field information 1 or field information 2 in the memory 1 is cleared.

[0073] In this way, based on the top address information of the call stack in the memory 2 and the exception stack information in the field information 1 or the field information 2, the complete information of the call stack when the CPU 300 is hung this time is determined. The complete information of the call stack is used to indicate the function call relationship of the CPU core when the CPU 300 is hung. Therefore, the reason for the CPU 300 hanging is determined based on the register status information included in the field information 1 or the field information 2 in the memory 2 and the complete information of the call stack.

[0074] Figure 6 A schematic diagram of the structure of a device 600 provided in an embodiment of the present application is shown. Figure 6As shown, the device 600 may include a main control board 610 and a service board 620, and an inter-board management channel 630 may be included between the main control board 610 and the service board 620. The device 600 may be, for example, a frame-type device. The service board 620 may also be any other type of single board in the device 600 except the main control board 610, for example, the service board 620 may also be replaced by a network board (also referred to as an interface board or a forwarding board).

[0075] The CPU in the main control board 610 can be recorded as CPU 611, and the CPU in the service board 620 can be recorded as CPU 621. Both CPU 611 and CPU 612 can refer to Figure 3 The reference numerals in the CPU 300, CPU 611 and CPU 612 shown in FIG. Figure 3 The main control board 610 may further include a memory 11 and a memory 12, and the service board 620 may further include a memory 21.

[0076] For the description of the memory 11 and the memory 21, please refer to the description of the memory 1. For the description of the memory 12, please refer to the description of the memory 2.

[0077] As an example, when the CPU 611 hangs, the process of the main control board 610 recording the scene information can be seen in Figure 5 The recording process shown is not limited in the embodiments of the present application.

[0078] As another example, when the CPU 621 hangs, Figure 7 As shown, the process of recording on-site information by the service board 620 may include:

[0079] S41, the CPU core attempts to obtain the field information of each module in the CPU 621 through the system bus 320. If successful, S42 to S43 are executed, otherwise S44 is executed.

[0080] S42 , the CPU core records the acquired field information 1 into the memory 21 .

[0081] S43, IMU 340 senses that CPU 621 is hung and IMU 340 resets CPU 621.

[0082] S44, IMU 340 senses that CPU 621 is hung, IMU 340 obtains field information 2 of each module in CPU 621 through DJTAG bus 330, records the obtained field information 2 into memory 21, and IMU 340 resets CPU 621.

[0083] S45, after the memory 21 records the scene information 1 or the scene information 2, the collection success flag is set.

[0084] S46, after the device 600 is reset, if the collection success flag in the memory 21 is set, the field information 1 or the field information 2 in the memory 21 is transferred to the memory 12 through the inter-board management channel 630, and the stack top address information of the call stack is saved in the memory 12.

[0085] It is understandable that when the device 600 is started, it first needs to check whether the collection success flag in the memory 21 is set. If it is set, the program counter (PC) pointer is deduced according to the field information 1 or field information 2 stored in the memory 21. The previous and subsequent preset number (such as 10) instructions are derived to obtain the exception stack information before the CPU 621 is reset. Then, the register state information, the exception stack information and the stack top address information of the call stack (also called the head address information of the call stack) are transferred to the memory 12 through the inter-board management channel 630, and the field information 1 or field information 2 in the memory 21 is cleared.

[0086] In this way, based on the top address information of the call stack in the memory 12 and the exception stack information in the field information 1 or the field information 2, the complete information of the call stack when the CPU 621 is hung this time is determined. The complete information of the call stack is used to indicate the function call relationship of the CPU core when the CPU 621 is hung. Therefore, the reason for the hang of the CPU 621 is determined based on the register status information included in the field information 1 or the field information 2 in the memory 2 and the complete information of the call stack.

[0087] Figure 8 A schematic diagram of a method 100 for obtaining information provided in an embodiment of the present application is shown. Figure 8 As shown, the method 100 is applied to a device including a processor, in which a monitoring module and a diagnostic bus are added, and the monitoring module monitors other modules in the processor through the diagnostic bus. The processor may be, for example, Figure 3 to Figure 7 The method 100 may include, for example, the following S101:

[0088] S101, when the monitoring module determines that the processor is hung, the monitoring module obtains the field information of the processor through the diagnostic bus, and the field information is used to determine the cause of the processor hanging. The processor hanging is a state in which the processor stops running. The monitoring module is a module in the processor that monitors the processor through the diagnostic bus.

[0089] As an example, the monitoring module determining that the processor is hung in S101 may include: the monitoring module does not receive a message from the processor core for a preset period of time. The preset period of time may be determined based on the period of periodic interaction of monitoring messages between the monitoring module and the processor core, for example, the preset period of time may be equal to a preset number of the periods.

[0090] As another example, the monitoring module in S101 determines that the processor is hung, which may include: the monitoring module receives an abnormal indication sent by the processor core through the diagnostic bus, and the abnormal indication is generated by the processor core when determining that the processor is hung. The processor core sends the abnormal indication to the monitoring module through the diagnostic bus, which may be actively initiated by the processor core; or, it may be a response initiated based on an inquiry request from the monitoring module. For example, after the monitoring module senses that the processor is hung, it sends an inquiry request to the processor core through the diagnostic bus. When the processor core determines that the processor is hung, as a response to the inquiry request, it generates and sends an abnormal indication to the monitoring module through the diagnostic bus.

[0091] Optionally, the method 100 may further include:

[0092] S102, the monitoring module saves the field information to a first memory connected to the processor via a diagnostic bus.

[0093] As an example, when the monitoring module saves the field information to the first memory connected to the processor, the collection success flag of the first memory may be set, and the control processor may be restarted.

[0094] As an example, the first memory is a power-off volatile storage unit connected to the processor, and the processor is also connected to a second memory, and the second memory is a power-off non-volatile storage unit. The method 100 may also include: after the processor is restarted, the processor determines that the collection success flag is in position, then transfers the field information to the second memory, and deletes the field information from the first memory to free up space in the first memory to ensure the performance of the processor.

[0095] As an example, after the processor is restarted, the processor can also obtain the top address information of the call stack, which can be used to determine the complete information of the call stack in combination with the field information, and the complete information of the call stack is used to indicate the function call relationship of the processor core.

[0096] As an example, the field information may include exception stack information and register status information, wherein the exception stack information is used to determine the complete information of the call stack, the complete information of the call stack is used to indicate the function call relationship of the processor core, and the register status information is used to determine the cause of the processor hang in combination with the complete information of the call stack.

[0097] It can be seen that under the condition that the embodiment of the present application provides a processor including a monitoring module and a diagnostic bus, through the method 100, the monitoring module of the processor not only senses that the processor is hung, but also can obtain the on-site information of the processor core through the diagnostic bus when the processor is sensed to be hung, and the "last words" of the processor when it is hung can be recorded without the help of other devices external to the processor. The processor can obtain on-site information more simply and safely, making it possible to conveniently and safely analyze the cause of the processor hanging.

[0098] It should be noted that in the embodiments of the present application, hardware improvements may include: a monitoring module and a diagnostic bus are set up in the processor, and the monitoring module has the ability of a master node of the system bus and the diagnostic bus. Software improvements may include: the monitoring module can realize the state monitoring function of multiple processor cores, the function of collecting register state information, the function of collecting exception stack information, and the function of deriving complete information of the call stack.

[0099] Accordingly, Fig. 9 The present application provides a device 900 for obtaining information, which is applied to a device including a processor, and the processor includes a monitoring module. The device 900 for obtaining information includes: a receiving unit 901;

[0100] The receiving unit 901 is configured to, when a monitoring module of a processor determines that the processor is hung, obtain field information of the processor through a diagnostic bus by the monitoring module, wherein the field information is used to determine a cause of the processor being hung, wherein the processor being hung is a state in which the processor stops running, and the monitoring module is a module in the processor that monitors the processor through the diagnostic bus;

[0101] Optionally, the device 900 may further include a storage unit 902, wherein the storage unit 902 is used for the monitoring module to save the field information to a first memory connected to the processor via a diagnostic bus.

[0102] Optionally, the device 900 may further include a processing unit, which is specifically used to: the monitoring module does not receive a message from the processor core for a preset period of time, and determines that the processor is hung; or the monitoring module receives an abnormal indication sent by the processor core through the diagnostic bus, and determines that the processor is hung, and the abnormal indication is generated by the processor core when determining that the processor is hung.

[0103] Optionally, when the monitoring module saves the field information to a first memory connected to the processor, a collection success flag of the first memory is set, and the processor is restarted.

[0104] Optionally, the first memory is a power-off volatile storage unit connected to the processor, and the processor is also connected to a second memory, and the second memory is a power-off non-volatile storage unit. The storage unit 902 is also used for after the processor is restarted, the processor determines that the collection success flag is in position, then transfers the field information to the second memory, and deletes the field information from the first memory.

[0105] Optionally, the receiving unit 901 is also used for the processor to obtain the top address information of the call stack after the processor is restarted. The top address information of the call stack is used to determine the complete information of the call stack in combination with the field information. The complete information of the call stack is used to indicate the function call relationship of the processor core.

[0106] Optionally, the field information includes exception stack information and register status information, the exception stack information is used to determine the complete information of the call stack, the complete information of the call stack is used to indicate the function call relationship of the processor core, and the register status information is used to determine the cause of the processor hang in combination with the complete information of the call stack.

[0107] It can be seen that the device 900 of the embodiment of the present application can correspond to the method described in the embodiment of the present application, and the above and other operations and / or functions of each unit in the device 900 are respectively for implementing the corresponding processes of the above method. For the sake of brevity, they will not be repeated here.

[0108] The above is only a specific implementation of the present application. Those skilled in the art may conceive of changes or substitutions based on the specific implementation provided by the present application, which should all be included in the protection scope of the present application.

Claims

1. A processor, characterized in that: Including monitoring module and diagnostic bus, The monitoring module is used to obtain the field information of the processor through the diagnostic bus when determining that the processor is hung, and the field information is used to determine the cause of the processor hanging. The processor hanging is a state in which the processor stops running.

2. The processor according to claim 1, characterized in that It also includes the processor core, The monitoring module is specifically used to determine that the processor is hung when no message from the processor core is received within a preset period of time.

3. The processor according to claim 1, wherein: The processor also includes a processor core, The processor core is used to send an abnormal indication to the monitoring module through the diagnostic bus when determining that the processor is hung; The monitoring module is specifically configured to determine that the processor is hung based on the abnormal indication.

4. The processor according to any one of claims 1 to 3, characterized in that: The processor includes a processor core and other modules, the field information includes relevant information of the processor core and relevant information of the other modules, and the other modules include at least one of the following modules: a power processing unit PPE, a network processor NP or a double data rate controller DDRC.

5. The processor according to any one of claims 1 to 4, characterized in that: The processor is any one of the following types: a central processing unit CPU or a graphics processing unit GPU.

6. The processor according to any one of claims 1 to 5, characterized in that: The diagnostic bus is any one of the following buses: a Data Joint Test Action Group DJTAG bus, a Joint Test Action Group JTAG bus or an out-of-band bus.

7. The processor according to any one of claims 1 to 6, characterized in that: The monitoring module is an internal monitoring unit IMU.

8. The processor according to any one of claims 1 to 7, characterized in that: The monitoring module is also used to save the field information to a memory connected to the processor via the diagnostic bus.

9. A single board, characterized in that: It comprises a first memory and the processor according to any one of claims 1 to 8, wherein the first memory is used to store the on-site information.

10. The single board according to claim 9, characterized in that The single board is a main control board, the first memory is a power-off volatile memory unit in the single board, the single board further includes a second memory, and the second memory is a power-off non-volatile memory unit, The first memory is also used to save the on-site information to the second memory.

11. The single board according to claim 9, characterized in that The single board is a service board or a network board, the first memory is a power-off volatile memory unit in the single board, the device where the single board is located also includes a main control board, the main control board includes a second memory, and the second memory is a power-off non-volatile memory unit, The first memory is also used to save the field information to the second memory through the main control board.

12. A device, characterized in that: A single board comprising any one of claims 9 to 11.

13. A method for obtaining information, characterized in that: include: When the monitoring module of the processor determines that the processor is hung, the monitoring module obtains the field information of the processor through the diagnostic bus, and the field information is used to determine the cause of the processor hanging. The processor hanging is a state in which the processor stops running. The monitoring module is a module in the processor that monitors the processor through the diagnostic bus.

14. The method according to claim 13, characterized in that The processor further includes a processor core, and the monitoring module determines that the processor is hung, including: The monitoring module does not receive a message from the processor core for a preset period of time; Alternatively, the monitoring module receives an abnormality indication sent by the processor core through the diagnostic bus, where the abnormality indication is generated by the processor core when determining that the processor is hung.

15. The method according to claim 13 or 14, characterized in that When the monitoring module saves the field information to the first memory connected to the processor, the collection success flag of the first memory is set, and the processor is restarted.

16. The method according to claim 15, characterized in that The first memory is a power-off volatile storage unit connected to the processor, the processor is further connected to a second memory, and the second memory is a power-off non-volatile storage unit, and the method further includes: After the processor is restarted, the processor determines that the collection success flag is set, transfers the field information to the second memory, and deletes the field information from the first memory.

17. The method according to claim 15 or 16, characterized in that Also includes: After the processor is restarted, the processor obtains the top address information of the call stack, and the top address information of the call stack is used to determine the complete information of the call stack in combination with the field information, and the complete information of the call stack is used to indicate the function call relationship of the processor core.

18. The method according to any one of claims 13 to 17, characterized in that: The field information includes exception stack information and register status information. The exception stack information is used to determine the complete information of the call stack. The complete information of the call stack is used to indicate the function call relationship of the processor core. The register status information is used to determine the cause of the processor hang in combination with the complete information of the call stack.

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