Memory device, memory management method, and compute fast link memory device

Abstract

A memory device, a memory management method, and a compute fast link memory device are provided. The memory device includes a memory and a controller. The memory is configured to store data. The controller is configured to receive first address data based on a multi-level page from the processing unit, convert the first address data into second address data by performing a page table traversal of levels of the multi-level page, and access the memory using the second address data.

Description

[0001] This patent application claims the priority benefit of Korean Patent Application No. 10-2023-0088375 filed on July 7, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The following description relates to a virtual memory-based memory management method and a device using the same. Background Art

[0003] Virtual memory is a memory management method that allocates the memory space of a process to a virtual address space instead of directly allocating the memory space to a physical memory space. A process can read and write data using virtual addresses of a virtual address space. However, before the data can be accessed, the virtual address needs to be converted to a physical address of a physical memory space. The conversion of virtual addresses to physical addresses occurs via a data structure called a page table.

[0004] In single-level paging, a single-level page table stores entries for all virtual pages of a virtual address space. However, a single-level page table can become quite large, potentially consuming a large portion of physical memory, thereby reducing the available space for actual data and programs.

[0005] In multi-level paging, a page table is divided into smaller hierarchical levels, each level pointing to the next level to create a multi-level page table, which is used to convert virtual memory addresses to physical memory addresses without consuming a large portion of physical memory, thereby increasing the available space for actual data and programs. In multi-level paging, a virtual memory address is converted to a physical memory address by performing a page table walk to walk through multiple levels of page tables. However, because a page table walk may involve multiple memory accesses before reaching a physical address, system performance may be reduced. Summary of the invention

[0006] According to one embodiment, a memory device includes a memory and a controller. The memory is configured to store data. The controller is configured to: receive first address data based on multi-level paging from a processing unit, convert the first address data into second address data by performing a page table traversal of a level of the multi-level paging, and use the second address data to access the memory.

[0007] According to one embodiment, a memory management method of a memory device includes: receiving first address data based on multi-level paging from a processing unit; converting the first address data into second address data by performing a page table traversal of a level of the multi-level paging; and accessing a memory using the second address data.

[0008] According to one embodiment, a compute fast link (CXL) memory device includes a memory and a controller. The memory is configured to store data. The controller is configured to: receive first address data based on multi-level paging from a host device using a CXL connection, convert the first address data into second address data by performing a page table traversal of a level of the multi-level paging, and access the memory using the second address data.

[0009] According to one embodiment, an electronic device is provided, the electronic device including a memory device and a processing unit. The memory device includes a memory and a controller. The processing unit is configured to: perform a page table traversal of at least one level among multiple levels on a first virtual address to output a second virtual address to the memory device. The controller is configured to: perform a page table traversal of at least one remaining level among the multiple levels on the second virtual address to generate a third virtual address for accessing data stored in the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of an address conversion operation of a memory device according to an embodiment is shown.

[0011] Figure 2A An example of an address conversion operation according to an embodiment is shown.

[0012] Figure 2B An example of address data based on multi-level paging and page table traversal for the address data according to an embodiment is shown.

[0013] Figure 2C An example of offloading of page management for a memory device according to an embodiment is shown.

[0014] Figure 3A An example of a configuration of a memory device according to an embodiment is shown.

[0015] Figure 3B An example of a configuration of a memory device including a page manager according to an embodiment is shown.

[0016] Figure 3C A flow chart of a swap load operation according to an embodiment is shown.

[0017] Figure 3D A flow chart of a swap storage operation according to an embodiment is shown.

[0018] Figure 4 An example of a configuration of an electronic device according to an embodiment is shown.

[0019] Figure 5 and Figure 6 An example of a Compute Express Link (CXL) system according to an embodiment is shown.

[0020] Figure 7 An example of conversion processing for large pages and subpages according to an embodiment is shown.

[0021] Figure 8 A flowchart of a memory management method of a memory device according to an embodiment is shown. DETAILED DESCRIPTION

[0022] Embodiments will now be described more fully below with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Throughout the disclosure, the same reference numerals may indicate the same components.

[0023] It should be noted that if one component is described as being "connected," "coupled," or "engaged" to another component, although the first component may be directly connected, coupled, or engaged to the second component, the third component may be "connected," "coupled," or "engaged" between the first and second components. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0024] Figure 1 An example of an address conversion operation of a memory device according to an embodiment is shown. Figure 1 , the memory device 100 may include a controller 110 (e.g., a control circuit) and a memory 120. The memory 120 may store data. The memory 120 may correspond to a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetic random access memory (MRAM), a phase change random access memory (PRAM), etc., but is not limited thereto.

[0025] The controller 110 may perform various control operations related to the memory device 100 for accessing the memory 120. For example, the control operation may include a load operation and a store operation. The load operation may read data from the memory 120 based on a received read address, and the store operation may store data to the memory 120 based on a received write address. For example, the controller 110 may correspond to a memory controller, a buffer chip (e.g., a dual in-line memory module (DIMM) buffer chip), a server controller (e.g., a baseboard management controller (BMC)), but is not limited thereto.

[0026] As system memory capacity increases, the tasks of virtual memory may occupy a large portion of the workload of a processing unit (e.g., a central processing unit (CPU) or a host) in the system. In one embodiment, the controller 110 acts as an accelerator for the processing unit by offloading the functions for page management in the virtual memory management system.

[0027] According to an embodiment, the controller 110 may perform near memory processing (NMP) or processing in memory (PIM). NMP may refer to a memory technology that calculates data while storing data at the same time. According to NMP, unlike a general computing structure, a read function and a write function may be performed near the memory device 100 or inside the memory device 100. Therefore, some operations of the processing unit may be offloaded to the memory device 100.

[0028] According to NMP, data movement can be reduced. Because the data to be processed is processed by the memory device 100 close to the data, the data movement cost can be reduced. In addition, a large amount of data does not need to be transferred between the memory device 100 and the processing unit, and can be directly processed by the memory device 100.

[0029] According to the NMP, high throughput and low latency can be achieved. The NMP can use the memory sub-parallel structure unique to the memory device 100, and thus high throughput can be achieved. In addition, because the data and the processing subject (e.g., the data to be processed) are physically close, the delay and response time can be reduced.

[0030] According to NMP, energy efficiency can be improved. Data movement between the memory device 100 and the processing unit can account for a large portion of system power consumption, and NMP technology can reduce this cost by minimizing data movement.

[0031] According to the NMP, high scalability can be provided through parallel processing. The parallel processing of data can be performed using some independent memory substructures unique to the memory device 100, and this is applicable to large-scale data work.

[0032] When NMP is executed by the controller 110, the memory device 100 may correspond to an NMP memory device such as an accelerated DIMM (AXDIMM), a compute express link-AXDIMM (CXL-AXDIMM), and a CXL disaggregated memory pool (CXL-DMP). According to an embodiment, the memory device 100 includes a calculator (e.g., a logic circuit), and the controller 110 uses the calculator to process an unloaded operation. According to an embodiment, the calculator has an operation architecture based on a memory crossbar switch for NMP, but is not limited thereto.

[0033] The processing unit in the system may include a memory management unit (MMU). The MMU may perform address translation operations. The controller 110 may be distinguished from the MMU of the processing unit. The controller 110 may perform address translation operations in cooperation with the MMU or independently. The MMU may be implemented using hardware and include logic circuits, registers, and tables.

[0034] When processing data-intensive applications that require high memory bandwidth, NMP-based acceleration techniques can be useful. However, when NMP is applied to conventional computing systems, it may be difficult to support the virtual memory of the processing unit. In a virtual memory system, the operating system (or kernel) of the processing unit can map the virtual memory address to the physical memory address space of the main memory in units of pages, and the page mapping metadata containing the mapping information can be stored in a table (e.g., a page table).

[0035] Therefore, even when data has continuous virtual memory addresses, the data may be dispersed in the actual main memory. When the memory device 100 attempts to process data based on NMP, if the virtual address system of the data to be processed is unknown, it may be difficult to map the virtual memory address to the physical memory address.

[0036] In this process, the address translation process using the page table may be an obstacle. When copying and executing the page table traversal of the processing unit, delay problems, processor compatibility problems or synchronization problems may occur. The memory area to be used by the NMP can be reserved in the main memory in advance when the system is started, and the system maps the memory area and dedicates it to the NMP. However, this may lead to inefficient use of memory usage or data moving to the reserved area.

[0037] According to an embodiment, page table management and page table traversal are performed by the memory device 100. Therefore, the operation cost of the processing unit is offloaded to the memory device 100. In addition, the memory device 100 can manage a predetermined portion of the virtual memory by itself without the intervention of the processing unit or the operating system. For example, the memory device 100 can manage a predetermined sub-portion of the virtual memory address.

[0038] In one embodiment, when the processing unit uses 4-level multi-level paging, the memory area of ​​the memory device 100 (e.g., CXL memory) is set as a large page (e.g., a 2MB large page), the processing unit performs the first-level address conversion to the third-level address conversion, and the controller 110 of the memory device 100 may perform the remaining fourth-level address conversion. In this embodiment, the address converted in the third level may be sent to the memory device 100, and the controller 110 may determine the physical address by using the sent address.

[0039] More specifically, the controller 110 may convert the first address data 101 into the second address data 111. For example, converting the first address data 101 into the second address data may be a fourth-level address conversion. A system including the memory device 100 may use a virtual memory, and the virtual memory may be managed based on multi-level paging. Virtual memory may be a memory management technique that allocates a memory space of a process to a virtual address space instead of directly allocating the required memory space to a physical memory. A virtual address space may be an abstract memory space provided to a process. Just as a process actually uses a physical memory, a process may use a virtual address space to read and write data. Multi-level paging may be one of a plurality of available virtual memory management techniques. Multi-level paging may be a technique that converts a virtual memory address (hereinafter referred to as a virtual address) into a physical memory address (hereinafter referred to as a physical address) using a hierarchical structure. A detailed description of multi-level paging is provided below.

[0040] In one embodiment, the controller 110 receives first address data 101 based on multi-level paging from a processing unit of the system, converts the first address data 101 into second address data 111 by performing a page table traversal on at least one level of the multi-level paging, and uses the second address data 111 to access the memory 120. According to the multi-level paging, the virtual memory address can be mapped to the physical memory address through each level of the hierarchical structure. The process of finding the mapping information of the virtual memory address and the physical memory address can be referred to as a page table traversal. In the multi-level paging, the page table traversal can be performed on each level of the hierarchical structure. A detailed description of the page table traversal is provided below.

[0041] The virtual address assigned to the process may be referred to as an initial virtual address or a first virtual address. The address conversion result of the page table traversal based on the portion in the level based on the initial virtual address or the first virtual address may be referred to as an intermediate virtual address or an nth virtual address. Here, n may be an integer greater than 1 and less than or equal to N, where N may correspond to the number of levels included in the multi-level paging.

[0042] The first address data 101 may be sent by a processing unit in the system. The first address data 101 may correspond to a first virtual address or an nth virtual address. When the first address data 101 is sent when a page table traversal is not performed by the processing unit, the first address data 101 may correspond to the first virtual address. When a page table traversal of a portion in a level of multi-level paging is performed by the processing unit, the first address data 101 may correspond to the nth virtual address of a page table traversal of a next level that requires a portion in the level. For example, when a page table traversal of the first level is performed by the processing unit, the first address data 101 may correspond to a second virtual address, and when a page table traversal of the first level to a page table traversal of the third level is performed by the processing unit, the first address data 101 may correspond to a fourth virtual address.

[0043] The controller 110 may convert the first address data 101 into the second address data 111 by performing a page table traversal on at least one level of the multi-level paging. When the first address data 101 is sent when the page table traversal is not performed by the processing unit, in other words, when the first address data 101 corresponds to the first virtual address, the page table traversal of all levels of the multi-level paging may be performed by the controller 110. When the page table traversal of a portion of the levels of the multi-level paging is performed by the processing unit, the page table traversal of the remaining levels of the multi-level paging may be performed by the controller 110. The first virtual address may be converted into the first address data 101 by the page table traversal of a portion of the levels, and the first address data 101 may be converted into the second address data 111 corresponding to the physical address by the page table traversal of the remaining levels.

[0044] In one embodiment, the multi-level paging has a hierarchical structure having a total of 4 levels. In this embodiment, when the page table traversal is not performed by the processing unit, the page table traversal of the first level to the page table traversal of the fourth level are performed by the controller 110. In one embodiment, when the page table traversal of the first level to the page table traversal of the third level are performed by the processing unit, the page table traversal of the fourth level is performed by the controller 110.

[0045] After converting the first address data 101 into the second address data 111, the controller 110 may access the memory 120 using the second address data 111. For example, the controller 110 may load the page data of the second address data 111, or may store the page data in the second address data 111. The second address data 111 may indicate a physical address corresponding to the final conversion result. For example, the controller 110 may read the page data stored at the physical address or store the page data at the physical address.

[0046] Figure 2A An example of an address translation operation according to an embodiment is shown. Virtual memory may be one of the methods of managing memory in a computing system, and may be a method of assigning a virtual memory address to a process instead of an actual physical memory address. By using virtual memory, the memory size of the actual physical memory may be logically expanded for use. Virtual memory may be managed in units of pages, and physical memory may be managed in units of frames.

[0047] Reference Figure 2A , through operations 201 to 204, the virtual address may be converted to a physical address. Operations 201 to 204 may be performed by an MMU of a processing unit and / or a controller of a memory device. When the memory device includes a page table manager, the page table manager may participate in address conversion of the memory device. In one embodiment, the page table manager may be implemented by a logic circuit.

[0048] In operation 201, a cache buffer search is performed. The cache buffer may be used to improve the efficiency of address translation operations by reducing the number of memory accesses required for address translation processing. In one embodiment, the cache buffer corresponds to a pseudo cache that is different from the cache of the processor. For example, a table lookaside buffer (TLB) of a processing unit and a table cache of a memory device may correspond to a cache buffer for address translation operations.

[0049] Through the cache buffer search, it is determined whether the mapping information associated with a given virtual address exists in the cache buffer. The page table can store the mapping information between the virtual address and the physical address. The page table can correspond to the mapping table between the virtual address and the physical address, and the individual mapping information in the mapping table can be referred to as a page table entry (PTE).

[0050] In operation 202, the cache hit status is checked. Through the cache buffer search, it can be determined whether the PTE associated with a given virtual address exists in the cache buffer. Information of the PTE recently used for address translation can be stored in the cache buffer. The cache buffer can store recent information as large as a predetermined size. When the mapping information associated with the given virtual address exists in the cache buffer, a cache hit can occur, and when the mapping information associated with the given virtual address does not exist in the cache buffer, a cache miss can occur.

[0051] If a cache hit occurs, then address translation is performed in operation 203. Address translation may be performed using the PTEs in the cache buffer without performing additional memory accesses.

[0052] When a cache miss occurs, a page table walk is performed in operation 204. A page table walk may be an operation of accessing a page table to obtain mapping information. Memory access may be performed by a page table walk, and address translation may be performed by mapping information of a page table in memory. When a PTE for a given virtual address does not exist in a page table of memory, a page fault may occur, and the page table may be updated based on a page replacement algorithm. The page table may be updated based on page information sent to memory from an auxiliary storage device (e.g., a disk).

[0053] Figure 2B An example of address data based on multi-level paging and page table traversal for address data according to an embodiment is shown. Figure 2B , the virtual address 251 can be converted into a physical address 252 by performing a page table traversal based on multi-level paging. Figure 2B An example of using a hierarchical structure having 4 levels is shown, but the embodiment is not limited thereto. For example, a hierarchical structure having more than 5 levels (eg, 64 levels) or less than 4 levels may be used.

[0054] Each operation of the process can be performed in units of pages. The number of pages can be determined based on the page size of the page and the number of representable bits supported by the processor. For example, when the number of representable bits of the virtual address 251 is 48 bits, a virtual memory space of 256TB as 2^48 can be represented by the virtual address 251. When the page size is 4KB, 64 billion pages as 256TB / 4KB can be obtained. Since the page table supports as many indexes as the number of pages, 64 billion indexes can be included, and the virtual address 251 can occupy an address space ranging from 0x000000000_00000000 to 0x0000ffff_ffffffff.

[0055] As described above, when using virtual addresses 251 without a hierarchical structure, too much address space may be required. Therefore, multi-level paging based on a page table with multiple levels may be used to manage virtual addresses 251. When using multi-level paging, a page table traversal may be performed for each level of the hierarchical structure.

[0056] Reference Figure 2B , the high bits of the virtual address 251 except the page offset can be respectively assigned to the levels of the hierarchical structure. For example, the number of representable bits of the virtual address 251 can be 48 bits, and 9 bits can be assigned to each of the L1 index to the L4 index. In this case, by using a total of 36-bit indexes, a page table in a hierarchical structure with 4 levels can be operated. When the virtual page number is specified based on a 4-level page table traversal using the 36-bit index of the virtual address 251, the remaining 12-bit page offset of the virtual address 251 can be used to specify the PTE in the page table based on the virtual page number. In this case, the memory coverage of the page offset and the L1 index to the L4 index can be 4KB, 2MB, 1GB, 512GB and 256TB, respectively.

[0057] When the entry of a data set (e.g., table) of a level is specified based on the index of the level, the entry can be used as a pointer indicating the data set of the next level. For example, the first data set 210 can be constructed based on the L4 index of the first level, and each entry of the first data set 210 can be used as a pointer indicating the second data set 220 of the second level.

[0058] The first base address of the first data set 210 may be stored in the CR3 register. The sum of the first base address and the L4 index may specify the first entry 211. The first entry 211 may specify the second base address of the second data set 220. Using the method described above, the third entry 231 of the third data set 230 and the fourth entry 241 of the fourth data set 240 may be specified based on the L2 index and the L1 index. The third data set 230 may correspond to a page directory table, and the fourth data set 240 may correspond to a page table. The third entry 231 may correspond to a page directory entry (PDE), and the fourth entry 241 may correspond to a PTE. When a page is specified by the fourth entry 241, a physical address 252 in the page may be determined using a page offset. For example, the physical address 252 may be determined based on the PTE and the page offset.

[0059] In the LINUX operating system, the virtual address 251 can be converted to a physical address 252 through a first-level page global directory (PGD), a second-level page upper directory (PUD), a third-level page middle directory (PMD), and a fourth-level PTE. However, the embodiment is not limited to any particular operating system. When multi-level paging is used, access to the memory (or a device storing a page table) in each operation may be required. When the page size is 4KB, a cache buffer miss may result in a memory access cost of 4 accesses.

[0060] Figure 2C An example of offloading of page management for a memory device according to an embodiment is shown. Figure 2C An example of using N-level multi-level paging is shown. The processing unit may perform a first-level page table traversal 271 to a n-1-th level page table traversal 272, and the memory device may perform an n-th level page table traversal 273 to a N-th level page table traversal 274. However, the embodiment is not limited thereto. The page table traversal 271 to the page table traversal 274 may be the same as Figure 2C The examples shown in may be combined differently and may be executed by a processing unit and / or a memory device (e.g., the first-level page table traversal 271 may be executed by a processing unit and the rest may be executed by a memory device, or the first-level page table traversal 271 to the N-th-level page table traversal 274 may be executed by a memory device). Here, n may be an integer greater than 1 and less than or equal to N, where N may correspond to the number of levels included in the multi-level paging.

[0061] The processing unit may perform a first-level page table traversal 271 based on the virtual address 261. The second virtual address 262 may be determined by the first-level page table traversal. The second virtual address 262 may include a conversion result of the first-level page table traversal 271 (e.g., Figure 2B The first entry 211 of the multi-level paging system, the remaining indexes of the remaining levels of the multi-level paging system (eg, Figure 2BThe L4 index, L3 index, and L2 index of the virtual address 251) and the page offset (e.g., Figure 2B The page offset of the virtual address 251).

[0062] The processing unit may perform an n-1th level page table traversal 272 based on an n-1th virtual address (not shown). The n-th virtual address 263 may be determined by the n-1th level page table traversal 272. The n-th virtual address 263 may be sent to the memory device. For example, n=4. In this case, the n-th virtual address 263 may include a conversion result (e.g., a third level) of the n-1th level (e.g., the third level) page table traversal 272. Figure 2B The third entry 231 of ), the remaining indexes of the remaining levels of the multi-level paging (eg, Figure 2B The L1 index of the virtual address 251), and the page offset (eg, Figure 2B The page offset of the virtual address 251).

[0063] The memory device may perform an n-th level page table traversal 273 based on the n-th virtual address 263. The n+1-th virtual address (not shown) may be determined by the n-th level page table traversal 273. When performing the N-1-th level page table traversal, the N-th virtual address 264 may be determined, and the memory device may perform the N-th level page table traversal 274 based on the N-th virtual address 264. For example, when N=4, the n-th level page table traversal 273 may be the same as the N-th level page table traversal 274. In this case, the memory device may store the page offset 265 (e.g., Figure 2B The page offset of the virtual address 251) and the conversion result of the n-th level page table traversal 273 or the N-th level page table traversal 274 (for example, Figure 2B The fourth entry 241) is added to determine the physical address 266.

[0064] Figure 3A An example of a configuration of a memory device according to an embodiment is shown. Figure 3A , the memory device 300 may include a controller 310 (eg, control circuitry), a page table manager 320 (eg, logic circuitry), and a memory 330. In one embodiment, the memory is configured to store regular pages having a first size and large pages having a second size greater than the first size.

[0065] The controller 310 may convert the first address data 301 into the second address data 311. When the first address data 301 is sent when the page table traversal is not performed by the processing unit, the first address data 301 may correspond to the first virtual address. When the page table traversal of the portion in the level of multi-level paging is performed by the processing unit, the first address data 301 may correspond to the nth virtual address of the page table traversal of the next level that requires the portion in the level.

[0066] When the first address data 301 is sent and the page table traversal is not performed by the processing unit when the first address data 301 corresponds to the first virtual address, the first address data 301 may include the initial virtual address (eg, Figure 2B When a page table traversal of a portion in a level of multi-level paging is performed by a processing unit and the first address data 301 corresponds to an nth virtual address of a next level of a page table traversal of the portion in the level, the first address data 301 may include a conversion result of the page table traversal of the portion in the level, remaining indexes of the remaining levels of the multi-level paging, and page offsets.

[0067] For example, when the page table traversal from the first level to the third level of multi-level paging is performed by the processing unit, the first address data 301 may correspond to the fourth virtual address. In this case, the first address data 301 may include a third entry of the third data set corresponding to the conversion result of the page table traversal from the first level to the third level (for example, Figure 2B The third entry 231 of the third data set 230 of the embodiment of the present invention, the remaining indexes of the remaining fourth level (eg, Figure 2B The L1 index of the virtual address 251) and the page offset (eg, Figure 2B The controller 310 may determine the second address data 311 by performing a page table traversal of the remaining levels of the multi-level paging based on the conversion result, the remaining index, and the page offset. For example, the controller 310 may determine the second address data 311 by converting the third entry (e.g., Figure 2B The third entry 231 of the third data set 230) and the remaining indexes of the remaining fourth level (eg, Figure 2B The L1 index of the virtual address 251) is added to specify the fourth entry (eg, Figure 2B The fourth entry 241 of the fourth data set 240 of FIG. 1 may be obtained by aligning the fourth entry with the page offset (eg, Figure 2B The second address data 311 is determined by adding the page offset of the virtual address 251 of FIG. 310. The second address data 311 may correspond to the physical address.

[0068] The controller 310 may convert the first address data 301 into the second address data 311 using the page table manager 320. The page table manager 320 may be implemented by a hardware module and / or a software module. Figure 3A The page table manager 320 is shown as being external to the controller 310. Figure 3A Differently, the page table manager 320 may be located inside the controller 310. According to an embodiment, the memory device 300 includes a calculator, and at least some of the controller 110, the page table manager 320, and the table walker 322 use the calculator to process offloaded operations (eg, address translation operations).

[0069] The page table manager 320 may include a table cache 321 storing recent page table data (e.g., information of a PTE recently used for address translation) and a table walker 322, the table cache 321 storing recent page table data (e.g., information of a PTE recently used for address translation), and the table walker 322 performing page table walk to find the required page table data when the required page table data does not exist in the table cache 321. The controller 310 may request the page table manager 320 to perform address translation of the first address data 301, and the page table manager 320 may determine the second address data 311 by performing address translation using the table cache 321 and the table walker 322. The page table manager 320 may be based on Figure 2A The page table manager 320 may determine the second address data 311 by performing a page table traversal of the remaining levels of the multi-level paging based on the conversion result, the remaining index, and the page offset. The page table manager 320 may return the second address data 311 corresponding to the address conversion result to the controller 310.

[0070] Figure 3B An example of a configuration of a memory device including a page manager according to an embodiment is shown. Figure 3B ,and Figure 3A Compared to the memory device 300 of FIG. 305 , the memory device 305 further includes a page manager 340 (e.g., a logic circuit). According to an embodiment, a large page having a larger size than a regular page may be used. For example, a regular page may have a size of 4KB, and the large page 351 may have a size of 2MB, however, the embodiment is not limited thereto. The first address data 301 may correspond to a result of a page table traversal at a step in which a large page is identified.

[0071] Memory management efficiency can be improved by using large pages in the trend of increasing workload and memory capacity. For example, by using large pages, address translation processing can be simplified and cache buffer hit rate can be increased. However, because large pages have a larger size than conventional pages, memory efficiency may be reduced when only a portion of the large page is used. When large pages are managed as segmented subpages in a memory device 305 (e.g., a CXL memory device), memory efficiency can be improved. The conversion relationship between large pages and subpages is described below.

[0072] The controller 310 may operate the compressed pages using the page manager 340. The page manager 340 may be implemented by a hardware module and / or a software module. Figure 3B The page manager 340 is shown as being external to the controller 310. Figure 3BDifferently, the page manager 340 may be located inside the controller 310. According to an embodiment, the memory device 300 includes a calculator, and at least some of the controller 110, the page table manager 320, the table walker 322, and the page manager 340 use the calculator to process offloaded operations (eg, compression operations and decompression operations).

[0073] In one embodiment, the page manager 340 compresses subpages of a large page that are less frequently used based on demand paging and least recently used (LRU) to generate compressed subpages, and stores the compressed subpages in a compressed memory space 355 in the memory 350. The page manager 340 can ensure an effective memory space in the regular memory space 351 by compressing the subpages that are less frequently used and storing the compressed subpages in the compressed memory space 355.

[0074] The memory 350 may include a regular memory space 351, a page table 354, and a compressed memory space 355. A subpage of the regular memory space 351 may be stored in the compressed memory space 355 in a compressed state, and a compressed subpage of the compressed memory space 355 may be stored in the regular memory space 351 in a decompressed state. An operation of compressing a subpage of the regular memory space 351 to generate a compressed subpage and storing the compressed subpage in the compressed memory space 355 may be referred to as a swap store. An operation of decompressing a compressed subpage of the compressed memory space 355 to generate a decompressed subpage and storing the decompressed subpage in the regular memory space 351 may be referred to as a swap load.

[0075] When a page to be accessed during the page table traversal process does not exist in the page table 354, a page fault may occur. The page manager 340 may receive information about the page (e.g., information for identifying the page (such as an effective address, a page frame number, and a subpage frame number)), may use the information to search for the page (e.g., compressed subpage 356) in the compressed memory space 355, and may perform a swap load operation on the page. In response to the swap load, the decompressed page (e.g., subpage 352) may be stored in the regular memory space 351. When the memory space of the regular memory space 351 is insufficient, a swap store operation may be performed on another page (e.g., subpage 353). In response to the swap store, the compressed page (e.g., subpage 357) may be stored in the compressed memory space 355.

[0076] By page compression, the efficiency of memory usage due to the use of large pages can be improved. According to an embodiment, in order to be compatible with an existing operating system or a processing unit (e.g., a CPU and a host), the memory device 305 (e.g., a CXL memory device) performs provisioning so that the memory device 305 provides a larger memory capacity than a physically provisionable memory capacity during a system initialization step, and the memory device 305 provides a virtual memory space to the operating system or the processing unit using a demand paging method and a compressed memory method. For example, when the page compression rate of the memory device 305 having a physical memory space of 512 GB is 50%, a memory space of 256 GB corresponding to 50% of the memory space can be further provided.

[0077] Reference Figure 3A The description provided is applicable to Figure 3B A memory device 305 is provided.

[0078] Figure 3C FIG. 1 is a flow chart showing a swap load operation according to an embodiment. Figure 3C , in operation 361, a page fault occurs. In operation 362, when a page fault occurs, a compressed subpage stored in a compressed memory space is decompressed to generate a decompressed subpage. In operation 363, the decompressed subpage is stored in a regular memory space (e.g., 351). Operations 362 and 363 may correspond to a swap load. In operation 364, page table information of the subpage is updated. In operation 365, a memory access is performed. For example, a load and / or store operation may be performed on the subpage through a memory access. In addition, Figure 3B The description applies to Figure 3C Swap load operation.

[0079] Figure 3D A flow chart of a swap storage operation according to an embodiment is shown. In operation 371, a memory shortage occurs. In operation 372, a search for an eviction target is performed. For example, the search may look for a subpage to be evicted. The eviction target may be selected based on demand paging and LRU. In operation 373, the subpage selected as the eviction target is compressed to generate a compressed subpage, and the compressed subpage is stored in a compressed memory space (e.g., 355). In operation 374, the page table information of the subpage is updated. In addition, Figure 3B The description applies to Figure 3D Swap storage operations.

[0080] Figure 4 An example of a configuration of an electronic device according to an embodiment is shown. Figure 4, the electronic device 400 includes a processing unit 410 and a memory device 420. The processing unit 410 includes a processor 411, an MMU 412, a TLB 413, and a table walker 414. The MMU 412, the TLB 413, or the table walker 414 may be implemented by a logic circuit. The processor 411 may perform processing based on the virtual address 401. In response to the address conversion of the virtual address 401, the physical address corresponding to the virtual address 401 may be determined, and access to the memory of the memory device 420 based on the physical address may be performed.

[0081] The address conversion of the virtual address 401 may be divided into a step performed by the processing unit 410 and a step performed by the memory device 420. The MMU 412 may convert the virtual address 401 into the first address data 402. The MMU 412 may use the TLB 413 and the table walker 414 to perform the address conversion. Figure 2A When a cache buffer hit occurs, address translation using TLB 413 may be performed, and when a cache buffer miss occurs, page table traversal using table walker 414 may be performed. Memory device 420 may convert first address data 402 into a physical address, and may use the physical address to access memory. For example, memory device 420 may perform a portion of page table traversal to generate a physical address.

[0082] Figure 5 and Figure 6 An example of a Compute Express Link (CXL) system according to an embodiment is shown. Figure 5 The CXL system 500 includes a host device 510, at least one CXL memory device (e.g., CXL memory device 540 and CXL memory device 550), and a CXL switch 520, the host device 510 executes a process that desires to perform memory access, the at least one CXL memory device (e.g., CXL memory device 540 and CXL memory device 550) is configured to receive first address data based on multi-level paging in response to the memory access of the host device 510, convert the first address data into second address data by performing a page table traversal of at least one level of the multi-level paging, and access a memory (e.g., memory 543 and memory 553) using the second address data, and the CXL switch 520 connects the host device 510 to the CXL memory device. The CXL connection can be used for connection between the host device 510 and the CXL switch 520, connection between the CXL switch 520 and the CXL memory device 540, and connection between the CXL switch 520 and the CXL memory device 550.

[0083] CXL can be a connection technology that supports cache coherence of processors, memory expanders, or accelerators. When a processor is connected to an add-on using CXL, memory coherence can be maintained between the memory space of the processor and the memory space of the add-on through CXL technology. In addition, performance can be improved through resource sharing, the complexity of the software stack can be reduced, and the overall system cost can be reduced. Users can focus on the workload of the accelerator rather than memory management. As an accelerator that compensates the processor to support new applications (such as artificial intelligence and machine learning), CXL can be set as an open standard interface for high-speed communication. CXL can provide a comprehensive interface environment for connecting multiple components (such as processors, memories, accelerators and other peripherals).

[0084] The host device 510 may be used as a processing unit. The host device 510 may include a processor, and an operating system or a kernel may be driven by the processor. The CXL switch 520 may connect the host device 510 to the CXL memory device 540 and the CXL memory device 550 using the CXL technology. Excellent scalability may be provided by the CXL switch 520. The memory 543 and the memory 553 of the CXL memory device 540 and the CXL memory device 550 may provide a large capacity space. The CXL memory device 540 and the CXL memory device 550 may correspond to a memory device.

[0085] In CXL system 500, address translation operations may be performed by host device 510, CXL switch 520, and at least some of CXL memory devices 540 and 550. Translation operations according to multi-level paging may be divided into steps, and some of these steps may be performed by host device 510, others of the steps may be performed by CXL switch 520, and the remaining steps may be performed by CXL memory devices 540 and 550. For example, when 4-level multi-level paging is used, a first-level page table traversal and a second-level page table traversal may be performed by host device 510, a third-level page table traversal may be performed by CXL switch 520, and a fourth-level page table traversal may be performed by controllers 541 and 551.

[0086] CXL switch 520 may request one of controller 541 and controller 551 to perform the remaining fourth-level page table traversal based on the result of the third-level page table traversal. When a page table based on the result of the third-level page table traversal is stored in memory 543, the fourth-level page table traversal may be requested by controller 541, and when the page table is stored in memory 553, the fourth-level page table traversal may be requested by controller 551. Hereinafter, it is assumed that controller 541 participates in address conversion.

[0087] The controller 541 may receive first address data based on multi-level paging from the host device 510 through a CXL connection, convert the first address data into second address data by performing a page table traversal of at least one level of the multi-level paging, and use the second address data to access data of the memory 543. The memory 543 may store data.

[0088] When a page table traversal of a portion of a level of multi-level paging is performed by the host device 510, a page table traversal of a remaining level of the multi-level paging may be performed by the controller 541. When the host device 510 performs a page table traversal of a portion of a level of multi-level paging on a virtual address, the first address data may include a conversion result of the page table traversal of the portion of the level and remaining address data of the remaining level of the multi-level paging. The controller 541 may determine the second address data by performing a page table traversal of the remaining level of the multi-level paging based on the conversion result and the remaining address data.

[0089] CXL switch 520, controller 541, and controller 551 may use page table manager 530, page table manager 542, and page table manager 552, respectively, for address translation. Page table manager 530, page table manager 542, and page table manager 552 may communicate with Figure 3A and Figure 3B In addition, refer to the page table manager 320. Figures 1 to 4 The description provided is applicable to CXL system 500 .

[0090] Reference Figure 6 , CXL system 600 includes host device 610, CXL switch 620, CXL memory pool 630, and CXL memory pool 640. Figure 6 The number of CXL memory pools is shown to be 2, but the number of CXL memory pools is not limited thereto. Figure 5 The CXL memory device 540 and the CXL memory device 550 may correspond to each other or may provide a larger memory space than the CXL memory device 540 and the CXL memory device 550. For example, the CXL memory pool 640 may include a plurality of CXL memory devices including the CXL memory device 540 and the CXL memory device 550.

[0091] In an embodiment of CXL system 600, address translation operations are performed by host device 610, CXL switch 620, and at least some of CXL memory pools 630 and 640. Translation operations according to multi-level paging may be divided into steps, and some of the steps performed may be performed by host device 610, others of the steps may be performed by CXL switch 620, and the remaining steps may be performed by CXL memory pools 630 and 640. For example, when 4-level multi-level paging is used, the first page table traversal may be performed by CXL switch 620, and the remaining page table traversal may be performed by CXL memory pools 630 and 640. In addition, referring to Figures 1 to 5 The description provided may be applicable to CXL system 600. In one embodiment, CXL memory pool 630 and CXL memory pool 640 may be CXL memory cards.

[0092] Figure 7 An example of conversion processing of large pages and subpages according to an embodiment is shown. In one embodiment, large pages 710 have a larger size than conventional pages. For example, a conventional page may have a size of 4KB, and large pages 710 may have a size of 2MB, but the embodiment is not limited thereto. With the trend of increasing workload and memory capacity, memory management efficiency can be improved by using large pages 710. For example, by using large pages 710, address conversion processing can be simplified and cache buffer hit rate can be increased. However, because large pages 710 have a larger size than conventional pages, memory efficiency can be reduced when only a portion of large pages 710 is used.

[0093] According to an embodiment, the processing unit performs address conversion on the level for managing the large page 710, and the memory device may perform address conversion on the remaining levels. Figure 2B The number of representable bits of the virtual address 251 is 48 bits, the L1 index to the L4 index use 9 bits respectively, and the page offset uses 12 bits. In this case, the processing unit can use the L4 index to perform the first level page table traversal, use the L3 index to perform the second level page table traversal, and use the L2 index to perform the third level page table traversal. Therefore, the address conversion result of the processing unit can indicate a 2MB large page 710. The memory device can find the PTE by performing a fourth level page table traversal using the L1 index, and can obtain the physical address by adding the page offset to the address value of the PTE. Therefore, the memory device can prevent the memory efficiency from being degraded due to the use of large pages 710, and increase the management convenience due to the use of large pages 710.

[0094] In one embodiment, large pages 710 are stored in a linear space with continuous addresses. When large pages 710 are split, subpages 720 of large pages 710 may be stored in a non-linear space with discontinuous (or non-continuous) addresses. Subpages 720 may be folded and converted to large pages 710 in a linear space.

[0095] When the large page 710 exists in the linear space, the data of the large page 710 can be accessed through the physical address of the large page 710. For example, the memory device can receive a request for the large page 710 using the virtual address of the designated large page 710 from the host device. The memory device can determine the page frame number from the virtual address, and can determine the physical address of the large page 710 using the offset value of the virtual address in the physical address of the large page 710 of the page frame number. The memory device can access the data of the large page 710 using the physical address of the large page 710.

[0096] When the large page 710 is segmented and exists as a subpage 720 in a nonlinear space, the corresponding physical address of the subpage 720 may need to be calculated. When a virtual address specifying the large page 710 is received from the host device, the memory device may identify the page frame number of the virtual address. When the segmentation state of the large page 710 is identified based on the page frame number, the memory device may use the page frame number to obtain the PTE and offset value of the subpage 720, and may obtain the physical address of the subpage 720 by adding the offset value to the address of the PTE.

[0097] Figure 8 A flow chart showing a memory management method of a memory device according to an embodiment of the present invention is shown. Figure 8 In operation 810, the memory device receives first address data based on multi-level paging from a processing unit; in operation 820, the memory device converts the first address data into second address data by performing a page table traversal of at least one level of the multi-level paging; and in operation 830, the memory device uses the second address data to access the memory.

[0098] When the page table traversal of a portion of the levels of the multi-level paging is performed, in operation 820 , the page table traversal of the remaining levels of the multi-level paging may be performed.

[0099] The virtual address may be converted into first address data through page table traversal of a portion in a stage, and the first address data may be converted into second address data corresponding to the physical address through page table traversal of the remaining stages.

[0100] Operation 810, operation 820, and operation 830 may be performed by another component other than the MMU of the processing unit.

[0101] When the processing unit performs a page table traversal on a portion of a level of multi-level paging on the virtual address, the first address data may include a conversion result of the page table traversal on the portion of the level and remaining address data of remaining levels of the multi-level paging.

[0102] Operation 820 may include an operation of determining second address data by performing a page table traversal of a remaining level of multi-level paging based on the conversion result and the remaining address data.

[0103] Operation 820 may include an operation of converting the first address data into the second address data using a page table manager (e.g., 320), the page table manager (e.g., 320) including a table cache (e.g., 321) for storing recent page table data and a table walker (e.g., 322) for performing a page table walk to find the required page table data when the required page table data does not exist in the table cache.

[0104] The first address data may indicate a large page (eg, 710 ) having a larger size than a regular page.

[0105] In addition, refer to Figures 1 to 7 The description provided is applicable to Figure 8 Memory management method.

[0106] The units described herein (e.g., MMU 412, TLB 413, table walker 322 / 414, page table manager 320, page manager 340, CXL switch 620, etc.) may be implemented using hardware components, software components, and / or combinations thereof. A processing device (e.g., processor 411, processing unit 410, etc.) may be implemented using one or more general or special-purpose computers (such as, for example, processors, controllers and arithmetic logic units (ALUs), DSPs, microcomputers, FPGAs, programmable logic units (PLUs), microprocessors, or any other device capable of responding to and executing instructions in a defined manner). The processing device may run an operating system (OS) and one or more software applications running on the OS. The processing device may also access, store, manipulate, process, and create data in response to the execution of software. For simplicity, the description of the processing device is used as a singular; however, those skilled in the art will appreciate that the processing device may include multiple processing elements and multiple types of processing elements. For example, the processing device may include multiple processors, or a single processor and a single controller. In addition, different processing configurations (such as parallel processors) are feasible.

[0107] Software may include a computer program, a piece of code, instructions, or a specific combination thereof, to independently or collectively command or configure a processing device to operate as required. Software and data may be stored in any type of machine, component, physical or virtual device, computer storage medium, or a device capable of providing instructions or data to a processing device or providing instructions or data interpreted by a processing device. Software may also be distributed on networked computer systems so that the software is stored and executed in a distributed manner. Software and data may be stored via one or more non-transitory computer-readable recording media.

[0108] The method according to the above example can be recorded in a non-transitory computer-readable medium, and the non-transitory computer-readable medium includes program instructions for implementing various operations of the above example. The medium can also include data files, data structures, etc., alone or in combination with program instructions. The program instructions recorded on the medium can be program instructions specially designed and constructed to implement the above embodiments. Examples of non-transitory computer-readable media include: magnetic media (such as hard disks, floppy disks and tapes), optical media (such as CD-read-only memory (ROM) disks, DVDs and / or blue discs), magneto-optical media (such as optical disks), and hardware devices (such as read-only memory (ROM), random access memory (RAM), flash memory (for example, USB flash drive, memory card, memory stick, etc.)) specially configured to store and execute program instructions. Examples of program instructions include both machine code (such as generated by a compiler) and files containing higher-level codes that can be executed by a computer using an interpreter.

[0109] The above-mentioned apparatus may be configured to act as one or more software modules in order to perform the operations of the above-mentioned embodiments, and vice versa.

[0110] As described above, although various embodiments have been described with reference to the provided drawings, those skilled in the art may apply various technical modifications and variations on this basis. For example, if the described techniques are performed in a different order and / or if the components in the described systems, architectures, devices, or circuits are combined in a different manner and / or replaced or supplemented by other components or their equivalents, then suitable results may be achieved.

Claims

1. A memory device, comprising: a memory configured to store data; as well as The controller is configured to receive first address data based on multi-level paging from a processing unit, convert the first address data into second address data by performing a page table traversal of at least one level of the multi-level paging, and access a memory using the second address data.

2. The memory device according to claim 1, wherein: When the page table traversal of the portion of the levels of the multi-level paging is performed by the processing unit, the page table traversal of the remaining levels of the multi-level paging is performed by the controller.

3. The memory device according to claim 2, wherein: The virtual address is converted into first address data by a page table traversal of the portion in the stage, and The first address data is converted into second address data corresponding to a physical address through page table traversal of the remaining stages except the portion of the stages.

4. The memory device according to claim 1, wherein: The controller is distinct from the memory management unit of the processing unit.

5. The memory device according to claim 1, wherein: When a page table traversal of a portion of a level of multi-level paging is performed on a virtual address by a processing unit, the first address data includes a conversion result of the page table traversal of the portion of the level, remaining indexes and page offsets of remaining levels of the multi-level paging except the portion of the level.

6. The memory device according to claim 5, wherein: The controller is configured to determine second address data by performing a page table traversal of the remaining levels of multi-level paging based on the conversion result, the remaining index, and the page offset.

7. The memory device according to any one of claims 1 to 6, further comprising: The page table manager includes a table cache and a table walker, wherein the table cache stores recent page table data, and the table walker performs page table walk to search for the page table data when the page table data required by the table cache does not exist. The controller is configured to use a page table manager to convert the first address data into the second address data.

8. The memory device according to any one of claims 1 to 6, wherein: The first address data indicates a large page having a larger size than a regular page.

9. A memory management method for a memory device, the memory management method comprising: receiving first address data based on multi-level paging from a processing unit; converting the first address data to the second address data by performing a page table traversal of at least one level of the multi-level paging; as well as The second address data is used to access memory in the memory device.

10. The memory management method according to claim 9, wherein: When a page table traversal of a portion of the level of multi-level paging is performed by the processing unit, in an operation of converting first address data into second address data, a page table traversal of remaining levels of the multi-level paging except the portion of the level is performed by the processing unit.

11. The memory management method according to claim 10, wherein: The virtual address is converted into first address data by a page table traversal of the portion in the stage, and The first address data is converted into second address data corresponding to the physical address through the remaining levels of page table traversal.

12. The memory management method according to claim 9, wherein: The step of converting the first address data into the second address data is performed by a further component than the memory management unit of the processing unit.

13. The memory management method according to claim 9, wherein: When a page table traversal of part of the level of multi-level paging is performed by the processing unit on the virtual address, the first address data includes a conversion result of the page table traversal of the part of the level and address data of the remaining levels of the multi-level paging.

14. The memory management method according to claim 13, wherein: The step of converting the first address data into the second address data includes determining the second address data by performing a page table traversal of the remaining levels of the multi-level paging based on the conversion result and the address data.

15. The memory management method according to any one of claims 9 to 14, wherein: The step of converting the first address data into the second address data comprises: A page table manager is used to convert the first address data into the second address data. The page table manager includes a table cache storing recent page table data and a table walker. The table cache stores recent page table data. The table walker performs page table walk to search for page table data when page table data required by the table cache does not exist.

16. The memory management method according to any one of claims 9 to 14, wherein: The first address data indicates a large page having a larger size than a regular page.

17. A computing fast link memory device, comprising: a memory configured to store data; as well as A controller is configured to receive first address data based on multi-level paging from a host device using a computing fast link connection, convert the first address data into second address data by performing a page table traversal of at least one level of the multi-level paging, and access a memory using the second address data.

18. The computing fast link memory device of claim 17, wherein: The page table traversal of the portion of the levels of the multi-level paging is performed by the host device, and the page table traversal of the remaining levels of the multi-level paging is performed by the controller.

19. The computing fast link memory device of claim 17, wherein: When a page table traversal of part of the level of multi-level paging is performed by the host device on the virtual address, the first address data includes a conversion result of the page table traversal of the part of the level and address data of the remaining levels of the multi-level paging.

20. The computing fast link memory device of claim 19, wherein: The controller is configured to determine second address data by performing a page table traversal of the remaining levels of multi-level paging based on the conversion result and the address data.

21. An electronic device comprising: A memory device, comprising: a memory and a controller; and a processing unit configured to: perform a page table traversal of at least one level among a plurality of levels on the first virtual address to output a second virtual address to a memory device, The controller is configured to perform a page table traversal of at least one remaining level among the multiple levels except the at least one level on the second virtual address to generate a third virtual address for accessing data stored in the memory.

22. The electronic device according to claim 21, wherein: The controller adds the page offset to the third virtual address to generate a physical address and accesses the data using the physical address.

23. The electronic device according to claim 21 or 22, wherein: The memory is configured to store regular pages having a first size, large pages having a second size greater than the first size, and the first virtual address corresponds to one of the large pages.

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