Encryption device and operation method thereof

Abstract

The invention provides an encryption device and an operation method thereof. The encryption device comprises a memory array and a memory control device. The memory array is used for storing lock data. The memory control device determines whether the locking data is equal to a preset value according to the operation instruction. When the memory control device judges that the locking data is equal to the preset value, the write-in data and the output key are subjected to logical operation to generate encrypted write-in data, and the encrypted data are written into the memory array to form encrypted data.

Description

Technical Field

[0001] The present invention relates to an encryption device and an operation method thereof, and in particular to an encryption device and an operation method thereof which utilize write lock, key lock and summary information to increase security. Background Art

[0002] In cryptography, encryption refers to the process of changing plaintext into ciphertext that is difficult to understand in order to protect its content. Only a device with a decryption method can restore the ciphertext to normal readable content through the decryption process. Ideally, only authorized personnel can read the information that the ciphertext is intended to convey. Encryption itself cannot prevent the transmission of information from being intercepted, but it can prevent the interceptor from understanding the content of the information. Summary of the invention

[0003] The present invention proposes an encryption device and an operation method thereof, which can set a write lock according to user needs to strengthen the protection of the content of the encrypted data to prevent the possibility of tampering. In addition, the encryption device proposed by the present invention uses the Cipher Block Chaining-Message Authentication Code (CBC-MAC) mode to generate summary information and store it in the memory array, which provides an extra layer of protection for the encrypted data to ensure the security and integrity of the internal program. Furthermore, the encryption device proposed by the present invention uses a key lock, so that when reading, the summary information must be confirmed to unlock the subsequent decryption process to prevent tampering from flowing into the encryption device.

[0004] In view of this, the present invention provides an encryption device, comprising a memory array and a memory control device. The memory array is used to store a lock data. The memory control device determines whether the lock data is equal to a preset value according to an operation instruction. When the memory control device determines that the lock data is equal to the preset value, a write data and an output key are subjected to a logic operation to generate an encrypted write data, and the encrypted data is written into the memory array to be an encrypted data.

[0005] According to an embodiment of the present invention, the memory controller includes a first register, a second register, a third register, a first comparator, a second comparator, a bus interface, a memory interface, a buffer, a first logic gate, a second logic gate and a controller. The first register is used to temporarily store a write lock. The second register is used to temporarily store a key lock. The third register is used to temporarily store an information authentication code of an information authentication code memory address of the memory array. The first comparator is used to compare the lock data and the preset value to generate a first comparison result. The second comparator is used to compare a summary information and the information authentication code to generate a second comparison result. The bus interface receives the operation instruction, an encryption enable signal, the write data, an operation memory address, an encryption memory address, a key, a random number and a setting information from a bus, and the key, the random number and the setting information correspond to the encryption memory address. The encrypted memory address includes a starting memory address, an ending memory address and an information authentication code memory address, wherein the encrypted data is stored in the starting memory address, and the locked data is stored in the ending memory address. The memory interface is coupled to the memory array. The buffer is coupled to the memory interface. When the first comparator compares the locked data with the preset value, the buffer temporarily stores the locked data. The buffer temporarily stores the encrypted write data and the encrypted data. The first logic gate performs an exclusive or logic operation on the write data and the output key to generate the encrypted write data. The second logic gate performs the exclusive or logic operation on the encrypted data and the output key to generate a read data. The controller controls the memory array through the memory interface using a memory control signal according to the operation instruction and the operation memory address, and accesses the memory array through the buffer and the memory interface. The controller determines whether the locked data and the preset value are equal according to the first comparison result. When the lock data is equal to the preset value, the controller enables the first register with a write lock enable signal and sets the write lock to an unlocked state with a write lock input signal. When the lock data is not equal to the preset value, the controller sets the write lock to a locked state.

[0006] According to an embodiment of the present invention, the memory controller further includes a cryptographic device. The cryptographic device includes a fourth register, a first multiplexer, a judgment unit, a first encryption unit, a second encryption unit, a cryptographic unit, a second multiplexer and a third logic gate. The fourth register is used to store the encryption enable signal, the encryption memory address, the key, the random number and the setting information. The first multiplexer outputs one of the key, the random number and the setting information according to a determination signal. When the judgment unit determines that the operation memory address is located in the encryption memory address, the judgment unit generates the judgment signal and a key enable signal according to the key lock, the write lock, an operation signal, an information authentication code enable signal and a protection area selection signal. The first encryption unit performs a first encryption operation on the random number and the operation memory address output by the first multiplexer to generate a first encryption result. The second encryption unit receives the encryption data and the lock data stored in the memory array, and performs a second encryption mode operation on the encryption data, the lock data, the setting information output by the first multiplexer, and a start memory address and an end memory address of the operation memory address to generate a second encryption result. The password unit generates a key stream using the first encryption result and the key output by the first multiplexer, or generates summary information using the second encryption result and the key output by the first multiplexer. The second multiplexer outputs the first encryption result or the second encryption result to the password unit according to an encryption selection signal generated by the controller. The third logic gate performs a logical AND operation on the key stream and the key enable signal to generate the output key.

[0007] According to one embodiment of the present invention, when a user sets the encryption enable signal to an enable state through the bus interface, the controller sets the write lock and the key lock to a lock state. The controller does not write the write data into the encryption memory address according to the write lock in the lock state. The third logic gate does not output the key stream as the output key according to the key enable signal in the lock state. The user further sets the encryption memory address, the key, the random number and the setting information through the bus interface.

[0008] According to one embodiment of the present invention, the controller writes a value into the end memory address as the lock data, and the value is different from the preset value. The controller further reads the encrypted data of the encrypted memory address and the lock data of the value, and the password unit generates the summary information corresponding to the encrypted memory address. The controller writes the summary information generated by the password unit into the information authentication code memory address as the information authentication code, and sets the key lock corresponding to the encrypted memory address to an unlocked state.

[0009] According to one embodiment of the present invention, the controller uses the protection area selection signal to select the encrypted memory address to verify the information authentication code, and enables the information authentication code enable signal. The controller reads the encrypted data, the locking data and the information authentication code of the encrypted memory address. The password unit generates the summary information based on the encrypted data and the locking data, and the second comparator compares whether the summary information is equal to the information authentication code. When the summary information is equal to the information authentication code, the controller sets the key lock to the unlocked state. When the summary information is not equal to the information authentication code, the controller sets the key lock to the locked state.

[0010] According to an embodiment of the present invention, the judgment unit judges whether the operation memory address is in the encrypted memory address. When the operation memory address is in the encrypted memory address, the operation signal is in a write state, and the write lock is in the unlock state, the judgment unit enables the key enable signal. The cryptographic unit generates the key stream using the first encryption result generated by the first encryption unit and the key, and the third logic gate outputs the key stream as the output key according to the enabled key enable signal. The first logic gate encrypts the write data using the output key to generate encrypted write data, and the controller writes the encrypted write data into the operation memory address of the memory array to be encrypted data.

[0011] According to an embodiment of the present invention, the judgment unit judges whether the operation memory address is in the encrypted memory address. When the operation memory address is in the encrypted memory address, the operation signal is in a read state, and the key lock is in the unlock state, the judgment unit enables the key enable signal. The third logic gate outputs the key stream as the output key according to the key enable signal. The second logic gate uses the output key to decrypt the encrypted data stored in the operation memory address of the memory array into the read data.

[0012] According to an embodiment of the present invention, the second encryption mode operation is a cipher block concatenation-message authentication code mode.

[0013] The present invention further provides an operation method, which is applicable to an encryption device. The encryption device includes a memory array, and the memory array stores a lock data. The operation method includes: determining whether the lock data is equal to a preset value; when the lock data is determined to be equal to the preset value, setting a write lock to an unlock state; when the write lock is the unlock state, encrypting a write data with an output key to generate an encrypted write data; and writing the encrypted write data into the memory array.

[0014] According to an embodiment of the present invention, the operation method further includes: when setting an encrypted memory address, executing a setting method; when comparing the encrypted data, executing a comparison method; when burning an information authentication code of the encrypted memory address, executing a burning method; when verifying the information authentication code, executing a verification method; when performing a write operation on the memory array, executing a write method; and when performing a read operation on the memory array, executing a read method. Before executing the write method, the setting method and the comparison method need to be executed at least once in sequence. Before executing the read method, the setting method, the burning method and the verification method need to be executed at least once in sequence.

[0015] According to one embodiment of the present invention, the above-mentioned setting method further includes: setting the above-mentioned encrypted memory address, a key, a random number, a setting information and an encryption enable signal through a bus interface, wherein the above-mentioned key, the above-mentioned random number and the above-mentioned setting information correspond to the above-mentioned encrypted memory address, wherein the above-mentioned encrypted memory address includes a starting memory address, an ending memory address and an information authentication code memory address; and according to the above-mentioned encryption enable signal, setting the above-mentioned write lock and a key lock corresponding to the above-mentioned encrypted memory address to a locked state.

[0016] According to one embodiment of the present invention, the above-mentioned comparison method further includes: reading the above-mentioned lock data of the above-mentioned encrypted memory address, wherein the above-mentioned lock data is stored in the above-mentioned end memory address; determining whether the above-mentioned lock data is equal to the above-mentioned preset value; when it is determined that the above-mentioned lock data is equal to the above-mentioned preset value, setting the above-mentioned write lock to the above-mentioned unlocked state; and when it is determined that the above-mentioned lock data is not equal to the above-mentioned preset value, setting the above-mentioned write lock to the above-mentioned locked state.

[0017] According to one embodiment of the present invention, the above-mentioned burning method further includes: writing a value into the above-mentioned end memory address as the above-mentioned locking data, wherein the above-mentioned value is not equal to the above-mentioned preset value; selecting the above-mentioned encrypted memory address for burning; reading the above-mentioned encrypted data and the above-mentioned locking data of the above-mentioned encrypted memory address of the above-mentioned memory array; generating a summary information of the above-mentioned encrypted memory address according to the above-mentioned encrypted data, the above-mentioned locking data, the above-mentioned start memory address, the above-mentioned end memory address and the above-mentioned setting information; writing the above-mentioned summary information into the above-mentioned information authentication code memory address; and after writing the above-mentioned summary information, setting the above-mentioned key lock to the above-mentioned unlocking state.

[0018] According to an embodiment of the present invention, the step of generating the summary information of the encrypted memory address according to the encrypted data, the locking data, the starting memory address, the ending memory address and the setting information further comprises: performing an encryption mode operation on the encrypted data, the locking data, the starting memory address, the ending memory address and the setting information to generate an encryption result; and generating the summary information according to the encryption result and the key. The encryption mode operation is a cipher block concatenation-message authentication code mode.

[0019] According to one embodiment of the present invention, the verification method further includes: selecting the encrypted memory address for verification; reading the encrypted data, the locking data and the information authentication code of the encrypted memory address of the memory array; generating the summary information of the encrypted memory address according to the encrypted data, the locking data, the starting memory address, the ending memory address and the setting information; determining whether the information authentication code is equal to the summary information; when the information authentication code is equal to the summary information, setting the key lock of the encrypted memory address to the unlocked state; and when the information authentication code is not equal to the summary information, setting the key lock of the encrypted memory address to the locked state.

[0020] According to one embodiment of the present invention, the write method further includes: receiving an operation memory address to perform a write operation; determining whether the operation memory address is in the encrypted memory address; when the operation memory address is in the encrypted memory address, determining whether the write lock is in the unlocked state; when the write lock is in the unlocked state, generating a key stream according to the operation memory address, the random number and the key; encrypting the write data using the key stream to generate the encrypted data; and writing the encrypted data into the memory array.

[0021] According to an embodiment of the present invention, the step of generating the key stream according to the operation memory address, the random number and the key further includes: performing an encryption mode operation on the operation memory address and the random number to generate an encryption result; generating the key stream according to the encryption result and the key; enabling a key enable signal according to the operation memory address being in the encryption memory address and the write lock being in the unlock state; and outputting the key stream as an output key according to the key enable signal. The output key is further used to encrypt the write data, and the encryption mode operation is a counter mode.

[0022] According to one embodiment of the present invention, the reading method further includes: receiving an operation memory address to perform a read operation; determining whether the operation memory address is in the encrypted memory address; when the operation memory address is in the encrypted memory address, determining whether the key lock is in the unlocked state; when the key lock is in the unlocked state, generating a key stream according to the operation memory address, the random number and the key; using the key stream to decrypt the encrypted data to generate a read data; and transmitting the read data to a host.

[0023] According to one embodiment of the present invention, the reading method further includes: when the operating memory address is not in the encrypted memory address, the key stream is not generated; when the key is locked to the locked state, the key stream is not generated; and directly reading the encrypted data of the operating memory address of the memory array as the read data. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A block diagram showing an encryption device according to an embodiment of the present invention;

[0025] Figure 2 Display a corresponding table of encrypted memory addresses, keys, random numbers, and setting information according to an embodiment of the present invention;

[0026] Figure 3 A flowchart showing an operating method according to an embodiment of the present invention;

[0027] Figure 4 A flowchart showing a setting method according to an embodiment of the present invention;

[0028] Figure 5 A flowchart showing a comparison method according to an embodiment of the present invention;

[0029] Figure 6 A flowchart showing a method for burning according to an embodiment of the present invention;

[0030] Figure 7 A flowchart showing a verification method according to an embodiment of the present invention;

[0031] Figure 8 A flowchart showing a writing method according to an embodiment of the present invention; and

[0032] Fig. 9 A flowchart of a reading method according to an embodiment of the present invention is shown.

[0033] Reference Numbers

[0034] 100: Encryption device

[0035] 110: memory control device

[0036] 111: first bus interface

[0037] 112: Controller

[0038] 113: Buffer

[0039] 114: Memory interface

[0040] 115: First logic gate

[0041] 116: Second logic gate

[0042] 117: First register

[0043] 118: Second register

[0044] 119: The third register

[0045] 120: Memory array

[0046] 130: Password device

[0047] 131: The fourth register

[0048] 132: First multiplexer

[0049] 133: Judgment unit

[0050] 134: First encryption unit

[0051] 135: Second encryption unit

[0052] 136: Second multiplexer

[0053] 137: Cryptographic unit

[0054] 138: The third logic gate

[0055] 200: Correspondence table

[0056] 300: Operation method

[0057] 400: Setting method

[0058] 500: Comparison method

[0059] 600: Burning method

[0060] 700: Verification method

[0061] 800:Write method

[0062] 900: Reading method

[0063] BUS: Bus

[0064] INS: Operation Instructions

[0065] WDATA: Write data

[0066] RDATA: Read data

[0067] HADDR: Operation memory address

[0068] HWRITE: Operation signal

[0069] SADDRP: Starting memory address

[0070] DADDRP: End memory address

[0071] MADDRP: message authentication code memory address

[0072] EMICTL: memory control signal

[0073] KS: Key Stream

[0074] KO: Output key

[0075] KSEN: Key enable signal

[0076] EWDATA: Encrypted write data

[0077] CT: Encrypted Data

[0078] LOCK: Lock data

[0079] BUS: Bus

[0080] CMP1: First comparator

[0081] CMP2: Second comparator

[0082] WLK: Write Lock

[0083] WLKEN: Write lock enable signal

[0084] WLKDIN: Write lock input signal

[0085] DLK: Key Lock

[0086] DLKEN: Key lock enable signal

[0087] DLKDIN: Key lock input signal

[0088] MAC: Message Authentication Code

[0089] MACEN: Information authentication code enable signal

[0090] MACDIN: Information authentication code input signal

[0091] DEF:Default value

[0092] EQ1: First comparison result

[0093] EQ2: Second comparison result

[0094] DSG: Summary Information

[0095] PRIEN: encryption enable signal

[0096] EADDR: Encrypted memory address

[0097] KEY: key

[0098] KEY1: First key

[0099] KEY2: Second key

[0100] KEYN:Nth key

[0101] NONCE: Random Number

[0102] NONCE1: The first random number

[0103] NONCE2: Second random number

[0104] NONCEN: Nth random number

[0105] INF: Setting information

[0106] INF1: First setting information

[0107] INF2: Second setting information

[0108] INFN: Nth setting information

[0109] SELE: Encryption selection signal

[0110] CNT: First encryption result

[0111] ECR: Second encryption result

[0112] DET: judgment signal

[0113] DINEN: Data input enable signal

[0114] PRSEL: Protection area selection signal

[0115] EADDR1: first memory address

[0116] EADDR2: Second memory address

[0117] EADDRN: Nth memory address

[0118] SADDR1: first starting address

[0119] DADDR1: First end address

[0120] MADDR1: first information authentication code memory address

[0121] SADDR2: second starting address

[0122] DADDR2: Second end address

[0123] MADDR2: Second information authentication code memory address

[0124] SADDRN: Nth starting address

[0125] DADDRN: Nth ending address

[0126] MADDRN: Nth information authentication code memory address

[0127] S301~S312,S401~S402,S501~S503,S601~S606,S701~S706,S801~S806,S901~S907: Step Flow DETAILED DESCRIPTION

[0128] The following description is an embodiment of the present application, which is intended to illustrate the general principles of the present application and should not be regarded as limiting the present application, the scope of which shall be determined by the claims.

[0129] It is worth noting that the content of the following application can provide multiple embodiments or examples for practicing the different features of the present application. The special device examples and arrangements described below are only used to briefly and concisely explain the spirit of the present application, and are not used to limit the scope of the present application. In addition, the following description may reuse the same device symbols or text in multiple examples. However, the purpose of re-use is only to provide a simplified and clear description, and is not used to limit the relationship between the multiple embodiments and / or configurations discussed below. In addition, the description of a feature connected to, coupled to, and / or formed on another feature described in the following description may actually include multiple different embodiments, including direct contact between these features, or including other additional features formed between these features, etc., so that these features are not in direct contact.

[0130] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the embodiments to describe the relative relationship of one device to another device in the figure. It is understood that if the device in the figure is turned upside down, the device described on the "lower" side will become the device on the "upper" side.

[0131] It is understood that although the terms "first", "second", "third", etc. may be used herein to describe various devices, components, regions, layers, and / or parts, these devices, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different devices, components, regions, layers, and / or parts. Therefore, a first device, component, region, layer, and / or part discussed below may be referred to as a second device, component, region, layer, and / or part without departing from the teachings of some embodiments of the present application.

[0132] Some embodiments of the present application can be understood together with the drawings, and the drawings of the embodiments of the present application are also considered as part of the description of the embodiments of the present application. It should be understood that the drawings of the embodiments of the present application are not drawn in proportion to the actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present application. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present application.

[0133] Here, the terms "about", "approximately" and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The numbers given here are approximate numbers, that is, in the absence of specific description of "about", "approximately" or "generally", the meanings of "about", "approximately" or "generally" can still be implied.

[0134] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which this application belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this application, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this application.

[0135] In some embodiments of the present application, terms such as "connection" and "interconnection" may refer to two structures being in direct contact with each other, or two structures not being in direct contact with each other, with another structure disposed between the two structures, unless otherwise specified. Such terms may also include situations where both structures are movable or both structures are fixed.

[0136] Figure 1 A block diagram of an encryption device according to an embodiment of the present invention is shown. Figure 1 As shown, the encryption device 100 includes a memory control device 110 and a memory array 120 . The memory control device 110 includes a first bus interface 111 , a controller 112 , a buffer 113 , a memory interface 114 , a first logic gate 115 , a second logic gate 116 and a cryptographic device 130 .

[0137] The first bus interface 111 receives an operation instruction INS, write data WDATA, an operation memory address HADDR, and an encrypted memory address EADDR from a bus BUS, and transmits the operation instruction INS and the operation memory address HADDR to the controller 112, so that the controller 112 performs a read operation or a write operation on the operation memory address HADDR of the memory array 120 through the buffer 113 and the memory interface 114 according to the operation instruction INS and the operation memory address HADDR. When the operation memory address HADDR is located in the encrypted memory address EADDR, the data written to or read from the operation memory address HADDR needs to be encrypted or decrypted.

[0138] According to one embodiment of the present invention, when the controller 112 performs a write operation on the memory array 120 according to the operation instruction INS and the operation memory HADDR is located in the encrypted memory address EADDR, the controller 112 controls the memory array 120 through the memory control signal EMICTL via the memory interface 114, and the first logic gate 115 performs a mutually exclusive OR operation on the write data WDATA and the output key KO to generate the encrypted write data EWDATA, and writes the encrypted write data EWDATA into the operation memory address HADDR of the memory array 120 through the buffer 113 and the memory interface 114 to obtain the encrypted data CT.

[0139] According to another embodiment of the present invention, when the controller 112 performs a read operation on the memory array 120 according to the operation instruction INS and the operation memory HADDR is located in the encrypted memory address EADDR, the controller 112 controls the memory array 120 through the memory control signal EMICTL via the memory interface 114, and reads the encrypted data CT stored in the operation memory address HADDR of the memory array 120 through the memory interface 114 and temporarily stores it in the buffer 113, and performs mutually exclusive or logical operations on the encrypted data CT and the output key KO through the second logic gate 116 to generate the read data RDATA, and transmits it to the host through the first bus interface 111 and the bus BUS.

[0140] like Figure 1 As shown, the encrypted memory address EADDR includes a start memory address SADDRP and an end memory address DADDRP. The memory array 120 stores the encrypted data CT between the start memory address SADDRP and the end memory address DADDRP minus 1, and stores the lock data LOCK at the end memory address DADDRP. The encrypted memory address EADDR further includes a message authentication code memory address MADDRP for storing a message authentication code MAC. The functions of the lock data LOCK and the message authentication code MAC will be described in detail below.

[0141] like Figure 1 As shown, the memory control device 110 further includes a first register 117, a second register 118, a third register 119, a first comparator CMP1, and a second comparator CMP2. The controller 112 uses a write lock enable signal WLKEN to allow the first register 117 to be written, and uses a write lock input signal WLKDIN to set the write lock WLK stored in the first register 117 to a locked state or an unlocked state.

[0142] The controller 112 uses the key lock enable signal DLKEN to allow the second register 118 to be written, and uses the key lock input signal DLKDIN to set the key lock DLK stored in the second register 118 to a locked state or an unlocked state. When the controller 112 accesses the information authentication code MAC stored in the memory array 120, the controller 112 temporarily stores the information authentication code memory address MADDRP of the read information authentication code MAC in the buffer 113, and uses the information authentication code enable signal MACEN to allow the third register 119 to be written, and then uses the information authentication code input signal MACDIN to write the information authentication code MAC into the third register 119 through the buffer 113.

[0143] When the controller 112 accesses the lock data LOCK stored in the end memory address DADDRP of the memory array 120, the read lock data LOCK is first temporarily stored in the buffer 113. The first comparator CMP1 is used to compare the lock data LOCK temporarily stored in the buffer 113 with the preset value DEF to generate a first comparison result EQ1, and provide the first comparison result EQ1 to the controller 112. The second comparator CMP2 is used to compare the information authentication code MAC stored in the third register 119 with the summary information DSG to generate a second comparison result EQ2, and provide the second comparison result EQ2 to the controller 112. The controller 112 determines whether the lock data LOCK is equal to the preset value DEF according to the first comparison result EQ1, and determines whether the information authentication code MAC is equal to the summary information DSG according to the second comparison result EQ2. According to some embodiments of the present invention, the preset value DEF can be set by the user through the bus BUS.

[0144] like Figure 1 As shown, the cryptographic device 130 is used to generate an output key KO and a summary information DSG, and includes a fourth register 131, a first multiplexer 132, a determination unit 133, a first encryption unit 134, a second encryption unit 135, a second multiplexer 136, a cryptographic unit 137 and a third logic gate 138.

[0145] The first bus interface 111 further receives an encryption enable signal PRIEN, a key KEY, a random number NONCE and setting information INF from the bus BUS, and stores them in the fourth register 131, wherein the encryption enable signal PRIEN is used to enable the memory control device 110 to perform an encryption write operation and / or a decryption read operation on the encryption memory address EADDR, and encrypt and decrypt the read and written data according to the key KEY, the random number NONCE and the setting information INF corresponding to the encryption memory address EADDR.

[0146] According to some embodiments of the present invention, the user sets the encryption enable signal PRIEN, the encryption memory address EADDR, the key KEY, the random number NONCE and the setting information INF stored in the fourth register 131 through the bus BUS and the bus interface 111. According to one embodiment of the present invention, when the operation signal HWRITE is in the write state, it represents that the encryption device 100 performs a write operation. According to another embodiment of the present invention, when the operation signal HWRITE is in the read state, it represents that the encryption device 100 performs a read operation. According to one embodiment of the present invention, the user can set the operation signal HWRITE to a write state or a read state through the bus BUS and the bus interface 111. The encryption memory address EADDR, the key KEY, the random number NONCE and the setting information INF will be described in detail below.

[0147] Figure 2 The corresponding table 200 shows the corresponding relationship between the encrypted memory address EADDR, the key KEY, the random number NONCE and the setting information INF of the protection area of ​​the memory array 120 according to an embodiment of the present invention.

[0148] like Figure 2 As shown in the embodiment, the protection area of ​​the memory array 120 includes a first encrypted memory address EADDR1, a second encrypted memory address EADDR2... and an Nth encrypted memory address EADDRN, wherein the first encrypted memory address EADDR1 includes a first starting memory address SADDR1, a first ending memory address DADDR1 and a first information authentication code memory address MADDR1, the second encrypted memory address EADDR2 includes a second starting memory address SADDR2, a second ending memory address DADDR2 and a second information authentication code memory address MADDR2, and the Nth encrypted memory address ADDRN includes an Nth starting memory address SADDRN, an Nth ending memory address DADDRN and an Nth information authentication code memory address MADDRN.

[0149] In other words, when the decrypted read operation and the encrypted write operation are performed on the memory addresses between the first starting memory address SADDR1 and the first ending memory address DADDR1 minus 1, between the second starting memory address SADDR2 and the second ending memory address DADDR2 minus 1, ... and between the Nth starting memory address SADDRN and the Nth ending memory address DADDRN minus 1 of the memory array 120 (that is, the operation memory address HADDR is located between the above addresses and the encryption enable signal PRIEN is in the enabled state), Figure 1The encryption device 100 decrypts the encrypted data CT read from the memory array 120 and encrypts the write data WDATA and writes it into the memory array 120. According to other embodiments of the present invention, the user can further select which of the first encrypted memory address EADDR1, the second encrypted memory address EADDR2, ... and the Nth encrypted memory address EADDRN to perform the decryption read operation and / or the encryption write operation.

[0150] like Figure 2 As shown, each of the first encrypted memory address EADDR1, the second encrypted memory address EADDR2, ... and the Nth encrypted memory address EADDRN has a corresponding first key KEY1, a second key KEY2, ... and the Nth key KEYN, a corresponding first random number NONCE1, a second random number NONCE2, ... and the Nth random number NONCEN, and a corresponding first setting information INF1, a second setting information INF2, ... and the Nth setting information INFN. According to some embodiments of the present invention, the first setting information INF1, the second setting information INF2, ... and the Nth setting information INFN can be user information, chip information, external memory information, version information, encryption and decryption algorithm, creation date, etc., and can also be a random variable like the random number NONCE.

[0151] According to one embodiment of the present invention, the user can set the first encrypted memory address EADDR1, the second encrypted memory address EADDR2, ... and the Nth encrypted memory address EADDRN of the protection area through the bus BUS and the first bus interface 111, and can also set the first random number NONCE1, the second random number NONCE2, ... and the Nth random number NONCEN stored in the fourth register 131. According to other embodiments of the present invention, the user can set the first key KEY1, the second key KEY2, ... and the Nth key KEYN stored in the fourth register 131 and the first setting information INF1, the second setting information INF2, ... and the Nth setting information INFN stored in the fourth register 131 through the bus BUS and the first bus interface 111.

[0152] According to some embodiments of the present invention, Figure 1The encrypted memory address EADDR is one of the first encrypted memory address EADDR1, the second encrypted memory address EADDR2, ... and the Nth encrypted memory address EADDRN. Similarly, the start memory address SADDRP is one of the first start memory address SADDR1, the second start memory address SADDR2, ... and the Nth start memory address SADDRN, the end memory address DADDRP is one of the first end memory address DADDR1, the second section memory address DADDR2, ... and the Nth end memory address DADDRN, and the information authentication code memory address MADDRP is one of the first information authentication code memory address MADDR1, the second information authentication code memory address MADDR2, ... and the Nth information authentication code memory address MADDRN, where P is 1, 2, .. or N.

[0153] In addition, corresponding to the first encrypted memory address EADDR1, the second encrypted memory address EADDR2 . . . and the Nth encrypted memory address EADDRN, Figure 1 The first register 117, the second register 118 and the third register 119 are used to store N sets of write lock WLK, N sets of key lock DLK and N sets of information authentication code MAC, and correspond to the first encrypted memory address EADDR1, the second encrypted memory address EADDR2, ... and the Nth encrypted memory address EADDRN respectively.

[0154] Back to Figure 1 The first multiplex signal 132 outputs one of the key KEY, the random number NONCE and the setting information INF according to the determination signal DET. When the determination unit 133 determines that the operation memory address HADDR is located in the encryption memory address EADDR, the determination unit 133 outputs the determination signal DET and the key enable signal KSEN according to the key lock DLK, the write lock WLK, the operation signal HWRITE, the information authentication code enable signal MACEN and the protection area selection signal PRSEL.

[0155] Specifically, when the operation signal HWRITE is in the write state, the judgment unit 133 enables the key enable signal KSEN according to the operation memory address HADDR being located at the encryption memory address EADDR and the write lock WLK being in the unlock state. When the operation signal HWRITE is in the read state, the judgment unit 133 enables the key enable signal KSEN according to the operation memory address HADDR being located at the encryption memory address EADDR and the key lock DLK being in the unlock state. When the information authentication code enable signal MACEN is in the enable state, the judgment unit 133 does not enable the key enable signal KSEN.

[0156] When the operation signal HWRITE is in the write state or the read state, the operation memory address HADDR is located at Figure 2 When the encryption memory address EADDR is in the state where the write lock WLK or the key lock DLK is unlocked, the determination unit 133 controls the first multiplexer 132 using the determination signal DET, and provides the random number NONCE corresponding to the encryption memory address EADDR to the first encryption unit 134, and provides the key KEY corresponding to the encryption memory address EADDR to the password unit 137. The first encryption unit 134 performs a first encryption mode operation on the random number NONCE output by the first multiplexer 132 and the operation memory address HADDR, and generates a first encryption result CNT, and provides it to the second multiplexer 136. According to one embodiment of the present invention, the first encryption mode operation is a counter mode.

[0157] When the information authentication code enable signal MACEN is enabled, the judgment unit 133 selects the starting memory address SADDRP and the ending memory address DADDRP of the corresponding encrypted memory address EADDRR according to the protection area selection signal PRSEL and provides them to the second encryption unit 135, and provides the encrypted memory address EADDR to the controller 112, and uses the judgment signal DET to control the first multiplexer 132 to provide the setting information INF corresponding to the encrypted memory address EADDR and the corresponding key KEY to the second encryption unit 135 and the password unit 137 respectively. At the same time, the controller 112 uses the data input enable signal DINEN to notify the second encryption unit 135 that the input data is ready, and provides the encrypted data CT stored in the starting memory address SADDRP of the memory array 120 and the locking data LOCK stored in the ending memory address DADDRP to the second encryption unit 135, so that the second encryption unit 135 performs a second encryption mode operation on the starting memory address SADDRP, the ending memory address DADDRP, the setting information INF, and the encrypted data CT and the locking data LOCK stored in the memory array 120 to generate a second encryption result ECR.

[0158] For example, when the operation memory address HADDR is within the second encryption memory address EADDR2, the determination unit 133 provides the second encryption memory address EADDR2 to the controller 112, and the determination unit 133 provides the second start memory address SADDR2 and the second end memory address DADDR2 to the second encryption unit 135. Then, the controller 112 reads the encryption data CT and the lock data LOCK corresponding to the second encryption memory address EADDR2 of the memory array 120, and provides them to the second encryption unit 135.

[0159] Subsequently, the second encryption unit 135 performs a second encryption mode operation on the second start memory address SADDR2, the second end memory address DADDR2, the second setting information INF2, and the encryption data CT and the lock data LOCK stored in the memory array 120 to generate a second encryption result ECR. According to one embodiment of the present invention, the second encryption mode operation is a Cipher-block chaining Message Authentication Code (CBC-MAC) mode.

[0160] The second multiplexer 136 provides one of the first encryption result CNT and the second encryption result ECR to the cryptographic unit 137 according to the encryption selection signal SELE generated by the controller 112, so that the cryptographic unit 137 generates a key stream KS using the first encryption result CNT output by the second multiplexer 136 and the key KEY output by the first multiplexer 132, or generates a summary information DSG using the second encryption result ECR output by the second multiplexer 136 and the key KEY output by the first multiplexer 132, wherein the summary information DSG is provided to the controller 112 and the second comparator CMP2. The third logic gate 138 outputs the key stream KS as an output key KO according to the key enable signal KSEN. According to one embodiment of the present invention, the third logic gate 138 performs a logical AND operation on the key enable signal KSEN and the key stream KS to generate the output key KO.

[0161] According to one embodiment of the present invention, before the second encryption unit 135 generates the second encryption result ECR, the cryptographic unit 137 first generates the key stream KS using the first encryption unit CNT, so that the second logic gate 116 can decrypt the encrypted data CT stored in the memory array 120 and provide it together with the lock data LOCK to the second encryption unit 135, and then the cryptographic unit 137 generates the summary information DSG according to the second encryption result ECR generated by the second encryption unit 135. According to another embodiment of the present invention, the encrypted data CT does not need to be decrypted, and is directly provided to the second encryption unit 135 together with the lock data LOCK.

[0162] According to some embodiments of the present invention, the data processed by the second encryption unit 135 is a fixed number of bits. When the encrypted data CT and / or the locking data LOCK are less than an integer multiple of the fixed number of bits, zero padding is used to make up the integer multiple of the fixed number of bits. For example, when the data processed by the second encryption unit 135 is 128 bits, if the encrypted data CT and the locking data LOCK are less than 128 bits or an integer multiple of 128 bits, zero padding is used to make up the integer multiple of 128 bits.

[0163] Figure 3 A flowchart showing an operation method according to an embodiment of the present invention is shown. Figure 3 The description of method 300 will be accompanied by Figure 1 The encryption device 100 is described in detail.

[0164] like Figure 3 As shown, the controller 112 determines whether the user sets the encryption memory address EADDR, the key KEY, the random number NONCE, the setting information INF and the encryption enable signal PRIEN stored in the fourth register 131 through the bus BUS and the bus interface 111 (step S301), wherein the corresponding relationship between the encryption memory address EADDR, the key KEY, the random number NONCE and the setting information INF is as shown in FIG. Figure 2 As shown in the corresponding table 200, the encryption enable signal PRIEN is stored in the fourth register 131 to enable or disable the cryptographic device 130 to perform encryption. In other words, the encryption enable signal PRIEN is used to enable or disable the cryptographic device 130 to generate the output key KO.

[0165] When the judgment in step S301 is yes, the controller 112 executes Figure 4 When the judgment result of step S301 is no, the controller 112 determines whether to compare the lock data LOCK (step S303). When the judgment result of step S303 is yes, the controller 112 executes Figure 5 When the determination result of step S303 is no, the controller 112 determines whether to burn the information identification code MAC of the protection area (step S305).

[0166] When the judgment in step S305 is yes, the controller 112 executes Figure 6 When the judgment of step S305 is no, the controller determines whether to verify the information authentication code MAC (step S307). When the judgment of step S307 is yes, the controller 112 executes Figure 7 Verification method 700 (step S308). When the determination result of step S307 is no, the controller 112 determines whether to perform a write operation on the operation memory address HADDR (step S309).

[0167] When the judgment in step S309 is yes, the controller 112 executes Figure 8 When the step S309 is judged as no, the controller 112 judges whether to perform a read operation on the operation memory address HADDR (step S311). When the step S311 is judged as yes, the controller 112 executes Fig. 9When the determination result of step S312 is no, the controller 112 ends the operation method 300 .

[0168] According to some embodiments of the present invention, when the encryption device 100 is just turned on, the controller 112 must sequentially execute step S302 and step S304 at least once, and then can execute step S310 and step S306 at any time; the controller 112 must sequentially execute step S302 and step S308 at least once, and then can execute step S312 at any time. Thereafter, step S302, step S304, step S306 or step S308 can be executed at any time. According to one embodiment of the present invention, when the user sets the operation signal HWRITE to the write state through the bus interface 111, the encryption device 100 executes the write method 800; when the user sets the operation signal HWRITE to the read state through the bus interface 111, the encryption device 100 executes the read method 900. In other words, in step S309 and step S311, step S310 or step S312 is executed according to the state of the operation signal HWRITE.

[0169] Figure 4 A flow chart showing a setting method according to an embodiment of the present invention is shown. Figure 4 As shown, the controller 112 stores the encrypted memory address EADDR, key KEY, random number NONCE, setting information INF and encryption enable signal PRIEN set by the user through the bus interface 111 in the fourth register 131 (step S401). According to one embodiment of the present invention, the encrypted memory address EADDR, key KEY, random number NONCE and setting information INF set by the user are as follows: Figure 2 As shown in the corresponding table 200, the encrypted memory address EADDR includes the start memory address SADDRP, the end memory address DADDRP and the information authentication code memory address MADDRP.

[0170] Next, the controller 112 locks or unlocks the write lock WLK and the key lock DLK of the encrypted memory address EADDR according to the encryption enable signal PRIEN (step S402). According to one embodiment of the present invention, when the encryption enable signal PRIEN is in an enabled state, the controller 112 sets the write lock WLK and the key lock DLK corresponding to the encrypted memory address EADDR to a locked state. According to another embodiment of the present invention, when the encryption enable signal PRIEN is in a disabled state, the controller 112 sets the write lock WLK and the key lock DLK corresponding to the encrypted memory address EADDR to an unlocked state. The following is a description of the controller 112 setting the write lock WLK and the key lock DLK to a locked state according to the enabled encryption enable signal PRIEN.

[0171] Figure 5 A flowchart of a comparison method according to an embodiment of the present invention is shown. Figure 5 As shown, the controller 112 uses the memory control signal EMICTL to read the lock data LOCK stored in the end memory address DADDRP to the buffer 113 (step S501). According to some embodiments of the present invention, the end memory address DADDRP is Figure 2 One of the first ending memory address DADDR1, the second ending memory address DADDR2, . . . and the Nth ending memory address DADDRN.

[0172] Next, the first comparator CMP1 compares the lock data LOCK with the preset value DEF to generate a first comparison result EQ1, and the controller 112 determines whether the lock data LOCK is equal to the preset value DEF according to the first comparison result EQ1 (step S502). When it is determined that the lock data LOCK is equal to the preset value DEF, the controller 112 sets the write lock WLK to the unlocked state (step S503). When it is determined that the lock data LOCK is not equal to the preset value DEF, the controller 112 ends the comparison method 500 and sets the write lock WLK to the locked state.

[0173] Figure 6 A flowchart showing a method for burning data according to an embodiment of the present invention is shown. Figure 6As shown, when the user wants to burn the information authentication code MAC of the encrypted memory address EADDR, the controller 112 writes a non-preset value into the end memory address DADDRP of the encrypted memory address EADDR, and sets the write lock WLK corresponding to the encrypted memory address EADDR to a locked state (step S601). For example, when the user wants to burn the information authentication code MAC of the second encrypted memory address EADDR2, the controller 112 writes a non-preset value into the lock data LOCK corresponding to the second encrypted memory address EADDR2 of the memory array 120 in step S601, and sets the write lock WLK corresponding to the second encrypted memory address EADDR2 to a locked state.

[0174] Next, the controller 112 uses the protection region selection signal PRSEL to select the information authentication code MAC of the corresponding encrypted memory address EADDR for burning, and sets the information authentication code enable signal MACEN to an enabled state (step S602). As in the above embodiment, when the user wants to burn the information authentication code MAC of the second encrypted memory address EADDR2, the controller 112 uses the protection region selection signal PRSEL to select the second encrypted memory address EADDR2, and sets the information authentication code enable signal MACEN to an enabled state to enable the second encryption unit 135 and disable the first encryption unit 134.

[0175] Subsequently, the controller 112 uses the memory control signal EMICTL to read the encrypted data CT and the lock data LOCK of the encrypted memory address EADDR (step S603). As in the above embodiment, when the user burns the information authentication code MAC to the second encrypted memory address EADDR2, the controller 112 uses the memory control signal EMICTL to read the encrypted data CT and the lock data LOCK corresponding to the second encrypted memory address EADDR2, and provides the read encrypted data CT and the lock data LOCK to the second encryption unit 135.

[0176] Next, the cryptographic device 130 generates summary information DSG (step S604). As in the above embodiment, the second encryption unit 135 performs a second encryption mode operation on the encryption data CT and the lock data LOCK corresponding to the second encryption memory address EADDR2, the second start memory address SADDR2, the second end memory address DADDR2, and the second setting information INF2 corresponding to the second encryption memory address EADDR2 provided by the first multiplexer 132 to generate a second encryption result ECR. According to one embodiment of the present invention, the second encryption mode operation is a cipher block concatenation-information authentication code mode. Subsequently, the second multiplexer 136 provides the second encryption result ECR to the cryptographic unit 137 according to the encryption selection signal SELE provided by the controller 112, and the cryptographic unit 137 uses the second key KEY2 corresponding to the second encryption memory address EADDR2 and the second encryption result ECR to generate summary information DSG.

[0177] The controller 112 writes the generated summary information DSG into the corresponding information authentication code memory address MADDRP, and sets the information authentication code MAC (step S605), and sets the key lock DLK corresponding to the encryption memory address EADDR to the unlocked state (step S606). As in the above embodiment, the controller 112 uses the memory control signal EMICTL to write the summary information DSG into the second information authentication code memory address MADDR2 of the memory array 120, and sets the key lock DLK stored in the encryption memory address EADDR to the unlocked state (step S606). Figure 1 The key lock DLK corresponding to the second encryption memory address EADDR2 of the first register 117 is set to an unlocked state.

[0178] Figure 7 A flowchart of a verification method according to an embodiment of the present invention is shown. Figure 7 As shown, when the user wants to verify the encrypted memory address EADDR, the controller 112 uses the protection region selection signal PRSEL to select the encrypted memory address EADDR for verification, and sets the information authentication code enable signal MACEN to an enabled state (step S701). Figure 2 When the second encryption memory address EADDR2 is received, the controller 112 selects the second encryption end memory address EADDR2 using the protection region selection signal PRSEL, and sets the information authentication code enable signal MACEN to an enabled state.

[0179] The controller 112 uses the memory control signal EMICTL to read the encrypted data CT, the lock data LOCK and the information authentication code MAC in the protection area (step S702). As in the above embodiment, the controller 112 reads the encrypted data CT, the lock data LOCK and the information authentication code MAC corresponding to the second encryption memory address EADDR2, wherein the encrypted data CT and the lock data LOCK are provided to the second encryption unit 135, and the information authentication code MAC is stored in the third register 119. Next, the cryptographic device 130 generates the summary information DSG (step S703), wherein the generation method of the summary information DSG is as described in step S604, and will not be repeated here.

[0180] After step S703, the second comparator CMP2 compares the message authentication code MAC to the digest information DSG generated by the cryptographic device 130 to generate a second comparison result EQ2, and the controller 112 determines whether the message authentication code MAC is equal to the digest information DSG according to the second comparison result EQ2 (step S704).

[0181] When the step S704 is judged as yes, the controller 112 sets the key lock DLK corresponding to the encryption memory address EADDR to an unlocked state (step S705). When the step S704 is judged as no, the controller 112 sets the key lock DLK corresponding to the encryption memory address EADDR to a locked state (step S706). As in the above embodiment, when the information authentication code MAC stored in the second information authentication code memory address MADDR2 of the second encryption memory address EADDR2 is equal to the summary information DSG generated by the cryptographic device 130, it means that the encrypted data CT stored in the second encryption memory address EADDR2 has not been tampered with, so the key lock DLK is set to an unlocked state. When the information authentication code MAC is not equal to the summary information DSG, it means that the encrypted data CT stored in the second encryption memory address EADDR2 has been changed, so the key lock DLK is set to a locked state to protect data security.

[0182] Figure 8 A flowchart showing a writing method according to an embodiment of the present invention is shown. Figure 8 As shown, the determination unit 133 determines whether the operating memory address HADDR input by the user through the bus BUS is within the range of the encrypted memory address EADDR (step S801). For example, the determination unit 133 determines whether the operating memory HADDR received from the bus interface 111 is within the range of the encrypted memory address EADDR. Figure 2The first encrypted memory address EADDR1, the second encrypted memory address EADDR2, and the Nth encrypted memory address EADDRN are within the range of the first encrypted memory address EADDR1, the second encrypted memory address EADDR2, and the Nth encrypted memory address EADDRN. According to an embodiment of the present invention, when the write method 800 is executed, the operation signal HWRITE is in the write state.

[0183] If step S801 is determined to be negative, the determination unit 133 disables the key enable signal KSEN, so that the cryptographic device 130 stops outputting the key stream KS as the output key KO (step S802). Furthermore, the controller 112 directly writes the write data WDATA into the memory array 120 (step S803) without performing encryption.

[0184] If the determination result of step S801 is yes, the determination unit 133 determines whether the write lock WLK corresponding to the encrypted memory address EADDR is in an unlocked state (step S804). For example, when step S801 determines that the operation memory address HADDR falls within the second encrypted memory address EADDR2, the determination unit 133 determines whether the write lock WLK corresponding to the second encrypted memory address EADDR2 is in a locked state in step S804.

[0185] When the judgment result of step S804 is yes, the cryptographic device 130 generates a key stream KS (step S805), and the first logic gate 115 uses the key stream KS to encrypt the write data WDATA, thereby generating encrypted write data EWDATA, and writing the encrypted write data EWDATA into the operation memory address HADDR of the memory array 120 as encrypted data CT (step S806). When the judgment result of step S804 is no, the write method 800 ends. According to some embodiments of the present invention, when the judgment result of step S804 is no, the encryption device 100 does not write the write data WDATA into the memory array 120.

[0186] For example, in step S805, the determination unit 133 provides the operation memory address HADDR to the first encryption unit 134, so that the first encryption unit 134 performs a first encryption mode operation on the operation memory address HADDR and the corresponding random number NONCE (i.e., the second random number NONCE2 in the above embodiment) to generate a first encryption result CNT. The second multiplexer 136 provides the first encryption result CNT to the cryptographic unit 137 according to the encryption selection signal SELE provided by the controller 112. The cryptographic unit 137 generates a key stream KS according to the first encryption result CNT and the corresponding key KEY (i.e., the second key KEY2 in the above embodiment).

[0187] Next, the determination unit 133 enables the key enable signal KSEN according to the fact that the operation signal HWRITE is in the write state, the operation memory address HADDR is located in the encryption memory address EADDR, and the write lock WLK is in the unlock state. The third logic gate 138 outputs the key stream KS as the output key KO according to the enabled key enable signal KSEN, so that the first logic gate 115 encrypts the write data WDATA according to the output key KO to generate the encrypted write data EWDATA, and the controller 112 further uses the memory control signal EMICTL to write the encrypted write data EWDATA to the operation memory address HADDR of the memory array 120 as the encrypted data CT.

[0188] Fig. 9 A flowchart showing a reading method according to an embodiment of the present invention is shown. Fig. 9 As shown, first, the determination unit 133 determines whether the operating memory address HADDR input by the user is within the range of the encrypted memory address (step S901). For example, the determination unit 133 determines whether the operating memory HADDR is within the range of the encrypted memory address. Figure 2 The encrypted memory address EADDR1, the encrypted memory address EADDR2, and the Nth encrypted memory address EADDRN are within the range of the first encrypted memory address EADDR1, the second encrypted memory address EADDR2, and the Nth encrypted memory address EADDRN.

[0189] If the judgment result of step S901 is no, the judgment unit 133 disables the key enable signal KSEN, so that the cryptographic device 130 does not output the key stream KS and outputs the output key KO as a low logic level (step S902). In addition, the controller 112 directly reads the encrypted data CT stored in the operation memory address HADDR of the memory array 120 as the read data RDATA (step S903), and no decryption operation is required. Then, the controller 112 transmits the read data RDATA to the host via the bus interface 111 and the bus BUS (step S904). In detail, since the operation memory address HADDR is not in the encryption memory address EADDR, the cryptographic device 130 does not need to generate the output key KO, and the controller 112 can directly read the corresponding data of the memory array 120.

[0190] If the judgment result of step S901 is yes, the judgment unit 133 judges whether the key lock DLK corresponding to the encrypted memory address EADDR is in an unlocked state (step S905). For example, when the judgment unit 133 judges in step S901 that the operation memory address HADDR is located in the second encrypted memory address EADDR2, the judgment unit 133 judges in step S905 whether the key lock DLK of the second encrypted memory address EADDR2 is in an unlocked state.

[0191] If the determination unit 133 determines in step S905 that the key lock DLK is not in the unlocked state, that is, when the key lock DLK is in the locked state, step S902 is executed. According to one embodiment of the present invention, when it is determined that the operation memory address HADDR is located at the encryption memory address EADDR and the key lock DLK is in the locked state, the cryptographic device 130 does not output the key stream KS as the output key KO, so that the corresponding encrypted data CT cannot be decrypted, thereby protecting the security of the encrypted data CT. According to one embodiment of the present invention, when it is found that the key lock DLK is in the locked state, the verification method 700 can be executed through step S307 of the operation method 300 to set the key lock DLK to the unlocked state.

[0192] If the determination unit 133 determines in step S905 that the key lock DLK is in the unlocked state, the cryptographic device 130 outputs the key stream KS as the output key KO (step S906). In detail, the determination unit 133 enables the key enable signal KSEN according to the operation signal HWRITE being in the read state, the operation memory address HADDR being in the encryption memory address EADDR and the corresponding key lock DLK being in the unlocked state. The third logic gate 138 outputs the key stream KS as the output key KO according to the enabled key enable signal KSEN. After step S906, the second logic gate 116 performs a mutually exclusive or logical operation on the output key KO and the encrypted data CT read from the operation memory address HADDR of the memory array 120 to generate the read data RDATA (step S907). Then, the read data RDATA is transmitted to the host through the bus interface 111 and the bus BUS (step S904).

[0193] In detail, when the key lock DLK is in the unlocked state, the judgment unit 133 generates a judgment signal DET according to the key lock DLK, and provides the corresponding random number NONCE (such as the above embodiment, the second random number NONCE2 corresponding to the second encryption memory address EADDR2) to the first encryption unit 134. The first encryption unit 134 performs a first encryption mode operation on the operation memory address HADDR and the random number NONCE provided by the judgment unit 133, and generates a first encryption result CNT. The second multiplexer 136 provides the first encryption result CNT to the cipher unit 137 according to the encryption selection signal SELE provided by the controller 112. The cipher unit 137 uses the first encryption result CNT output by the second multiplexer 136 and the corresponding key KEY output by the first multiplexer 132 (such as the above embodiment, the second key KEY2 corresponding to the second encryption memory address EADDR2) to generate a key stream KS (step S906).

[0194] The third logic gate 138 outputs the key stream KS as the output key KO according to the enabled key enable signal KSEN. The controller 112 uses the memory control signal EMICTL to read the encrypted data CT of the operation memory address HADDR of the memory array 120 and temporarily stores it in the buffer 113. The second logic gate 116 decrypts the read encrypted data CT into the read data RDATA according to the output key KO (step S907). Then, the controller 112 transmits the decrypted read data RDATA to the host via the bus interface 111 and the bus BUS (step S904).

[0195] The present invention proposes an encryption device and an operation method thereof, which can set a write lock according to user needs to strengthen the protection of the content of the encrypted data to prevent the possibility of tampering. In addition, the encryption device proposed by the present invention uses the Cipher Block Chaining-Message Authentication Code (CBC-MAC) mode to generate summary information and store it in the memory array, which provides an extra layer of protection for the encrypted data to ensure the security and integrity of the internal program. Furthermore, the encryption device proposed by the present invention uses a key lock, so that when reading, the summary information must be confirmed to unlock the subsequent decryption process to prevent tampering from flowing into the encryption device.

[0196] Although the embodiments and advantages of the present application have been disclosed as above, it should be understood that any technician in the technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present application. In addition, the scope of protection of the present application is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any technician in the technical field can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of some embodiments of the present application. As long as the same functions can be implemented in the embodiments described here or the same results can be obtained, they can be used according to some embodiments of the present application. Therefore, the scope of protection of the present application includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each patent application constitutes an individual embodiment, and the scope of protection of the present application also includes the combination of each patent application and the embodiment.

Claims

1. An encryption device, characterized in that: include: A memory array for storing a locking data; as well as A memory control device determines whether the locking data is equal to a preset value according to an operation instruction. When the memory control device determines that the locking data is equal to the preset value, a logic operation is performed on a write data and an output key to generate an encrypted write data, and the encrypted data is written into the memory array to be an encrypted data.

2. The encryption device according to claim 1, characterized in that The memory controller includes: a first register for temporarily storing a write lock; a second temporary register for temporarily storing a key lock; a third temporary register for temporarily storing an information identification code of an information identification code memory address of the memory array; a first comparator, used for comparing the locking data and the preset value to generate a first comparison result; a second comparator, used for comparing a summary message and the message authentication code to generate a second comparison result; a bus interface, receiving the operation instruction, an encryption enable signal, the write data, an operation memory address, an encryption memory address, a key, a random number and a setting information from a bus, wherein the key, the random number and the setting information correspond to the encryption memory address, wherein the encryption memory address includes a start memory address, an end memory address and an information authentication code memory address, wherein the encryption data is stored in the start memory address, and the lock data is stored in the end memory address; a memory interface coupled to the memory array; a buffer coupled to the memory interface, wherein when the first comparator compares the locking data with the preset value, the buffer temporarily stores the locking data, wherein the buffer temporarily stores the encrypted write data and the encrypted data; a first logic gate, performing an exclusive OR logic operation on the write data and the output key to generate the encrypted write data; a second logic gate, performing the above-mentioned exclusive OR logic operation on the above-mentioned encrypted data and the above-mentioned output key to generate a read data; and a controller, which controls the memory array through the memory interface using a memory control signal according to the operation instruction and the operation memory address, and accesses the memory array through the buffer and the memory interface; wherein the controller determines whether the locking data and the preset value are equal according to the first comparison result; When the lock data is equal to the preset value, the controller enables the first register using a write lock enable signal, and sets the write lock to an unlock state using a write lock input signal; When the lock data is not equal to the preset value, the controller sets the write lock to a lock state.

3. The encryption device according to claim 2, characterized in that: The memory controller further comprises: A cryptographic device comprising: a fourth register, used to store the encryption enable signal, the encryption memory address, the key, the random number and the setting information; a first multiplexer, outputting one of the key, the random number and the setting information according to a determination signal; a determination unit, wherein when the determination unit determines that the operation memory address is located in the encryption memory address, the determination unit generates the determination signal and a key enable signal according to the key lock, the write lock, an operation signal, an information authentication code enable signal and a protection area selection signal; a first encryption unit, performing a first encryption mode operation on the random number output by the first multiplexer and the operation memory address to generate a first encryption result; a second encryption unit, receiving the encrypted data and the locking data stored in the memory array, and performing a second encryption mode operation on the encrypted data, the locking data, the setting information output by the first multiplexer, and a starting memory address and an ending memory address of the encrypted memory address to generate a second encryption result; a cryptographic unit, which generates a key stream by using the first encryption result and the key output by the first multiplexer, or generates summary information by using the second encryption result and the key output by the first multiplexer; a second multiplexer, outputting the first encryption result or the second encryption result to the cipher unit according to an encryption selection signal generated by the controller; and A third logic gate performs a logic AND operation on the key stream and the key enable signal to generate the output key.

4. The encryption device according to claim 3, characterized in that: When a user sets the encryption enable signal to an enable state through the bus interface, the controller sets the write lock and the key lock to a lock state; wherein the controller does not write the write data into the encrypted memory address according to the write lock in the locked state; wherein the third logic gate does not output the key stream as the output key according to the key enable signal in the locked state; The user further sets the encryption memory address, the key, the random number and the setting information through the bus interface.

5. The encryption device according to claim 4, characterized in that: The controller writes a value into the end memory address as the lock data, and the value is different from the preset value; The controller further reads the encrypted data of the encrypted memory address and the locked data of the value; wherein the cryptographic unit generates the summary information corresponding to the encrypted memory address; The controller writes the summary information generated by the password unit into the information authentication code memory address to obtain the information authentication code, and sets the key lock corresponding to the encryption memory address to an unlocked state.

6. The encryption device according to claim 5, characterized in that: The controller selects the encrypted memory address using the protection area selection signal to verify the information authentication code and enables the information authentication code enable signal; The controller reads the encrypted data, the locking data and the information authentication code of the encrypted memory address; The cryptographic unit generates the summary information according to the encrypted data and the locked data; wherein the second comparator compares the summary information with the information authentication code to see whether they are equal; When the summary information is equal to the information authentication code, the controller sets the key lock to the unlocked state; When the summary information is not equal to the information authentication code, the controller sets the key lock to the lock state.

7. The encryption device according to claim 6, characterized in that: The judgment unit judges whether the operation memory address is within the encryption memory address; When the operation memory address is within the encryption memory address, the operation signal is in a write state, and the write lock is in the unlock state, the judgment unit enables the key enable signal; The cryptographic unit generates the key stream using the first encryption result generated by the first encryption unit and the key, and the third logic gate outputs the key stream as the output key according to the enabled key enable signal; wherein the first logic gate encrypts the write data using the output key to generate encrypted write data; The controller writes the encrypted write data into the operation memory address of the memory array to obtain encrypted data.

8. The encryption device according to claim 3, characterized in that: The first encryption mode operation is a counter mode, wherein the second encryption mode operation is a cipher block chaining-message authentication code mode.

9. An operating method, applicable to an encryption device, characterized in that: The encryption device includes a memory array, the memory array stores a locking data, wherein the operation method includes: Determining whether the locking data is equal to a preset value; When it is determined that the lock data is equal to the preset value, setting a write lock to an unlock state; When the write lock is in the unlock state, encrypting a write data and an output key to generate an encrypted write data; and The encrypted write data is written into the memory array.

10. The operating method according to claim 9, characterized in that: Also includes: When setting an encrypted memory address, executing a setting method; When comparing the encrypted data, a comparison method is performed; When burning an information authentication code of the encrypted memory address, executing a burning method; When verifying the above information authentication code, executing a verification method; When a write operation is performed on the memory array, a write method is executed; as well as When a read operation is performed on the memory array, a read method is performed; Before executing the writing method, the setting method and the comparing method need to be executed at least once in sequence. Before executing the reading method, the setting method, the burning method and the verifying method need to be executed at least once in sequence.

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