Determination method and device for artificial intelligence chip design parameters and storage medium

Abstract

Embodiments of the invention provide an artificial intelligence chip design parameter determination method and device, and a storage medium. The method comprises the steps of obtaining target computing power of a to-be-designed artificial intelligence chip, forwarding time required by a hardware queue in the artificial intelligence chip for forwarding a task to a computing core and a first calculation amount corresponding to the task; according to the target computing power, the forwarding time and the first calculation amount, design parameters of the artificial intelligence chip are determined, the design parameters comprise the number of cores, the single-core computing power and the number of hardware queues, and the first calculation amount is related to the computing power requirement of a task needing to be executed by the artificial intelligence chip in the target application scene. And the determined design parameters of the artificial intelligence chip can accurately match the computing power demand of the target application scene, so that the artificial intelligence chip matched with the market demand can be designed.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of artificial intelligence technology, and in particular, to a method, device, and storage medium for determining artificial intelligence chip design parameters. Background Art

[0002] With the development of artificial intelligence technology, a large number of tasks of artificial intelligence models are implemented through artificial intelligence chips. When designing artificial intelligence chips, multiple computing cores and multiple hardware queues are configured for the artificial intelligence chip. The hardware queues are used to store tasks sent by the central processor and send the received tasks to the computing core for execution.

[0003] At present, in the design process of artificial intelligence chips, it is necessary to determine the design parameters of artificial intelligence chips. In related technologies, the design parameters of artificial intelligence chips are determined based on existing artificial intelligence chip products on the market or based on the personal experience of architects. On the one hand, since the artificial intelligence chips to be designed are different from the products already on the market, the designed artificial intelligence chips cannot achieve the same effect as the artificial intelligence chip products already on the market; on the other hand, the personal experience of architects is generally the architect's past experience in designing artificial intelligence chips, and these personal experiences are likely to be different from the current market demand, resulting in the designed artificial intelligence chips being difficult to meet the current market demand. Summary of the invention

[0004] The embodiments of the present invention provide a method, device and storage medium for determining artificial intelligence chip design parameters, so as to design an artificial intelligence chip that meets current market demand.

[0005] In a first aspect, the present application provides a method for determining the design parameters of an artificial intelligence chip, the method comprising: obtaining the target computing power of the artificial intelligence chip to be designed, the forwarding time required for a hardware queue in the artificial intelligence chip to forward a task to a computing core, and a first computing amount corresponding to a task; determining the design parameters of the artificial intelligence chip based on the target computing power, forwarding time, and the first computing amount, the design parameters including the number of cores, single-core computing power, and the number of hardware queues, wherein the first computing amount is related to the computing power requirements of the tasks that the artificial intelligence chip needs to perform in the target application scenario.

[0006] Through the above scheme, the target computing power of the artificial intelligence chip to be designed, the forwarding time required for the hardware queue in the artificial intelligence chip to forward a task to the computing core, and the first computing amount corresponding to a task are obtained. The first computing amount is related to the computing power requirement of the task that the artificial intelligence chip needs to perform in the target application scenario. Therefore, the design parameters of the artificial intelligence chip determined according to the target computing power, forwarding time and the first computing amount can accurately match the computing power requirement of the target application scenario, and then an artificial intelligence chip that matches market demand can be designed.

[0007] In a possible implementation, the design parameters of the artificial intelligence chip are determined according to the target computing power, the forwarding time, and the first computing amount, including:

[0008] Determine the single-core computing power of the artificial intelligence chip based on the forwarding time and the first computing amount;

[0009] Determine the number of cores and hardware queues of the artificial intelligence chip based on the forwarding time, target computing power, and the first computing amount.

[0010] In one possible implementation, the single-core computing power of the artificial intelligence chip is determined based on the forwarding time and the first computing amount, including: determining the single-core computing power of the artificial intelligence chip based on the first computing amount, the execution time required for a task to be executed on a computing core in the artificial intelligence chip, and a first preset condition; the first preset condition includes that the execution time is greater than or equal to the forwarding time.

[0011] In one possible implementation, the number of cores and the number of hardware queues of the artificial intelligence chip are determined according to the forwarding time, the target computing power and the first computing amount, including: determining the number of cores and the number of hardware queues of the artificial intelligence chip according to the target computing power, the first computing amount, the execution time required for a task to be executed on a computing core in the artificial intelligence chip and a first preset condition; the first preset condition includes that the execution time is greater than or equal to the forwarding time.

[0012] In a possible implementation, the number of hardware queues is less than or equal to the number of cores.

[0013] In one possible implementation, the first computational amount is determined based on the computational amount of a target task in a target model under a target application scenario, wherein the target task is a task whose execution time corresponding to all tasks in the target model respectively reaches a first threshold value in a normal distribution with a distribution probability.

[0014] In one possible implementation, the target application scenario is a model reasoning scenario.

[0015] In a second aspect, the present application provides a device for determining artificial intelligence chip design parameters, comprising:

[0016] An acquisition unit, used to acquire a target computing power of the artificial intelligence chip to be designed, a forwarding time required for a hardware queue in the artificial intelligence chip to forward a task to a computing core, and a first computing amount corresponding to a task;

[0017] The processing unit is used to determine the design parameters of the artificial intelligence chip according to the target computing power, forwarding time and a first computing amount, wherein the design parameters include the number of cores, single-core computing power and the number of hardware queues, wherein the first computing amount is related to the computing power requirement of the task that the artificial intelligence chip needs to perform in the target application scenario.

[0018] In a third aspect, the present application provides a computer device, comprising a memory, a processor chip, and a computer program stored in the memory and executable on the processor chip, wherein the processor chip implements the method in the above-mentioned first aspect or any possible implementation manner of the first aspect when executing the computer program.

[0019] In a fourth aspect, the present application provides a computer-readable storage medium, comprising computer-executable instructions. When the computer-executable instructions are executed on a computer, the computer executes the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0020] In a fifth aspect, the present application provides a computer program product, wherein the computer program product stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a computer, the computer executes the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0021] The technical effects that can be achieved in any of the second to fifth aspects mentioned above can refer to the description of the beneficial effects in the first aspect mentioned above or any possible implementation method of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a system architecture applicable to an embodiment of the present application;

[0023] Figure 2 A schematic diagram of the structure of an artificial intelligence chip provided in an embodiment of the present application;

[0024] Figure 3 A schematic diagram of the structure of an artificial intelligence chip provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of a flow chart of a method for determining artificial intelligence chip design parameters provided by an embodiment of the present invention;

[0026] Figure 5A schematic diagram of the structure of a device for determining artificial intelligence chip design parameters provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] Figure 1 This is a system architecture diagram applicable to the embodiments of the present application. The system architecture includes a central processing unit (CPU) 100 and an artificial intelligence chip 200. The number of artificial intelligence chips 200 can be one or more, and the present application does not specifically limit the number of artificial intelligence chips. It should be understood that the system architecture may also include other modules or components, which are not specifically limited in the present application. For ease of description, the following embodiments are described by taking an artificial intelligence chip as an example.

[0029] The central processing unit 100 can handle non-computational tasks in artificial intelligence applications, and the artificial intelligence chip 200 can handle a large number of computing tasks in artificial intelligence applications. For example, the operation of the artificial intelligence model can be realized by the artificial intelligence chip 200. The operation of the artificial intelligence model can be realized by the operators in the computational graph, where the computational graph is a multi-graph structure used to represent the computing tasks and data flow processes of the artificial intelligence model, and the operator refers to various operations performed on the tensors of each layer in the artificial intelligence model.

[0030] In actual applications, the central processor 100 can send tasks in the artificial intelligence model to the artificial intelligence chip 200, and the artificial intelligence chip 200 executes the tasks sent by the central processor 100.

[0031] The artificial intelligence chip in the embodiment of the present application is also referred to as an AI accelerator or computing card. The artificial intelligence chip can be, for example, a graphics processing unit (GPU) or a general-purpose graphics processing unit (GPGP U).

[0032] Figure 2 This is a schematic diagram of the structure of an artificial intelligence chip provided in an embodiment of the present application. Figure 2 As shown, the artificial intelligence chip 200 includes a hardware queue 201 and multiple computing cores 202.

[0033] The hardware queue 201 is used to store tasks sent by the central processing unit 100 and forward the tasks to a computing core 202 .

[0034] The computing core 202 is used to execute tasks from the hardware queue 201. The computing core 202 is a unit in the artificial intelligence chip that executes computing tasks. The computing core 202 may be, for example, a streaming processing cluster (SPC), a computing unit (CU), or an execution unit (EU), which is not limited in this application.

[0035] It should be noted that Figure 2 A hardware queue 201 is exemplarily shown in the figure, and the hardware queue 201 corresponds to multiple computing cores 202, that is, the hardware queue 201 can serve multiple computing cores 202, and the hardware queue 201 forwards each task sent by the central processing unit to each computing core 202 respectively.

[0036] The artificial intelligence chip may also include multiple hardware queues 201, each hardware queue 201 corresponds to at least one computing core 202. For example, the artificial intelligence chip includes n computing cores 202, and at most n hardware queues 201 can be designed. Figure 3 In the artificial intelligence chip 200 shown, each hardware queue 201 corresponds to a computing core 202, that is, for any hardware queue 201, the hardware queue 201 receives a task from the central processing unit 100, and then forwards the received task to the computing core 202 corresponding to the hardware queue 201.

[0037] It should be understood that the present application does not limit the number of hardware queues 201 included in the artificial intelligence chip, nor does it limit the number of computing cores 202 included in the artificial intelligence chip. The specific number of hardware queues 201 and the specific number of computing cores 202 included in the artificial intelligence chip can be determined by the method described below. The artificial intelligence chip 200 may also include other modules or components. For example, the artificial intelligence chip may also include a video memory (not described in Figure 2 ), used to store data and tasks sent by the central processing unit and to store the results of the computing core after executing the task, which is not limited in this application.

[0038] In the process of designing artificial intelligence chips, it is necessary to determine the design parameters of the artificial intelligence chips, such as the number of cores, single-core computing power, and number of hardware queues of the artificial intelligence chips. The relevant technologies are based on the existing artificial intelligence chip products on the market or based on the personal experience of the architect. On the one hand, since the artificial intelligence chip to be designed is different from the existing products on the market, the designed artificial intelligence chip cannot achieve the same effect as the existing artificial intelligence chip products on the market; on the other hand, the personal experience of the architect is generally the architect's past experience in designing artificial intelligence chips. These personal experiences are likely to be different from the current market demand, resulting in the designed artificial intelligence chip being difficult to meet the current market demand.

[0039] It should be noted that the single-core computing power involved in this application is the computing power of the smallest computing unit in the artificial intelligence chip. For example, if the smallest computing unit of the artificial intelligence chip is SPC, then the single-core computing power is the computing power of a single SPC, and the number of cores is the number of SPCs included in the artificial intelligence chip. For another example, if the smallest computing unit of the artificial intelligence chip is CU, then the single-core computing power is the computing power of a single CU, and the number of cores is the number of CUs included in the artificial intelligence chip. For another example, if the smallest computing unit of the artificial intelligence chip is EU, then the single-core computing power is the computing power of a single EU, and the number of cores is the number of EUs included in the artificial intelligence chip.

[0040] In view of this, the present application provides a process of a method for determining an artificial intelligence chip design parameter. The process of the method can be executed by an artificial intelligence chip design parameter determination device or a component in the determination device, such as Figure 4 As shown, the method comprises the following steps:

[0041] Step 401, obtain the target computing power of the artificial intelligence chip to be designed, the forwarding time required for the hardware queue in the artificial intelligence chip to forward a task to the computing core, and the first computing amount corresponding to a task.

[0042] There are many ways to obtain the target computing power of the artificial intelligence chip to be designed in the above step 401. Several feasible methods are provided below.

[0043] For example, the target computing power can be determined according to the computing power of the artificial intelligence chip required by the market. For example, the mainstream models on the current market are some large models, such as the chatGPT model. The computing power of the artificial intelligence chip required by the market can be determined according to the computing power required by the chatGPT model. For another example, the mainstream model on the current market is a small model, such as ResNet50. The computing power of the artificial intelligence chip required by the market can be determined according to the computing power required by ResNet50. This application does not limit the type of mainstream models.

[0044] For another example, the target computing power can also be determined based on the product positioning of the artificial intelligence chip to be designed. For example, the product positioning of the artificial intelligence chip to be designed is to achieve the computing power of the artificial intelligence chip with the largest computing power on the current market. Another example is that the product positioning of the artificial intelligence chip to be designed is to achieve 90% of the computing power of the artificial intelligence chip with the largest computing power on the current market.

[0045] For another example, the target computing power is determined based on the computing power of the artificial intelligence chip required by the market and the product positioning of the artificial intelligence chip to be designed.

[0046] The forwarding time in the above step 401 can be determined by the hardware design and simulation data in the early stage of the artificial intelligence chip design process. For this task, it is generally sent by the central processing unit to the hardware queue in the artificial intelligence chip, and then forwarded by the hardware queue to a computing core in the artificial intelligence chip. The forwarding time in the above step 401 can be defined as the time from the sending moment corresponding to the task sent by the central processing unit to the arrival moment of the task at the computing core. In a specific implementation, the time required for a task to reach the computing core from the central processing unit can be determined based on the hardware design and simulation data in the early stage of the artificial intelligence chip design process as the forwarding time.

[0047] In the above step 401, the first computing amount corresponding to a task is related to the computing power requirement of the task that the artificial intelligence chip needs to perform in the target application scenario.

[0048] In a possible implementation, the first computational amount is determined based on the computational amount of a target task in a target model under a target application scenario, where the target task is a task whose execution time corresponding to all tasks in the target model respectively reaches a first threshold in a normal distribution with a distribution probability.

[0049] The execution time corresponding to all tasks in the target model satisfies the normal distribution. The 3sigma principle can be used to describe the probability that the execution time corresponding to all tasks appears in a specific interval under the normal distribution curve. The 3sigma principle includes that the probability that the value is distributed in (μ-3σ, μ+3σ) is 99.73%, that is, the probability that the value is distributed in the interval of 3 standard deviations (σ) from the mean (μ) is about 99.73%; the probability that the value is distributed in (μ-2σ, μ+2σ) is 95.45%; the probability that the value is distributed in (μ-σ, μ+σ) is 68.26%. In an embodiment of the present application, the first threshold value can be set to 95.45%, that is, the target task is a task whose execution time corresponding to all tasks in the target model has a distribution probability of 95.45% in the normal distribution. In this case, multiple tasks can be determined as target tasks, and the first calculation amount can be determined according to the calculation amount corresponding to each task in the target task, for example, the average value of the calculation amount corresponding to each task, or the maximum value of the calculation amount corresponding to each task. Of course, the first threshold value can also be set to other values, and the present application does not limit this. In some other embodiments, the target task can also be the task whose execution time in the target model is closest to the mean (μ), and the mean (μ) is the average value of the execution time corresponding to all tasks in the target model.

[0050] Among them, the target application scenario can be a model reasoning scenario or a model training scenario.

[0051] In a specific implementation, the amount of calculation of a task in a model training scenario is greater than the amount of calculation of a task in a model reasoning scenario. The first amount of calculation in the above step 401 is determined based on the amount of calculation of a task in the model training scenario, and the single-core computing power determined based on the first amount of calculation is relatively large, which is suitable for calculating a task of the target model in the model training scenario. If the single-core computing power determined in this way is used to calculate the task of the target model in the model reasoning scenario, since the computing power required for a task in the model reasoning scenario is relatively small, and a computing core can only calculate one task at the same time, the utilization rate of the single-core computing power is relatively low, which will cause a waste of the single-core computing power. The first amount of calculation in the above step 401 is determined based on the amount of calculation of a task in the model reasoning scenario, and the single-core computing power determined is relatively small, which is suitable for calculating the task of the target model in the model reasoning scenario, and can also be used to calculate the task of the target model in the model training scenario. Although the computing power of a single computing core may not be able to meet the calculation of a task in the model training scenario, multiple computing cores can be used to calculate a task in the model training scenario.

[0052] In order to be compatible with the computing power requirements of a single task in the target model in the model training scenario, the present application determines the first computing amount in the above step 401 according to the computing amount of a single task in the target model in the model reasoning scenario. In this way, the single-core computing power determined based on the first computing amount can meet both the computing power requirements of a single task in the target model in the model reasoning scenario and the computing power requirements of a single task in the target model in the model training scenario.

[0053] The type of the target model can be a large model or a small model. The computing power required for a task in a large model is generally greater than the computing power required for a task in a small model. When the target model used for the target application scenario is a large model, the first computing amount in the above step 401 can be determined based on the computing amount of the target task in the mainstream large model; when the target model used for the target application scenario is a small model, the first computing amount in the above step 401 can be determined based on the computing amount of the target task in the mainstream small model.

[0054] In order to be compatible with the computing power requirements of tasks in large models and small models, the present application determines the first computing amount in the above step 401 based on the computing amount of a task in the mainstream small model in the target application scenario. In this way, the single-core computing power determined based on the first computing amount can meet both the computing power requirements of a task in the small model in the target application scenario and the computing power requirements of a task in the large model in the target application scenario.

[0055] Based on any of the above embodiments, the computational amount of a target task can be counted for the mainstream model in the target application scenario as the first computational amount. For a mainstream model, the target task can be a task whose execution time corresponding to all tasks in the mainstream model has a distribution probability of reaching a first threshold in a normal distribution. The first threshold here can be set according to actual needs, for example, the first threshold is set to 95%, or it can be set to other values.

[0056] Step 402, determining the design parameters of the artificial intelligence chip according to the target computing power, forwarding time and the first computing amount, the design parameters including the number of cores, single-core computing power and the number of hardware queues.

[0057] In a possible implementation, the single-core computing power of the artificial intelligence chip is determined based on the forwarding time and the first calculation amount.

[0058] Specifically, the single-core computing power of the artificial intelligence chip is determined according to the first computing amount, the execution time required for a task to be executed on a computing core in the artificial intelligence chip, and the first preset condition, wherein the first preset condition includes that the execution time is greater than or equal to the forwarding time.

[0059] Taking the target computing power of the artificial intelligence chip to be designed as W, the forwarding time as T, and the first computing amount as M as an example, assume that there is a non-zero integer λ, λ>0, so that a task requires λT time to complete calculation on a computing core, that is, the execution time is λT.

[0060] Assuming the single-core computing power is c and the number of cores is n, then c satisfies the following formula (1) and formula (2):

[0061] W = c*n Formula (1);

[0062] M=c*λT Formula (2);

[0063] From the above formula (2), we can get the following formula (3):

[0064] λ=M / (c*T) Formula (3);

[0065] In formula (3), λ>0, the value of λ can be divided into the following three cases:

[0066] Case 1, λ<1, then the relationship between λT and T satisfies the following formula (4):

[0067] λT<T formula (4);

[0068] In formula (4), λT represents the execution time of a task, and T represents the forwarding time of a task. Therefore, formula (4) means that the execution time of a task is less than the forwarding time of a task. Substituting formula (3) into formula (4), we can get the following formula (5):

[0069] M / c<T Formula (5);

[0070] It can be seen from formula (5) that c is obviously too large.

[0071] Case 2, λ = 1, then the relationship between λT and T satisfies the following formula (6):

[0072] λT=T formula (6);

[0073] In formula (6), λT represents the execution time of a task, and T represents the forwarding time of a task. Therefore, formula (6) indicates that the execution time of a task is equal to the forwarding time of a task. Substituting formula (3) into formula (6), we can obtain the following formula (7):

[0074] M / c=T Formula (7);

[0075] It can be seen from formula (7) that c is acceptable.

[0076] Case 3, λ>1, then the relationship between λT and T satisfies the following formula (8):

[0077] λT>T formula (8);

[0078] In formula (8), λT represents the execution time of a task, and T represents the forwarding time of a task. Therefore, formula (8) means that the execution time of a task is greater than the forwarding time of a task. Substituting formula (3) into formula (8), we can get the following formula (9):

[0079] M / c>T Formula (9);

[0080] It can be seen from formula (9) that c is relatively reasonable.

[0081] Combining the analysis of the above three cases, in a well-designed system, it is more reasonable to calculate the single-core computing power when λ≥1 (i.e., the above cases 2 and 3). Therefore, combining the above formula (7) and formula (9), the following formula (10) can be obtained:

[0082] c≤M / T Formula (10);

[0083] In formula (10), M represents the first computing amount corresponding to a task, which is a known quantity; T represents the forwarding time required for the hardware queue to forward a task, which is a known quantity; therefore, formula (10) can be used to determine that the upper limit of the single-core computing power c is M / T.

[0084] In a possible implementation, the number of cores and the number of hardware queues of the artificial intelligence chip are determined based on the forwarding time, the target computing power, and the first computing amount.

[0085] Specifically, the number of cores of the artificial intelligence chip is determined according to the target computing power, the first computing amount, the execution time required for a task to be executed on a computing core in the artificial intelligence chip, and the first preset condition, wherein the first preset condition includes that the execution time is greater than or equal to the forwarding time.

[0086] Substituting the above formula (1) into formula (10), we can get the following formula (11):

[0087] n≥(T*W) / M Formula (11)

[0088] In formula (11), W represents the target computing power of the artificial intelligence chip, which is a known quantity; T represents the forwarding time required for the hardware queue to forward a task, which is a known quantity; M represents the first computing amount corresponding to a task, which is a known quantity; therefore, formula (11) can be used to determine that the lower limit of the number of cores n of the artificial intelligence chip is (T*W) / M.

[0089] The number of hardware queues of the artificial intelligence chip is determined according to the target computing power, the first computing amount, the execution time required for a task to be executed on a computing core in the artificial intelligence chip, and a first preset condition, wherein the first preset condition includes that the execution time is greater than or equal to the forwarding time.

[0090] Let the number of hardware queues be x and continue with the above assumptions, that is, assume that there is a non-zero integer λ, λ>0, so that a task requires λT time to be calculated on a computing core. Then a hardware queue can forward at most λ tasks within λT time. Since a computing core can only execute one task at a time, a hardware queue can forward at most λ tasks to λ computing cores within λT time. Therefore, n computing cores require at least n / λ hardware queues, that is, the number of hardware queues satisfies formula (12):

[0091] x ≥ n / λ Formula (12);

[0092] Substituting the above formula (1) and formula (3) into formula (12), we can get the following formula (13):

[0093] x≥(T / M)*W Formula (13)

[0094] Since a computing core can only execute one task at a time, even if the computing amount of this task or command cannot make the computing core utilization reach 100%, n computing cores require at most n hardware queues, that is, the number of hardware queues is less than or equal to the number of cores. Therefore, the number of hardware queues satisfies formula (14):

[0095] (T / M)*W≤x≤n Formula (14);

[0096] In formula (14), W represents the target computing power of the artificial intelligence chip, which is a known quantity; T represents the forwarding time required for the hardware queue to forward a task, which is a known quantity; M represents the first computing amount corresponding to a task, which is a known quantity; therefore, formula (14) can be used to determine that the upper limit value of the number of hardware queues x of the artificial intelligence chip is n, and the lower limit value is (T*W) / M.

[0097] Through the above scheme, the target computing power of the artificial intelligence chip to be designed, the forwarding time required for the hardware queue in the artificial intelligence chip to forward a task to the computing core, and the first computing amount corresponding to a task are obtained. The first computing amount is related to the computing power requirement of the task that the artificial intelligence chip needs to perform in the target application scenario. Therefore, the design parameters of the artificial intelligence chip determined according to the target computing power, forwarding time and the first computing amount can accurately match the computing power requirement of the target application scenario, and then an artificial intelligence chip that matches market demand can be designed.

[0098] Based on the same technical concept, the present application provides a device for determining the design parameters of an artificial intelligence chip, such as Figure 5 As shown, the determining device includes:

[0099] An acquisition unit 501 is used to acquire a target computing power of the artificial intelligence chip to be designed, a forwarding time required for a hardware queue in the artificial intelligence chip to forward a task to a computing core, and a first computing amount corresponding to the task;

[0100] The processing unit 502 is used to determine the design parameters of the artificial intelligence chip according to the target computing power, the forwarding time and the first computing amount, wherein the design parameters include the number of cores, the computing power of a single core and the number of hardware queues, wherein the first computing amount is related to the computing power requirement of the task that the artificial intelligence chip needs to perform in the target application scenario.

[0101] In one possible implementation, the processing unit 502 is specifically used to: determine the single-core computing power of the artificial intelligence chip based on the forwarding time and the first computing amount; determine the number of cores of the artificial intelligence chip and the number of hardware queues based on the forwarding time, the target computing power and the first computing amount.

[0102] In one possible implementation, the processing unit 502 is specifically used to determine the single-core computing power of the artificial intelligence chip based on the first computing amount, the execution time required for executing the task on a computing core in the artificial intelligence chip, and a first preset condition; the first preset condition includes that the execution time is greater than or equal to the forwarding time.

[0103] In one possible implementation, the processing unit 502 is specifically used to determine the number of cores of the artificial intelligence chip and the number of hardware queues according to the target computing power, the first computing amount, the execution time required for executing a task on a computing core in the artificial intelligence chip, and a first preset condition; the first preset condition includes that the execution time is greater than or equal to the forwarding time.

[0104] In a possible implementation, the number of the hardware queues is less than or equal to the number of cores.

[0105] In a possible implementation, the first computational amount is determined according to the computational amount of a target task in a target model under the target application scenario, and the target task is a task whose execution time corresponding to all tasks in the target model respectively has a distribution probability in a normal distribution reaching a first threshold.

[0106] In a possible implementation, the target application scenario is a model reasoning scenario.

[0107] Based on the same inventive concept, the present application provides a computer device, which includes a memory, a processor chip, and a computer program stored in the memory and executable on the processor chip. When the processor chip executes the computer program, the method steps in any of the above method embodiments are implemented.

[0108] Based on the same technical concept, an embodiment of the present application provides a computer-readable storage medium, including computer-executable instructions. When the computer-executable instructions are executed on a computer, the computer executes the method steps in any of the above method embodiments.

[0109] Based on the same technical concept, an embodiment of the present application provides a computer program product, which stores a computer program. The computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the method steps in any of the above method embodiments.

[0110] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, devices (equipment), systems, chips, computer-readable storage media, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware, which are collectively referred to as "modules" or "systems" herein.

[0111] The present application is described with reference to at least one of the following diagrams of the method, apparatus (device) or system of the present application: a flowchart, a block diagram. It should be understood that at least one of the following can be implemented by computer program instructions: each process in the flowchart, each box in the block diagram, and a combination of a process in the flowchart and a box in the block diagram.

[0112] These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce instructions for implementing at least one of the following: Figure 1 Devices or blocks that specify functions in a process or multiple processes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0113] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, the instruction device implementing at least one of the following: Figure 1 A function or a block specified in a process or multiple processes Figure 1 A function specified in one or more boxes.

[0114] These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing at least one of the following: steps for specifying a function in one or more processes in a flowchart, steps for specifying a function in one or more boxes in a block diagram.

[0115] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A method for determining design parameters of an artificial intelligence chip, characterized in that: include: Obtaining a target computing power of the artificial intelligence chip to be designed, a forwarding time required for a hardware queue in the artificial intelligence chip to forward a task to a computing core, and a first computing amount corresponding to the task, where the first computing amount is related to a computing power requirement of a task to be performed by the artificial intelligence chip in a target application scenario; According to the target computing power, the forwarding time and the first computing amount, the design parameters of the artificial intelligence chip are determined, and the design parameters include the number of cores, single-core computing power and the number of hardware queues.

2. The method according to claim 1, characterized in that The step of determining the design parameters of the artificial intelligence chip according to the target computing power, the forwarding time, and the first computing amount includes: Determining a single-core computing power of the artificial intelligence chip according to the forwarding time and the first computing amount; The number of cores of the artificial intelligence chip and the number of hardware queues are determined according to the forwarding time, the target computing power and the first computing amount.

3. The method according to claim 2, characterized in that The determining, according to the forwarding time and the first computing amount, the single-core computing power of the artificial intelligence chip includes: Determine the single-core computing power of the artificial intelligence chip based on the first computing amount, the execution time required for executing the task on a computing core in the artificial intelligence chip, and a first preset condition; the first preset condition includes that the execution time is greater than or equal to the forwarding time.

4. The method according to claim 2, characterized in that The determining, according to the forwarding time, the target computing power, and the first computing amount, the number of cores of the artificial intelligence chip and the number of hardware queues includes: The number of cores of the artificial intelligence chip and the number of hardware queues are determined according to the target computing power, the first computing amount, the execution time required for executing the task on a computing core in the artificial intelligence chip, and a first preset condition; the first preset condition includes that the execution time is greater than or equal to the forwarding time.

5. The method according to claim 4, characterized in that The number of hardware queues is less than or equal to the number of cores.

6. The method according to any one of claims 1 to 5, characterized in that: The first computational amount is determined according to the computational amount of a target task in a target model under the target application scenario, and the target task is a task whose execution time corresponding to all tasks in the target model respectively has a distribution probability in a normal distribution reaching a first threshold.

7. The method according to claim 6, characterized in that The target application scenario is a model reasoning scenario.

8. A computer device comprising a memory, a processor chip, and a computer program stored in the memory and executable on the processor chip, characterized in that: When the processor chip executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

9. A computer-readable storage medium, characterized in that: The method comprises computer executable instructions, which, when executed on a computer, cause the computer to execute the steps of the method according to any one of claims 1 to 7.

10. A computer program product, characterized in that The computer program product stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a computer, the computer is caused to execute the steps of the method according to any one of claims 1 to 7.

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