Hybrid fault simulation method and device based on dominating tree guide circuit division

Abstract

The invention discloses a hybrid fault simulation method and device for guiding circuit division based on a dominating tree. The method comprises the steps that an optimized dominating tree corresponding to the circuit relation of a target chip is constructed by introducing a pseudo root node and segmenting a first node which is doubly dominated, the first node is influenced by a plurality of dominating nodes, and all dominating paths formed by the first node and the dominating nodes are independent; according to the logic depth and the fan-in number of the candidate areas in the optimization dominating tree, identifying a circuit area suitable for compiling simulation in the target chip to perform compiling simulation; a forward propagation scheme and a backward mapping scheme are adopted to carry out event-driven simulation based on the hierarchical structure of the optimized dominating tree, the forward propagation scheme realizes hierarchical event processing by utilizing a convergence and divergence relationship between child nodes and father nodes, and the backward mapping scheme is used for mapping a detected fault back to a fault injection point. According to the method and the device, the technical problem of relatively low fault simulation efficiency of the chip in related technologies is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a hybrid fault simulation method and device based on dominator tree guided circuit partitioning. Background Art

[0002] This section is intended to provide a background or context to what is stated in the claims or specification, and no admission is made that what is described herein is prior art by inclusion in this section.

[0003] As the complexity of electrical circuits continues to grow, the efficiency of fault simulation becomes more and more of a bottleneck. Fault simulation is a key component of the design phase, especially in the Design for Testability (DFT) process, where it is widely used in Automatic Test Pattern Generation (ATPG) and fault diagnosis. During ATPG, fault simulation is iteratively performed to evaluate fault coverage, while in fail-safe analysis, it is used to evaluate the system's ability to recover from faults. The speed of fault simulation directly affects the efficiency of the chip design process. However, as the complexity of chips used in mission-critical applications continues to increase, simulating millions of faults to evaluate diagnostic coverage will result in significant time overhead, further exacerbating the efficiency challenge.

[0004] Traditional fault simulation methods are mainly event-driven simulation and compiled simulation. Event-driven simulation is the first choice for fault simulation because it only focuses on simulating the difference between fault-free and faulty circuits, and the computational load is relatively low. However, it requires more memory access compared to compiled simulation. Compiled simulation optimizes the execution order by predetermining the lines to be evaluated, reducing event scheduling and circuit netlist access. However, in fault simulation, calculating the behavior of a faulty circuit that is identical to a fault-free circuit results in redundant calculations.

[0005] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0006] The embodiments of the present application provide a hybrid fault simulation method and device based on dominator tree guided circuit partitioning, so as to at least solve the technical problem of low chip fault simulation efficiency in the related art.

[0007] According to one aspect of an embodiment of the present application, a hybrid fault simulation method based on dominator tree-guided circuit partitioning is provided, including: constructing an optimized dominator tree corresponding to the circuit relationship of a target chip by introducing a pseudo-root node and splitting a first node that is doubly dominated, wherein the first node is affected by multiple dominator nodes and is independent of all dominator paths composed of each dominator node; identifying circuit regions in the target chip suitable for compilation simulation according to the logic depth and fan-in number of candidate regions in the optimized dominator tree for compilation simulation to simplify the circuit structure of the target chip; and performing event-driven simulation using a forward propagation scheme and a backward mapping scheme based on the hierarchical structure of the optimized dominator tree, wherein the forward propagation scheme utilizes the convergence-divergence relationship between child nodes and parent nodes in the optimized dominator tree to realize hierarchical event processing, and the backward mapping scheme is used to map the detected fault back to the fault injection point starting from the termination node of the fault propagation.

[0008] Optionally, an optimized dominator tree corresponding to the circuit relationship of the target chip is constructed by introducing a pseudo-root node and splitting the dual-dominant nodes, including: connecting isolated nodes and subgraphs in the original circuit flow graph of the target chip to a pseudo-root node to obtain a target circuit flow graph; converting the target circuit flow graph into an original dominator tree according to the circuit relationship; performing node splitting on the dual-dominant nodes in the original dominator tree based on dual-dominant attributes to obtain the optimized dominator tree: determining a first node in the original dominator tree that is affected by multiple dominator nodes and all dominant paths are independent, splitting the first node into multiple second nodes, and connecting each of the second nodes to one of the dominant paths to replace the first node, to obtain an optimized dominator tree, wherein the second nodes connected to any two of the dominant paths are different.

[0009] Optionally, according to the logic depth and fan-in number of the candidate area in the optimized dominator tree, the circuit area in the target chip suitable for compilation simulation is identified for compilation simulation, including: determining the logic depth and fan-in number of the candidate area in the optimized dominator tree, wherein the candidate area is the area to be compiled and fused; determining the fusion priority of the candidate area according to adjacency, and compiling and fusion the candidate area using a fusion strategy according to the fusion priority; and injecting the fault to be tested into the instruction function sequence obtained by compilation and fusion for fault simulation.

[0010] Optionally, determining the logical depth and fan-in number of the candidate area in the optimized dominator tree includes: starting from the bottom layer of the optimized dominator tree, traversing the nodes of each layer in a preset order; determining the adjacency between the traversed third node and the parent node of the third node; determining that the area composed of the parent node of the third node and each child node of the parent node is the candidate area; and obtaining the fan-in count of the candidate area, wherein the fan-in count is the number of inputs connected to the node or area after compilation and fusion.

[0011] Optionally, the fusion priority of the candidate area is determined according to the adjacency, and the candidate area is compiled and fused using a fusion strategy according to the fusion priority, including: when the adjacency indicates that the third node in the candidate area is adjacent to the parent node of the third node in the optimized dominator tree but not adjacent to the target circuit flow graph, compiling and fusion of the candidate area is performed using a fusion strategy according to a first priority; when the adjacency indicates that the third node in the candidate area is adjacent to the parent node of the third node in the optimized dominator tree and adjacent to the target circuit flow graph, compiling and fusion of the candidate area is performed using a fusion strategy according to a second priority, wherein the second priority is lower than the first priority.

[0012] Optionally, a fusion strategy is adopted to compile and fuse the candidate area, including: when the fan-in count of the candidate area is less than a first threshold, allowing the candidate area to be compiled and fused, but not immediately generating a corresponding instruction function sequence; when the fan-in count of the candidate area is greater than a second threshold, not compiling and fusing the candidate area; when the fan-in count of the candidate area is greater than or equal to the first threshold and less than or equal to the second threshold, directly compiling and fusing the candidate area into a composite node and generating a corresponding instruction function sequence.

[0013] Optionally, a forward propagation scheme and a backward mapping scheme are used based on the hierarchical structure of the optimized dominator tree to perform event-driven simulation, including: determining the fault transmission path where the fault injection node and the forward propagation node of the fault injection node are located based on the hierarchical structure of the optimized dominator tree, updating the forward propagation information of the nodes on the fault transmission path starting from the fault injection node, and storing the newly triggered events in a hierarchical event queue according to the hierarchical structure of the optimized dominator tree; during event processing, processing the events in the hierarchical event queue in order from the lower layer to the upper layer of the hierarchy, wherein the hierarchical event queue is used to store different events of each layer; after the forward propagation simulation is completed, starting from the termination node of the fault propagation, the detected fault is mapped back to the fault injection point using the hierarchical structure of the optimized dominator tree and the reversible computability of fault impact propagation.

[0014] According to another aspect of an embodiment of the present application, a hybrid fault simulation device based on dominator tree-guided circuit partitioning is also provided, including: a dominator tree construction unit, used to construct an optimized dominator tree corresponding to the circuit relationship of the target chip by introducing a pseudo-root node and splitting a first node that is doubly dominated, wherein the first node is affected by multiple dominator nodes and is independent of all dominator paths composed of each dominator node; a compilation simulation unit, used to identify circuit areas in the target chip that are suitable for compilation simulation according to the logic depth and fan-in number of candidate areas in the optimized dominator tree to perform compilation simulation, so as to simplify the circuit structure of the target chip; a driving simulation unit, used to perform event-driven simulation based on the hierarchical structure of the optimized dominator tree using a forward propagation scheme and a backward mapping scheme, wherein the forward propagation scheme uses the convergence and divergence relationship between child nodes and parent nodes in the optimized dominator tree to realize hierarchical event processing, and the backward mapping scheme is used to map the detected fault back to the fault injection point starting from the termination node of the fault propagation.

[0015] According to another aspect of an embodiment of the present application, a storage medium is further provided, which includes a stored program, and the above method is executed when the program is run.

[0016] According to another aspect of an embodiment of the present application, an electronic device is further provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the above method through the computer program.

[0017] According to one aspect of the present application, a computer program product or a computer program is provided, the computer program product or the computer program comprising computer instructions, the computer instructions being stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any one of the embodiments of the above method.

[0018] In an embodiment of the present application, an optimized dominator tree corresponding to the circuit relationship of the target chip is constructed by introducing a pseudo-root node and splitting the first node that is doubly dominated. The first node is affected by multiple dominator nodes, and all dominator paths composed of each dominator node are independent; according to the logic depth and fan-in number of the candidate area in the optimized dominator tree, the circuit area suitable for compilation simulation in the target chip is identified for compilation simulation to simplify the circuit structure of the target chip; based on the hierarchical structure of the optimized dominator tree, a forward propagation scheme and a backward mapping scheme are adopted to perform event-driven simulation. The forward propagation scheme utilizes the convergence and divergence relationship between child nodes and parent nodes in the optimized dominator tree to realize hierarchical event processing, and the backward mapping scheme is used to map the detected fault back to the fault injection point starting from the termination node of the fault propagation, thereby solving the technical problem of low fault simulation efficiency of the chip in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 is a flow chart of a hybrid fault simulation method based on dominator tree guided circuit partitioning according to an embodiment of the present application;

[0021] Figure 2 is a schematic diagram of an optional dominator tree construction algorithm according to an embodiment of the present application;

[0022] Figure 3 is a schematic diagram of an optional dominator tree construction solution according to an embodiment of the present application;

[0023] Figure 4 is a schematic diagram of an optional dominator tree adjacency according to an embodiment of the present application;

[0024] Figure 5 is a schematic diagram of an optional dominator tree node fusion according to an embodiment of the present application;

[0025] Figure 6 is a schematic diagram of an optional compilation fault injection solution according to an embodiment of the present application;

[0026] Figure 7 is a schematic diagram of an optional compilation fault injection process according to an embodiment of the present application;

[0027] Figure 8 is a schematic diagram of mixed fault simulation results based on dominator tree guided circuit partitioning according to an embodiment of the present application;

[0028] Fig. 9is a schematic diagram of an optional hybrid fault simulation device based on dominator tree guided circuit partitioning according to an embodiment of the present application; and,

[0029] Fig.10 It is a structural block diagram of a terminal according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] Compiled simulation is a static simulation strategy that increases simulation speed by predetermining the evaluation order of logic gates in a circuit and converting them into machine instructions for execution. In fault simulation, compiled simulation can reduce memory accesses but increase the number of redundant calculations. Event-driven simulation is a dynamic simulation strategy that triggers logic calculations based on changes in circuit state. This strategy is suitable for fault simulation because it avoids invalid simulations and only focuses on the differences between faulty and normal circuit behaviors. However, it requires memory access for each event, which consumes a lot of memory.

[0033] Hybrid simulation strategy: The hybrid simulation strategy can combine the advantages of compiled simulation and event-driven simulation. It uses compiled simulation in the circuit fitting part to reduce memory access and improve efficiency, and uses event-driven simulation in fault effect propagation to avoid invalid calculations as much as possible. This strategy improves the simulation speed while ensuring the accuracy of the simulation results.

[0034] In the hybrid fault simulation approach, the circuit can be partitioned based on concepts such as fan-out free regions (FFRs) or multiple fan-out clusters (Mffcs), and then different simulation strategies are applied in different areas.

[0035] Circuit partitioning based on fanout free regions (FFRs): A method that applies compiled simulation to fanout free regions (FFRs), where each gate has only one output subcircuit. In FFRs, simulation is accelerated by pre-compiling logic expressions. Event-driven simulation is used to select FFRs for simulation. When a fault is injected into an FFR, an event is triggered if the effect of the fault propagates to the output. This method focuses on the local circuit structure, ignoring the overall characteristics of the circuit and the inherent signal propagation relationship. It fails to fully utilize the logical characteristics of different regions of the circuit, resulting in the partitioned regions not being well matched with the simulation strategy.

[0036] Circuit partitioning based on multiple fan-out clusters (Mffc): Based on the concept of FFR, further work introduced more advanced concepts such as multiple fan-out clusters (Mffc), which not only considers the absence of fan-out, but also considers the relationship between signal flow and logic gates, such as introducing concepts such as signal-related dynamic dominators and stem regions. However, this method often relies heavily on the characteristics of small-scale circuits and ignores the overall characteristics of large-scale circuits. In addition, these methods have not been integrated with the advantages of compilation.

[0037] In summary, the above circuit partitioning methods are relatively simple and fail to fully consider the dominance relationship within the circuit. Dominance relationship refers to the control and influence of certain key nodes in the circuit on other nodes, reflecting the inherent logical dependency of the circuit. Ignoring this relationship will cause the divided areas to not match the compiled simulation or event-driven simulation well, affecting the efficiency of hybrid simulation. For example, dividing a large combinational logic block into multiple areas will introduce additional event synchronization overhead. In addition, for circuits containing isolated nodes or multiple dominator nodes, the above methods are difficult to give a suitable partition. The existence of these nodes breaks the boundaries of the region and increases the complexity of partitioning and simulation.

[0038] Dominator tree is a graph theory data structure used to represent the dominance relationship between nodes in a directed graph. Dominator tree can represent the path of signal propagation in a circuit, where the dominance relationship of nodes is crucial for fault propagation analysis. Dominator point: In a directed graph, a set of vertices a is said to dominate a vertex u if every path from u to a specified endpoint includes at least one vertex from a. If A consists of a single vertex, that vertex is called the direct dominator of u. If a contains exactly two vertices, A is called a pair of co-dominators, which means that every path from u passes through at least one of the two vertices in A.

[0039] The principle of using dominator trees to optimize fault simulation is based on the observation that signal propagation in circuits usually involves inherent dominance relationships. Some signal paths are naturally dominant because they pass through key logic gates or connections, and changes in their values ​​directly affect the final output of the circuit. Changes in circuits are usually controlled by dominance relationships, that is, changes in inputs or internal nodes trigger a series of chain reactions. Several key properties of the Dominator tree make it an ideal tool for optimizing directed graph structures and improving the efficiency of fault simulation.

[0040] Path uniqueness: In the Dominator tree, there is a unique path from the root node to any leaf node. This feature simplifies the analysis of fault propagation because it allows deterministic tracking of signal transmission. Node dominance relationship: Dominance relationships define a hierarchy between nodes, which facilitates the identification of critical paths within the circuit. Focusing on these critical paths during fault simulation can improve efficiency.

[0041] The process of forming this application plan experienced the following technical difficulties:

[0042] How to introduce additional nodes into the circuit diagram to unify isolated nodes and subgraphs. The existence of isolated nodes and subgraphs will affect the integrity of the construction and partitioning of the Dominator tree. A mechanism needs to be designed to connect them to the main circuit. How to deal with nodes with multiple dominators to better reflect the circuit structure. Multi-dominator nodes reflect the repeated structure in the circuit. Directly constructing the Dominator tree will lose this information. Such nodes need special processing to more accurately represent the original circuit. How to design metrics based on the structure of the Dominator tree to guide circuit partitioning. The Dominator tree provides hierarchical information of the circuit, but further analysis is required to determine which areas are suitable for compilation and simulation. Appropriate metrics must be designed, taking into account factors such as fan-in size and logic depth.

[0043] Based on this, the present application provides a hybrid fault simulation scheme (HyFAST) based on dominator tree guided circuit partitioning. Figure 1 is a flow chart of a hybrid fault simulation method based on dominator tree guided circuit partitioning according to an embodiment of the present application, such as Figure 1 As shown, the method may include the following steps:

[0044] Step S1, constructing an optimized dominator tree corresponding to the circuit relationship of the target chip by introducing a pseudo-root node and splitting a first node that is doubly dominated, wherein the first node is affected by multiple dominator nodes and is independent of all dominator paths formed by each dominator node. Step S1 includes:

[0045] 1) connecting the isolated nodes and subgraphs in the original circuit flow graph of the target chip to the pseudo root node to obtain the target circuit flow graph;

[0046] 2) converting the target circuit flow graph into an original dominator tree according to the circuit relationship;

[0047] 3) performing node segmentation on the dual-dominance nodes in the original dominance tree based on dual-dominance attributes to obtain the optimized dominance tree: determining in the original dominance tree a first node that is affected by multiple dominance nodes and all dominance paths are independent, segmenting the first node into multiple second nodes, and connecting each of the second nodes to one of the dominance paths to replace the first node, to obtain an optimized dominance tree, wherein the second nodes connected by any two of the dominance paths are different.

[0048] Step S2, identifying a circuit region in the target chip suitable for compilation simulation according to the logic depth and fan-in number of the candidate region in the optimized dominator tree, and performing compilation simulation to simplify the circuit structure of the target chip.

[0049] Step S2 includes:

[0050] 1) determining the logical depth and fan-in number of a candidate region in the optimized dominator tree, wherein the candidate region is a region to be compiled and fused: starting from the bottom layer of the optimized dominator tree, traversing the nodes of each layer in a preset order, determining the adjacency between a traversed third node and a parent node of the third node, determining that a region consisting of a parent node of the third node and each child node of the parent node is the candidate region, and obtaining a fan-in count of the candidate region, wherein the fan-in count is the number of inputs connected to the node or region after compilation and fusion.

[0051] 2) Determine the fusion priority of the candidate area according to the adjacency, and compile and fuse the candidate area using a fusion strategy according to the fusion priority: when the adjacency indicates that the third node in the candidate area is adjacent to the parent node of the third node in the optimized dominator tree but not adjacent to the target circuit flow graph, compile and fuse the candidate area using a fusion strategy according to the first priority; when the adjacency indicates that the third node in the candidate area is adjacent to the parent node of the third node in the optimized dominator tree and adjacent to the target circuit flow graph, compile and fuse the candidate area using a fusion strategy according to the second priority, and the second priority is lower than the first priority.

[0052] During specific fusion, when the fan-in count of the candidate area is less than the first threshold, the candidate area is allowed to be compiled and fused, but the corresponding instruction function sequence is not immediately generated; when the fan-in count of the candidate area is greater than the second threshold, the candidate area is not compiled and fused; when the fan-in count of the candidate area is greater than or equal to the first threshold and less than or equal to the second threshold, the candidate area is directly compiled and fused into a composite node, and the corresponding instruction function sequence is generated.

[0053] 3) Inject the fault to be tested into the instruction function sequence obtained by compilation and fusion to perform fault simulation.

[0054] Step S3, based on the hierarchical structure of the optimized dominator tree, a forward propagation scheme and a backward mapping scheme are used to perform event-driven simulation, wherein the forward propagation scheme uses the convergence-divergence relationship between child nodes and parent nodes in the optimized dominator tree to realize hierarchical event processing, and the backward mapping scheme is used to map the detected fault back to the fault injection point starting from the termination node of the fault propagation. Step S3 includes:

[0055] 1) determining the fault transmission path where the fault injection node and the forward propagation node of the fault injection node are located based on the hierarchical structure of the optimized dominator tree, updating the forward propagation information of the nodes on the fault transmission path starting from the fault injection node, and storing the newly triggered events in the hierarchical event queue according to the hierarchical structure of the optimized dominator tree, and in the event processing process, processing the events in the hierarchical event queue in sequence from the lower layer to the upper layer according to the hierarchical structure, wherein the hierarchical event queue is used to store different events of each layer;

[0056] 2) After the forward propagation simulation is completed, starting from the termination node of the fault propagation, the detected fault is mapped back to the fault injection point by utilizing the hierarchical structure of the optimized dominator tree and the reversible computation of the fault impact propagation.

[0057] In order to reduce the simulation time, we can try to directly combine compiled simulation and event-driven simulation, but it is difficult to achieve the corresponding effect due to unreasonable circuit partitioning and lack of analysis of circuit structure. For example, the circuit partitioning method based on fan-out free regions (FFRs) focuses on the properties of a single circuit in a small area. This method ignores the complex circuit logic structure with favorable compilation characteristics and ignores the overall event propagation characteristics of the circuit.

[0058] In order to capture a wider range of circuit information, this scheme deeply studies the intrinsic dominance relationship within the circuit. Some circuit nodes exert a dominant influence on other nodes within the circuit due to their connection to key logic gates or due to connections. In order to take advantage of this to guide circuit area division and fault propagation analysis, the circuit diagram can be converted into an optimized Dominator tree. This structure takes advantage of the inherent advantages of signal propagation and logic gate behavior in the circuit. In a Dominator tree, a node (parent node) is directly affected by all its subordinate nodes. This hierarchical relationship enables the event of the parent node to include the events of all its child nodes, allowing event processing to be concentrated on nodes with direct logical dependencies.

[0059] However, to combine the advantages of compiled simulation and event-driven simulation with optimal partitioning, two key issues need to be addressed. One key issue is how to identify suitable circuit regions for compiled simulation based on the constructed Dominator tree. Regions with small fan-in and deep logic are more suitable for compiled simulation. These regions usually have fewer inputs and more complex logic paths, which helps to further reduce the number of events and memory accesses required during simulation. Another key issue is to determine how events are ordered in event-driven simulation. It is crucial to find the best sequence for event processing, maximize the integration of repeated events, allow maximum reuse of events on parent nodes, and minimize redundant events.

[0060] Therefore, based on the constructed Dominator tree, the present application solves the above two problems, thereby achieving efficient hybrid simulation. In order to facilitate the identification of suitable areas for compilation simulation based on the Dominator tree, the present scheme proposes two heuristic metrics that combine logic depth and low fan-in properties. These indicators guide the circuit partitioning based on the Dominator tree, aiming to identify areas that are conducive to higher performance optimization through compilation integration. On this basis, in order to achieve more efficient fault simulation, fault injection can be implemented through compilation to achieve economical and efficient fault propagation. In order to solve the challenge of event processing order in event-driven simulation, the present scheme proposes a tree-based hierarchical queue system based on the observation property of parent node event convergence on the Dominator tree, and the principle of compact access to logic gates at the same level to reduce memory access overhead. On this basis, the present scheme introduces forward event propagation and backward mapping algorithms, utilizing the convergence-divergence relationship between parent nodes and child nodes on the tree.

[0061] This application proposes a circuit partitioning method based on an optimized Dominator tree for mixed fault simulation. This method makes full use of the inherent dominance relationship of the circuit and guides circuit partitioning by constructing an optimized Dominator tree. Compared with the existing methods, this application has the following innovations:

[0062] Introducing a pseudo-root node to uniformly connect isolated nodes and subgraphs, by adding a virtual node to the original circuit and connecting all the main output nodes and main input nodes of the original circuit to this node, this method unifies the scattered circuit fragments into a connected graph, which ensures the integrity of the Dominator tree and simplifies the subsequent analysis steps;

[0063] The multi-dominator nodes are split to refine the structure of the Dominator tree. The traditional method directly removes the multi-dominator nodes, which causes the Dominator tree to lose important structural information of the circuit. The present application splits the multi-dominator nodes into multiple independent nodes according to the number of dominators and dominance paths. The split nodes are inserted into the Dominator tree as child nodes of their respective dominators, which more accurately reflects the hierarchical characteristics of the circuit.

[0064] A metric based on adjacency and fan-in size is designed to divide regions. Compared with traditional methods, this application proposes two novel metrics: one is the ratio of Dominator tree nodes to adjacent nodes of the original circuit, and the other is the average fan-in size of the Dominator subtree. The former reflects the similarity between the Dominator tree and the original circuit structure, while the latter measures the complexity within the subtree. Taking the two indicators into consideration, it is possible to identify areas suitable for compilation simulation, i.e., areas with low fan-in and large logic depth. Such areas are tightly connected internally, and the compilation optimization effect is better.

[0065] A complete circuit partitioning process based on Dominator tree and metrics is given. This application details the steps of optimizing Dominator tree construction, including pseudo-root node introduction, initial tree construction, multi-dominator node splitting, etc. On this basis, a method for automatically partitioning circuits using metrics is given. By recursively traversing the Dominator tree, calculating the metric value of each subtree, and deciding whether to mark it as a compilation simulation area based on a preset threshold, the entire process has a high degree of automation, which can significantly reduce the labor cost of circuit partitioning.

[0066] Through the above steps, an optimized dominator tree corresponding to the circuit relationship of the target chip is constructed by introducing a pseudo-root node and splitting the first node that is doubly dominated, wherein the first node is affected by multiple dominator nodes and is independent of all dominator paths composed of the respective dominator nodes; according to the logic depth and fan-in number of the candidate area in the optimized dominator tree, a circuit area in the target chip suitable for compilation simulation is identified for compilation simulation to simplify the circuit structure of the target chip; based on the hierarchical structure of the optimized dominator tree, a forward propagation scheme and a backward mapping scheme are adopted to perform event-driven simulation, wherein the forward propagation scheme utilizes the convergence and divergence relationship between child nodes and parent nodes in the optimized dominator tree to realize hierarchical event processing, and the backward mapping scheme is used to map the detected fault back to the fault injection point starting from the termination node of the fault propagation, which can solve the technical problem of low fault simulation efficiency of the chip in the related art.

[0067] As circuit complexity continues to grow, the efficiency of fault simulation becomes more and more of a bottleneck. This application provides an efficient hybrid fault simulation solution based on an optimized Dominator tree, which effectively integrates the advantages of compiled simulation and event-driven simulation. By modeling the circuit as an optimized dominator tree, the partitioning algorithm is guided by the dominance relationship to efficiently and accurately identify circuit areas suitable for compiled simulation. In addition, in order to minimize the number of events in event-driven simulation, a Forward Backward simulation model based on the hierarchy of the Dominator tree is introduced. Practical results show that compared with commercial tools, the solution achieves a maximum acceleration of 21 times and an average acceleration of more than 3 times. For large circuits with more than 100k gates, the acceleration effect is particularly obvious. As an optional embodiment, the technical solution of the present application is further described in detail below in conjunction with a specific implementation method:

[0068] In mixed fault simulation, compiled simulation increases simulation speed by predetermining the evaluation order of logic gates in the circuit and converting them into machine instructions. For example, in simulation acceleration based on function-level compilation, a bipartite graph matching algorithm can be used for compiled logic evaluation. However, this compiled simulation method applies it to the entire circuit without considering the differences within the circuit. This results in a large amount of redundant calculations introduced into the compilation process, reducing simulation efficiency.

[0069] It fails to fully utilize the structural characteristics of the circuit to guide the scope of application of compilation simulation. Specifically, the logical characteristics of different regions in the circuit vary greatly, and their sensitivity to compilation optimization is also different. Applying compilation simulation to the entire circuit will ignore this difference and cause unnecessary complexity. In particular, for areas with large fan-out or shallow logic depth, the effect of compilation optimization is not obvious, but may reduce simulation performance due to the introduction of additional compilation overhead. In addition, existing methods also lack a means to perform compilation fusion in local areas based on dominance relationships. Although large-grained compilation integration speeds up simulation, it also brings difficulties to test response analysis.

[0070] The development process of this application has experienced the following technical difficulties: how to design measurement indicators based on the structural characteristics of the Dominator tree to automatically identify areas suitable for compilation simulation. It is difficult to handle large-scale circuits relying solely on manual experience, and a quantitative measurement mechanism needs to be established; within the selected compilation simulation area, how to further refine the compilation group to achieve better compilation acceleration. Simply compiling all nodes in the area into one group will limit parallelism, and a more fine-grained compilation fusion strategy is required; how to minimize the complexity of test response analysis while performing compilation optimization. Global compilation integration will blur the boundaries of each sub-area, causing inconvenience to subsequent fault effect analysis, and a balance must be struck between the two.

[0071] In mixed fault simulation, event-driven simulation triggers logic calculations based on changes in circuit states to avoid invalid simulations. However, this method requires memory access for each event. Existing event-driven simulation methods usually use a single event queue to process events in order of timestamp or gate level. This approach does not consider the internal control structure of the circuit, resulting in event redundancy and frequent memory access, which affects simulation performance.

[0072] Based on this, this application proposes a hybrid fault simulation method guided by a dominator tree, called HyFAST. HyFAST achieves logical, efficient and accurate regional division of the circuit by constructing an optimized dominator tree. Based on this tree, the compiled simulation and event-driven simulation algorithms are further optimized to achieve efficient integration of compiled simulation and event-driven simulation. The complete HyFAST simulation process includes the following three parts:

[0073] Construction and optimization of dominator tree: HyFAST first constructs an optimized dominator tree containing circuit relations. Then, pseudo-root nodes are introduced and some dual-dominator nodes are split to optimize the dominator tree and increase the circuit information it contains.

[0074] Compilation and simulation based on the dominator tree: Under the guidance of the constructed dominator tree, the circuit area suitable for compilation and simulation is identified and compiled, and the faults are injected into the integrated node during the fault simulation process.

[0075] Event-driven simulation based on dominator tree: After completing the compilation simulation, the dominator tree is subjected to event-driven simulation. In order to minimize redundant events and improve the reusability of events, this scheme proposes an optimized event-driven algorithm using the hierarchical structure of the dominator tree.

[0076] 1) Construction and optimization of dominance tree

[0077] In order to fully capture the circuit information and utilize the dominance relationship for circuit partitioning, an enhanced dominance tree is constructed from the circuit diagram. Figure 2 As shown in the algorithm (Enhanced Dominator Tree Construction Algorithm), the basic algorithm for constructing a dominator tree from a flow graph is used. The algorithm adopts depth-first search and an efficient method to calculate the functions defined on the paths in the tree, thereby achieving lower time complexity.

[0078] In the enhanced Dominator tree construction algorithm, the input is CircuitGraph G = (V, E), and the output is Dominator tree T; the first line indicates initializing an empty tree T; the second line indicates creating a pseudo root node p; the third line indicates connecting p to all POs and PPOs; the fourth line indicates performing a graph-tree conversion; lines 5-12 indicate that for each vertex v, if v is dominated by multiple (two) dominating nodes, and the dominating paths (to PO, PPO) are unintersecting, then v is split into multiple (two) vertices v', and for each vertex v', v' is inserted into T as a child of its respective Dominator; otherwise, v is directly inserted into T as a child of p.

[0079] In line 4 of the algorithm, our proposal expresses it as a function GraphToTree() that requires a flow graph with a starting vertex as input and generates a basic dominator tree as output.

[0080] However, this basic dominator tree is not sufficient in circuit partitioning and has several limitations. First, integrating all trees with isolated nodes is complex, making it difficult to aggregate test results and support efficient event propagation. In addition, during the construction of the baseline dominator tree, some nodes may not have a single dominator point, but are affected by multiple dominators at the same time. For such nodes, the traditional dominator tree may not accurately reflect the logical structure and signal propagation path of the circuit. In order to solve the above problems, this application proposes two enhancements:

[0081] Add pseudo-root node (see line 2 of the algorithm): Before building the tree, in order to simplify the definition of the dominance relationship, introduce a pseudo-parent node (refer to Figure 3PR node in the dominator tree), which connects isolated nodes and subgraphs to the pseudo root node. This node is linked to all primary output (PO) and pseudo primary output (PPO) points and serves as the root node of the dominator tree, representing the final output port of the circuit. Figure 3 An example is shown in the left subgraph of . Then, the circuit graph G with the pseudo-root node added is used as the input of the function GraphToTree() to form a complete dominator tree.

[0082] This approach makes it possible to aggregate data from circuit output nodes (PO and PPO) at a single point by consolidating all output points under one entity using a pseudo-root node, simplifying subsequent processing and calculations. It also ensures that each circuit generates a unique dominator tree with the pseudo-root node as the end point for fault propagation.

[0083] Node splitting strategy (line 5-13 of the algorithm): After building the tree T, node splitting is performed based on the dual dominance attribute (refer to Figure 3 ), more finely reflects some special dominance relationships in the circuit diagram, and enriches the tree's representation of circuit information. Nodes that do not have a single dominance point but are affected by multiple dominance points are candidates for splitting. For a node with two dominance points, if all its dominance paths (to PO or PPO) are independent, a node splitting strategy can be used to split it into two independent nodes and add them to the dominance tree. Figure 3 In the example shown in the right sub-figure, a node splitting mechanism is shown. Here, a node with dual dominance attributes (and independent paths to PO and PPO) is split into two independent nodes (G12'), and the transformation from node G12 to node G12' shows the splitting operation and its impact on the tree structure.

[0084] Node segmentation enhances the accuracy of the dominator tree, providing a more accurate representation of complex logic relationships and signal propagation paths in the circuit. It also increases the scope of the tree, improves the reusability of event traversal based on the tree structure, and optimizes the fault propagation path, thereby improving simulation efficiency.

[0085] 2) Compilation simulation based on dominator tree

[0086] Based on the constructed dominator tree, this application proposes a circuit partitioning method for selecting circuit areas suitable for compilation simulation. This solution first compiles and merges the selected circuit areas to simplify the circuit structure, and then injects faults into the compiled results.

[0087] 2.1) Compilation Fusion Based on Circuit Partitioning

[0088] This application uses the dominance relationship provided by the dominance tree to help identify key areas suitable for compilation. After the circuit diagram is divided, compilation fusion is performed on the basis of the subtree. The main challenge of compilation simulation comes from its static nature. As the complexity of circuit design increases, it often leads to redundant calculations of inactive parts, resulting in a large number of redundant calculations. In order to effectively solve this problem, this application constructs two indicators based on the dominance tree as a guide to help identify circuit areas with low fan-in and deep logic levels, such as fan-out overlap. Next, this application will introduce the definitions of these two indicators and the method for determining the compilation fusion area based on these two indicators and the compilation fusion strategy.

[0089] Circuit Region Selection Metrics: To effectively identify circuit regions suitable for compilation based on dominator trees, this application constructs two metrics to balance the logic depth and fan-in number of the selected regions.

[0090] Adjacency in dominator tree and circuit graph: This metric is used to measure whether the adjacency of circuit nodes in the tree and the graph is consistent. Specifically, when the circuit graph is converted to a dominator tree, some nodes are not adjacent in the circuit graph but are adjacent in the tree. Therefore, in this case there are two types of nodes: nodes that are not adjacent in the graph but are adjacent in the tree, and nodes that are adjacent in both the graph and the tree. Figure 4 As shown, the left side illustrates the situation where G1 and G4 are adjacent in the tree but not in the graph due to fan-out re-merger, while the right side shows the situation where the nodes are adjacent in both the tree and the graph.

[0091] Fan-in count: The number of inputs connected to a node or region after compilation fusion, which significantly affects the performance of compiled simulation. Note that this solution predefines a fan-in count threshold. If the actual fan-in count is equal to the threshold, it is classified as "medium fan-in count"; if it is lower than the threshold, it is considered "low fan-in count"; if it exceeds the threshold, it is marked as "high fan-in count".

[0092] Circuit Region Selection Method: Based on the above indicators, this scheme designs a search strategy to systematically identify regions suitable for compilation fusion and generate the final compilation results. Figure 5 Examples are shown. This scheme traverses the nodes layer by layer from the bottom of the tree, in order. First, based on the "Adjacency in Dominator Tree and Circuit Graph" metric, this scheme prioritizes the fusion of all nodes that are adjacent in the tree but not in the graph. All nodes on these paths are compiled and fused. Then, the fusion strategy is determined based on the fan-in count of the region:

[0093] Medium fan-in count: Directly compile fusion and generate instruction sequences.

[0094] Low fan-in count: Fusion is performed but instruction sequences are not generated immediately, allowing for possible further fusion in the future.

[0095] High fan-in count: No fusion is performed, and these nodes are treated independently.

[0096] like Figure 5 As shown in subgraphs (1) and (2) of , node G12 is adjacent in the dominator tree but not in the circuit diagram. The dominator path of G12 passes through G10 and G11 and finally reaches G7, thus demarcating the region. Given that the fan-in count of the region is equal to the predefined threshold, these nodes are fused to form a composite node, denoted as COM1.

[0097] Next, we traverse the remaining nodes in the graph that are adjacent in both the graph and the tree, perform region fusion on all nodes on the path from this node to its parent node, and then determine the fusion strategy based on the fan-in count of the region, which is the same as the previous case.

[0098] like Figure 5 As shown in subgraphs (3) and (4) of , at this point, all nodes that are adjacent in the dominator tree but not in the circuit diagram have been processed. Next, by traversing the nodes that are adjacent in both the dominator tree and the circuit diagram layer by layer, G13 is processed first, and its dominator path reaches G9. Since the fan-in count of this area is lower than the threshold, it is temporarily fused. Then traverse to G5, G6, and COM1, and evaluate the fan-in counts of their areas after merging with the parent node. Since their fan-in counts all exceed the threshold, they are not fused.

[0099] When traversing to G8, its dominant path extends to G4, and since the fan-in count of this region is below the threshold, it is fused. Then the region containing G9 and G13 is evaluated, and even after fusing G4, G8, G9, and G13, the fan-in count is still below the threshold, so the fusion result is retained.

[0100] Continue to traverse G2 and G3. Analysis shows that the fan-in count of the region after they are merged with the parent node exceeds the threshold, so it is decided not to merge. Finally, evaluate the previously formed region containing G4, G8, G9, and G13. Fusing this region with G1 will exceed the fan-in count threshold, so the fusion with G1 is canceled and the original G4, G8, G9, and G13 are retained to form the COM2 node. After all nodes are traversed in order, the fusion process ends. Through these operations, the original circuit is divided into multiple compiled fusion regions, laying the foundation for subsequent compilation simulation.

[0101] Compile fusion strategy: Based on the nodes selected by the circuit region selection method, compile fusion is performed to maintain circuit performance and improve simulation efficiency. The logical functions of the selected nodes are merged to form a unified representation and compiled into an instruction function sequence. Accordingly, the dominator tree is updated to reflect the fusion to ensure accurate modeling of the current circuit node status.

[0102] 2.2) Compilation Fault Injection

[0103] In order to simulate the logic gate behavior of the fused circuit part when a fault occurs, it is necessary to inject the fault into the fused circuit area. Since the circuit has been fused and compiled, this solution directly injects the fault into the compiled instruction function sequence, almost without changing the original instruction function sequence, thereby accelerating fault simulation and further reducing the memory access caused by fault injection. Figure 6 shown.

[0104] Compilation fault injection strategies include:

[0105] Fault model definition: Define the fault type and injection location (e.g., stuck-at fault) based on the fault model of the circuit;

[0106] Fault node selection: locate the specific location of the fault injection node (logic gate) within the compiled fusion area and lock the corresponding instruction address;

[0107] Fault injection: Use the CALL instruction to directly access the fault injection instruction, inject a fault at the instruction address corresponding to the selected logic gate, and simulate fault propagation.

[0108] like Figure 6 As shown, during the fault injection process at gate G10 in the COM1 node, the compiled instruction corresponding to G10 is first identified, replaced with a CALL instruction, the original instruction is relocated to the beginning of the fault injection instruction sequence, the SA fault injection instruction is continued, and then the normal instruction flow is restored using a JUMP instruction.

[0109] The use of dominator trees provides a flexible method to select the circuit parts that should be fused and compiled, allowing the algorithm to adapt to different circuit characteristics. By using the dominator tree and two indicators defined in this scheme, the area suitable for compilation fusion can be accurately located.

[0110] 3) Event-driven simulation based on dominator tree

[0111] After completing the compilation simulation part, this scheme proposes a hierarchical event-driven simulation method based on the dominator tree to reduce redundant event propagation. The performance bottleneck of event-driven simulation mainly comes from the memory access overhead caused by event scheduling and calculation. In addition, the scattered memory access caused by the relatively random triggering order of previous events increases the memory overhead.

[0112] In order to reduce redundant event propagation and optimize memory access while ensuring simulation accuracy, this scheme develops a forward-backward simulation model based on the hierarchical structure of the dominator tree. The forward propagation simulation uses the convergence-divergence relationship between child nodes and parent nodes in the dominator tree to implement hierarchical event processing. At the same time, a corresponding backward mapping algorithm is proposed to accurately map the simulation results back to each fault point and obtain the final correct simulation results. The forward propagation simulation and backward mapping algorithm of the event hierarchical queue are shown in Figure 2. Figure 7 shown.

[0113] 3.1) Forward propagation simulation

[0114] Forward simulation is designed to simulate the propagation of faults in a circuit, starting from the fault injection point and propagating along the circuit's logic path to the output. In the context of a tree-based hierarchy, the process starts from the bottom node of the tree and moves upward to the output point of the circuit.

[0115] The structure of the dominator tree is used to establish a clear path for fault propagation, thereby improving the efficiency of the process. Once a fault is injected into a logic gate, its impact propagates along the path of the dominator tree to other logic gates or final output points that may be affected. The unique path from the root node to the leaf node in the dominator tree ensures the determinism of fault propagation. Based on this, the process of forward propagation simulation is as follows:

[0116] Initialization: prepare an array to record the forward propagation information of each logic gate. The length of the array matches the number of nodes in the dominator tree. The array will be used for subsequent simulation state tracking and to build an event queue. When events occur, they enter the queue according to the hierarchy of the nodes in the dominator tree.

[0117] Fault injection: According to the defined fault model, the fault is injected into the node of the dominator tree (usually a logic gate or region in the circuit), flipping the logic value at the fault location and triggering an event. The event enters the queue, such as Figure 7 As shown on the left, a fault is injected into all nodes in the tree, causing all events to enter the queue according to the tree hierarchy;

[0118] Hierarchical queue event processing: When processing events, retrieve the corresponding events from the queue in order. For each bit affected by the fault (the bit where the fault value is different from the correct logical value), flip the correct logical value of the node and trigger the event. Propagate the fault impact to the parent node of the current node. In this process, merge each fault impact propagated from the current node to the parent node into the erroneous logical state of the parent node. Update the forward propagation information of the current node by performing an XOR operation on the correct logical value of the parent node and the fault value propagated from the current node to the parent node. For newly triggered events, enter them into the queue according to the circuit hierarchy. Note that if there are duplicate events at a single node in the queue, they will be merged. After processing this event, retrieve the next event from the queue in order. Repeat the above fault impact propagation process until the queue is empty and the simulation terminates. Figure 7 As shown on the left, events corresponding to G5 are processed first. During the process of fault impact propagation from G5 to G2, the forward propagation information of G5 is updated. Events of G6, COM1, etc. are processed from the queue in order.

[0119] In the forward propagation simulation, events are queued according to the corresponding levels and processed sequentially from the lower level to the upper level. Through this process, the scheme uses the convergence-divergence relationship between child nodes and parent nodes in the dominator tree to achieve hierarchical event processing. This strategy ensures that all events from child nodes are processed and propagated to parent nodes before processing parent node events. It ensures the orderly propagation and convergence of fault effects and reduces redundant event triggering and calculation. By establishing a hierarchical event queue to store different events at each level, during the event processing, the scheme processes events sequentially according to the level. This produces a more organized and compact trigger gate memory access pattern, reducing cache misses and further reducing memory access overhead.

[0120] 3.2) Backward Mapping Method

[0121] Backward mapping aims to confirm whether the fault can be observed at the output of the circuit after the forward propagation simulation is completed. This scheme uses the hierarchical structure of the dominator tree and the reversible computation of fault impact propagation to map the detected bits from the output point back to the injection point.

[0122] The core principle of backward mapping is to start from the end point of fault propagation and check whether the fault affects the observable output of the circuit. The current test vector determines whether the fault can be detected. The specific implementation process is as follows:

[0123] End point information collection: When each fault impact reaches the pseudo-root node of the tree and propagates to the PO or PPO, all corresponding fault impact detection information, i.e., the backward mapping information of the pseudo-root node, is collected;

[0124] Backward mapping information update: In the backward mapping method, the nodes are queued in the reverse order of the event triggering in the forward propagation simulation, starting from the level below the pseudo-root node, that is, the PO and PPO levels, and performing a hierarchical backward traversal. This propagation method ensures that when processing the backward mapping information of a child node, the backward mapping information of its parent node has been updated. The backward propagation information of a node is equal to the bitwise AND operation of its own recorded forward propagation information and the backward mapping information of its parent node. Figure 7 As shown on the right, the backward mapping information of node G2 in the figure is calculated by the Boolean expression "Backward(G2)=Forward(G2)AND Backward(G1)". The update order follows the order indicated by the arrows in the figure, starting from G1, then COM2, G3, etc.;

[0125] Result analysis: If there is a bit with a value of 1 in the backward mapping information and the fault can be propagated to the output port of the corresponding node, the fault is detected and the simulation results of all faults are obtained.

[0126] The scheme was compared with commercial tools. The data is divided into two parts. For circuits with less than 100k gates: In smaller circuits, HyFAST of the scheme achieved an average performance improvement of 1.523 times compared with the commercial tool TMAX; compared with Tessent, the performance improvement of HyFAST was an average of 10.395 times, etc. For circuits with more than 100k gates: HyFAST achieved a speedup from a minimum of 1.88 times to a maximum of 6.14 times on TMAX, with an average speedup of 3.078 times; compared with Tessent, the speedup was more significant, ranging from 5.76 times to 21.90 times, and an average speedup of 11.39 times on circuits with more than 100k gates, etc.

[0127] It can be observed that HyFAST achieves commendable results in various circuit complexities (from hundreds of thousands to nearly 10 million gates). In addition, the approach of this scheme shows significant superior enhancement in larger circuits compared to smaller circuits. First, the larger circuit depth and wider dominator tree in larger circuits effectively reduce the occurrence of redundant events, thereby optimizing the overall simulation efficiency. Second, large-scale circuits are characterized by a large number of logic gates and events, which requires a large amount of data storage, and thus the probability of encountering cache misses during memory accesses increases significantly. By implementing strategic optimizations such as event sorting and region-based compile fusion, the approach of this scheme significantly optimizes compilation and event-driven simulation. This refinement leads to a reduction in the number of circuit events and reduces the associated memory access overhead.

[0128] Evaluation of fan-in count thresholds. This solution tests various fan-in count thresholds for all circuits. Figure 8An analysis of the simulation performance of HyFAST for different fanin count threshold parameters is presented, taking openE902 and openC910 circuits as examples. Curve ① plots the fault simulation time, curve ② plots the cumulative count of event-triggered scheduling of compute nodes, and curve ③ plots the cumulative number of bit-computation operations. The data show that with increasing fan-in count threshold, the initial decrease in fault simulation time reaches a minimum before rising again, identifying an optimal threshold range. Correspondingly, an increase in the fan-in count threshold is associated with fewer event triggers and a surge in bit operations. This pattern highlights the need to calibrate the fan-in count threshold, which coordinates the event trigger frequency with the amount of bit operations to optimize simulation results.

[0129] HyFAST first builds an optimized dominator tree from the circuit diagram, using dominator relationships to guide circuit partitioning and determine areas suitable for compiled simulation. In addition, it optimizes the event propagation process in the event-driven simulation paradigm by leveraging the hierarchical structure of the Dominator tree. This optimization ensures maximum event reusability and reduces the total number of events to be processed. Experimental results on a variety of standard benchmark circuits demonstrate the effectiveness of HyFAST, with a maximum speedup of 21 times and an average speedup of more than 3 times compared to commercial tools. The acceleration effect is particularly significant for large circuits with more than 100k gates.

[0130] It should be noted that this method is mainly aimed at combinational circuits and full scan circuits. This application proposes the following important contributions:

[0131] 1) A fast hybrid fault simulation scheme (called HyFAST) combining compiled simulation and event-driven simulation is proposed. By converting the circuit diagram into an optimized dominator tree, this scheme can better capture and utilize the dominator relationship in the circuit for circuit partitioning.

[0132] 2) To identify circuit regions suitable for compilation simulation, this scheme analyzes the relationship between circuit structural features that are conducive to compilation simulation and the constructed Dominator tree. HyFAST integrates a metric-based circuit selection method that combines the characteristics of logic depth and low fan-in.

[0133] 3) HyFAST optimizes event propagation under the event-driven simulation paradigm, ensuring that the events of each parent node are fully utilized. This reduces the total number of events to be processed, thereby improving simulation efficiency.

[0134] 4) Extensive experimental results on a series of standard benchmark circuits show that Hfast achieves an average speedup of more than 3 times compared with commercial tools for circuits with more than 100k gates.

[0135] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0136] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0137] According to another aspect of the embodiments of the present application, a hybrid fault simulation device based on dominator tree guided circuit partitioning for implementing the above hybrid fault simulation method based on dominator tree guided circuit partitioning is also provided. Fig. 9 is a schematic diagram of an optional hybrid fault simulation device based on dominator tree guided circuit partitioning according to an embodiment of the present application, such as Fig. 9 As shown, the device may include:

[0138] A dominator tree construction unit 101 is used to construct an optimized dominator tree corresponding to the circuit relationship of the target chip by introducing a pseudo-root node and splitting a first node that is doubly dominated, wherein the first node is affected by multiple dominator nodes and is independent of all dominator paths formed by the respective dominator nodes;

[0139] A compiling and simulating unit 103, configured to identify a circuit region in the target chip suitable for compiling and simulating according to the logic depth and fan-in number of the candidate region in the optimized dominator tree, and to perform compiling and simulating to simplify the circuit structure of the target chip;

[0140] The driving simulation unit 105 is used to perform event-driven simulation based on the hierarchical structure of the optimized dominator tree by adopting a forward propagation scheme and a backward mapping scheme. The forward propagation scheme utilizes the convergence and divergence relationship between child nodes and parent nodes in the optimized dominator tree to realize hierarchical event processing, and the backward mapping scheme is used to map the detected fault back to the fault injection point starting from the termination node of the fault propagation.

[0141] It should be noted that the examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the contents disclosed in the above embodiments. It should be noted that the above modules, as part of the device, can be run in a corresponding hardware environment, can be implemented by software, and can also be implemented by hardware, wherein the hardware environment includes a network environment.

[0142] According to another aspect of an embodiment of the present application, a server or terminal for implementing the above-mentioned hybrid fault simulation method based on dominator tree-guided circuit partitioning is also provided.

[0143] Fig.10 is a structural block diagram of a terminal according to an embodiment of the present application, such as Fig.10 As shown, the terminal may include: one or more (only one is shown in the figure) processors 1101, a memory 1103, and a transmission device 1105, such as Fig.10 As shown, the terminal may also include an input and output device 1107 .

[0144] Among them, the memory 1103 can be used to store software programs and modules, such as the program instructions / modules corresponding to the hybrid fault simulation method and device based on the dominator tree guided circuit partitioning in the embodiment of the present application. The processor 1101 executes various functional applications and data processing by running the software programs and modules stored in the memory 1103, that is, realizing the above-mentioned hybrid fault simulation method based on the dominator tree guided circuit partitioning. The memory 1103 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1103 may further include a memory remotely arranged relative to the processor 1101, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0145] The above-mentioned transmission device 1105 is used to receive or send data via a network, and can also be used for data transmission between a processor and a memory. Specific examples of the above-mentioned network may include a wired network and a wireless network. In one example, the transmission device 1105 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices and routers via a network cable so as to communicate with the Internet or a local area network. In one example, the transmission device 1105 is a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet wirelessly.

[0146] Specifically, the memory 1103 is used to store application programs.

[0147] The processor 1101 may call the application stored in the memory 1103 through the transmission device 1105 to perform the following steps:

[0148] An optimized dominator tree corresponding to the circuit relationship of a target chip is constructed by introducing a pseudo-root node and splitting a first node that is doubly dominated, wherein the first node is affected by multiple dominator nodes and is independent of all dominator paths composed of the respective dominator nodes; circuit regions suitable for compilation simulation in the target chip are identified for compilation simulation according to the logic depth and fan-in number of candidate regions in the optimized dominator tree, so as to simplify the circuit structure of the target chip; event-driven simulation is performed by adopting a forward propagation scheme and a backward mapping scheme based on the hierarchical structure of the optimized dominator tree, wherein the forward propagation scheme utilizes the convergence-divergence relationship between child nodes and parent nodes in the optimized dominator tree to realize hierarchical event processing, and the backward mapping scheme is used to map the detected fault back to the fault injection point starting from the termination node of the fault propagation.

[0149] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment will not be described in detail here.

[0150] It can be understood by those skilled in the art that Fig.10 The structure shown is for illustration only, and the terminal may be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile Internet device (Mobile Internet Devices, MID), a PAD, or other terminal devices. Fig.10 It does not limit the structure of the above electronic device. For example, the terminal may also include Fig.10 More or fewer components (such as network interfaces, display devices, etc.) shown in, or having Fig.10 Different configurations are shown.

[0151] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0152] The embodiment of the present application further provides a storage medium. Optionally, in this embodiment, the storage medium can be used to execute the program code of the hybrid fault simulation method based on dominator tree guided circuit partitioning.

[0153] Optionally, in this embodiment, the storage medium may be located on at least one network device among a plurality of network devices in the network shown in the above embodiment.

[0154] Optionally, in this embodiment, the storage medium is configured to store program codes for executing the following steps:

[0155] An optimized dominator tree corresponding to the circuit relationship of a target chip is constructed by introducing a pseudo-root node and splitting a first node that is doubly dominated, wherein the first node is affected by multiple dominator nodes and is independent of all dominator paths composed of the respective dominator nodes; circuit regions suitable for compilation simulation in the target chip are identified for compilation simulation according to the logic depth and fan-in number of candidate regions in the optimized dominator tree, so as to simplify the circuit structure of the target chip; event-driven simulation is performed by adopting a forward propagation scheme and a backward mapping scheme based on the hierarchical structure of the optimized dominator tree, wherein the forward propagation scheme utilizes the convergence-divergence relationship between child nodes and parent nodes in the optimized dominator tree to realize hierarchical event processing, and the backward mapping scheme is used to map the detected fault back to the fault injection point starting from the termination node of the fault propagation.

[0156] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment will not be described in detail here.

[0157] Optionally, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store program codes.

[0158] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0159] If the integrated units in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in the above computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling one or more computer devices (which may be personal computers, servers, or network devices, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.

[0160] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0161] In the several embodiments provided in the present application, it should be understood that the disclosed client can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0162] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0163] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0164] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A hybrid fault simulation method based on dominator tree guided circuit partitioning, characterized in that: include: An optimized dominator tree corresponding to the circuit relationship of the target chip is constructed by introducing a pseudo-root node and splitting a first node that is doubly dominated, wherein the first node is affected by multiple dominator nodes and is independent of all dominator paths formed by the respective dominator nodes; According to the logic depth and fan-in number of the candidate area in the optimized dominator tree, identifying the circuit area in the target chip suitable for compilation simulation to perform compilation simulation, so as to simplify the circuit structure of the target chip; Based on the hierarchical structure of the optimized dominator tree, a forward propagation scheme and a backward mapping scheme are used to perform event-driven simulation, wherein the forward propagation scheme utilizes the convergence-divergence relationship between child nodes and parent nodes in the optimized dominator tree to realize hierarchical event processing, and the backward mapping scheme is used to map the detected fault back to the fault injection point starting from the termination node of the fault propagation.

2. The method according to claim 1, characterized in that By introducing pseudo-root nodes and splitting dual-dominant nodes, an optimized dominator tree corresponding to the circuit relationship of the target chip is constructed, including: Connecting isolated nodes and subgraphs in the original circuit flow graph of the target chip to a pseudo-root node to obtain a target circuit flow graph; Converting the target circuit flow graph into an original dominator tree according to the circuit relationship; The dual-dominance nodes in the original dominance tree are node-segmented based on dual-dominance attributes to obtain the optimized dominance tree: a first node that is affected by multiple dominance nodes and whose all dominance paths are independent is determined in the original dominance tree, the first node is segmented into multiple second nodes, and each of the second nodes is connected to one of the dominance paths to replace the first node, to obtain the optimized dominance tree, wherein the second nodes connected by any two of the dominance paths are different.

3. The method according to claim 2, characterized in that According to the logic depth and fan-in number of the candidate area in the optimized dominator tree, a circuit area suitable for compilation simulation in the target chip is identified for compilation simulation, including: Determine the logic depth and fan-in quantity of a candidate region in the optimized dominator tree, wherein the candidate region is a region to be compiled and fused; Determine the fusion priority of the candidate region according to the adjacency, and compile and fuse the candidate region using a fusion strategy according to the fusion priority; The fault to be tested is injected into the instruction function sequence obtained by compilation and fusion to perform fault simulation.

4. The method according to claim 3, characterized in that Determining the logic depth and fan-in quantity of the candidate region in the optimized dominator tree includes: Starting from the bottom layer of the optimized dominator tree, traversing the nodes of each layer in a preset order; Determine the adjacency between the traversed third node and the parent node of the third node; Determine a region consisting of a parent node of the third node and each child node of the parent node as the candidate region; The fan-in count of the candidate region is obtained, wherein the fan-in count is the number of inputs connected to the node or region after compilation and fusion.

5. The method according to claim 3, characterized in that: Determining the fusion priority of the candidate region according to the adjacency, and compiling and fusing the candidate region using a fusion strategy according to the fusion priority, including: When the adjacency indicates that the third node in the candidate region is adjacent to the parent node of the third node in the optimized dominator tree but not adjacent to the target circuit flow graph, compile and fuse the candidate region using a fusion strategy according to a first priority; When the adjacency indicates that the third node in the candidate region is adjacent to the parent node of the third node in the optimized dominator tree and in the target circuit flow graph, the candidate region is compiled and fused using a fusion strategy according to a second priority, wherein the second priority is lower than the first priority.

6. The method according to claim 3, characterized in that The candidate regions are compiled and merged using a fusion strategy, including: When the fan-in count of the candidate region is less than a first threshold, the candidate region is allowed to be compiled and merged, but a corresponding instruction function sequence is not generated immediately; When the fan-in count of the candidate region is greater than a second threshold, not compiling and fusing the candidate region; When the fan-in count of the candidate region is greater than or equal to the first threshold and less than or equal to the second threshold, the candidate region is directly compiled and merged into a composite node, and a corresponding instruction function sequence is generated.

7. The method according to any one of claims 1 to 6, characterized in that The event-driven simulation is performed by adopting a forward propagation scheme and a backward mapping scheme based on the hierarchical structure of the optimized dominator tree, including: Determine the fault transmission path where the fault injection node and the forward propagation node of the fault injection node are located based on the hierarchical structure of the optimized dominator tree, update the forward propagation information of the nodes on the fault transmission path starting from the fault injection node, and store the newly triggered event in a hierarchical event queue according to the hierarchical structure of the optimized dominator tree, and in the event processing process, process the events in the hierarchical event queue in sequence from the lower layer to the upper layer according to the hierarchical structure, wherein the hierarchical event queue is used to store different events of each layer; After the forward propagation simulation is completed, starting from the termination node of the fault propagation, the detected fault is mapped back to the fault injection point by utilizing the hierarchical structure of the optimized dominator tree and the reversible computation of the fault impact propagation.

8. A hybrid fault simulation device based on dominator tree guided circuit partitioning, characterized in that: include: a dominator tree construction unit, configured to construct an optimized dominator tree corresponding to the circuit relationship of the target chip by introducing a pseudo-root node and splitting a first node that is doubly dominated, wherein the first node is affected by multiple dominator nodes and is independent of all dominator paths formed by the respective dominator nodes; A compiling and simulating unit, configured to identify a circuit region in the target chip suitable for compiling and simulating according to the logic depth and fan-in number of the candidate region in the optimized dominator tree, and to perform compiling and simulating so as to simplify the circuit structure of the target chip; A driving simulation unit is used to perform event-driven simulation based on the hierarchical structure of the optimized dominator tree by adopting a forward propagation scheme and a backward mapping scheme, wherein the forward propagation scheme utilizes the convergence-divergence relationship between child nodes and parent nodes in the optimized dominator tree to realize hierarchical event processing, and the backward mapping scheme is used to map the detected fault back to the fault injection point starting from the termination node of the fault propagation.

9. A computer-readable storage medium, characterized in that: The storage medium includes a stored program, wherein the program executes the method described in any one of claims 1 to 7 when executed.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: The processor executes the method described in any one of claims 1 to 7 through the computer program.

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