General wiring performance prediction method based on few-sample learning

Abstract

The invention relates to a general wiring performance prediction method based on few sample learning, and belongs to the technical field of integrated circuit computer aided design. According to the method, general wiring performance prediction is converted into a meta learning scene, and a prediction method based on Few-Shot Learning (FSL) is provided. The method can flexibly adapt to a new prediction task only by providing features of a query chip and a tag pair example set, and extra training is not needed. In order to solve the problem of data imbalance generally existing in the field of electronic design automation, the invention further introduces a meta-learning strategy based on importance sampling, and the meta-learning strategy is used for optimizing the training process of the model. In order to train the proposed method, an FSL data set based on a CircuitNet data set and an ISPD2015 data set is constructed.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit computer-aided design, and in particular relates to a general routability prediction method based on few-sample learning. Background Art

[0002] The continuous reduction of VLSI (Very Large Scale Integration) design feature size and the increasing complexity of on-chip connectivity have challenged the scalability of Electronic Design Automation (EDA) technology. Routability is one of the most challenging issues in the EDA process, and the core goal is to use data from the layout stage to evaluate the difficulty of chip design routing. Typical metrics include routing congestion and the distribution of Design Rule Check (DRC) violations. Routing has been proven to be an NP-hard problem, which leads to a long feedback cycle in the design process. It is particularly critical to quickly and accurately predict routability in the early design stage, which helps improve the efficiency of feedback and accelerate the convergence of the design process. Predicting results in the early design stage through machine learning (ML) to promote optimization between design steps has become a popular method in EDA, providing faster convergence and reducing pessimism.

[0003] The key challenges of routability prediction through ML include missing data sets, data imbalance, and domain offset problems. This is a major obstacle to the use of ML for routability prediction. Different application scenarios pose diverse design goals for chips, which requires customized adjustments to EDA tools and continuous updates to routability prediction tasks. To meet these challenges, chip design engineers need to train models from scratch or fine-tune existing models. However, the training of neural networks requires not only machine learning knowledge, but also computing resources, labeled data, and human labor. This is an almost insurmountable obstacle for engineers who lack these resources, which in turn affects the efficiency of chip design.

[0004] FSL aims to quickly learn and adapt to new tasks through a small amount of data annotation, thereby effectively alleviating the problem of data scarcity. In chip design, the same register transfer level (RTL) design is often reused and optimized through EDA processes. Summary of the invention

[0005] The purpose of the present invention is to provide a universal routability prediction method based on few-shot learning, which can flexibly handle different routability metrics, chip types, design scales, manufacturing technologies and unknown tasks, and realize universal routability prediction.

[0006] To achieve the above objectives, the technical solution of the present invention is: a universal routability prediction method based on few-sample learning, which converts the universal routability prediction into a meta-learning scenario, proposes a prediction method based on few-sample learning FSL, and realizes the query chip routability prediction.

[0007] In one embodiment of the present invention, the method includes:

[0008] The task of routability prediction of a chip layout divided into arbitrary W×H grids Defined as Where X represents the chip characteristics used. The tasks include different routability metrics (e.g., congestion and DRC violations), technology nodes (e.g., 28nm and 14nm), chip types (e.g., CPU, GPU, and AI chips), and RTL designs (e.g., different scales and design goals).

[0009] Modeling the general routability prediction task as a meta-learning scenario and building a general few-shot learner By leveraging unseen chip designs, we can query X q Chip data with the same RTL design is called support set Adaptable to any routability prediction task Generate accurate routability prediction models Leveraging a meta-training dataset covering a variety of routability prediction tasks The routability prediction model is trained through meta-learning, so that the routability prediction model can master general knowledge after going through multiple FSL processes.

[0010] In order to fully utilize the spatial correlation information between chip features and labels, the general routability prediction task is modeled as a dense prediction problem. Use 4 features that are widely used in routability prediction tasks;

[0011] For the routability prediction task t of chip design, the routability prediction model is used to query A support set consisting of chip features and their labels for the same RTL design As input; in the support set, each chip feature and its label are cascaded in the channel dimension, and the cross block promotes the information interaction between the support set and the query, thereby achieving routability results accurate predictions.

[0012] In one embodiment of the present invention, the routability prediction model is trained by meta-learning, so that the routability prediction model can master general knowledge during multiple FSL processes, and an importance sampling technique is introduced into the meta-learning to optimize the loss of the model on different tasks. The goal is to enable the model to adaptively adjust the loss L of different tasks during the training process. t Dynamic changes in task sampling Each task retains the most recent 10 historical loss values ​​and updates them dynamically during the training process.

[0013] In one embodiment of the present invention, before training begins, a batch of tasks t is selected by random sampling until 10 samples are collected for each task, and then the meta-learning strategy based on importance sampling is started; in the task sampling stage, in order to introduce randomness and prevent the model from forgetting past knowledge, the probability p of task sampling is calculated. t When adding a constant γ = 0.01, the meta-training data set D train The number of tasks in is n; based on p t Sample a task t of batch B B ; From each task t b∈B Medium sampling query and support set To prevent the model from overfitting on a specific task and improve data diversity, we perform and support set Perform data enhancement; finally, train on S t Under the condition of the support set, the accuracy of the model's routability prediction for a given query is improved, and the model can master general knowledge about FSL through meta-learning.

[0014] In one embodiment of the present invention, the four features widely used in routability prediction tasks are: rectangular uniform wire density RUDY, RUDY pins, macro area, and cell density.

[0015] In one embodiment of the present invention, for the routability prediction task t of chip design, the routability result is achieved. In the accurate prediction process of , UniverSeg is used as the backbone to adapt to support sets of different sizes.

[0016] In one embodiment of the present invention, the meta-training data set Built on CricuitNet and ISPD2015 datasets.

[0017] In one embodiment of the present invention, the data set corresponding to each chip design routability prediction task is constructed into three disjoint partitions d={ds ,d v ,d t}, containing 60%, 20%, and 20% of the data respectively; the model uses the support partition d in the training set s and test partition d t To train the model, use the validation split d v to perform model selection and hyperparameter tuning.

[0018] The present invention also provides a general routability prediction system based on few-sample learning, comprising a memory, a processor, and computer program instructions stored in the memory and executable by the processor. When the processor executes the computer program instructions, the method steps described above can be implemented.

[0019] The present invention also provides a computer-readable storage medium, on which computer program instructions that can be executed by a processor are stored. When the processor executes the computer program instructions, the method steps described above can be implemented.

[0020] Compared with the prior art, the present invention has the following beneficial effects: the method of the present invention transforms the general routability prediction into a meta-learning scenario, and proposes a prediction method based on Few-Shot Learning (FSL). The method only needs to provide the features of the query chip and a set of label pair examples, and can be flexibly adapted to new prediction tasks without additional training. In view of the data imbalance problem that is prevalent in the field of electronic design automation, the present invention also introduces a meta-learning strategy based on importance sampling to optimize the training process of the model. In order to train the proposed method, an FSL dataset based on CircuitNet and ISPD2015 datasets was constructed. The method of the present invention can flexibly handle different routability metrics, chip types, design scales, manufacturing technologies, and unknown tasks to achieve general routability prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a model architecture diagram of the method of the present invention. DETAILED DESCRIPTION

[0022] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings.

[0023] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0024] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0025] The present invention provides a general routability prediction method based on few-shot learning, converts the general routability prediction into a meta-learning scenario, proposes a prediction method based on few-shot learning FSL, and realizes the routability prediction of the query chip; the method comprises:

[0026] Modeling the general routability prediction task as a meta-learning scenario and building a general few-shot learner By leveraging unseen chip designs, we can query X q Chip data with the same RTL design is called support set Adaptable to any routability prediction task Generate accurate routability prediction models Leveraging a meta-training dataset covering a variety of routability prediction tasks The routability prediction model is trained through meta-learning, so that the routability prediction model can master general knowledge after going through multiple FSL processes.

[0027] In order to fully utilize the spatial correlation information between chip features and labels, the general routability prediction task is modeled as a dense prediction problem. Use 4 features that are widely used in routability prediction tasks;

[0028] For the routability prediction task t of chip design, the routability prediction model is used to query A support set consisting of chip features and their labels for the same RTL design As input; in the support set, each chip feature and its label are cascaded in the channel dimension, and the cross block promotes the information interaction between the support set and the query, thereby achieving routability results accurate predictions.

[0029] The following is the specific implementation process of the present invention.

[0030] This embodiment provides a general routability prediction method based on few-sample learning, which is specifically implemented as follows:

[0031] 1. Modeling the general routability prediction task as a meta-learning scenario

[0032] In the iterative process of chip design, the same RTL design is often reused and optimized through EDA processes for different design goals, thereby accumulating rich data annotations. By using and unseen chip design (query) X q Chip data with the same RTL design (support set) Flexible adaptation to any routability prediction task This generates accurate routability predictions Leveraging a meta-training dataset covering a variety of routability prediction tasks The model is trained through meta-learning so that it can master general knowledge after going through multiple FSL processes. Flexible and adaptable to different tasks to generate accurate predictions for query chips.

[0033] 2. Feature extraction

[0034] Given that routability annotations are usually presented in a 2D array format, in order to fully utilize the spatial correlation information between chip features and labels, the general routability prediction task is modeled as a dense prediction problem. Four features that are widely used in routability prediction tasks are used: Rectangular Uniform Wire Density (RUDY), RUDY pins, macro area, and cell density.

[0035] 3. Meta-learning strategy based on importance sampling

[0036] To cope with the inherent data imbalance problem, such as the interaction of multiple factors such as chip type, design scale, and technology node, we introduce importance sampling techniques for meta-learning to smoothly optimize the model's loss on different tasks. The goal is to enable the model to adaptively adjust the loss L of different tasks during training. t Dynamic changes in task sampling Specifically, each task retains the most recent 10 historical loss values ​​and is dynamically updated during the training process. Before training begins, a batch of tasks t is selected by random sampling until 10 samples are collected for each task, and then the meta-learning strategy based on importance sampling is started. In the task sampling stage, in order to introduce randomness and prevent the model from forgetting past knowledge, the probability p of task sampling is calculated. t When adding a constant γ = 0.01, n is the meta-training data set D train The number of tasks in. Based on p t Sample a task t of batch B BFrom each task t b∈B Medium sampling query and support set In order to prevent the model from overfitting on a specific task and improve the diversity of the data, we query and support set Perform data augmentation. Finally, the training is performed on t Under the condition of the support set, the accuracy of the model's routability prediction for a given query is improved, and the model can master general knowledge about FSL through meta-learning.

[0037] 4. Model and Reasoning

[0038] In order to fully integrate information across spatial scales, UniverSeg is used as the backbone, as shown in Figure 1 As shown in the figure. For the routability prediction task t of a specific chip design, the model is based on query A support set consisting of chip features and their labels for the same RTL design As input. In the support set, each chip feature and its label are cascaded in the channel dimension, and the cross block promotes the information interaction between the support set and the query, thereby achieving routability results The number of annotated chip data in the EDA field is variable and scarce. Using UniverSeg as the backbone can flexibly adapt to support sets of different sizes, thus better meeting the application needs of FSL in the EDA field.

[0039] 5.FSL Dataset

[0040] In order to train the model, a dataset for FSL is constructed based on CricuitNet and ISPD2015 datasets. This dataset covers different routability metrics, technology nodes, chip types, scales, etc. For different optimization goals, the same RTL design is often reused. Therefore, under specific technology nodes and metrics, the chip data annotation with the same RTL design is divided into a task. The datasets corresponding to these tasks contain chip designs for different optimization goals such as performance, power consumption and area. All feature and label sizes are adjusted to 256×256 pixels, and the labels are normalized to the range [0,1] through maximum and minimum. The dataset corresponding to each task constructs three non-overlapping partitions d={d s ,d v ,d t}, containing 60%, 20%, and 20% of the data respectively. The model uses the support partition d in the training set s and test partition d t To train the model, use the validation split d v to perform model selection and hyperparameter tuning.

[0041] The present invention also provides a general routability prediction system based on few-sample learning, comprising a memory, a processor, and computer program instructions stored in the memory and executable by the processor. When the processor executes the computer program instructions, the method steps described above can be implemented.

[0042] The present invention also provides a computer-readable storage medium, on which computer program instructions that can be executed by a processor are stored. When the processor executes the computer program instructions, the method steps described above can be implemented.

[0043] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0044] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0045] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0046] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0047] The above is only a preferred embodiment of the present invention, and does not limit the present invention in other forms. Any technician familiar with the profession may use the above disclosed technical content to change or modify it into an equivalent embodiment with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the technical solution of the present invention still belongs to the protection scope of the technical solution of the present invention.

Claims

1. A general routability prediction method based on few-shot learning, characterized in that: The general routability prediction is transformed into a meta-learning scenario, and a prediction method based on few-shot learning (FSL) is proposed to realize query chip routability prediction.

2. The general routability prediction method based on few-shot learning according to claim 1, characterized in that: The method comprises: The task of routability prediction of a chip layout divided into arbitrary W×H grids Defined as Where X represents the chip characteristics used; the tasks include different routability metrics, technology nodes, chip types, and RTL designs; Modeling the general routability prediction task as a meta-learning scenario and building a general few-shot learner By leveraging unseen chip designs, we can query X q Chip data with the same RTL design is called support set Adaptable to any routability prediction task Generate accurate routability prediction models Leveraging a meta-training dataset covering a variety of routability prediction tasks The routability prediction model is trained through meta-learning, so that the routability prediction model can master general knowledge after going through multiple FSL processes. In order to fully utilize the spatial correlation information between chip features and labels, the general routability prediction task is modeled as a dense prediction problem. Use 4 features that are widely used in routability prediction tasks; For the routability prediction task t of chip design, the routability prediction model is used to query A support set consisting of chip features and their labels for the same RTL design As input; in the support set, each chip feature and its label are cascaded in the channel dimension, and the cross block promotes the information interaction between the support set and the query, thereby achieving routability results accurate predictions.

3. The general routability prediction method based on few-sample learning according to claim 2, characterized in that: The routability prediction model is trained by meta-learning, so that the routability prediction model can master general knowledge during multiple FSL processes, and an importance sampling technique is introduced for meta-learning to optimize the loss of the model on different tasks. The goal is to enable the model to adaptively adjust the loss L of different tasks during the training process. t Dynamic changes in task sampling where p t μ and∑p t =1; Each task retains the most recent 10 historical loss values ​​and updates them dynamically during training.

4. The general routability prediction method based on few-shot learning according to claim 3, characterized in that: Before training begins, a batch of tasks t is selected by random sampling until 10 samples are collected for each task, and then the meta-learning strategy based on importance sampling is started; in the task sampling stage, in order to introduce randomness and prevent the model from forgetting past knowledge, the probability p of task sampling is calculated. t When adding a constant γ = 0.01, the meta-training data set D train The number of tasks in is n; based on p t Sample a task t of batch B B ; From each task t b∈B Medium sampling query and support set To prevent the model from overfitting on a specific task and improve data diversity, we perform and support set Perform data enhancement; finally, train on S t Under the condition of the support set, the accuracy of the model's routability prediction for a given query is improved, and the model can master general knowledge about FSL through meta-learning.

5. The general routability prediction method based on few-sample learning according to claim 2, characterized in that: The four features widely used in routability prediction tasks are: rectangular uniform wire density RUDY, RUDY pins, macro area and cell density.

6. The general routability prediction method based on few-sample learning according to claim 2, characterized in that: Targeting the routability prediction task of chip design, achieving routability results In the accurate prediction process of , UniverSeg is used as the backbone to adapt to support sets of different sizes.

7. The general routability prediction method based on few-sample learning according to claim 2, characterized in that: The meta-training dataset Built on CricuitNet and ISPD2015 datasets.

8. The general routability prediction method based on few-sample learning according to claim 7, characterized in that: The data set corresponding to the routability prediction task of each chip design constructs three disjoint partitions d = {d s ,d v ,d t }, containing 60%, 20%, and 20% of the data respectively; the model uses the support partition d in the training set s and test partition d t To train the model, use the validation split d v to perform model selection and hyperparameter tuning.

9. A general routability prediction system based on few-shot learning, characterized in that: The method comprises a memory, a processor and computer program instructions stored in the memory and executable by the processor. When the processor executes the computer program instructions, the method steps as claimed in any one of claims 1 to 8 can be implemented.

10. A computer-readable storage medium storing computer program instructions that can be executed by a processor, wherein when the processor executes the computer program instructions, the method steps according to any one of claims 1 to 8 can be implemented.

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