An epitaxial wafer and a method for preparing the same

Abstract

The present application provides an epitaxial wafer and a preparation method thereof. The preparation method includes: introducing first hydrogen and hydrogen chloride gas into the epitaxial reaction chamber to etch the inner wall of the epitaxial reaction chamber and the surface of the susceptor. The first hydrogen has a first flow rate of Q1 L / min; stop introducing the hydrogen chloride gas, perform the first cooling, keep the flow rate of the first hydrogen at the first flow rate Q1 L / min, and at the same time introduce gaseous trichlorosilane into the epitaxial reaction chamber to deposit an intrinsic silicon layer on the surface of the susceptor; stop introducing the gaseous trichlorosilane, adjust the flow rate of the first hydrogen to a second flow rate Q2 L / min, and perform the second cooling; place the substrate in the epitaxial reaction chamber, perform heating, and grow an epitaxial layer on the surface of the substrate; wherein, Q1 < Q2. This preparation method shortens the overall process time, and at the same time makes the front particles and silicon stacking conditions of the wafer reach an ideal state, ensuring the quality of the epitaxial wafer while improving the preparation efficiency.

Description

Technical Field

[0001] This application belongs to the technical field of silicon-on-insulator, and particularly relates to an epitaxial wafer and a preparation method thereof. Background Art

[0002] In the field of semiconductor device manufacturing, a layer of single-crystalline silicon is usually formed on a silicon substrate as an epitaxial layer, and the epitaxial layer can be ion-implanted and doped subsequently to form an implanted base region, an emitter region, etc. During the epitaxial growth of a heavily doped substrate, in order to solve the problem of self-doping effect in epitaxial processing, a series of steps are usually required before the epitaxial film growth process to improve the quality and stability of the material. One common operation is to grow an intrinsic silicon thin film with a film thickness meeting the requirements on the surface of the susceptor after the susceptor is cooled to the crystal growth temperature, and by controlling the temperature stability, the diffusion of impurities between the substrate and the epitaxial layer is eliminated or reduced, so as to improve the quality and uniformity of the doped layer and ensure the consistency of the structure and performance of the epitaxial film. However, the process of controlling the temperature will lead to a reduction in the efficiency of the wafer processing.

[0003] Therefore, in the prior art, there is a need for a process that can reduce the processing steps and improve the impact on the wafer processing efficiency while ensuring the quality and stability of the epitaxial layer. Summary of the Invention

[0004] The present invention provides an epitaxial wafer and a preparation method thereof, aiming to solve the problems of long preparation time and low efficiency in the epitaxial wafer preparation process in the existing semiconductor device manufacturing process.

[0005] On the one hand, an embodiment of the present application provides a method for preparing an epitaxial wafer, including the following steps:

[0006] Provide an epitaxial reaction chamber, the epitaxial reaction chamber includes a susceptor, introduce first hydrogen and hydrogen chloride gas into the epitaxial reaction chamber, etch the inner wall of the epitaxial reaction chamber and the surface of the susceptor, and the first hydrogen has a first flow rate Q1 L / min;

[0007] Stop introducing the hydrogen chloride gas, perform the first cooling, keep the flow rate of the first hydrogen at the first flow rate Q1 L / min, and at the same time introduce trichlorosilane gas into the epitaxial reaction chamber to deposit an intrinsic silicon layer on the surface of the susceptor;

[0008] Stop introducing the trichlorosilane gas, adjust the flow rate of the first hydrogen to a second flow rate Q2 L / min, and perform the second cooling;

[0009] Provide a substrate, place the substrate in the epitaxial reaction chamber, perform heating, and grow an epitaxial layer on the surface of the substrate;

[0010] Wherein, Q1 < Q2.

[0011] In some embodiments, the first flow rate Q1 L / min and the second flow rate Q2 L / min satisfy:

[0012] Q1:Q2 = 1:2 to 2.25.

[0013] In some embodiments, in the step of introducing the first hydrogen gas and hydrogen chloride gas into the epitaxial reaction chamber, the hydrogen chloride gas has a third flow rate Q3 L / min;

[0014] In the step of introducing trichlorosilane gas into the epitaxial reaction chamber, the trichlorosilane gas has a fourth flow rate Q4 L / min;

[0015] Satisfy: Q3:Q1 = 1:1 to 1:2.

[0016] In some embodiments, Q4:Q1 = 1:2 to 2:3.

[0017] In some embodiments, the first flow rate Q1 L / min, the second flow rate Q2 L / min, the third flow rate Q3 L / min, and the fourth flow rate Q4 L / min further satisfy at least one of the following characteristics:

[0018] a) 20 L / min ≤ Q1 ≤ 40 L / min;

[0019] b) 40 L / min ≤ Q2 ≤ 45 L / min;

[0020] c) 10 L / min ≤ Q3 ≤ 20 L / min;

[0021] d) 10 L / min ≤ Q4 ≤ 15 L / min.

[0022] In some embodiments, the temperature for etching the inner wall of the epitaxial reaction chamber and the surface of the pedestal is 1170 - 1190 °C.

[0023] In some embodiments, the end temperature of the first temperature reduction is 1130 - 1150 °C.

[0024] In some embodiments, the end temperature of the second temperature reduction is 800 - 850 °C.

[0025] In some embodiments, the etching time is t1 s, the time for the first temperature reduction is t2 s, and the time for the second temperature reduction is t3 s, satisfying:

[0026] t1:t2 = 2:1 to 5:1.

[0027] In some embodiments, the etching time satisfies: 15 s ≤ t1 ≤ 60 s.

[0028] In some embodiments, the time of the first temperature drop satisfies: 8s ≤ t2 ≤ 12s.

[0029] In some embodiments, the first temperature drop has a first rate of v1 °C / s;

[0030] The second temperature drop has a second rate of v2 °C / s;

[0031] Satisfying: v1 ≤ v2.

[0032] In some embodiments, the first rate satisfies: 5 °C / s ≤ v1 ≤ 10 °C / s.

[0033] In some embodiments, the second rate satisfies: 5 °C / s ≤ v2 ≤ 10 °C / s.

[0034] In some embodiments, before the step of etching the surface of the substrate by introducing first hydrogen and hydrogen chloride gas into the epitaxial reaction chamber, it further includes:

[0035] Introducing second hydrogen into the epitaxial reaction chamber and simultaneously heating the epitaxial reaction chamber. The second hydrogen has a fifth flow rate of Q5 L / min, satisfying: Q5 ≤ Q1.

[0036] In some embodiments, the fifth flow rate Q5 L / min satisfies: 20 L / min ≤ Q5 ≤ 40 L / min.

[0037] In some embodiments, the heating has a third rate of v3 °C / s, satisfying: 5 °C / s ≤ v3 ≤ 10 °C / s.

[0038] On the other hand, an embodiment of the present application further provides an epitaxial wafer, which is prepared by using the preparation method of the epitaxial wafer in any of the above embodiments.

[0039] In some embodiments, the epitaxial wafer includes a substrate layer and an epitaxial layer disposed on one side of the substrate layer; the thickness ratio of the intrinsic silicon layer to the epitaxial layer is 1:10 to 1:20.

[0040] In some embodiments, the thickness of the intrinsic silicon layer is 1 to 1.5 μm.

[0041] In some embodiments, the thickness of the epitaxial layer is 20 to 30 μm.

[0042] The present application provides a method for preparing an epitaxial wafer, which includes the following steps: providing an epitaxial reaction chamber, where the epitaxial reaction chamber includes a susceptor, introducing first hydrogen and hydrogen chloride gas into the epitaxial reaction chamber, etching the inner wall of the epitaxial reaction chamber and the surface of the susceptor, and the first hydrogen has a first flow rate Q1 L / min; ending the introduction of hydrogen chloride gas, performing a first temperature reduction, maintaining the flow rate of the first hydrogen at the first flow rate Q1 L / min, and simultaneously introducing gaseous trichlorosilane into the epitaxial reaction chamber to deposit an intrinsic silicon layer on the surface of the susceptor; ending the introduction of gaseous trichlorosilane, adjusting the flow rate of the first hydrogen to a second flow rate Q2 L / min, and performing a second temperature reduction; providing a substrate, placing the substrate in the epitaxial reaction chamber, heating up, and growing an epitaxial layer on the surface of the substrate; performing a third temperature reduction to complete the preparation of the epitaxial wafer; where Q1 < Q2. By combining the step of depositing the intrinsic silicon layer with the step of the first temperature reduction, the step of first adjusting the temperature and then depositing the intrinsic silicon layer in the original process is replaced, shortening the overall process time and improving the preparation efficiency; at the same time, by reducing the flow rate of the first hydrogen in the step of depositing the intrinsic silicon layer, the concentration of trichlorosilane in the epitaxial reaction chamber is increased, making the front surface particles and silicon stacking conditions of the wafer reach an ideal state, ensuring the quality of the epitaxial wafer while improving the preparation efficiency. Description of the Drawings

[0043] The following will combine the drawings and describe in detail the specific embodiments of the present application, making the technical solutions and other beneficial effects of the present application obvious.

[0044] Figure 1 It is a reaction temperature change diagram in a method for preparing an epitaxial wafer provided by an embodiment of the present application;

[0045] Figure 2 It is a first hydrogen flow rate change diagram in a method for preparing an epitaxial wafer provided by an embodiment of the present application;

[0046] Figure 3 It is a trichlorosilane flow rate change diagram in a method for preparing an epitaxial wafer provided by an embodiment of the present application;

[0047] Figure 4 It is a front partial characterization diagram of an epitaxial wafer provided in Comparative Example 1 of the present application;

[0048] Figure 5 It is a back partial characterization diagram of an epitaxial wafer provided in Comparative Example 2 of the present application. Detailed Description of the Embodiments

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0050] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations. In the description of the present application, the meaning of "a plurality" is two or more, unless otherwise clearly specifically limited. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features.

[0051] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application.

[0052] The first embodiment of the present application provides a method for preparing an epitaxial wafer, including the following steps:

[0053] Provide an epitaxial reaction chamber, the epitaxial reaction chamber includes a pedestal, introduce first hydrogen and hydrogen chloride gas into the epitaxial reaction chamber, etch the inner wall of the epitaxial reaction chamber and the surface of the pedestal, and the first hydrogen has a first flow rate Q1 L / min;

[0054] Stop introducing the hydrogen chloride gas, perform the first cooling, keep the flow rate of the first hydrogen at the first flow rate Q1 L / min, and at the same time introduce gaseous trichlorosilane into the epitaxial reaction chamber to deposit an intrinsic silicon layer on the surface of the pedestal;

[0055] Stop introducing the gaseous trichlorosilane, adjust the flow rate of the first hydrogen to the second flow rate Q2 L / min, and perform the second cooling;

[0056] Provide a substrate, place the substrate in the epitaxial reaction chamber, perform heating, and grow an epitaxial layer on the surface of the substrate;

[0057] Wherein, Q1 < Q2.

[0058] In the preparation process of the epitaxial wafer, the present application combines the step of depositing the intrinsic silicon layer before growing the epitaxial wafer with the step of the first temperature reduction, replacing the step of first adjusting the temperature and then depositing the intrinsic silicon layer in the original process, shortening the overall process time and improving the preparation efficiency. At the same time, by reducing the flow rate of the first hydrogen gas in the step of depositing the intrinsic silicon layer, the concentration of trichlorosilane in the epitaxial reaction chamber is increased, further enhancing the reaction rate and improving the preparation efficiency.

[0059] In some embodiments, the first flow rate Q1 L / min and the second flow rate Q2 L / min satisfy:

[0060] Q1:Q2 = 1:2 to 2.25.

[0061] It can be understood that the value of Q1:Q2 can be any value among 1:2, 1:2.1, 1:2.2, 1:2.3, 1:2.4, 1:2.5 or the range between any two values. By introducing hydrogen gas in the etching stage and the stage of depositing the intrinsic silicon layer, on the one hand, it can react hydrogen gas with impurities in the epitaxial reaction chamber to make the surface of the intrinsic silicon layer cleaner, and on the other hand, it can also prevent the silicon wafer from oxidation, thereby improving the quality of the intrinsic silicon layer. When the supply of trichlorosilane stops, controlling the temperature drop in the epitaxial reaction chamber, continuously introducing hydrogen gas at this time can continue to clean the surface of the intrinsic silicon layer and can also remove the unreacted gases and compounds remaining on the surface of the intrinsic silicon layer. When the ratio of the first flow rate Q1 L / min to the second flow rate Q2 satisfies the above value range, it can improve the preparation efficiency of the intrinsic silicon layer while ensuring the quality of the surface of the intrinsic silicon layer.

[0062] In some embodiments, in the step of introducing the first hydrogen gas and hydrogen chloride gas into the epitaxial reaction chamber, the hydrogen chloride gas has a third flow rate Q3 L / min;

[0063] In the step of introducing gaseous trichlorosilane into the epitaxial reaction chamber, the gaseous trichlorosilane has a fourth flow rate Q4 L / min;

[0064] Satisfy: Q3:Q1 = 1:1 to 1:2.

[0065] It can be understood that the value of Q3:Q1 can be any value among 1:1, 1:1.2, 1:1.4, 1:1.6, 1:1.8, 1:2 or the range between any two values. Hydrogen chloride is used to etch the inner wall of the epitaxial reaction chamber and the surface of the pedestal. When the flow rate of hydrogen chloride is too high, it may cause over-etching and erosion of other materials, while when the flow rate of hydrogen chloride is too low, the quality and efficiency of etching may decline. When the third flow rate Q3 of the hydrogen chloride gas and the first flow rate Q1 satisfy the above value range, it can ensure that the etching step has both ideal efficiency and quality.

[0066] In some embodiments, Q4:Q1 = 1:2 to 2:3.

[0067] It can be understood that the value of Q4:Q1 can be any value among 1:2, 1:2.2, 1:2.4, 1:2.6, 1:2.8, 1:3 or the range between any two values. Trichlorosilane is used to deposit the intrinsic silicon layer (also known as silicon coating). When the flow rate of trichlorosilane is too low, it may lead to poor deposition of the intrinsic silicon layer, resulting in silicon stacking on the back of the wafer; when the flow rate of trichlorosilane is too high, it may lead to an increase in the thickness of the intrinsic silicon layer, causing particle bright spots on the front of the wafer. When the fourth flow rate Q4 and the first flow rate Q1 of trichlorosilane satisfy the above value range, an ideal thickness and surface quality of the formed intrinsic silicon layer can be obtained.

[0068] In some embodiments, the first flow rate Q1 L / min, the second flow rate Q2 L / min, the third flow rate Q3 L / min, and the fourth flow rate Q4 L / min further satisfy at least one of the following characteristics:

[0069] a) 20 L / min ≤ Q1 ≤ 40 L / min;

[0070] b) 40 L / min ≤ Q2 ≤ 45 L / min;

[0071] c) 10 L / min ≤ Q3 ≤ 20 L / min;

[0072] d) 10 L / min ≤ Q4 ≤ 15 L / min.

[0073] It can be understood that the value of the first flow rate Q1 (L / min) can be any value among 20, 25, 30, 35, 40 or the range between any two values; the value of the second flow rate Q2 (L / min) can be any value among 40, 41, 42, 43, 44, 45 or the range between any two values; the value of the third flow rate Q3 (L / min) can be any value among 10, 12, 14, 16, 18, 20 or the range between any two values; the value of the fourth flow rate Q4 (L / min) can be any value among 10, 11, 12, 13, 14, 15 or the range between any two values. When the first flow rate Q1, the second flow rate Q2, the third flow rate Q3, and the fourth flow rate Q4 satisfy the above value range, the process efficiency and quality in the etching and silicon coating steps can be further ensured.

[0074] In some embodiments, the temperature for etching the inner wall of the epitaxial reaction chamber and the surface of the pedestal is 1170 - 1190 °C.

[0075] It can be understood that the value of the temperature (unit: °C) for etching the inner wall of the epitaxial reaction chamber and the surface of the base can be any value among 1170, 1175, 1180, 1185, 1190 or the range between any two values. When the temperature for etching the inner wall of the epitaxial reaction chamber and the surface of the base satisfies the above value range, the etching of the inner wall of the epitaxial reaction chamber and the surface of the base can have an ideal etching rate and a high etching selectivity at the same time.

[0076] In some embodiments, the end temperature of the first temperature reduction is 1130 - 1150 °C.

[0077] It can be understood that the value of the end temperature of the first temperature reduction (unit: °C) can be any value among 1130, 1135, 1140, 1145, 1150 or the range between any two values. When the temperature for etching the inner wall of the epitaxial reaction chamber and the surface of the base (i.e., the starting point of the first temperature reduction) and the end temperature of the first temperature reduction satisfy the above value range, the step of depositing the silicon layer can be in a suitable temperature range throughout the process, thereby minimizing the impact of temperature reduction on the quality of silicon encapsulation, and ensuring the quality of the wafer while improving the overall efficiency of the epitaxial process.

[0078] In some embodiments, the end temperature of the second temperature reduction is 800 - 850 °C.

[0079] It can be understood that the value of the end temperature of the second temperature reduction (unit: °C) can be any value among 800, 810, 820, 830, 840, 850 or the range between any two values. When the end temperature of the second temperature reduction satisfies the above value range, the epitaxial wafer can grow in a more suitable temperature environment in the subsequent steps.

[0080] In some embodiments, the etching time is t1 s, the time for the first temperature reduction is t2 s, and the time for the second temperature reduction is t3 s, satisfying:

[0081] t1:t2 = 2:1 - 5:1.

[0082] It can be understood that the value of t1:t2 can be any value among 2:1, 3:1, 4:1, 5:1 or the range between any two values. If the etching time is insufficient, it will affect the particles on the front side of the wafer. If the time for silicon encapsulation is insufficient, silicon slag is likely to occur on the back side of the wafer. These two phenomena both affect the yield of this process and subsequent processes.

[0083] In some embodiments, the etching time satisfies: 15 s ≤ t1 ≤ 60 s.

[0084] In some embodiments, the time for the first temperature reduction satisfies: 8 s ≤ t2 ≤ 12 s.

[0085] It can be understood that the value of the etching time (unit: s) can be any value among 15, 20, 25, 30, 35, 40, 45, 50, 55, 60 or the range between any two values; the value of the time for the first temperature drop (unit: s) can be any value among 8, 9, 10, 11, 12 or the range between any two values.

[0086] In some embodiments, the first temperature drop has a first rate of v1 °C / s;

[0087] The second temperature drop has a second rate of v2 °C / s;

[0088] Satisfying: v1 ≤ v2.

[0089] Since the deposition of the silicon layer for characterization will be carried out in the reaction chamber during the first temperature drop process, therefore, controlling the rate of the first temperature drop to be slightly lower than the rate of the second temperature drop can better balance the balance between the silicon encapsulation quality and the total efficiency of the two temperature drop stages.

[0090] In some embodiments, the first rate satisfies: 5 °C / s ≤ v1 ≤ 10 °C / s.

[0091] In some embodiments, the second rate satisfies: 5 °C / s ≤ v2 ≤ 10 °C / s.

[0092] It can be understood that the value of the first rate (unit: °C / s) can be any value among 5, 6, 7, 8, 9, 10 or the range between any two values; the value of the second rate (unit: °C / s) can be any value among 5, 6, 7, 8, 9, 10 or the range between any two values. When the first rate and the second rate satisfy the above value ranges, the balance between the silicon encapsulation quality and the total efficiency of the two temperature drop stages can be further ensured.

[0093] In some embodiments, before the step of etching the surface of the substrate by introducing the first hydrogen and hydrogen chloride gas into the epitaxial reaction chamber, it further includes:

[0094] Introducing the second hydrogen into the epitaxial reaction chamber and simultaneously heating the epitaxial reaction chamber. The second hydrogen has a fifth flow rate of Q5 L / min, satisfying: Q5 ≤ Q1.

[0095] In some embodiments, the fifth flow rate Q5 L / min satisfies: 20 L / min ≤ Q5 ≤ 40 L / min.

[0096] It can be understood that the value of the fifth flow rate Q5 (unit: L / min) can be any value among 20, 25, 30, 35, 40 or the range between any two values.

[0097] In some embodiments, the temperature increase has a third rate v3 °C / s, satisfying: 5 °C / s ≤ v3 ≤ 10 °C / s.

[0098] It can be understood that the value of the third rate v3 (unit: °C / s) can be any value among 5, 6, 7, 8, 9, 10 or the range between any two values.

[0099] The second embodiment of the present application also provides an epitaxial wafer, which is prepared by using the preparation method of the epitaxial wafer in any of the above embodiments.

[0100] In some embodiments, the epitaxial wafer includes a substrate layer and an epitaxial layer provided on one side of the substrate layer; the thickness ratio of the intrinsic silicon layer to the epitaxial layer is 1:10 to 1:20.

[0101] It can be understood that the value of the thickness ratio of the intrinsic silicon layer to the epitaxial layer can be any value among 1:10, 1:12, 1:14, 1:16, 1:18, 1:20 or the range between any two values. When the thickness ratio of the intrinsic silicon layer to the epitaxial layer satisfies the above value range, the formed epitaxial wafer has better performance.

[0102] In some embodiments, the thickness of the intrinsic silicon layer is 1 to 1.5 μm.

[0103] It can be understood that the value of the thickness of the intrinsic silicon layer (unit: μm) can be any value among 1, 1.1, 1.2, 1.3, 1.4, 1.5 or the range between any two values.

[0104] In some embodiments, the thickness of the epitaxial layer is 20 to 30 μm.

[0105] It can be understood that the value of the thickness of the epitaxial layer (unit: μm) can be any value among 20, 22, 24, 26, 28, 30 or the range between any two values.

[0106] The following is an explanation of the epitaxial wafer provided by the present application with specific embodiments:

[0107] Embodiment 1

[0108] Embodiment 1 provides an epitaxial wafer and its preparation method. Refer to Figures 1 to 3 , and the preparation method includes the following steps:

[0109] Provide an epitaxial reaction chamber. The epitaxial reaction chamber includes a pedestal. Introduce a second hydrogen into the epitaxial reaction chamber, and at the same time preheat the epitaxial reaction chamber. The second hydrogen has a fifth flow rate of 20 L / min;

[0110] Introduce the first hydrogen gas and hydrogen chloride gas into the epitaxial reaction chamber, and etch the inner wall of the epitaxial reaction chamber and the surface of the pedestal. The first hydrogen gas has a first flow rate of 20 L / min;

[0111] Stop introducing the hydrogen chloride gas, perform the first cooling, keep the flow rate of the first hydrogen gas at the first flow rate of 20 L / min, and at the same time introduce trichlorosilane gas into the epitaxial reaction chamber to deposit an intrinsic silicon layer on the surface of the pedestal;

[0112] Stop introducing the trichlorosilane gas, adjust the flow rate of the first hydrogen gas to the second flow rate of 40 L / min, and perform the second cooling;

[0113] Provide a substrate, place the substrate in the epitaxial reaction chamber, perform heating, grow an epitaxial layer on the surface of the substrate, and obtain an epitaxial wafer.

[0114] Examples 2 - 3

[0115] The preparation methods of the epitaxial wafers in Examples 2 - 3 are the same as those in Example 1, except for the adjustment of process parameters.

[0116] Comparative Examples 1 - 2

[0117] The preparation methods of the epitaxial wafers in Comparative Examples 1 - 2 are the same as those in Example 1, except for the adjustment of process parameters.

[0118] The relevant process parameters in Examples 1 - 3 and Comparative Examples 1 - 2 are shown in Table 1.

[0119] Table 1

[0120]

[0121]

[0122] Test the epitaxial wafers provided in the examples and comparative examples of the present application. Observe the front and back appearances of the obtained epitaxial wafers under a strong light in a dark room. Under the various conditions used in this example, the particles and silicon stacking conditions on the front of the epitaxial wafer can meet the use requirements. The front characterization diagram of the epitaxial wafer obtained in Comparative Example 1 is shown in Figure 4 , it can be seen that due to the too low flow rate of trichlorosilane (Q4), the silicon encapsulation condition is not good, resulting in silicon stacking on the back of the wafer, which does not meet the process requirements. The back characterization diagram of the epitaxial wafer obtained in Comparative Example 2 is shown in Figure 5 , it can be seen that due to the too high flow rate of trichlorosilane (Q4), the silicon encapsulation thickness increases, resulting in particle bright spots on the front of the wafer, which does not meet the requirements.

[0123] The above has introduced in detail an epitaxial wafer and a method for preparing the same provided by the embodiments of the present application. Specific examples are used in the present application to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing an epitaxial wafer, characterized in that: The steps include: Providing an epitaxial reaction chamber, wherein the epitaxial reaction chamber includes a susceptor, introducing a first hydrogen gas and a hydrogen chloride gas into the epitaxial reaction chamber, etching an inner wall of the epitaxial reaction chamber and a surface of the susceptor, wherein the first hydrogen gas has a first flow rate of Q1 L / min; End the introduction of the hydrogen chloride gas, perform the first temperature reduction, maintain the flow rate of the first hydrogen gas at a first flow rate of Q1 L / min, and simultaneously introduce gaseous trichlorosilane into the epitaxial reaction chamber to deposit an intrinsic silicon layer on the surface of the base; End the introduction of the gaseous trichlorosilane, adjust the flow rate of the first hydrogen to the second flow rate Q2 L / min, and perform a second cooling; Providing a substrate, placing the substrate in an epitaxial reaction chamber, heating the substrate, and growing an epitaxial layer on the surface of the substrate; Performing a third cooling step to complete the preparation of the epitaxial wafer; Wherein, Q1<Q2, the first flow rate Q1 L / min and the second flow rate Q2 L / min satisfy: Q1:Q2=1:2~2.

25.

2. The method for preparing an epitaxial wafer according to claim 1, characterized in that: In the step of introducing the first hydrogen gas and the hydrogen chloride gas into the epitaxial reaction chamber, the hydrogen chloride gas has a third flow rate Q3 L / min; In the step of introducing gaseous trichlorosilane into the epitaxial reaction chamber, the gaseous trichlorosilane has a fourth flow rate Q4 L / min; Satisfy: Q3:Q1=1:1~1:2; and / or, Q4:Q1=1:2~2:

3.

3. The method for preparing an epitaxial wafer according to claim 2, characterized in that: The first flow rate Q1 L / min, the second flow rate Q2 L / min, the third flow rate Q3 L / min, and the fourth flow rate Q4 L / min further satisfy at least one of the following characteristics: a) 20L / min≤Q1≤40L / min; b) 40L / min≤Q2≤45L / min; c) 10L / min≤Q3≤20L / min; d) 10L / min≤Q4≤15L / min.

4. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The temperature for etching the inner wall of the epitaxial reaction chamber and the surface of the susceptor is 1170-1190° C.; and / or, The end point temperature of the first cooling is 1130-1150° C.; and / or, The end point temperature of the second cooling is 800-850°C.

5. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The etching time is t1 s, and the first cooling time is t2 s, satisfying: t1:t2=2:1~5:

1.

6. The method for preparing an epitaxial wafer according to claim 5, characterized in that: The etching time satisfies: 15s≤t1≤60s; and / or, The first cooling time satisfies: 8s≤t2≤12s.

7. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The first temperature reduction has a first rate v1 °C / s; The second cooling has a second rate v2 °C / s; Satisfies: v1≤v2.

8. The method for preparing an epitaxial wafer according to claim 7, characterized in that: The first rate satisfies: 5°C / s≤v1≤10°C / s; and / or, The second rate satisfies: 5°C / s≤v2≤10°C / s.

9. The method for preparing an epitaxial wafer according to claim 1, characterized in that: Before the step of introducing the first hydrogen gas and the hydrogen chloride gas into the epitaxial reaction chamber to etch the surface of the substrate, the method further comprises: A second hydrogen gas is introduced into the epitaxial reaction chamber, and the epitaxial reaction chamber is preheated at the same time, wherein the second hydrogen gas has a fifth flow rate Q5 L / min, satisfying: Q5≤Q1.

10. The method for preparing an epitaxial wafer according to claim 9, characterized in that: The fifth flow rate Q5 L / min satisfies: 20 L / min≤Q5≤40 L / min; and / or, The temperature increase has a third rate v3°C / s, satisfying: 5°C / s≤v3≤10°C / s.

11. An epitaxial wafer, characterized in that: The epitaxial wafer is prepared by the method for preparing the epitaxial wafer according to any one of claims 1 to 10.

12. An epitaxial wafer according to claim 11, characterized in that: The epitaxial wafer comprises a substrate layer and an epitaxial layer arranged on one side of the substrate layer; the thickness ratio of the intrinsic silicon layer to the epitaxial layer is 1:10-1:

20.

13. An epitaxial wafer according to claim 12, characterized in that: The thickness of the intrinsic silicon layer is 1-1.5 μm; and / or, The thickness of the epitaxial layer is 20-30 μm.

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