Electronic device and manufacturing method thereof

Abstract

An electronic device includes: an electronic unit having a first side and a second side; an encapsulation layer surrounding the electronic unit and having a plurality of openings exposing a second side of the electronic unit; the first circuit structure is arranged on the first side of the electronic unit and is electrically connected with the electronic unit; a second circuit structure disposed on a second side of the electronic unit; the through hole penetrates through the packaging layer and is electrically connected with the first circuit structure and the second circuit structure; the heat dissipation layer is arranged on the second side of the electronic unit, and the heat dissipation layer is in contact with the electronic unit through the plurality of openings.

Description

Technical Field

[0001] The present invention relates to an electronic device and a manufacturing method thereof, and in particular to an electronic device including a heat dissipation layer and a manufacturing method thereof. Background Art

[0002] With the development of digital technology, electronic devices have been widely used in all aspects of daily life. Electronic devices may include power components, packaging components or other electronic components. Traditional packaging components have a large volume and thickness because they include wirebonding. Therefore, when traditional packaging components are electrically connected to other electronic components, the reliability and electrical properties of the electronic device may be reduced due to the long path. Summary of the invention

[0003] According to some embodiments of the present disclosure, an electronic device is provided, which includes: an electronic unit having a first side and a second side, wherein the first side is opposite to the second side; a packaging layer surrounding the electronic unit and having a plurality of openings exposing the second side of the electronic unit; a first circuit structure disposed on the first side of the electronic unit and electrically connected to the electronic unit; a second circuit structure disposed on the second side of the electronic unit; a through hole penetrating the packaging layer and electrically connecting the first circuit structure and the second circuit structure; and a heat dissipation layer disposed on the second side of the electronic unit, wherein the heat dissipation layer contacts the electronic unit through the plurality of openings.

[0004] According to some embodiments of the present disclosure, a method for manufacturing an electronic device is provided, comprising: providing an electronic unit, a through hole, and a packaging layer, wherein the packaging layer surrounds the electronic unit and the through hole and exposes a first side of the electronic unit and a top of a conductive component of the through hole; providing a first circuit structure on the first side of the electronic unit and the through hole; forming a plurality of openings to expose a portion of the second side of the electronic unit; and forming a heat dissipation layer on the second side of the electronic unit and forming a second circuit structure on the through hole. The second circuit structure is electrically connected to the first circuit structure through the through hole, and the heat dissipation layer is located between the second circuit structure and the second side of the electronic unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are described in detail below with reference to the accompanying drawings, wherein:

[0006] Figure 1A is a schematic plan view of an electronic device according to an embodiment of the present disclosure;

[0007] Figure 1B According to an embodiment of the present disclosure, Figure 1A The electronic device is shown as a cross-sectional schematic diagram taken along line AA';

[0008] Figure 1CAccording to another embodiment of the present disclosure, Figure 1A The electronic device is shown as a cross-sectional schematic diagram taken along line AA';

[0009] Figure 2 is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0010] FIG. 3A to FIG. 3D is a schematic diagram of a semi-finished electronic device during the manufacture of the electronic device according to an embodiment of the present disclosure;

[0011] FIG. 4A to FIG. 4C is a schematic diagram of a semi-finished electronic device during the manufacture of the electronic device according to an embodiment of the present disclosure;

[0012] FIG. 5A to FIG. 5C is a schematic diagram of a semi-finished electronic device during the manufacture of the electronic device according to an embodiment of the present disclosure;

[0013] FIG. 6A to FIG. 6E is a schematic diagram of a semi-finished electronic device during the manufacture of the electronic device according to an embodiment of the present disclosure; and

[0014] 7A to 7F FIG. 4 is a schematic diagram of a semi-finished electronic device during the manufacturing of the electronic device according to an embodiment of the present disclosure.

[0015]

Explanation of symbols

[0016] 10: Electronic unit

[0017] 10S1: First side

[0018] 10S2: Second side

[0019] 101: Chips

[0020] 101U: Active surface

[0021] 101B: Back

[0022] 101S: Side surface

[0023] 101P: Input / output pads

[0024] 103: Protective layer

[0025] 20: Bonding layer

[0026] 30: Encapsulation layer

[0027] 30U: Upper surface

[0028] 30B: Bottom surface

[0029] 40: First protective layer

[0030] 50: First circuit structure

[0031] 501: first conductive layer

[0032] 503: second conductive layer

[0033] 60: Second protective layer

[0034] 70: Second circuit structure

[0035] 701: third conductive layer

[0036] 703: fourth conductive layer

[0037] 90: Heat dissipation layer

[0038] 901: Heat dissipation pattern

[0039] 9011,9013: sublayer

[0040] E: Pad

[0041] O1, O2, O3: Open

[0042] V1: Through hole

[0043] VH: Via Hole Opening

[0044] VM, VM': Conductive components

[0045] VMB,VMB': bottom

[0046] VMT,VMT':Top

[0047] VMS,VMS': side

[0048] VM1: Conductive metal layer

[0049] VM2: Conductive layer

[0050] W1: back width

[0051] W2: opening width

[0052] W3: Spacing

[0053] T1, T2: thickness

[0054] H1,H2: Height

[0055] R1, R2, R3, R4: Release layer

[0056] C1, C2, C3: Carrier board

[0057] A1, A2, A3: Seed layer

[0058] M1: Metal layer

[0059] D1: Step Difference DETAILED DESCRIPTION

[0060] The following description lists various embodiments of the present invention to introduce the basic concepts of the present invention and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the claims. The following will refer to exemplary embodiments of the present disclosure in detail, and examples of exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and description to represent the same or similar parts.

[0061] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to make it easier for readers to understand and for the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not intended to limit the scope of the present disclosure.

[0062] The directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. It is understood that if the device in the accompanying drawings is turned upside down, the components described on the "down" side will become components on the "up" side. In the accompanying drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these figures should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0063] A structure (or layer, component, substrate) described in the present disclosure is located on / above another structure (or layer, component, substrate), which may refer to the two structures being adjacent and directly connected, or it may refer to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate gap) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be a single-layer or multi-layer physical structure or can be composed of non-physical structures, without limitation. In the present disclosure, when a certain structure is disposed "on" other structures, it may refer to that the certain structure is "directly" on the other structure, or it may refer to that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

[0064] The term "A surrounds B" in the present disclosure means that at least part of B is in A, and in a cross-sectional view, A at least directly or indirectly contacts one side surface of B. The term "A indirectly contacts B" in the present disclosure means that there is an intervening structure between A and B. The term "A directly contacts B" in the present disclosure means that there is no intervening structure between A and B.

[0065] In some embodiments of the present disclosure, terms related to bonding and connection, such as "connection", "interconnection", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct (indirect) contact, wherein there is another structure disposed between the two structures. Such terms related to bonding and connection may also include situations where both structures are movable, or where both structures are fixed. In addition, the term "electrically connected" includes energy transfer between two structures by means of direct or indirect electrical connection, or energy transfer between two separate structures by means of mutual induction.

[0066] The terms "approximately", "equal to", "equal to" or "same", "substantially" or "approximately" are generally interpreted as within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range. The term "between a and b" refers to a range that includes all values ​​greater than or equal to a, less than or equal to b, and between a and b.

[0067] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify components. They do not imply or represent the number of any prefix of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The same words may not be used in the claims and the specification. Accordingly, the first component in the specification may be the second component in the claims.

[0068] Certain words are used throughout the present disclosure and the appended claims to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components with different names. This document does not intend to distinguish between components that have the same function but different names.

[0069] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0070] The electronic device may include a power module, an imaging device, a semiconductor device, a display device, a light-emitting device, a backlight device, an antenna device, a sensing device, a packaging device, a splicing device, a touch display, a curved display, or a free shape display, but the present disclosure is not limited thereto. The electronic device may, for example, include a liquid crystal, a light-emitting diode, fluorescence, phosphorescence, other suitable display media, or any combination thereof, but the present disclosure is not limited thereto. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device. The sensing device may be a sensing device for sensing capacitance, light, heat, or ultrasound, but the present disclosure is not limited thereto. The splicing device may, for example, be a display splicing device or an antenna splicing device, but the present disclosure is not limited thereto.

[0071] The electronic device may be a bendable or flexible electronic device. The shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The process of the electronic device described in the present disclosure may be applied, for example, to a wafer-level package (WLP) process or a panel-level package (PLP) process, which may be chip first or chip last (RDL first).

[0072] The electronic device of the present disclosure may include an electronic unit. The electronic unit may include passive components, active components or a combination thereof, such as capacitors, resistors, inductors, varactors, variable capacitors, filters, diodes, transistors, sensors, micro-electromechanical system components (MEMS), liquid crystal chips, etc., but the present disclosure is not limited thereto. The diode may include a light-emitting diode or a non-light-emitting diode. The diode may include a PN junction diode, a PIN diode or a constant current diode. The light-emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro light-emitting diode (micro LED), a quantum dot light-emitting diode (quantum dot LED), a fluorescence diode, a phosphor diode or other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. The sensor may include, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or pen sensors, but the present disclosure is not limited thereto.

[0073] It should be understood that according to the embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable methods may be used to measure the depth, thickness, width, or height of each component, or the spacing or distance between components. According to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the component to be measured, and measure the depth, thickness, width, or height of each component, or the spacing or distance between components.

[0074] One aspect of the present disclosure is to provide an electronic device. Figure 1A is a schematic plan view of an electronic device according to an embodiment of the present disclosure. Figure 1B According to an embodiment of the present disclosure, Figure 1AThe cross-sectional view of the electronic device shown is taken along line AA'. The "cross-sectional view" herein refers to a view taken along the normal direction (ie, the Z direction) of the electronic device.

[0075] The electronic device disclosed in the present invention includes an electronic unit 10 having a first side 10S1 and a second side 10S2 opposite to the first side 10S1; a packaging layer 30 surrounding the electronic unit 10 and having a plurality of openings O1 exposing the second side 10S2 of the electronic unit 10; a first circuit structure 50 disposed on the first side 10S1 of the electronic unit 10 and electrically connected to the electronic unit 10; a second circuit structure 70 disposed on the second side 10S2 of the electronic unit 10; a through hole V1 penetrating the packaging layer 30 and electrically connecting the first circuit structure 50 and the second circuit structure 70; and a heat dissipation layer 90 disposed on the second side 10S2 of the electronic unit 10, wherein the heat dissipation layer 90 contacts the electronic unit 10 through the plurality of openings O1.

[0076] The electronic unit 10 may include a chip 101 and a protective layer 103. The chip 101 may include an active surface 101U, a back surface 101B opposite to the active surface 101U, and a side surface 101S of the chip 101 connecting the active surface 101U and the back surface 101B. In some embodiments, the back surface 101B of the chip 101 may be equal to the second side 10S2 of the electronic unit 10, such as Figure 1B As shown, but the present disclosure is not limited thereto. The back surface 101B of the chip 101 has a back surface width W1 in a first direction (e.g., X direction) perpendicular to the normal direction of the electronic device. The input / output pad (I / O pad) 101P may be located on the active surface 101U of the chip 101. The protection layer 103 is disposed on the active surface 101U of the chip 101 and exposes the input / output pad 101P.

[0077] In some embodiments, the chip 101 may include a chip made of silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), sapphire (Sapphire) or a glass substrate, but the present disclosure is not limited thereto. In some embodiments, the chip 101 may include a semiconductor package component, such as a ball grid array (BGA) package component, a chip size package (CSP) component, a flip chip or a 2.5D / 3D semiconductor package component, but the present disclosure is not limited thereto. In some embodiments, the chip 101 may include a flip chip bonding component, such as an integrated circuit, a transistor, a thyristor rectifier, a valve, a capacitor, an inductor, a variable capacitor, a filter, a resistor, a diode, a micro-electromechanical system component (MEMS), a liquid crystal chip, a semiconductor structure, or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the chip 101 may be a known good die (KGD), which may include various electronic components, such as (but not limited to) wires, transistors, circuit boards, or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, a plurality of chips may be included, wherein adjacent chips may have different functions from each other, such as an integrated circuit, RFIC, D-RAM, but the present disclosure is not limited thereto.

[0078] In some embodiments, the protective layer 103 may include nitride, oxide, oxynitride, perfluoroalkoxyalkane (PFA), epoxy, Ajinomoto build-up film (ABF), polybenzoxazole (PBO), photosensitive polyimide (PSPI), polyimide (PI), other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the protective layer 103 may include organic materials, inorganic materials, or other suitable insulating materials, such as (but not limited to) epoxy, silicon nitride (SiNx), silicon oxide (SiOx), or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the protective layer 103 may be a stack including a multilayer film, such as a stack including at least one inorganic material layer and at least one organic material layer, wherein the inorganic material layer is disposed between the organic material layer and the chip 101. In some embodiments, the coefficient of thermal expansion (CTE) of the protective layer 103 may be between 0.1 and 50 ppm / C, or between 0.1 and 30 ppm / C. The positive modulus may be between 3 and 15 GPa, and / or the tensile strength may be between 50 and 110 MPa. In some embodiments, the protective layer 103 may include a filler having a particle size between 0.05 and 20 μm.

[0079] The packaging layer 30 having a plurality of openings O1 surrounds the electronic unit 10. Figure 1B In the cross-sectional schematic diagram of the electronic device shown, the encapsulation layer 30 is in direct or indirect contact with at least the side surface 101S of the chip 101. In some embodiments, the encapsulation layer 30 is in direct or indirect contact with the back surface 101B of the chip 101. In some embodiments, the encapsulation layer 30 covers the side surface 101S and part of the back surface 101B of the chip 101 and exposes the active surface 101U. In some embodiments, the encapsulation layer 30 may include organic materials, inorganic materials or other suitable insulating materials, such as (but not limited to) epoxy resin (epoxy), polymer, photosensitive polyimide (photosensitive polyimide, PSPI), polyimide (polyimide, PI), silicon nitride (SiNx), silicon oxide (silicon oxide, SiOx) or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the encapsulation layer 30 may include fillers with a particle size between 0.1 and 50 μm. Surrounding the electronic unit with the encapsulation layer 30 can reduce the impact of environmental water and oxygen on the electronic device, but is not limited thereto.

[0080] The packaging layer 30 may have an upper surface 30U and a bottom surface 30B opposite to the upper surface 30U. The bottom surface 30B of the packaging layer 30 may be adjacent to the back surface 101B of the chip 101. In some embodiments, the back surface 101B of the chip 101 may be located between the bottom surface 30B of the packaging layer 30 and the active surface 101U of the chip 101. In some embodiments, in the Z direction, the upper surface 30U of the packaging layer 30 may be spaced apart from the first side 10S1 of the electronic unit 10 by a step difference D1 (see FIG. 1 ). Figures 6B to 6E ) to reduce the risk of delamination of the first circuit structure 50 formed on the upper surface 30U of the packaging layer 30. In some embodiments, the step difference D1 may be between 1 and 10 μm, but the present disclosure is not limited thereto. In some embodiments, the packaging layer 30 has a thickness T1 in the normal direction of the electronic device (i.e., the Z direction). That is, in the Z direction, the upper surface 30U of the packaging layer 30 is a first distance away from the bottom surface 30B, and the first distance is equal to the thickness T1. In some embodiments, the packaging layer 30 located on the back side 101B of the chip 101 and covering the back side 101B of the chip 101 has a thickness T2. That is, the bottom surface 30B of the packaging layer 30 is a second distance away from the back side 101B of the chip 101, and the second distance is equal to the thickness T2. A plurality of openings O1 extend from the bottom surface 30B of the packaging layer 30 to the back side 101B of the chip 101 and expose a portion of the back side 101B of the chip 101, such as Figure 1A and Figure 1B As shown. In some embodiments, the thickness T2 is approximately equal to the second distance and is approximately equal to the opening depth of the opening O1. In this embodiment, each opening O1 has an opening width W2 in the first direction (i.e., the X direction) and an opening depth in the normal direction of the electronic device (i.e., the Z direction), wherein the opening depth is approximately equal to the thickness T2. In some embodiments, two openings O1 among the plurality of openings O1 are spaced apart by a spacing W3. In some embodiments, the opening width W2>spacing W3. In some embodiments, the opening width W2 and the spacing W3 satisfy the following relationship:

[0081] 1 / 4X opening width W2≦pitch W3≦3 / 4X opening width W2.

[0082] The heat dissipation layer 90 fills the opening O1 and contacts the back side 101B of the chip 101 through the opening O1. In some embodiments, part of the packaging layer 30 is located between the chip 101 and the heat dissipation layer 90, and the thickness T2 of these parts of the packaging layer 30 and the thickness T1 of the packaging layer 30 have a ratio (thickness T2 / thickness T1) between 0.01 and 0.5, that is, 0.01≤T2 / T1≤0.5. Through the above design, the heat dissipation efficiency of the heat dissipation layer 90 can be improved or the risk of delamination between the packaging layer 30 and the chip 101 can be reduced, but it is not limited to this. In some embodiments, the heat dissipation layer 90 may have a plurality of heat dissipation patterns 901, and each heat dissipation pattern 901 may be filled into an opening O1 of the packaging layer 30 and contact the back side 101B of the chip 101, such as Figure 1A as well as Figure 1B As shown. In this embodiment, the contact width between the heat dissipation pattern 901 in each opening O1 and the back side 101B of the chip 101 is approximately equal to the opening width W2 of the opening O1, and the thickness of the heat dissipation pattern 901 in the Z direction is approximately equal to the opening depth of the opening O1. In some embodiments, the sum of the contact widths between the heat dissipation layer 90 and the back side 101B of the chip 101 is equal to the sum of the opening widths W2 of the opening O1, and the ratio of the sum of the contact widths between the heat dissipation layer 90 and the back side 101B of the chip 101 / the back side width W1 of the back side 101B of the chip 101 may be between 0.2 and 0.7. In this embodiment, the heat dissipation layer 90 of the electronic device disclosed in the present invention can fully exert the heat dissipation function, or through the above design, it can avoid the back side 101B of the chip 101 from contacting a large area of ​​metal, reduce the probability of mismatching the thermal expansion coefficients of the chip 101 and the metal, and thereby reduce the probability of warping, or reduce the risk of cracking due to insufficient bonding area between the packaging layer 30 and the chip 101, thereby providing an electronic device with good heat dissipation and reliability.

[0083] The heat dissipation layer 90 may include a single-layer structure or a multi-layer structure having a plurality of layers. For example, in some embodiments, the heat dissipation layer 90 may be a multi-layer structure including a first sub-layer 9011 and a second sub-layer 9013. The first sub-layer 9011 may be located between the second sub-layer 9013 and the back side 101B of the chip 101, but the present disclosure is not limited thereto. In some embodiments, the heat dissipation layer 90 may be a single-layer structure including a sub-layer 9013. In some embodiments, the thermal conductivity of the heat dissipation layer 90 may be greater than or equal to 10W / mK and less than or equal to 505W / mK. That is, the heat dissipation layer 90 may include any material with a thermal conductivity greater than or equal to 10W / mK and less than or equal to 505W / mK. In some embodiments, the first sub-layer 9011 may include a seed layer, a metal, or a combination thereof. In some embodiments, examples of metals may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), silver (Ag), tantalum (Ta), nitrides, other suitable metal materials or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the second sublayer 9013 may include a metal. Examples of metals are described above, so they are not repeated here. In some embodiments, the thermal conductivity of the first sublayer 9011 may be different from the thermal conductivity of the second sublayer 9013. For example, the thermal conductivity of the first sublayer 9011 is less than the thermal conductivity of the second sublayer 9013, wherein the thermal conductivity of the first sublayer 9011 may be greater than or equal to 10W / mK and less than or equal to 50W / mK and the thermal conductivity of the second sublayer 9013 may be greater than or equal to 50W / mK and less than or equal to 505W / mK.

[0084] The first circuit structure 50 may be disposed on the first side 10S1 of the electronic unit 10, the upper surface 30U of the packaging layer 30, and the through hole V1. The first circuit structure 50 may include a single-layer structure or a multi-layer structure having multiple layers. For example, in some embodiments, the first circuit structure 50 may be a multi-layer structure including at least one first conductive layer 501 and at least one second conductive layer 503. The first conductive layer 501 may be located between the second conductive layer 503 and the input / output pad 101P and electrically connect the second conductive layer 503 and the input / output pad 101P, but the present disclosure is not limited thereto. In some embodiments, the first circuit structure 50 may be electrically connected to the pad E of the chip 101, wherein the pad E may be, for example, one of a source, a gate, or a drain, such as Figure 1A As shown. In some embodiments, the first circuit structure 50 may be a single-layer structure including a second conductive layer 503. The first conductive layer 501 may include a seed layer, a metal, or a combination thereof. In some embodiments, the second conductive layer 503 may include a metal. Examples of metals are described above, so they are not repeated here.

[0085] The second circuit structure 70 is disposed on the second side 10S2 of the electronic unit 10. In some embodiments, the second circuit structure 70 and the heat dissipation layer 90 can be formed by the same process to simplify the process of the electronic device of the present disclosure. In detail, the second circuit structure 70 and the heat dissipation layer 90 can be formed by the same step. That is, the second circuit structure 70 and the heat dissipation layer 90 can be formed in one piece, but the present disclosure is not limited thereto. In some embodiments, the second circuit structure 70 is electrically connected to the heat dissipation layer 90. In some embodiments, the second circuit structure 70 is electrically insulated from the heat dissipation layer 90. The second circuit structure 70 may include a single-layer structure or a multi-layer structure having multiple layers. For example, in some embodiments, the second circuit structure 70 may be a multi-layer structure including at least one third conductive layer 701 and at least one fourth conductive layer 703. The third conductive layer 701 may be located between the fourth conductive layer 703 and the bottom surface 30B of the encapsulation layer 30. In some embodiments, the second circuit structure 70 may be a single-layer structure including the fourth conductive layer 703. The third conductive layer 701 may include a seed layer, a metal, or a combination thereof. In some embodiments, the fourth conductive layer 703 may include metal. Examples of metals are described above and are not described in detail here. Through the design of a multi-layer structure, such as a seed layer design, the bonding force between subsequent conductive layers and insulating layers can be improved, but is not limited to this. The circuit structure referred to in the present disclosure can be used as a redistribution layer (RDL), which can redistribute the circuits of an electronic device and / or further increase the circuit fan-out area, or different electronic components can be electrically connected to each other via the first circuit structure 50 or the second circuit structure 70. For example, the spacing between two adjacent contact pads of the first circuit structure 50 that contacts one end of the chip 101 may be less than or equal to the spacing between two adjacent contact pads of the first circuit structure 50 away from one end of the chip 101, so that the first circuit structure 50 can adjust the circuit fan-out condition, but is not limited to this.

[0086] The through hole V1 includes a through hole opening VH penetrating the packaging layer 30 and a conductive component VM located in the through hole opening VH. The through hole V1 can electrically connect the first circuit structure 50 and the second circuit structure 70 through the conductive component VM. The conductive component VM may have a bottom VMB adjacent to the second circuit structure 70, a top VMT adjacent to the first circuit structure 50, and a side VMS connecting the bottom VMB and the top VMT. In some embodiments, the bottom VMB of the conductive component VM may protrude from the through hole opening VH. That is, the bottom VMB of the conductive component VM may protrude from the bottom surface 30B of the packaging layer 30. In other words, the through hole V1 may have a bottom, a top, and a side connecting the bottom and the top, wherein the bottom of the through hole V1 is connected to the second circuit structure 70 and the bottom protrudes from the bottom surface 30B of the packaging layer 30. In this embodiment, the bottom surface 30B of the packaging layer 30 may be located between the bottom VMB of the conductive component VM and the second side 10S2 of the electronic unit 10, as shown in FIG. Figure 1B In some embodiments, the side edge VMS of the conductive component VM may include a slanted edge in the cross-sectional schematic diagram of the electronic device, such as Figure 1B As shown, but the present disclosure is not limited to this. In some embodiments, the side VMS of the conductive component VM may include a stepped edge in the cross-sectional schematic diagram of the electronic device, as shown in the dotted box. The conductive component VM may include a single-layer structure or a multi-layer structure having multiple layers. In some embodiments, the conductive component VM may be a multi-layer structure including a conductive layer VM2 and a conductive metal layer VM1. The conductive layer VM2 may be located between the conductive metal layer VM1 and the packaging layer 30. In some embodiments, the conductive component VM may be a single-layer structure including a conductive metal layer VM1. The conductive layer VM2 may include a seed layer, a metal, or a combination thereof. In some embodiments, the conductive metal layer VM1 may include a metal. Examples of metals are described above, so they are not repeated here.

[0087] In some embodiments, the electronic device may further include a bonding layer 20 on the second circuit structure 70. The electronic device may be electrically connected to other electronic devices through the bonding layer 20. In some embodiments, the bonding layer 20 may be disposed on the top surface of the second circuit structure 70. That is, in the Z direction, the second circuit structure 70 may be disposed between the bonding layer 20 and the second side 10S2 of the electronic unit 10, but the present disclosure is not limited thereto. In some embodiments, the bonding layer 20 may be disposed on the side surface of the second circuit structure 70 to achieve electrical connection of the side. The bonding layer 20 may include tin (Sn), gold (Au), nickel (Ni), other suitable metal materials, alloys thereof, or any combination thereof, but the present disclosure is not limited thereto. Examples of other electronic devices may include, but are not limited to, printed circuit boards, flexible circuit boards, flexible printed circuit boards, or any combination thereof.

[0088] In some embodiments, the electronic device may further include a first protective layer 40 on the first circuit structure 50. The first protective layer 40 may cover the first circuit structure 50 to reduce the risk of oxidation of the first circuit structure 50. Figure 1B The first protective layer 40 may include an organic material, an inorganic material or other suitable insulating material, such as (but not limited to) resin, Ajinomoto laminated film, polybenzoxazole, photosensitive polyimide, polyimide, silicon nitride, silicon oxide or any combination thereof, but the present disclosure is not limited thereto.

[0089] In some embodiments, the electronic device may further include a second protective layer 60 disposed on the bottom surface 30B of the packaging layer 30. For example, the second protective layer 60 contacts a portion of the bottom surface 30B of the packaging layer 30 and is located on the second side 10S2 of the electronic unit 10. The second protective layer 60 may surround the second circuit structure 70 to reduce the risk of oxidation of the second circuit structure 70, such as Figure 1A The second protective layer 60 is in direct or indirect contact with at least the side surface of the second circuit structure 70. In some embodiments, the second protective layer 60 may be in direct contact with the side surface of the second circuit structure 70, such as Figure 1B As shown, but the present disclosure is not limited thereto. In some embodiments, the second protective layer 60 and the side surface of the second circuit structure 70 may be in indirect contact with each other with a gap therebetween. The second protective layer 60 may include an organic material, an inorganic material or other suitable insulating material, such as (but not limited to) resin, Ajinomoto laminated film, polybenzoxazole, photosensitive polyimide, polyimide, silicon nitride, silicon oxide or any combination thereof, but the present disclosure is not limited thereto.

[0090] Figure 1C According to another embodiment of the present disclosure, Figure 1A The electronic device shown is a cross-sectional schematic diagram taken along line AA'. In addition to the conductive component VM', Figure 1C The structure of the electronic device shown is Figure 1B The structures of the electronic devices shown are substantially the same, so only the conductive element VM' is described below.

[0091] like Figure 1C As shown, the conductive component VM' includes a bottom VMB' adjacent to the second circuit structure 70, a top VMT' adjacent to the first circuit structure 50, and a side VMS' connecting the bottom VMB' and the top VMT'. In some embodiments, the bottom VMB' of the conductive component VM' may protrude from the through hole opening VH. That is, the bottom VMB' of the conductive component VM' may protrude from the bottom surface 30B of the packaging layer 30. In this embodiment, the bottom surface 30B of the packaging layer 30 may be located between the bottom VMB' of the conductive component VM' and the second side 10S2 of the electronic unit 10, as shown in FIG. Figure 1CIn some embodiments, in the cross-sectional view of the electronic device, the side edge VMS' of the conductive component VM' includes a stepped edge, as shown in the dashed box, and the stepped edge is adjacent to the second circuit structure 70, as shown in the dashed box. Figure 1C As shown, but the present disclosure is not limited thereto. In other words, in this embodiment, the through hole V1 including the conductive element VM' may have a bottom, a top, and a side connecting the bottom and the top, wherein the bottom of the through hole V1 is connected to the second circuit structure 70 and the side of the through hole V1 includes a stepped edge. Through the stepped design, the film layers are not coplanar, which can increase the contact area and thus improve the bonding ability, but is not limited thereto.

[0092] Another aspect of the present disclosure is to provide a method for manufacturing an electronic device. Figure 2 FIG. 1 is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure. Figure 2 As shown, the manufacturing method of an electronic device according to an embodiment of the present disclosure includes: step S201 of providing an electronic unit, a through hole and a packaging layer; step S203 of providing a first circuit structure on the first side of the electronic unit and the through hole; step S205 of forming a plurality of openings to expose a portion of the second side of the electronic unit; and step S207 of forming a heat dissipation layer on the second side of the electronic unit and forming a second circuit structure on the through hole. The electronic unit provided in step S201 is adjacent to the through hole, and the packaging layer surrounds the electronic unit and the through hole and exposes the first side of the electronic unit and the top of the conductive component of the through hole. The first circuit structure provided in step S203 is located on the first side of the electronic unit and the top of the conductive component and electrically connects the electronic unit and the through hole. The second circuit structure formed in step S207 is electrically connected to the first circuit structure through the through hole.

[0093] FIG. 3A to FIG. 3D is a schematic diagram of a semi-finished electronic device during the manufacturing of an electronic device according to an embodiment of the present disclosure. Figure 2 and FIG. 3A to FIG. 3D The manufacturing method of the electronic device disclosed in the present invention is further described.

[0094] The step S201 of providing an electronic unit, a through hole and a packaging layer may include an electronic unit providing process for providing the electronic unit 10 on a carrier, a packaging layer forming process for forming a packaging layer 30, and a through hole forming process for forming a through hole V1. In some embodiments, step S201 may include sequentially performing an electronic unit providing process, a packaging layer forming process, and a through hole forming process, but the present disclosure is not limited thereto. In some embodiments, step S201 may include sequentially performing an electronic unit providing process, a through hole forming process, and a packaging layer forming process. The following is an embodiment in which step S201 includes sequentially performing an electronic unit providing process, a packaging layer forming process, and a through hole forming process. Figure 3AStep S201 is described.

[0095] In this embodiment, the electronic unit providing process may include placing an electronic unit 10 having a first side 10S1 and a second side 10S2 opposite to the first side 10S1 on a carrier. In some embodiments, the electronic unit 10 may be placed on the carrier in a manner such that the first side 10S1 faces the carrier, that is, a chip-down process method, but the present disclosure is not limited thereto. In some embodiments, the electronic unit 10 may be placed on the carrier in a manner such that the second side 10S2 faces the carrier, that is, a chip-up process method. The encapsulation layer forming process may include forming an encapsulation layer 30 on the carrier and surrounding the electronic unit 10. In this embodiment, the encapsulation layer 30 is in direct or indirect contact with the second side 10S2 of the electronic unit 10 and the side of the electronic unit 10. The through-hole forming process may include inverting the electronic unit 10 and the packaging layer 30 surrounding the electronic unit 10 on a carrier C1 on which a release layer R1 is disposed to expose the first side 10S1 of the electronic unit 10, forming a through-hole opening VH next to the electronic unit 10, and filling the conductive component VM in the through-hole opening VH to form the through-hole V1. In some embodiments, the through-hole opening VH may be formed by a laser perforation process, a mechanical perforation process, and / or a yellow light process. In some embodiments, the conductive component VM may be filled into the through-hole opening VH by an electroplating process, a chemical plating process, and / or a sputtering process. In this embodiment, the packaging layer 30 surrounds the electronic unit 10 and the through-hole V1 and exposes the first side 10S1 of the electronic unit 10 and the top VMT of the conductive component VM of the through-hole V1. The resulting structure can refer to Figure 3A .

[0096] In step S203, the first circuit structure 50 including the first conductive layer 501 and the second conductive layer 503 may be provided on the input / output pad 101P and the first side 10S1 of the electronic unit 10 exposed through the packaging layer 30 and the top VMT of the through hole V1 to electrically connect the electronic unit 10 and the through hole V1. In some embodiments, step S203 may include an electroplating process, a chemical plating process, and / or a sputtering process. In some embodiments, the manufacturing method of the electronic device of the present disclosure may further include a first protective layer forming step of forming a first protective layer 40 on the first circuit structure 50 to reduce the risk of oxidation of the first circuit structure 50. The structure obtained after the first protective layer forming step is as shown in FIG. Figure 3A In some embodiments, the first protective layer 40 may be omitted.

[0097] The step S205 of forming a plurality of openings to expose the second side of the electronic unit may include a packaging layer removal step of removing a portion of the packaging layer 30 and an opening etching step of forming the opening O1. In some embodiments, the packaging layer removal step is performed until the conductive component VM of the through hole V1 is exposed, but the present disclosure is not limited thereto. In some embodiments, the bottom VMB of the conductive component VM is still covered by the packaging layer 30 after the packaging layer removal step.

[0098] The following combination Figure 2 as well as FIG. 3B to FIG. 3D The embodiment in which the encapsulation layer removal step in step S205 is performed until the conductive element VM is exposed is further described. Before performing step S205, the structure obtained in step S203 is first inverted on a carrier C2 on which a release layer R2 is disposed, and then the release layer R1 and the carrier C1 are removed to expose the bottom surface 30B of the encapsulation layer 30. In step S205, the encapsulation layer removal step is performed to remove a portion of the encapsulation layer 30 until the conductive element VM is exposed, such as Figure 3B The encapsulation layer removal step may include a grinding process. The opening etching step, such as Figure 3C As shown by the arrow, it is performed after the encapsulation layer removal step. In some embodiments, the opening etching step may include a first etching process for etching the encapsulation layer 30 surrounding the conductive component VM and a second etching process for locally etching a portion of the encapsulation layer 30 on the back side 101B of the chip 101. The first etching process can make the bottom VMB of the conductive component VM protrude from the encapsulation layer 30 to reduce the risk of delamination of the subsequent layer formed thereon. The second etching process can form a plurality of openings O1 exposing the back side 101B of the chip 101. In some embodiments, the first etching process can be omitted. In some embodiments, the encapsulation layer 30 after the first etching process may have a thickness T1 in the Z direction. In some embodiments, the opening O1 formed by the second etching process may have an opening width W2 in the first direction (i.e., the X direction) and an opening depth in the normal direction of the electronic device (i.e., the Z direction). In some embodiments, two openings O1 among the plurality of openings O1 are spaced apart by a spacing W3. In some embodiments, the opening width W2>spacing W3. In some embodiments, the opening width W2 and the spacing W3 meet the following relationship:

[0099] 1 / 4X opening width W2≦pitch W3≦3 / 4X opening width W2.

[0100] In some embodiments, the first etching process may include a plasma etching process, a laser etching process, a chemical etching process, other suitable etching processes or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the second etching process may include a laser perforation process, a mechanical perforation process, a yellow light process, other suitable etching processes or any combination thereof, but the present disclosure is not limited thereto.

[0101] The heat dissipation layer 90 and the second circuit structure 70 are formed on the second side 10S2 of the electronic unit 10 and the through hole V1 in step S207. The heat dissipation layer 90 is located between the second circuit structure 70 and the second side 10S2 of the electronic unit 10. The through hole V1 electrically connects the second circuit structure 70 and the first circuit structure 50. The obtained structure is as shown in FIG. Figure 3D As shown. The heat dissipation layer 90 may include a plurality of heat dissipation patterns 901 that fill the plurality of openings O1 formed in step S205 to contact the back side 101B of the chip 101 through the openings O1. The sum of the contact widths of the heat dissipation layer 90 and the back side 101B of the chip 101 is equivalent to the sum of the opening widths W2 of the openings O1. In some embodiments, the ratio of the sum of the contact widths of the heat dissipation layer 90 and the back side 101B of the chip 101 / the back side width W1 of the back side 101B of the chip 101 may be between 0.2 and 0.7. The encapsulation layer 30 located between the chip 101 and the second circuit structure 70 has a thickness T2, and the thickness T2 is approximately equal to the opening depth of the opening O1. In some embodiments, the thickness T2 / thickness T1 may be between 0.01 and 0.5.

[0102] In some embodiments, the heat dissipation layer 90 and the second circuit structure 70 can be formed by different processes. In some embodiments, the heat dissipation layer 90 and the second circuit structure 70 in step S207 can be formed by the same process. Specifically, in some embodiments, the heat dissipation layer 90 and the second circuit structure 70 can be obtained by depositing a metal layer on the second side 10S2 of the electronic unit 10 and the bottom VMB of the conductive component VM, and then patterning the metal layer, but the present disclosure is not limited thereto. In some embodiments, the thickness of the deposited metal layer in the Z direction is greater than the opening depth of the opening O1.

[0103] In some embodiments, the manufacturing method of the electronic device disclosed in the present invention may further include a step of forming a bonding layer 20 in which a bonding layer 20 is disposed on the second circuit structure 70 to electrically connect to other electronic devices, and a step of forming a second protective layer 60 surrounding the second circuit structure 70 on the second side 10S2 of the electronic unit 10 to reduce the risk of oxidation of the second circuit structure 70. The structure obtained after the bonding layer 20 formation step and the second protective layer formation step is as follows: Figure 3D In some embodiments, the bonding layer 20 and / or the second protective layer 60 may be omitted.

[0104] FIG. 4A to FIG. 4C is a schematic diagram of a semi-finished electronic device during the manufacture of an electronic device according to another embodiment of the present disclosure. Specifically, FIG. 4A to FIG. 4C This is an example of illustrating that the bottom VMB of the conductive element VM is still covered by the packaging layer 30 after the packaging layer removal step. Figure 2 as well as FIG. 4A to FIG. 4C The embodiment is described in which the bottom VMB of the conductive element VM is still covered by the packaging layer 30 after the packaging layer removal step.

[0105] After the encapsulation layer removal step is performed in step S205, the bottom VMB of the conductive element VM is still covered by the encapsulation layer 30. Figure 4A As shown. In this embodiment, the bottom VMB of the conductive component VM is protected by the encapsulation layer 30 during the encapsulation layer removal step, thereby reducing the risk of material extension of the conductive component VM. The opening etching step is performed after the encapsulation layer removal step. In some embodiments, the opening etching step may include a third etching process for locally etching the encapsulation layer 30 on the bottom VMB of the conductive component VM and a portion of the encapsulation layer 30 on the back side 101B of the chip 101. The third etching process may form a plurality of openings O1 exposing the back side 101B of the chip 101 and an opening O2 exposing the bottom VMB of the conductive component VM. The structure obtained after the opening etching step may be as shown. Figure 4B As shown. In some embodiments, the encapsulation layer 30 may have a thickness T1 in the Z direction. In some embodiments, the opening O1 has an opening width W2 in the first direction (i.e., the X direction) and has an opening depth in the normal direction of the electronic device (i.e., the Z direction). In some embodiments, the width of the opening O2 in the first direction (i.e., the X direction) is greater than the width of the bottom VMB of the conductive component VM in the first direction, but the present disclosure is not limited thereto. In some embodiments, the depth of the opening O2 in the normal direction of the electronic device (i.e., the Z direction) is approximately equal to the opening depth of the opening O1, but the present disclosure is not limited thereto. In some embodiments, the third etching process may include a laser perforation process, a mechanical perforation process, a yellow light process, other suitable etching processes, or any combination thereof, but the present disclosure is not limited thereto.

[0106] The heat dissipation layer 90 and the second circuit structure 70 are formed on the second side 10S2 of the electronic unit 10 and the through hole V1 in step S207. The heat dissipation layer 90 is located between the second circuit structure 70 and the second side 10S2 of the electronic unit 10, and the through hole V1 electrically connects the second circuit structure 70 and the first circuit structure 50. The obtained structure is as shown in FIG. Figure 4C As shown. In this embodiment, when forming the second circuit structure 70, part of the metal layer will fill the opening O2 and form a new conductive element VM' together with the conductive element VM. The side VMS' of the conductive element VM' may have a stepped edge. Except for forming the new conductive element VM', step S207 in this embodiment is substantially the same as the above step S207, so it will not be repeated here.

[0107] In some embodiments, the manufacturing method of the electronic device of the present disclosure may further include a bonding layer forming step of disposing a bonding layer 20 on the second circuit structure 70 to electrically connect to other electronic devices and a second protective layer forming step of disposing a second protective layer 60 surrounding the second circuit structure 70 on the second side 10S2 of the electronic unit 10 to reduce the risk of oxidation of the second circuit structure 70. The structure obtained after the bonding layer forming step and the second protective layer forming step is as shown in FIG. Figure 4C In some embodiments, the bonding layer 20 and / or the second protective layer 60 may be omitted.

[0108] FIG. 5A to FIG. 5C is a schematic diagram of a semi-finished electronic device during the manufacturing of an electronic device according to an embodiment of the present disclosure. Specifically, FIG. 5A to FIG. 5C is a drawing specifically illustrating step S207 in the method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0109] Figure 5A Shown in Figure 4B The embodiment of performing step S207 on the structure shown in FIG. 1 is taken as an example, but the present disclosure is not limited thereto. In some embodiments, referring to FIG. 5A to FIG. 5C Step S207 described above can also be performed in Figure 3C In some embodiments, the heat dissipation layer 90 and the second circuit structure 70 may be deposited on the second side 10S2 of the electronic unit 10 and the bottom VMB of the conductive element VM to obtain a metal layer M1 having a thickness greater than the opening depth of the opening O1 in the Z direction. Figure 5A After the structure shown in FIG. 1 is formed, the metal layer M1 is patterned, but the present disclosure is not limited thereto. In some embodiments, the patterned metal layer M1 includes an opening O3 that forms an exposure of the bottom surface 30B of the packaging layer 30. The opening O3 may be located between the electronic unit 10 and the through hole V1. In some embodiments, the opening O3 may partially overlap the electronic unit 10 in the Z direction, such as Figure 5B As shown, the present disclosure is not limited thereto.

[0110] In some embodiments, the manufacturing method of the electronic device disclosed in the present invention may further include a bonding layer forming step of disposing a bonding layer 20 on the second circuit structure 70 to electrically connect with other electronic devices, and a second protective layer forming step of disposing a second protective layer 60 surrounding the second circuit structure 70 on the second side 10S2 of the electronic unit 10 to reduce the risk of oxidation of the second circuit structure 70. In some embodiments, the second protective layer 60 may be disposed in the opening O3, and along the X direction, there may be a gap between the second protective layer 60 and the bonding layer 20 and the second circuit structure 70, such as Figure 5CIn some embodiments, the second protective layer 60 may be in direct contact with the bonding layer 20 and the second circuit structure 70. In some embodiments, the bonding layer 20 and / or the second protective layer 60 may be omitted.

[0111] FIG. 6A to FIG. 6E is a schematic diagram of a semi-finished electronic device during the manufacturing of an electronic device according to an embodiment of the present disclosure. Specifically, FIG. 6A to FIG. 6E The embodiment of the method for manufacturing an electronic device according to an embodiment of the present disclosure is to illustrate that step S201 includes sequentially performing an electronic unit providing process, a through hole forming process, and a packaging layer forming process.

[0112] In this embodiment, the electronic unit providing step may include disposing a plurality of electronic units 10 on a carrier C1 on which a release layer R1 and a seed layer A1 are disposed, wherein the seed layer A1 is located between the release layer R1 and the carrier C1. In some embodiments, each electronic unit 10 may be disposed on the carrier C1 with the first side 10S1 facing the carrier C1, but the present disclosure is not limited thereto. The through-hole forming process may include disposing a plurality of through-holes V1 on the carrier C1 with the top VMT of the conductive component VM therein facing the carrier C1. In some embodiments, the through-hole V1 may be disposed between two electronic units 10, but the present disclosure is not limited thereto. The packaging layer forming process may include forming a packaging layer 30 on the carrier C1, wherein the packaging layer 30 surrounds the electronic unit 10 and the through-hole V1. The packaging layer 30 may be in direct or indirect contact with the second side 10S2 of the electronic unit 10 and the bottom VMB and side VMS of the through-hole V1, such as Fig. 6A In this embodiment, in the Z direction, the electronic unit 10 may have a first height H1, the through hole V1 may have a second height H2, and the packaging layer 30 may have a thickness T1, wherein the thickness T1>the second height H2>the first height H1.

[0113] like Fig. 6A The structure shown may be inverted on a carrier C2 on which a release layer R2 and a seed layer A2 are disposed before step S203, wherein the seed layer A2 is located between the release layer R2 and the carrier C2. The release layer R1, the seed layer A1, and the carrier C1 may be removed before step S203 to expose the input / output pads 101P and the first side 10S1 of the electronic unit 10 and the top VMT of the through hole V1. In some embodiments, in the Z direction, the upper surface 30U of the packaging layer 30 may be spaced apart from the first side 10S1 of the electronic unit 10 by a step difference D1 (e.g., Figure 6B In some embodiments, the step difference D1 may be between 1 μm and 10 μm.

[0114] In step S203, the first circuit structure 50 including the first conductive layer 501 and the second conductive layer 503 may be provided on the input / output pad 101P and the first side 10S1 of the electronic unit 10 and the top VMT of the through hole V1 to electrically connect the electronic unit 10 and the through hole V1. In some embodiments, the manufacturing method of the electronic device disclosed in the present invention may further include a first protective layer forming step of forming a first protective layer 40 on the first circuit structure 50 to reduce the risk of oxidation of the first circuit structure 50. The structure obtained after the first protective layer forming step is as shown in FIG. Figure 6B In some embodiments, the first protective layer 40 may be omitted.

[0115] Before performing step S205, the structure obtained from step S203 may be inverted on a carrier C3 on which a release layer R3 and a seed layer A3 are disposed, wherein the seed layer A3 is located between the release layer R3 and the carrier C3. The release layer R2, the seed layer A2, and the carrier C2 may be removed before step S205 to expose the bottom surface 30B of the packaging layer 30. Step S205 may include a packaging layer removal step of removing a portion of the packaging layer 30 and an opening etching step of forming the opening O1. In this embodiment, the packaging layer removal step may be performed until the bottom VMB of the conductive element VM is exposed, such as Figure 6C As shown, but the present disclosure is not limited thereto. In some embodiments, the bottom VMB of the conductive component VM may still be covered by the packaging layer 30 after the packaging layer removal step. The packaging layer removal step may include a grinding process. The opening etching step is performed after the packaging layer removal step. In some embodiments, the opening etching step may include a first etching process for etching the entire packaging layer 30 and a second etching process for locally etching a portion of the packaging layer 30 on the back side 101B of the chip 101. The first etching process may cause the bottom VMB of the conductive component VM to protrude from the bottom surface 30B of the packaging layer 30 to reduce the risk of delamination of subsequent layers formed thereon. The second etching process may form a plurality of openings O1 exposing the back side 101B of the chip 101. In some embodiments, the first etching process may be omitted. In some embodiments, the packaging layer 30 after the first etching process may have a thickness T1 in the Z direction (such as Fig.6D In some embodiments, the opening O1 formed by the second etching process may have an opening width W2 (eg, Fig.6D ), and has an opening depth in the normal direction of the electronic device (i.e., the Z direction). In some embodiments, the first etching process may include a plasma etching process, a laser etching process, a chemical etching process, other suitable etching processes, or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the second etching process may include a plasma etching process, a laser etching process, other suitable etching processes, or any combination thereof, but the present disclosure is not limited thereto.

[0116] The heat dissipation layer 90 and the second circuit structure 70 are formed on the second side 10S2 of the electronic unit 10 and the through hole V1 in step S207, wherein the heat dissipation layer 90 is located between the second circuit structure 70 and the second side 10S2 of the electronic unit 10, and the through hole V1 electrically connects the second circuit structure 70 and the first circuit structure 50. In some embodiments, the method for manufacturing an electronic device of the present disclosure may further include a bonding layer forming step of disposing a bonding layer 20 on the second circuit structure 70 to electrically connect to other electronic devices, and a second protective layer forming step of disposing a second protective layer 60 surrounding the second circuit structure 70 on the second side 10S2 of the electronic unit 10 to reduce the risk of oxidation of the second circuit structure 70. The structure obtained after the bonding layer forming step and the second protective layer forming step is as shown in FIG. Fig.6D In some embodiments, the bonding layer 20 and / or the second protective layer 60 may be omitted.

[0117] In some embodiments, the method for manufacturing an electronic device of the present disclosure may further include a cutting process. The cutting process may separate the plurality of electronic units 10 to form Fig. 6E The electronic device shown comprises an electronic unit 10 .

[0118] 7A to 7F is a schematic diagram of a semi-finished electronic device during the manufacturing of an electronic device according to an embodiment of the present disclosure. Figure 2 and 7A to 7F The manufacturing method of the electronic device disclosed in the present invention is further described.

[0119] In this embodiment, the step S201 of providing an electronic unit, a through hole and a packaging layer may include an electronic unit providing process of providing the electronic unit 10 on a carrier, a packaging layer forming process of forming a packaging layer 30, and a through hole forming process of forming a through hole V1. For example, in some embodiments, the electronic unit providing process may include disposing an electronic unit 10 having a first side 10S1 and a second side 10S2 opposite to the first side 10S1 on a carrier C1 having a release layer R1. In some embodiments, the electronic unit 10 may be disposed on the carrier C1 with the first side 10S1 facing the carrier, but the present disclosure is not limited thereto. The packaging layer forming process may include forming a packaging layer 30 on the carrier C1, wherein the packaging layer 30 surrounds the electronic unit 10 and is in direct or indirect contact with the second side 10S2 of the electronic unit 10 and the side of the electronic unit 10, and the structure formed is as follows. Fig. 7A Before performing the through hole forming process, Fig. 7AThe structure shown can be inverted on the porous carrier C2, and the release layer R1 and the carrier C1 are removed to expose the first side 10S1 of the electronic unit 10 and the upper surface 30U of the packaging layer 30. In this embodiment, a release layer R2, a seed layer A1, and a release layer R3 may be further provided between the porous carrier C2 and the packaging layer 30, wherein the seed layer A1 is located between the release layer R2 and the release layer R3, and the release layer R2 is located between the seed layer A1 and the porous carrier C2. The through-hole forming process is performed on the upper surface 30U of the packaging layer 30. In one embodiment, the through-hole forming process may include forming a through-hole opening VH (such as VH) extending from the upper surface 30U of the packaging layer 30 to the seed layer A1. Figure 7B As shown) and forming a conductive component VM in the through-hole opening VH. Specifically, in some embodiments, the formation of the through-hole opening VH may include first forming an opening to expose the release layer R3 by a laser perforation process, a mechanical perforation process, and / or a yellow light process, and then removing the release layer R3 and a portion of the seed layer A1 by a chemical etching process. In some implementations, step S203 of forming a first circuit structure 50 including a first conductive layer 501 and a second conductive layer 503 may be performed simultaneously with the step of forming a conductive component VM in the through-hole opening VH. That is, the first circuit structure 50 and the conductive component VM can be formed by the same process to simplify the process of the electronic device disclosed in the present invention. In this embodiment, the bottom VMB of the conductive component VM formed in the through-hole opening VH will protrude from the other surface of the packaging layer 30, such as Figure 7C As shown, the present disclosure is not limited thereto.

[0120] In some embodiments, the manufacturing method of the electronic device of the present disclosure may further include a first protective layer forming step of forming a first protective layer 40 on the first circuit structure 50 to reduce the risk of oxidation of the first circuit structure 50. The structure obtained after the first protective layer forming step is as shown in FIG. Figure 7C In some embodiments, the first protective layer 40 may be omitted.

[0121] Before executing step S205, the structure obtained from step S203 can be inverted on a carrier C3 on which a release layer R4 is disposed, and then the release layer R2, the seed layer A1, the release layer R3, and the porous carrier C2 are removed to expose the bottom surface 30B of the packaging layer 30. Then the packaging layer removal step in step S205 is performed until the bottom VMB of the conductive component VM is exposed. The packaging layer removal step may include a grinding process. The opening etching step in step S205 may be performed after the packaging layer removal step. In some embodiments, the opening etching step may include a first etching process for etching the entire packaging layer 30 and a second etching process for locally etching a portion of the packaging layer 30 on the back side 101B of the chip 101. The structure obtained after the first etching process is as shown in FIG. Fig.7DAs shown, the structure obtained after the second etching process is as follows Fig. 7E As shown. In some embodiments, the encapsulation layer 30 after the first etching process may have a thickness T1 in the Z direction. The first etching process may cause the bottom VMB of the conductive component VM of the encapsulation layer 30 to protrude from the bottom surface 30B of the encapsulation layer 30 to reduce the risk of delamination of the subsequent layers formed thereon. The second etching process may form a plurality of openings O1 exposing the back side 101B of the chip 101. In some embodiments, the opening O1 has an opening width W2 in the first direction (i.e., the X direction) and an opening depth in the normal direction of the electronic device (i.e., the Z direction). In some embodiments, the first etching process may include a plasma etching process, a laser etching process, a chemical etching process, other suitable etching processes, or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the second etching process may include a plasma etching process, a laser etching process, other suitable etching processes, or any combination thereof, but the present disclosure is not limited thereto.

[0122] The heat dissipation layer 90 and the second circuit structure 70 are formed on the second side 10S2 of the electronic unit 10 and the through hole V1 in step S207, wherein the heat dissipation layer 90 is located between the second circuit structure 70 and the second side 10S2 of the electronic unit 10 and the through hole V1 is electrically connected to the second circuit structure 70 and the first circuit structure 50. The obtained structure is as shown in FIG. Figure 7F The step S207 described in this embodiment is substantially the same as the aforementioned step S207, and thus will not be described in detail herein.

[0123] In some embodiments, the manufacturing method of the electronic device of the present disclosure may further include a bonding layer forming step of disposing a bonding layer 20 on the second circuit structure 70 to electrically connect to other electronic devices and a second protective layer forming step of disposing a second protective layer 60 surrounding the second circuit structure 70 on the second side 10S2 of the electronic unit 10 to reduce the risk of oxidation of the second circuit structure 70. The structure obtained after the bonding layer forming step and the second protective layer forming step is as shown in FIG. Figure 7F In some embodiments, the bonding layer 20 and / or the second protective layer 60 may be omitted.

[0124] The electronic device manufactured according to the manufacturing method of the electronic device disclosed above can have a smaller volume. When the electronic device disclosed in the present invention is electrically connected to other electronic devices through the bonding layer, the path between it and other electronic devices improves the reliability and electrical properties of the electronic device. In addition, the manufacturing method of the electronic device disclosed in the present invention can solve the metal smear problem caused by the grinding process, thereby improving the quality of the electronic device.

[0125] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of some embodiments of the present disclosure. As long as the same functions can be implemented in the embodiments described herein or the same results can be obtained, they can be used according to some embodiments of the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each embodiment can replace, reorganize and mix the features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features between the embodiments can be mixed and matched as needed as long as they do not violate the spirit of the invention or conflict. Each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each claim and embodiment.

Claims

1. An electronic device, characterized in that: include: An electronic unit having a first side and a second side opposite to the first side; an encapsulation layer surrounding the electronic unit and having a plurality of openings exposing the second side of the electronic unit; A first circuit structure, disposed on the first side of the electronic unit and electrically connected to the electronic unit; A second circuit structure is disposed on the second side of the electronic unit; a through hole, penetrating the packaging layer and electrically connecting the first circuit structure and the second circuit structure; and a heat dissipation layer, disposed on the second side of the electronic unit, The heat dissipation layer contacts the electronic unit through the plurality of openings.

2. The electronic device according to claim 1, wherein: The electronic unit comprises a chip and a protection layer. The heat dissipation layer contacts the back side of the chip through the plurality of openings.

3. The electronic device according to claim 2, wherein: The ratio of the total contact width between the heat dissipation layer and the back surface of the chip to the back surface width of the chip is between 0.2 and 0.

7.

4. The electronic device as claimed in claim 2, characterized in that: The packaging layer has a thickness T1 , and the packaging layer between the chip and the second circuit structure has a thickness T2 , and the thickness T2 / thickness T1 is between 0.01 and 0.

5.

5. The electronic device according to claim 1, wherein: The thermal conductivity of the heat dissipation layer is greater than or equal to 10 W / mK and less than or equal to 505 W / mK.

6. The electronic device according to claim 1, wherein: The invention further comprises a second protection layer disposed on the packaging layer, wherein the second protection layer surrounds the second circuit structure.

7. A method for manufacturing an electronic device, characterized in that: include: Providing an electronic unit, a through hole and a packaging layer, wherein the packaging layer surrounds the electronic unit and the through hole and exposes a first side of the electronic unit and a top of the conductive component of the through hole; Providing a first circuit structure on the first side of the electronic unit and the through hole; forming a plurality of first openings to expose a portion of the second side of the electronic unit; as well as forming a heat dissipation layer on the second side of the electronic unit and forming a second circuit structure on the through hole, The second circuit structure is electrically connected to the first circuit structure through the through hole, and the heat dissipation layer is located between the second circuit structure and the second side of the electronic unit.

8. The method for manufacturing an electronic device according to claim 7, wherein: The electronic unit comprises a chip and a protection layer. The heat dissipation layer contacts the back side of the chip through the plurality of first openings.

9. The method for manufacturing an electronic device according to claim 8, wherein: The ratio of the total contact width between the heat dissipation layer and the back surface of the chip to the back surface width of the chip is between 0.2 and 0.

7.

10. The method for manufacturing an electronic device according to claim 8, wherein: The packaging layer has a thickness T1 , and the packaging layer between the chip and the second circuit structure has a thickness T2 , and the thickness T2 / thickness T1 is between 0.01 and 0.5.

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