Microelectronic devices including recesses in encapsulant materials and associated systems and methods

Abstract

The invention relates to microelectronic devices including recesses in an encapsulant material and associated systems and methods. The microelectronic device includes a semiconductor die operatively coupled to a substrate structure. The device further includes an encapsulant substantially surrounding the semiconductor die. The device also includes one or more grooves extending vertically from an upper surface of the encapsulant to one or more locations at or proximate to an upper surface of the base structure.

Description

[0001] Priority claim

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 512,425, filed on July 7, 2023, entitled “MICROELECTRONIC DEVICES INCLUDINGRECESSES IN AN ENCAPSULANT MATERIAL AND ASSOCIATED SYSTEMS AND METHODS,” under 35 U.S.C. §119(e), and claims the benefit of the filing date of U.S. Patent Application Serial No. 18 / 737,817, filed on June 7, 2024, entitled “MICROELECTRONIC DEVICES INCLUDING RECESSES IN AN ENCAPSULANT MATERIAL AND ASSOCIATED SYSTEMS AND METHODS.” Technical Field

[0003] Embodiments of the present disclosure relate generally to microelectronic devices. In particular, embodiments of the present disclosure relate to microelectronic devices including recesses in encapsulant materials and associated systems and methods. Background Art

[0004] During manufacturing and testing, packaged microelectronic devices, such as packaged semiconductor devices and assemblies, are subject to various stresses caused at least by heating and cooling the semiconductor devices and assemblies during assembly of the devices on a substrate and encapsulation of the assemblies, including applying an encapsulant such as epoxy molding compound (EMC), curing the EMC, and / or reflowing external conductive elements such as solder balls or bumps. These stresses can result in microelectronic device damage, such as semiconductor device delamination or warping.

[0005] Microelectronic devices, such as semiconductor devices, and packages including such devices, continue to decrease in size due to a number of factors, including the need for increased portability, computing power, memory capacity, and energy efficiency. The size of the constituent features (i.e., critical dimensions) that form the devices, such as circuit elements and interconnects, as well as the spacing between structures (i.e., spacing), also continue to decrease to facilitate this size reduction.

[0006] The reduction in size of microelectronic and semiconductor devices and packages can result in increased susceptibility to damage caused by stresses resulting from heating and cooling of semiconductor devices and assemblies as the thickness of the devices decreases. In addition, devices can be stacked to increase the circuit density of the device and reduce the surface area. However, packages including stacked semiconductor devices can result in increased sensitivity to warpage of the package. Summary of the invention

[0007] Thus, an embodiment of the present disclosure includes a microelectronic device. The device includes a semiconductor die operatively coupled to a base structure. The device further includes an encapsulant substantially surrounding the semiconductor die. The device also includes one or more grooves extending vertically from an upper surface of the encapsulant to one or more locations located at or near the upper surface of the base structure.

[0008] Another embodiment of the present disclosure includes an electronic system. The system includes: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device. The memory device includes a semiconductor die coupled to a base structure. The memory device further includes an encapsulant substantially surrounding the semiconductor die. The memory device also includes a recess defined in the encapsulant.

[0009] Other embodiments of the present disclosure include a method of forming a microelectronic device. The method includes positioning a semiconductor die on a substrate. The method further includes encapsulating the semiconductor die in a first molding material. The method also includes forming one or more grooves in the first molding material. The method also includes heating the microelectronic device after forming the one or more grooves. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 illustrates a simplified longitudinal cross-sectional view of a microelectronic device according to an embodiment of the present disclosure;

[0011] Figures 2A to 4C illustrates a simplified longitudinal cross-sectional view of a semiconductor device package according to an embodiment of the present disclosure;

[0012] Figure 5 and 6 A simplified perspective view illustrating a semiconductor device package according to an embodiment of the present disclosure; and

[0013] Figure 7 is a schematic block diagram of an electronic system according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following description provides specific details such as material composition, shape and size in order to provide a thorough description of the embodiments of the present disclosure. However, it should be understood by those skilled in the art that the embodiments of the present disclosure can be practiced without adopting these specific details. In fact, the embodiments of the present disclosure can be practiced in conjunction with conventional microelectronic device manufacturing techniques used in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device (such as a semiconductor device). The structure described below does not form a complete microelectronic device. Only those process actions and structures required to understand the embodiments of the present disclosure are described in detail below. Additional actions to form a complete microelectronic device from the structure can be performed by conventional manufacturing techniques.

[0015] The drawings presented herein are for illustration only and do not imply actual views of any particular material, component, structure, device, or system. Changes in the shapes depicted in the drawings due to, for example, manufacturing techniques and / or tolerances may be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or regions described, but rather include shape deviations, for example, caused by manufacturing. For example, a region described or described as a frame may have rough and / or nonlinear features, and a region described or described as a circle may include some rough and / or linear features. In addition, the sharp angles described may be rounded, and vice versa. Therefore, the regions described in the figures are schematic and their shapes do not wish to illustrate the precise shape of the regions and do not limit the scope of the claims of the present invention. The drawings are not necessarily drawn to scale. In addition, common elements between the figures may retain the same element symbols.

[0016] As used herein, the terms "configured" and "configuration" refer to the size, shape, material composition, material distribution, orientation, and arrangement of at least one feature (e.g., one or more of at least one structure, at least one material, at least one region, at least one device) that facilitates use of the at least one feature in a predetermined manner.

[0017] As used herein, the term "substantially" with respect to a given parameter means and includes the degree to which a given parameter, property, or condition is satisfied within a small degree of variation (e.g., within acceptable manufacturing tolerances) as understood by those skilled in the art. For example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied by at least 90.0%, satisfied by at least 95.0%, satisfied by at least 99.0%, satisfied by at least 99.9%, or even satisfied by 100.0%.

[0018] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes the numerical value and the degree of variation relative to the numerical value within an acceptable tolerance for the particular parameter as understood by those of ordinary skill in the art. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​within a range from 90.0% to 110.0% of the numerical value, such as within a range from 95.0% to 105.0% of the numerical value, within a range from 97.5% to 102.5% of the numerical value, within a range from 99.0% to 101.0% of the numerical value, within a range from 99.5% to 100.5% of the numerical value, or within a range from 99.9% to 100.1% of the numerical value.

[0019] As used herein, for ease of description, relative terms such as "below," "beneath," "lower," "bottom," "above," "up," "top," "front," "back," "left," "right," and the like may be used to describe the relationship of one element or feature to another element or features, as illustrated in the drawings. Unless otherwise noted, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the drawings. For example, if the material in the drawings is reversed, an element described as being "below" or "below" or "under" or "on the bottom" of other elements or features would be oriented to be "above" or "on the top" of the other elements or features. Thus, one of ordinary skill in the art should understand that the term "below" may encompass both above and below orientations, depending on the context in which the term is used. The material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped) and the spatially relative descriptors used herein interpreted accordingly.

[0020] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0021] As used herein, the term "and / or" means and includes any and all combinations of one or more of the associated listed items.

[0022] As used herein, the terms "vertical," "longitudinal," "horizontal," and "transverse" refer to a principal plane of a structure and are not necessarily defined by the Earth's gravitational field. A "horizontal" or "transverse" direction is a direction generally parallel to the principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction generally perpendicular to the principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the drawings, a "horizontal" or "transverse" direction may be perpendicular to the indicated "Z" axis and may be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; and a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, may be perpendicular to the indicated "X" axis, and may be perpendicular to the indicated "Y" axis.

[0023] As used herein, “conductive material” means and includes conductive materials such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based The invention also includes conductive materials such as conductive materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides) and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)). In addition, the term "conductive structure" means and includes a structure formed of a conductive material and including a conductive material.

[0024] As used herein, "insulating material" means and includes electrically insulating materials such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x )、ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x ), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g. silicon oxynitride (SiO x N y )), at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiO x C y )), at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiC x O y H z )) and at least one dielectric carboxyl nitride material (e.g., carboxyl silicon nitride (SiO x C z N y )). A chemical formula (e.g., SiOx 、AlO x , HfO x 、NbO x 、TiO x 、SiN y 、SiO x N y 、SiO x C y 、SiC x O y H z 、SiO x C z N y ) represents a material containing an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if any) for each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since the chemical formula represents relative atomic ratios rather than strict chemical structures, the insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds and the values ​​of "x", "y", and "z" (if any) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds having elemental compositions that cannot be represented by ratios of clearly defined natural numbers and that violate the law of definite proportions. In addition, an "insulating structure" means and includes a structure formed of and including an insulating material.

[0025] Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, one of ordinary skill in the art may select the technique for depositing or growing the material. Additionally, unless the context indicates otherwise, removal of the materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, grinding planarization (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0026] Figure 1A simplified longitudinal cross-sectional view of a microelectronic device package in the form of a semiconductor device package 100 is illustrated. The semiconductor device package 100 may include one or more semiconductor dies 102 disposed within an encapsulant, such as a molding material 104, such as an EMC. As shown, the semiconductor die 102 may be flipped in a "flip-chip" orientation, mechanically and electrically connected to a substrate in the form of an interposer 110 by one or more conductive elements 106, such as solder bumps, solder balls, microbumps, etc. In some microelectronic device packages, the semiconductor die may be secured to the interposer by its backside auxiliary elements and electrically connected to the interposer by wires extending from an active surface to conductive pads of the interposer. The interposer 110 may be mechanically and electrically coupled to a package substrate 130, such as a base structure, by one or more other conductive elements in the form of solder bumps 112, which are connected to conductive contact pads 132 of the package substrate 130. Conductive contact pads 132 may provide electrical connections between interposer 110 and package substrate 130 via one or more solder bumps 112. Package substrate 130 may include an organic material such as a printed circuit board or an inorganic material such as silicon or ceramic. Alternatively, for example, in wafer-level or panel-level packaging, a redistribution layer (RDL) including one or more levels of conductive traces carried by a dielectric material may be used as a substrate.

[0027] The interposer 110 may include one or more alternating conductive and insulating (i.e., dielectric) layers. For example, the interposer 110 may include a first patterned conductive layer 114 including a conductive material extending through a dielectric material, disposed on a second patterned conductive layer 116 including a conductive material extending through a dielectric material, and the second patterned conductive layer 116 is disposed on a third patterned conductive layer 118 including a conductive material extending through a dielectric material. Each patterned conductive layer 114, 116, and 118 may include conductive portions 120 separated by insulating portions 122. The patterned conductive layers 114, 116, and 118 may further include a dielectric layer 124, such as an interlayer dielectric layer or an intermetallic dielectric layer formed on and / or in the conductive portions 120 of the respective patterned conductive layers 114, 116, and 118.

[0028] As the microelectronic device package is constructed, the semiconductor device package 100 may undergo multiple thermal cycles, such as a reflow process, a mold curing process, under bump metallization (UBM), baking, etc. As the semiconductor device package 100 is heated, moisture within the semiconductor device package 100 (e.g., between the semiconductor die 102 and the interposer 110) may evaporate. If the evaporated moisture is trapped within the semiconductor device package 100, the expansion of the moisture as it evaporates may create a high vapor pressure in an area, which may cause the elements of the semiconductor device package 100 in the area to separate by delamination or bubbles (e.g., bursting). Such separation may cause the semiconductor device package 100 or an associated microelectronic device package to fail. Embodiments of the present disclosure describe features that may be configured to provide an escape path for the evaporated moisture, which may substantially reduce or prevent damage to the semiconductor device package 100 caused by localized vapor pressure.

[0029] Warpage may also occur within the semiconductor device package 100 for various reasons and at various times during the process of manufacturing the semiconductor device package 100. For example, warpage may occur during one or more of the heating processes, such as a reflow process, a mold curing process, an under bump metallization (UBM) process, baking, etc. Generally speaking, warpage of the semiconductor device package 100 is caused by different coefficients of thermal expansion (CTE) between materials used to form different portions of the semiconductor device package 100. Since the semiconductor device package 100 experiences significant temperature changes throughout the formation process, the different CTEs may cause the semiconductor device package 100 to warp or bow because some portions of the semiconductor device package 100 expand or contract at a greater rate than other portions of the semiconductor device package 100 in response to the temperature changes.

[0030] In some embodiments, the molding material 104 has a CTE that is significantly different from the CTE of other components, such as the semiconductor die 102, the interposer 110, and the package substrate 130. Therefore, increasing the volume of the molding material 104 may increase the warpage of the semiconductor device package 100 and reducing the volume of the molding material 104 may reduce the warpage of the semiconductor device package 100. Embodiments of the present disclosure describe features that may reduce the volume of the molding material 104 to substantially reduce the volume of the molding material.

[0031] As described in more detail below, the semiconductor device package of the present disclosure includes one or more grooves formed in a molding material. The grooves can be configured to provide an escape path for evaporated moisture of the associated semiconductor device package. In addition, the one or more grooves can result in a reduction in the volume of the molding material, such that the grooves can reduce warpage caused by any CTE mismatch between the molding material and other components of the associated semiconductor device package.

[0032] Figures 2A to 4CSimplified longitudinal cross-sectional views illustrating different semiconductor device packages according to embodiments of the present disclosure. Figure 2A A semiconductor device package 200A is illustrated. The semiconductor device package 200A includes a semiconductor die 202a secured to a substrate 204a. The substrate 204a may be a base structure, such as a package substrate (e.g., as described above with reference to Figure 1 The semiconductor die 202a may be a package substrate 130 as described above, a redistribution layer (RDL) or an interposer structure including one or more levels of conductive traces carried by a dielectric material, such as the interposer 110 described above. The base 204a may include an organic material (e.g., a carbon-containing material) or an inorganic material (e.g., silicon or ceramic) and one or more conductive structures, such as one or more of a conductive pad, a conductive trace, a pin, and a socket. The semiconductor die 202a is electrically coupled to one or more of the conductive structures. For example, the semiconductor die 202a may be directly coupled to the conductive structure by a solder bump, a wire, or other complementary conductive structure (e.g., a pin, a socket). The substrate 204a may also include conductive structures extending beyond the footprint of the semiconductor die 202a, such as one or more of a trace and a contact pad for wire bonding.

[0033] The encapsulant 206a may substantially surround the semiconductor die 202a. The encapsulant 206a may extend over a portion of the upper surface 214a of the substrate 204a and completely cover the semiconductor die 202a. The encapsulant 206a may include a plurality of recesses 208a extending from an outer surface 210a of the encapsulant 206a into the encapsulant 206a. Figure 2A , the recess 208a extends into the encapsulant 206a in an area outside the footprint of the semiconductor die 202a. The recess 208a is positioned adjacent to the lateral surface 220a of the semiconductor die 202a. The encapsulant 206a may include a plurality of recesses 208a positioned around the perimeter of the semiconductor die 202a. The recess 208a may be configured to define an escape path in which vapor may leave the semiconductor device package 200A during one or more of the heating processes. Positioning the recess 208a proximate to the lateral surface 220a of the semiconductor die 202a reduces the volume of the molding material of the encapsulant 206a between the recess 208a and the interface 222a between the semiconductor die 202a and the substrate 204a. Thus, moisture trapped in the interface 222a may evaporate and escape through the recess 208a without generating excessive vapor pressure and without potentially damaging the semiconductor die 202a or the substrate 204a at the interface 222a.

[0034] exist Figure 2A, the recess 208a terminates before reaching the upper surface 214a of the substrate 204a. Thus, the bottom boundary 212a of the recess 208a is positioned a distance 216a from the upper surface 214a of the substrate 204a. The area between the bottom boundary 212a of the recess 208a and the upper surface 214a of the substrate 204a can be filled with the molding material of the encapsulant 206a. Thus, the molding material of the encapsulant 206a can remain to perform insulation or other protective functions for any conductive structures of the substrate 204a positioned proximate to the recess 208a.

[0035] The recess 208a may be defined by substantially vertical sidewalls 218a of the encapsulant 206a. The sidewalls 218a may be oriented parallel to one another such that the recess 208a individually exhibits a substantially rectangular cross-sectional shape in the Y plane, wherein the upper boundary of the recess 208a is defined by the outer surface 210a of the encapsulant 206a. The cross-sectional shape of the recess 208a in the X plane about the axis 224 of the recess 208a may be any shape, such as circular, elliptical, rectangular, triangular, etc. The shape of the recess 208a may be selected based on structural features of the substrate 204a and the semiconductor die 202a. For example, the shape of the recess 208a may be selected such that the bottom boundary 212a of the recess 208a is not positioned above or near selected features (such as contact pads or wires) of the substrate 204a and the semiconductor die 202a (e.g., such that the recess 208a avoids selected features of the substrate 204a and the semiconductor die 202a). The shape or location of the groove 208a may be further selected based on the warpage problem. For example, the groove 208a may be positioned or shaped to pass through the most warpage-prone region of the substrate 204a. Positioning the groove 208a over the warpage-prone region may reduce the warpage induced in the region due to the CTE mismatch between the molded material of the encapsulant 206a and the substrate 204a by reducing the volume of the molded material of the encapsulant 206a in the most warpage-prone region.

[0036] The recess 208a may be formed by one or more desired processes. For example, the recess 208a may be formed after the encapsulant 206a is formed by a material removal process such as machining, dry etching, or wet etching. In another example, the encapsulant 206a may be formed with the recess 208a, such as in a molding process with a complementary protrusion extending from the molding or in an additive manufacturing process.

[0037] Figure 2B A semiconductor device package 200B is illustrated. The semiconductor device package 200B includes a semiconductor die 202b secured to a substrate 204b. In some cases, the semiconductor device package 200B may be Figure 2A For example, a single semiconductor device package 200A or 200B may include a semiconductor device package 200A or 200B having Figure 2AThe area of ​​configuration described in Figure 2B . As described above, substrate 204b may be a package substrate, a redistribution layer (RDL), or an interposer structure. Semiconductor die 202b is electrically coupled to one or more of the conductive structures, such as by solder bumps, wires, and / or other complementary conductive structures (such as pins or sockets). Substrate 204b may also include conductive structures extending beyond the footprint of semiconductor die 202b, such as traces and / or contact pads for wire bonding.

[0038] The encapsulant 206b substantially surrounds the semiconductor die 202b. In some embodiments, the encapsulant 206b extends over a portion of the upper surface 214b of the substrate 204b and completely covers the semiconductor die 202b. In other embodiments, the encapsulant 206b extends over a portion of the upper surface 214b of the substrate 204b and is flush with the upper surface of the semiconductor die 202b, such that the upper surface of the semiconductor die 202b is exposed through the encapsulant 206b. The encapsulant 206b includes a primary recess 208b and a secondary recess 226a extending from an outer surface 210b of the encapsulant 206b into the encapsulant 206b. Figure 2B In the embodiment illustrated in , the main groove 208b extends into the encapsulant 206b in an area outside the footprint of the semiconductor die 202b. The main groove 208b is located adjacent to the lateral surface 220b of the semiconductor die 202b. The encapsulant 206b may include a plurality of main grooves 208b located around the perimeter of the semiconductor die 202b. The main groove 208b may be configured to define an escape path in which vapor may leave the semiconductor device package 200B during one or more of the heating processes. Positioning the main groove 208b proximate to the lateral surface 220b of the semiconductor die 202b reduces the volume of the molding material of the encapsulant 206b between the main groove 208b and the interface 222b between the semiconductor die 202b and the substrate 204b. Thus, moisture trapped in the interface 222b may evaporate and escape through the main groove 208b without generating excessive vapor pressure and without potentially damaging the semiconductor die 202b or the substrate 204b at the interface 222b.

[0039] exist Figure 2B , the auxiliary recess 226a extends into a portion of the encapsulant 206b that vertically overlies and is within the horizontal region of the semiconductor die 202b. The encapsulant 206b may include therein a plurality of auxiliary recesses 226a positioned above the semiconductor die 202b. The auxiliary recesses 226a may be configured to define an escape path in which vapor may leave the semiconductor device package 200B during one or more of the heating processes.

[0040] exist Figure 2B , the main recess 208b terminates before reaching the upper surface 214b of the substrate 204b and the auxiliary recess 226a terminates before reaching the upper surface 230a of the semiconductor die 202b. Thus, the bottom boundary 212b of the main recess 208b is positioned a first distance 216b from the upper surface 214b of the substrate 204b and the bottom boundary 228a of the auxiliary recess 226a is positioned a second distance 232a from the upper surface 230a of the semiconductor die 202b. The areas between the bottom boundaries 212a, 212b of the main recess 208b and the auxiliary recess 226a and the respective upper surfaces 214b, 230a of the substrate 204b and the semiconductor die 202b may be filled with the molding material of the encapsulant 206b. Thus, the molding material of the encapsulant 206 b may remain to perform insulation or other protection functions for any structures of the substrate 204 b and the semiconductor die 202 b located proximate to the main recess 208 b and the auxiliary recess 226 a .

[0041] The groove 208b may be defined by substantially vertical sidewalls 218b of the encapsulant 206b. The sidewalls 218b may be oriented parallel to each other so that the grooves 208b individually exhibit a substantially rectangular cross-sectional shape in the Y plane, wherein the upper boundary of the groove 208b is defined by the outer surface 210b of the encapsulant 206b. The cross-sectional shape of the groove 208b in the X plane about the axis of the groove 208b may be any shape, such as circular, elliptical, rectangular, triangular, etc. As described above, the shape of the grooves 208b, 226a may be selected based on the structural features of the substrate 204b and the semiconductor die 202b. The shape or position of the grooves 208b, 226a may be further selected based on the warpage problem to, for example, reduce the volume of the molding material of the encapsulant 206b in the most warpage-prone area.

[0042] Figure 2C A semiconductor device package 200C is illustrated. The semiconductor device package 200C includes a semiconductor die 202c secured to a substrate 204c. In some cases, the semiconductor device package 200C may be Figure 2A and 2B 200A and / or 200B. For example, a single semiconductor device package 200A, 200B, or 200C may include a Figure 2A and / or the configuration described in 200B and having Figure 2C. As described above, substrate 204c may be a package substrate, a redistribution layer (RDL), or an interposer structure. Semiconductor die 202c is electrically coupled to one or more of the conductive structures, such as by solder bumps, wires, and / or other complementary conductive structures (such as pins or sockets). Substrate 204c may also include conductive structures extending beyond the footprint of semiconductor die 202c, such as traces and / or contact pads for wire bonding.

[0043] The encapsulant 206c substantially surrounds the semiconductor die 202c. The encapsulant 206c extends over a portion of the upper surface 214c of the substrate 204c and completely covers the semiconductor die 202c. The encapsulant 206c includes a main recess 208c and an auxiliary recess 226b extending from an outer surface 210c of the encapsulant 206c into the encapsulant 206c. Figure 2C , the main groove 208c extends into the encapsulant 206c in an area outside of a horizontal area (e.g., a horizontal footprint) of the semiconductor die 202c. The main groove 208c is positioned adjacent to a lateral surface 220c of the semiconductor die 202c. For example, a portion of the lateral surface 220c of the semiconductor die 202c may define a lower boundary of the main groove 208c. The encapsulant 206c may include a plurality of main grooves 208c positioned horizontally around a horizontal perimeter of the semiconductor die 202c. The main groove 208c may be configured to define an escape path in which vapor may exit the semiconductor device package 200C during one or more of the heating processes. Positioning the lower boundary of the main groove 208c at or substantially near the lateral surface 220c of the semiconductor die 202c reduces the volume of molding material of the encapsulant 206c between the main groove 208c and an interface 222c between the semiconductor die 202c and the substrate 204c. Thus, moisture trapped in the interface 222c can evaporate and escape through the primary recess 208c without creating excessive vapor pressure and potentially damaging the semiconductor die 202c or the substrate 204c at the interface 222c.

[0044] exist Figure 2C , the auxiliary recess 226b extends into a portion of the encapsulant 206c that vertically overlies and is within the horizontal region of the semiconductor die 202c. The encapsulant 206c may include a plurality of auxiliary recesses 226b positioned above the semiconductor die 202c. The auxiliary recesses 226b may be configured to define an escape path in which vapor may leave the semiconductor device package 200C during one or more of the heating processes.

[0045] exist Figure 2CIn the embodiment illustrated in , the main groove 208c extends to the upper surface 214c of the substrate 204c and the auxiliary groove 226b terminates before reaching the upper surface 230b of the semiconductor die 202c. Therefore, the bottom boundary 228b of the auxiliary groove 226b is positioned at a distance 232b from the upper surface 230b of the semiconductor die 202c. The area between the bottom boundary 228b of the auxiliary groove 226a and the upper surface 230b of the semiconductor die 202c can be filled with the molding material of the encapsulant 206c. Therefore, the molding material of the encapsulant 206c can be retained to perform insulation or other protective functions for any structure of the semiconductor die 202c positioned near the auxiliary groove 226b. The main groove 208c can be positioned above a region of the substrate 204c that is substantially free of conductive structures and electrical components, so that the portion of the upper surface 214c of the substrate 204c exposed by the main groove 208c is substantially free of conductive structures and other electrical components.

[0046] The main groove 208c can be defined by a generally vertical sidewall 218c of the encapsulant 206c. The sidewalls 218c can be oriented parallel to each other so that the main groove 208c individually exhibits a generally rectangular cross-sectional shape in the Y plane, wherein the upper boundary of the groove 208c is defined by the outer surface 210c of the encapsulant 206c. Similarly, the auxiliary groove 226b can be defined by a generally vertical sidewall 234b of the encapsulant 206c. The sidewalls 234b can be oriented parallel to each other so that the auxiliary groove 226b individually exhibits a generally rectangular cross-sectional shape in the Y plane, wherein the upper boundary of the auxiliary groove 226b is defined by the outer surface 210c of the encapsulant 206c. The cross-sectional shapes of the main groove 208c and the auxiliary groove 226b in the X plane about the axes of the respective main groove 208c and the auxiliary groove 226b can be any shape, such as circular, elliptical, rectangular, triangular, etc. As described above, the shape of the main grooves 208c, 226b can be selected based on the structural features of the substrate 204c and the semiconductor die 202c. The shape or location of the grooves 208c, 226b can be further selected based on warpage issues to reduce the volume of molding material of the encapsulant 206c in the most warpage-prone areas, for example.

[0047] Figure 3A A semiconductor device package 300A is illustrated. The semiconductor device package 300A includes a semiconductor die 302a secured to a substrate 304a (eg, a base structure). In some cases, the semiconductor device package 300A may be Figures 2A to 2C304a. As described above, substrate 304a may be a package substrate, a redistribution layer (RDL), or an interposer structure. Semiconductor die 302a is electrically coupled to one or more of the conductive structures, such as by solder bumps, wires, and / or other complementary conductive structures (such as pins or sockets). Substrate 304a may also include conductive structures extending beyond the footprint of semiconductor die 302a, such as traces and / or contact pads for wire bonding.

[0048] The encapsulant 306a substantially surrounds the semiconductor die 302a. The encapsulant 306a extends over a portion of the upper surface 314a of the substrate 304a and completely covers the semiconductor die 302a. The recess 308a extends from an outer surface 310a (eg, upper surface) of the encapsulant 306a into the encapsulant 306a. Figure 3A , the groove 308a extends into a portion of the encapsulant 306a beyond the horizontal area of ​​the semiconductor die 302a. The groove 308a is positioned vertically adjacent to the lateral surface 320a of the semiconductor die 302a. The encapsulant 306a may include a plurality of grooves 308a positioned horizontally around the horizontal perimeter of the semiconductor die 302a. The groove 308a may be configured to define an escape path in which vapor may leave the semiconductor device package 300A during one or more of the heating processes. Positioning the groove 308a at or substantially near the lateral surface 320a of the semiconductor die 302a reduces the volume of the molding material of the encapsulant 306a between the groove 308a and the interface 322a between the semiconductor die 302a and the substrate 304a. Thus, moisture trapped in the interface 322a may evaporate and escape through the groove 308a without generating excessive vapor pressure and without potentially damaging the semiconductor die 302a or the substrate 304a at the interface 322a.

[0049] The groove 308a can be at least partially defined by an inclined (e.g., non-vertically oriented) sidewall 318a of the encapsulant 306a. The groove 308a exhibits a generally triangular vertical cross-sectional shape, wherein the upper boundary of the groove 308a is defined by the outer surface 310a of the encapsulant 306a. In some embodiments, one sidewall 318a extends at an angle and the other sidewall 318a defining the same groove 308a can be generally vertical, similar to Figures 2A to 2C308a. For individual grooves 308a, the sidewalls 318a combine to form an angle A at the vertex 312a of the groove 308a. Angle A may be in a range from about 1° to about 60°, such as in a range from about 10° to about 45° or in a range from about 10° to about 30°. The horizontal (e.g., in the X plane) cross-sectional shape of the individual grooves 308a may be any desired shape, such as a circle, an ellipse, a rectangle, a triangle, or another shape. As described above, the shape of the groove 308a may be selected based on the structural features of the substrate 304a and the semiconductor die 302a. The shape or position of the groove 308a may be further selected based on the warpage problem to, for example, reduce the volume of the molding material of the encapsulant 306a in the most warpage-prone area.

[0050] In some embodiments, the recess 308a extends to the upper surface 314a of the substrate 304a. Figure 3A 304a. The recess 308a extends to the upper surface 314a of the substrate 304a so that the vertex 312a of the recess 308a is located at the upper surface 314a of the substrate 304a. In other embodiments, the recess 308a exposes a portion of the upper surface 314a of the substrate 304a. For example, the recess 308a may be formed so that the adjacent sidewalls 318a of the encapsulant 306a extend to the upper surface 314a of the substrate 304a in different locations and do not meet at the vertex 312a to expose the area of ​​the upper surface 314a between the sidewalls 318.

[0051] Figure 3B A semiconductor device package 300B is illustrated. The semiconductor device package 300B includes a semiconductor die 302b secured to a substrate 304b (eg, a base structure). In some cases, the semiconductor device package 300B may be Figures 2A to 3A 304b. The substrate 304b may be a package substrate, a redistribution layer (RDL), or an interposer structure. The semiconductor die 302b is electrically coupled to one or more of the conductive structures, such as by solder bumps, wires, and / or other complementary conductive structures (such as pins or sockets). The substrate 304b may also include conductive structures extending beyond the footprint of the semiconductor die 302b, such as traces and / or contact pads for wire bonding.

[0052] The encapsulant 306b substantially surrounds the semiconductor die 302b. The encapsulant 306b extends over a portion of the upper surface 314b of the substrate 304b and completely covers the semiconductor die 302b. The recess 308b extends from the outer surface 310b of the encapsulant 306b into the encapsulant 306b. Figure 3B, the groove 308b extends into a portion of the encapsulant 306b outside the horizontal area of ​​the semiconductor die 302b. The groove 308b is positioned adjacent to the lateral surface 320b of the semiconductor die 302b. The encapsulant 306b may include a plurality of grooves 308b positioned horizontally around the horizontal perimeter of the semiconductor die 302b. The groove 308b may be configured to define an escape path in which vapor may leave the semiconductor device package 300B during one or more of the heating processes. Positioning the groove 308b proximate to the lateral surface 320b of the semiconductor die 302b reduces the volume of the molding material of the encapsulant 306b between the groove 308b and the interface 322b between the semiconductor die 302b and the substrate 304b. Therefore, moisture trapped in the interface 322b can evaporate and escape through the groove 308b without generating excessive vapor pressure and without potentially damaging the semiconductor die 302b or the substrate 304b at the interface 322b.

[0053] The groove 308b can be defined by an inclined sidewall 318b of the encapsulant 306b. The groove 308b exhibits a generally triangular vertical cross-sectional shape, wherein the upper boundary of the groove 308b is defined by the outer surface 310b of the encapsulant 306b. In some embodiments, one sidewall 318b extends at an angle and the other sidewall 318b defining the same groove 308b can be generally vertical, similar to Figures 2A to 2C The side walls 218a, 218b, 218c described in the drawings. The groove 308b may terminate at the bottom boundary 312b and may not converge at the apex. Figure 3B , the recess 308b terminates before reaching the upper surface 314b of the substrate 304b. Thus, the bottom boundary 312b of the recess 308b is positioned a distance 316 from the upper surface 314b of the substrate 304b. The area between the bottom boundary 312b of the recess 308b and the upper surface 314b of the substrate 304b can be filled with the molding material of the encapsulant 306b. Thus, the molding material of the encapsulant 306b can remain to perform insulation or other protective functions for any conductive structures of the substrate 304b positioned proximate to the recess 308b.

[0054] The horizontal (e.g., in the X-plane) cross-sectional shape of the individual grooves 308b can be any desired shape, such as circular, elliptical, rectangular, triangular, or another shape. As described above, the shape of the grooves 308b can be selected based on the structural features of the substrate 304b and the semiconductor die 302b. The shape or location of the grooves 308b can be further selected based on warpage issues to, for example, reduce the volume of molding material of the encapsulant 306b in the most warpage-prone areas.

[0055] Figure 3CA semiconductor device package 300C is illustrated. The semiconductor device package 300C includes a semiconductor die 302c secured to a substrate 304c (eg, a base structure). In some cases, the semiconductor device package 300C may be Figures 2A to 3B 304c. The substrate 304c may be a package substrate, a redistribution layer (RDL), or an interposer structure. The semiconductor die 302c is electrically coupled to one or more of the conductive structures, such as by solder bumps, wires, and / or other complementary conductive structures (such as pins or sockets). The substrate 304c may also include conductive structures extending beyond the footprint of the semiconductor die 302c, such as traces and / or contact pads for wire bonding.

[0056] The encapsulant 306c substantially surrounds the semiconductor die 302c. The encapsulant 306c extends over a portion of the upper surface 314c of the substrate 304c and completely covers the semiconductor die 302c. The main recess 308c and the auxiliary recess 326 extend from the outer surface 310c of the encapsulant 306c into the encapsulant 306c. Figure 3C , the main groove 308c extends into a portion of the encapsulant 306c beyond the horizontal area of ​​the semiconductor die 302c. The main groove 308c is positioned adjacent to the lateral surface 320c of the semiconductor die 302c. The encapsulant 306c may include a plurality of main grooves 308c positioned horizontally around the horizontal perimeter of the semiconductor die 302c. The main grooves 308c may be configured to define an escape path in which vapor may exit the semiconductor device package 300C during one or more of the heating processes. Positioning the main grooves 308c at or substantially proximate to the lateral surface 320c of the semiconductor die 302c reduces the volume of molding material of the encapsulant 306c between the main grooves 308c and the interface 322c between the semiconductor die 302c and the substrate 304c. Thus, moisture trapped in the interface 322c can evaporate and escape through the primary recess 308c without creating excessive vapor pressure and potentially damaging the semiconductor die 302c or the substrate 304c at the interface 322c.

[0057] exist Figure 3C , the auxiliary recess 326 extends into a portion of the encapsulant 306c that is vertically located above and within the horizontal region of the semiconductor die 302c. The encapsulant 306c may include a plurality of auxiliary recesses 326 therein. The auxiliary recesses 326 may be configured to define an escape path in which vapor may leave the semiconductor device package 300C during one or more of the heating processes.

[0058] The groove 308c can be defined by an inclined sidewall 318c in the encapsulant 306c. The main groove 308c exhibits a generally triangular vertical cross-sectional shape, wherein the upper boundary of the main groove 308c is defined by the outer surface 310c of the encapsulant 306c. In some embodiments, one sidewall 318c extends at an angle and the other sidewall 318c defining the same groove 308c can be generally vertical, similar to Figures 2A to 2C 304c and the semiconductor die 302c. The shape or position of the groove 308c can be further selected based on the warpage problem to reduce the volume of the molding material of the encapsulant 306c, for example, in the most warpage-prone area.

[0059] In some embodiments, the main groove 308c extends to the upper surface 314c of the substrate 304c, such as Figure 3C In some embodiments, the main groove 308c extends to the upper surface 314c of the substrate 304c, so that the apex of the main groove 308c is located at the upper surface 314c of the substrate 304c. In other embodiments, as Figure 3C , the main grooves 308c may expose a portion of the upper surface 314c of the substrate 304c such that the bottom boundary of the individual main grooves 308c is formed by the upper surface 314c of the substrate 304c. For example, the main grooves 308c may be defined such that adjacent sidewalls 318c defining the main grooves 308c do not meet at an apex such that an area of ​​the upper surface 314c is exposed between the sidewalls 318c.

[0060] The auxiliary groove 326 may also be defined by an inclined sidewall 332 in the encapsulant 306c. The auxiliary groove 326 also exhibits a generally triangular vertical cross-sectional shape, wherein the upper boundary of the main groove 308c is defined by the outer surface 310c of the encapsulant 306c. In some embodiments, one sidewall 318c extends at an angle and the other sidewall 318c defining the same groove 308c may be generally vertical, similar to Figure 2B and 2C The sidewalls 234a, 234b described in the foregoing. The sidewalls 332 may terminate at the bottom boundary 328 and may not converge at the apex. Figure 3C, the auxiliary recess 326 terminates before reaching the upper surface 330 of the semiconductor die 302 c. Thus, the bottom boundary 328 of the auxiliary recess 326 is located a second distance 324 from the upper surface 330 of the semiconductor die 302 c. The area between the bottom boundary 328 of the auxiliary recess 326 and the upper surface 330 of the semiconductor die 302 c can be filled with the molding material of the encapsulant 306 c. Thus, the molding material of the encapsulant 306 c can remain to perform insulation or other protection functions for the semiconductor die 302 c.

[0061] In some embodiments, one or more of the recesses (e.g., recesses 208a, 208b, 208c, 226a, 226b, 308a, 308b, 308c, 326) may be filled with another material. For example, the recess may be filled with a material having a different CTE than an encapsulant configured to control warpage of an associated semiconductor device package. Figures 4A to 4C Schematic cross-sectional views illustrating various embodiments of semiconductor device packages including one or more filled recesses.

[0062] Figure 4A A semiconductor device package 400A is illustrated. The semiconductor device package 400A includes a semiconductor die 402a on a substrate 404a (e.g., a base structure) and encapsulated by an encapsulant 406a. A fill material 408a is positioned in one or more recesses of the encapsulant 406a such that the fill material 408a substantially fills the one or more recesses. The fill material 408a may be positioned outside of a horizontal region of the semiconductor die 402a. For example, the fill material 408a may be positioned horizontally outside of a lateral surface 412a of the semiconductor die 402a. In some embodiments, the fill material 408a terminates at an upper surface 410a of the substrate 404a such that the fill material 408a is in direct contact with the upper surface 410a of the substrate 404a. In other embodiments, such as Figure 4A As illustrated in , the fill material 408a terminates a distance above the upper surface 410a of the substrate 404a such that the molding material of the encapsulant 406a is positioned between the fill material 408a and the upper surface 410a of the substrate 404a.

[0063] In some embodiments, the filling material 408a is configured to control the warpage of the semiconductor device package 400A. For example, the filling material 408a may have a CTE greater than that of the surrounding molding material of the encapsulant 406a to induce warpage in the region corresponding to the filling material 408a. In another example, the filling material 408a may have a CTE less than that of the surrounding molding material of the encapsulant 406a to suppress the warpage in the region corresponding to the filling material 408a.

[0064] In some embodiments, the filling material 408a is a second molding material (eg, epoxy molding compound) formed in a second molding process. In other embodiments, the filling material 408a is a thermosetting polymer material that is injected or flowed into the associated groove and then cured by a heating process.

[0065] Figure 4B A semiconductor device package 400B is illustrated. The semiconductor device package 400B includes a semiconductor die 402b on a substrate 404b (e.g., a base structure) and encapsulated by an encapsulant 406b. A primary fill material 408b is positioned in one or more recesses of the encapsulant 406b such that the primary fill material 408b substantially fills the one or more recesses. The primary fill material 408b may be positioned outside of a horizontal region of the semiconductor die 402b. For example, the fill material 408b may be positioned horizontally outside of an adjacent lateral surface 412b of the semiconductor die 402b. In some embodiments, the primary fill material 408b terminates at an upper surface 410b of the substrate 404b, such as Figure 4B , so that the main filling material 408b is in direct contact with the upper surface 410b of the substrate 404b. In other embodiments, the main filling material 408b ends at a distance above the upper surface 410b of the substrate 404b, so that the molding material of the encapsulant 406b is positioned between the main filling material 408b and the upper surface 410b of the substrate 404b.

[0066] like Figure 4B As described in FIG. 1 , the auxiliary filling material 416a is positioned in an auxiliary groove (eg, auxiliary groove 226a ( FIG. 226b ) vertically overlying and within a horizontal region of the semiconductor die 402b). Figure 2A )、226b( Figure 2B )、326( Figure 3C )). The auxiliary filling material 416a may substantially fill the auxiliary groove. The auxiliary filling material 416a may be vertically positioned above and within the horizontal region of the semiconductor die 402b. In some embodiments, the auxiliary filling material 416a terminates at the upper surface 418a of the semiconductor die 402b, such that the auxiliary filling material 416a is in direct contact with the upper surface 418a of the semiconductor die 402b. In other embodiments, such as Figure 4B As illustrated in , the auxiliary fill material 416a terminates a distance above the upper surface 418a of the semiconductor die 402b such that the molding material of the encapsulant 406b is positioned between the auxiliary fill material 416a and the upper surface 418a of the semiconductor die 402b.

[0067] In some embodiments, at least one of the main filling material 408b and the auxiliary filling material 416a is configured to control the warpage of the semiconductor device package 400B. For example, at least one of the main filling material 408b and the auxiliary filling material 416a may be a material having a CTE greater than that of the surrounding molding material of the encapsulant 406b to induce warpage in a region corresponding to the main filling material 408b or the auxiliary filling material 416a. In another example, at least one of the main filling material 408b and the auxiliary filling material 416a may be a material having a CTE less than that of the surrounding molding material of the encapsulant 406b to suppress warpage in a region corresponding to the main filling material 408b or the auxiliary filling material 416a.

[0068] In some embodiments, different filling materials are used at different locations. For example, the main filling material 408b may be a material configured to suppress warpage (e.g., having a CTE less than the molding material of the encapsulant 406b) and the auxiliary filling material 416a may be a material configured to induce warpage (e.g., having a CTE greater than the molding material of the encapsulant 406b) to achieve desired warpage control. In another example, the main filling material 408b may be a material configured to induce warpage (e.g., having a CTE greater than the molding material of the encapsulant 406b) and the auxiliary filling material 416a may be a material configured to suppress warpage (e.g., having a CTE less than the molding material of the encapsulant 406b) to achieve desired warpage control.

[0069] In some embodiments, the primary filling material 408b and / or the secondary filling material 416a are molding materials (e.g., epoxy molding compounds) formed in a second molding process. In other embodiments, the primary filling material 408b and / or the secondary filling material 416a are thermosetting polymer materials that are injected or flowed into the associated grooves and subsequently cured by a heating process.

[0070] Figure 4C A semiconductor device package 400C is illustrated. The semiconductor device package 400C includes a semiconductor die 402c on a substrate 404c (e.g., a base structure) and encapsulated by an encapsulant 406c. The encapsulant 406c may include one or more recesses 420 therein. The recesses 420 may be positioned outside of a horizontal region of the semiconductor die 402c. For example, a fill material 408b may be positioned horizontally outside of a lateral surface 412c of the semiconductor die 402c. In some embodiments, the recesses 420 terminate at an upper surface 410c of the substrate 404c such that a portion of the upper surface 410c of the substrate 404c is exposed through the recesses 420. In other embodiments, such as Figure 4C404c, the groove 420 terminates a distance above the upper surface 410c of the substrate 404c such that the molding material of the encapsulant 406c is positioned between the groove 420 and the upper surface 410c of the substrate 404c. The groove 420 can be configured to define an escape path in which vapor can leave the semiconductor device package 400C during one or more of the heating processes. Positioning the groove 420 proximate to the lateral surface 412c of the semiconductor die 402c reduces the volume of the molding material of the encapsulant 406c between the groove 420 and the interface 414 between the semiconductor die 402c and the substrate 404c. Thus, moisture trapped in the interface 414 can evaporate and escape through the groove 420 without generating excessive vapor pressure and without potentially damaging the semiconductor die 402c or the substrate 404c at the interface 414.

[0071] like Figure 4C As illustrated in FIG. 4 , the auxiliary filling material 416 b is positioned in an auxiliary recess (e.g., auxiliary recesses 226 a, 226 b, 326) above the semiconductor die 402 c. The auxiliary filling material 416 b may substantially fill the auxiliary recess. In some embodiments, the auxiliary filling material 416 b may terminate at the upper surface 418 b of the semiconductor die 402 c, such that the auxiliary filling material 416 b is in direct contact with the upper surface 418 b of the semiconductor die 402 c. In other embodiments, such as Figure 4C As illustrated in FIG. 4 , the auxiliary fill material 416 b terminates a distance above the upper surface 418 b of the semiconductor die 402 c such that the molding material of the encapsulant 406 c is positioned between the auxiliary fill material 416 b and the upper surface 418 b of the semiconductor die 402 c .

[0072] In some embodiments, the auxiliary filling material 416b is configured to control the warpage of the semiconductor device package 400C. For example, the auxiliary filling material 416b may be a material having a CTE greater than that of the surrounding molding material of the encapsulant 406c to induce warpage in a region corresponding to the auxiliary filling material 416b. In another example, the auxiliary filling material 416b may be a material having a CTE less than that of the surrounding molding material of the encapsulant 406c to suppress warpage in a region corresponding to the auxiliary filling material 416b.

[0073] In some embodiments, the auxiliary filling material 416b is a molding material (eg, epoxy molding compound) formed in a second molding process. In other embodiments, the auxiliary filling material 416b is a thermosetting polymer material that is injected or flowed into the associated groove and then cured by a heating process.

[0074] Figure 5 and Figure 6 Simplified perspective views illustrating different embodiments of semiconductor device packages having different patterns of recesses defined in a surface of an encapsulant. Figure 5 A simplified perspective view of a semiconductor device package 500 is illustrated that includes a plurality of recesses 506 having a generally square horizontal cross-sectional area. The recesses 506 extend into an encapsulant 504 positioned above a substrate 502. The recesses 506 are separated by a through-thickness region of the encapsulant 504 such that an outer surface 508 of the encapsulant 504 extends between the recesses 506. The recesses 506 may form a square opening in the outer surface 508 of the encapsulant 504. In other embodiments, the recesses 506 form an opening having one or more other horizontal cross-sectional shapes, such as circular, triangular, and / or rectangular, in the outer surface 508 of the encapsulant 504. The recesses 506 may constitute at least about 5% of the horizontal area of ​​the encapsulant 504, such as in a range from about 5% of the total horizontal area of ​​the encapsulant 504 to about 70% of the total horizontal area of ​​the encapsulant 504 or from about 40% of the total horizontal area of ​​the outer surface 508 to about 60% of the total horizontal area of ​​the encapsulant 504.

[0075] As described above, the grooves 506 may be horizontally positioned around the horizontal perimeter of the semiconductor die, e.g. Figures 2A to 4C 202a, 202b, 202c, 302a, 302b, 302c, 402a, 402b, 402c, respectively, illustrated in FIG. 202a, 202b, 202c, 302a, 302b, 302c, 402a, 402b, 402c. In other embodiments, the recesses 506 may be positioned to at least partially horizontally overlap the semiconductor die. As described above, one or more of the recesses 506 may be filled with a fill material, such as another molding compound having a different CTE than the material of the encapsulant 504.

[0076] exist Figure 5 In the embodiment illustrated in , the plurality of grooves 506 are arranged in a generally uniform or symmetrical distribution. In other embodiments, the plurality of grooves 506 are arranged in a non-uniform or asymmetrical distribution. For example, the spacing between the plurality of grooves 506 produced by the through-thickness region of the encapsulant 504 may be different between different grooves 506. Some of the plurality of grooves 506 may have a different shape (e.g., horizontal cross-sectional shape) and / or size (e.g., horizontal area and / or major cross-sectional dimension) than other grooves 506 in the encapsulant 504. For example, a groove 506 positioned above (e.g., horizontally overlapping) a semiconductor die may have different properties (e.g., shape, size, arrangement) than a groove 506 arranged outside the horizontal perimeter of the semiconductor die.

[0077] Figure 6A simplified perspective view of a semiconductor device package 600 is illustrated that includes a plurality of recesses 606 having generally rectangular horizontal cross-sectional areas. The recesses 606 extend into an encapsulant 604 positioned above a substrate 602. The recesses 606 are separated by a through-thickness region of the encapsulant 604 such that an outer surface 608 of the encapsulant 604 extends between the recesses 606. The recesses 606 may form long openings in the outer surface 608 of the encapsulant 604, such as rectangular openings or oval openings. In other embodiments, the recesses 606 form openings in the outer surface 608 of the encapsulant 604 having other abstract shapes, such as a "C" shaped opening, an "E" shaped opening, etc. As described above, the shape of the opening may be determined based on the conductive structure of the substrate 602 or a semiconductor die (not shown). The openings defined by the grooves 606 in the outer surface 608 may constitute at least about 5% of the total horizontal area of ​​the encapsulant 604, such as in a range from about 5% to about 70% of the total horizontal area of ​​the encapsulant 604 or from about 40% to about 60% of the total horizontal area of ​​the encapsulant 604. As described above, one or more of the grooves 606 may be filled with a filler material, such as another molding compound having a different CTE than the material of the encapsulant 604.

[0078] As described above, the grooves 606 may be horizontally positioned around the horizontal perimeter of the semiconductor die, e.g. Figures 2A to 4C In other embodiments, the recess 606 may be positioned to at least partially horizontally overlap the semiconductor die.

[0079] exist Figure 6 , the plurality of grooves 506 are arranged in a generally symmetrical distribution. In other embodiments, the plurality of grooves 506 are arranged in an asymmetrical distribution. For example, the spacing between the plurality of grooves 606 created by the through-thickness region of the encapsulant 604 may be different between different grooves 606. Some of the plurality of grooves 606 may have a different shape (e.g., horizontal cross-sectional shape) and / or size (e.g., horizontal area and / or major cross-sectional dimension) than other grooves 606 in the encapsulant 604. For example, a groove 606 positioned above (e.g., horizontally overlapping) a semiconductor die may have different properties (e.g., shape, size, arrangement) than a groove 606 arranged outside the horizontal perimeter of the semiconductor die.

[0080] exist Figure 6, the recesses 606 are arranged in an arrangement substantially parallel to the outer edges of the encapsulant 604 and / or the semiconductor die. In other embodiments, one or more of the recesses 606 are arranged to extend horizontally at an angle relative to the outer edges of the encapsulant 604 and one or more of the semiconductor dies, such as diagonally across the upper surface of the semiconductor device package 600. In some embodiments, the semiconductor device package 600 or 500 includes a combination of both recesses 506 and long recesses 606 extending into the associated encapsulant 504, 604.

[0081] A microelectronic device (eg, semiconductor device package 100, 400 including the stacked structure of the present disclosure) may be included in an embodiment of an electronic system of the present disclosure. For example, Figure 7 is a block diagram of an electronic system 700 according to an embodiment of the present disclosure. The electronic system 700 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet computer, such as (for example) or Tablet computers, electronic books, navigation devices, etc. The electronic system 700 includes at least one memory device 702. For example, the memory device 702 may include an embodiment of a semiconductor device package previously described herein (e.g., previously referenced Figures 1 to 6 The semiconductor device packages 100, 200A, 200B, 200C, 300A, 300B, 300C, 400A, 400B, 400C, 500 or 600 described herein.

[0082] The electronic system 700 may further include at least one electronic signal processor device 704 (commonly referred to as a "microprocessor"). The electronic signal processor device 704 may optionally include an embodiment of one or more of the microelectronic devices and microelectronic device structures previously described herein. The electronic system 700 may further include one or more input devices 706 for inputting information into the electronic system 700 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 700 may further include one or more output devices 708 for outputting information (e.g., visual or audio output) to the user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 706 and the output device 708 may constitute a single touch screen device that can be used to input information to the electronic system 700 and to output visual information to the user. The input device 706 and the output device 708 may be in electrical communication with one or more of the memory device 702 and the electronic signal processor device 704.

[0083] Thus, an embodiment of the present disclosure includes a microelectronic device. The device includes a semiconductor die operatively coupled to a base structure. The device further includes an encapsulant substantially surrounding the semiconductor die. The device also includes one or more grooves extending vertically from an upper surface of the encapsulant to one or more locations located at or near the upper surface of the base structure.

[0084] Another embodiment of the present disclosure includes an electronic system. The system includes: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device. The memory device includes a semiconductor die coupled to a base structure. The memory device further includes an encapsulant substantially surrounding the semiconductor die. The memory device also includes a recess defined in the encapsulant.

[0085] Other embodiments of the present disclosure include a method of forming a microelectronic device. The method includes positioning a semiconductor die on a substrate. The method further includes encapsulating the semiconductor die in a first molding material. The method also includes forming one or more grooves in the first molding material. The method further includes heating the microelectronic device after forming the one or more grooves.

[0086] Embodiments of the present disclosure provide microelectronic devices or semiconductor device packages that are configured to provide an escape path to evacuate moisture from within the respective devices or packages. When the device is heated during various forming and curing processes, moisture trapped within the device expands into vapor. Promoting fluid and vapor evacuation can reduce vapor pressure within the respective devices and packages, which in turn can reduce device failures caused by vapor pressure, such as delamination, shorts, or open connections.

[0087] Embodiments of the present disclosure also provide options for reducing the volume of material having a different CTE than other materials in the corresponding package. Reducing the volume of material having a different CTE can result in reduced warping experienced by the corresponding device and package. Other embodiments can further control the warping of the associated device or package by providing additional materials having a CTE selected to inhibit or induce warping of the associated device or package. Controlling warping can facilitate matching the warping profile of an adjacent package or device to which the associated device or package will be coupled. Matching warping profiles can facilitate better connection between two devices or packages and improve the yield of the device.

[0088] Non-limiting exemplary embodiments include:

[0089] Embodiment 1: A microelectronic device comprising: a semiconductor die operatively coupled to a base structure; and an encapsulant substantially surrounding the semiconductor die; and one or more recesses extending vertically from an upper surface of the encapsulant to one or more locations at or near an upper surface of the base structure.

[0090] Embodiment 2: The microelectronic device of Embodiment 1, wherein a lower boundary of the one or more recesses is vertically positioned at an interface between the semiconductor die and the base structure.

[0091] Embodiment 3: The microelectronic device of any one of embodiments 1 and 2, wherein the one or more recesses are positioned outside a horizontal area of ​​the semiconductor die.

[0092] Embodiment 4: The microelectronic device of any one of Embodiments 1 to 3, wherein a lower boundary of the one or more recesses is vertically positioned between an upper surface of the semiconductor die and the upper surface of the base structure.

[0093] Embodiment 5: A microelectronic device according to any one of embodiments 1 to 4, further comprising one or more additional grooves extending vertically through a portion of the encapsulant within a horizontal region of the semiconductor die, the one or more additional grooves extending vertically from the upper surface of the encapsulant to one or more additional locations located at or near the upper surface of the semiconductor die.

[0094] Embodiment 6: The microelectronic device of any one of Embodiments 1 to 5, further comprising a filling material substantially filling at least one of the one or more recesses.

[0095] Embodiment 7: The microelectronic device of Embodiment 6, wherein the fill material comprises a material having a coefficient of thermal expansion (CTE) less than that of the encapsulant.

[0096] Embodiment 8: The microelectronic device of any one of Embodiments 1 to 7, wherein one or more grooves individually exhibit a rectangular vertical cross-sectional shape or a triangular vertical cross-sectional shape.

[0097] Embodiment 9: The microelectronic device of any one of embodiments 1 to 8, wherein the one or more grooves are horizontally positioned outside horizontal areas of the base structure and the conductive structures of the semiconductor die.

[0098] Embodiment 10: An electronic system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising: a semiconductor die coupled to a base structure; an encapsulant substantially surrounding the semiconductor die; and a recess defined in the encapsulant.

[0099] Embodiment 11: The electronic system of Embodiment 10, wherein the groove is horizontally positioned outside a horizontal area of ​​the semiconductor die.

[0100] Embodiment 12: The electronic system of Embodiment 11, wherein the recess portion is defined by two substantially vertical sidewalls of the encapsulant oriented parallel to each other.

[0101] Embodiment 13: The electronic system of any of Embodiments 11 and 12, wherein the recess portion is defined by two side walls of the encapsulant converging at an angle to each other.

[0102] Embodiment 14: The electronic system of Embodiment 13, wherein the angle is in a range from about 1° to about 60°.

[0103] Embodiment 15: The electronic system according to any one of embodiments 10 to 14, wherein the groove vertically extends to the upper surface of the base structure.

[0104] Embodiment 16: A method of forming a microelectronic device, the method comprising: positioning a semiconductor die over a substrate; encapsulating the semiconductor die in a first molding material; forming one or more recesses in the first molding material; and heating the microelectronic device after forming the one or more recesses.

[0105] Embodiment 17: The method of Embodiment 16, further comprising filling at least one of the one or more recesses with a second molding material having a second coefficient of thermal expansion (CTE) different from the first CTE of the first molding material.

[0106] Embodiment 18: The method of Embodiment 17, wherein filling the at least one of the one or more recesses with the second molding material comprises filling a recess positioned vertically above and within a horizontal region of the semiconductor die with the second molding material.

[0107] Embodiment 19: The method of any one of Embodiments 16 to 18, wherein forming one or more recesses in the first molding material comprises forming at least one of the one or more recesses at least partially horizontally positioned outside a horizontal region of the semiconductor die.

[0108] Embodiment 20: The method of any of Embodiments 16 to 19, wherein forming the one or more grooves in the first molding material comprises forming the one or more grooves using complementary protrusions extending from a molding.

[0109] The embodiments of the present disclosure described above and illustrated in the accompanying drawings do not limit the scope of the present invention, as these embodiments are merely examples of embodiments of the present invention, which are defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of the present disclosure. In fact, various modifications of the present disclosure, such as alternative useful combinations of the described elements, can be understood from the description by those skilled in the art, in addition to those shown and described herein. Such modifications and embodiments are also intended to fall within the scope of the appended claims and their legal equivalents.

Claims

1. A microelectronic device comprising: a semiconductor die operatively coupled to the base structure; and an encapsulant substantially surrounding the semiconductor die; and One or more grooves extend vertically from the upper surface of the encapsulant to one or more locations at or near the upper surface of the base structure. 2 . The microelectronic device of claim 1 , wherein a lower boundary of the one or more recesses is vertically positioned at an interface between the semiconductor die and the base structure. 3 . The microelectronic device of claim 1 , wherein the one or more recesses are positioned outside a horizontal area of ​​the semiconductor die. 4 . The microelectronic device of claim 1 , wherein a lower boundary of the one or more recesses is positioned vertically between an upper surface of the semiconductor die and the upper surface of the base structure.

5. The microelectronic device of claim 1 , further comprising one or more additional recesses extending vertically through a portion of the encapsulant within a horizontal region of the semiconductor die, the one or more additional recesses extending vertically from the upper surface of the encapsulant to one or more additional locations at or near the upper surface of the semiconductor die.

6. The microelectronic device of any one of claims 1 to 5, further comprising a filling material substantially filling at least one of the one or more recesses. 7 . The microelectronic device of claim 6 , wherein the fill material comprises a material having a coefficient of thermal expansion (CTE) less than that of the encapsulant.

8. The microelectronic device of any one of claims 1 to 5, wherein one or more grooves individually exhibit a rectangular vertical cross-sectional shape or a triangular vertical cross-sectional shape.

9. The microelectronic device of any one of claims 1 to 5, wherein the one or more grooves are horizontally positioned outside horizontal areas of the base structure and conductive structures of the semiconductor die.

10. An electronic system comprising: Input device; Output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and comprising: a semiconductor die coupled to a base structure; an encapsulant substantially surrounding the semiconductor die; and A recess is defined in the encapsulant. The electronic system of claim 10 , wherein the groove is horizontally positioned outside a horizontal area of ​​the semiconductor die. 12 . The electronic system of claim 11 , wherein the recess portion is defined by two substantially vertical sidewalls of the encapsulant oriented parallel to each other. 13 . The electronic system of claim 11 , wherein the recess portion is defined by two side walls of the encapsulant converging with each other at an angle.

14. The electronic system of claim 13, wherein the angle is in a range from about 1° to about 60°.

15. The electronic system according to any one of claims 10 to 14, wherein the groove vertically extends to an upper surface of the base structure.

16. A method of forming a microelectronic device, the method comprising: positioning a semiconductor die on a substrate; encapsulating the semiconductor die in a first molding material; forming one or more recesses in the first molding material; and The microelectronic device is heated after forming the one or more recesses.

17. The method of claim 16, further comprising filling at least one of the one or more recesses with a second molding material having a second coefficient of thermal expansion (CTE) different from a first coefficient of thermal expansion (CTE) of the first molding material. 18 . The method of claim 17 , wherein filling the at least one of the one or more recesses with the second molding material comprises filling a recess positioned vertically above and within a horizontal region of the semiconductor die with the second molding material.

19. The method of any one of claims 16 to 18, wherein forming one or more recesses in the first molding material comprises forming at least one of the one or more recesses at least partially horizontally positioned outside of a horizontal region of the semiconductor die.

20. The method of any one of claims 16-18, wherein forming the one or more grooves in the first molding material comprises forming the one or more grooves using complementary protrusions extending from a molding.

Images