Semiconductor die stack architecture and method of connecting same

Abstract

The semiconductor dies in the stack of semiconductor dies are interconnected using metal wires instead of bonding wires or through silicon vias (TSVs). The semiconductor dies in the stack are arranged in a stepped configuration such that a stepped corner is defined between a top surface of a first semiconductor die in the stack and a sidewall of a second semiconductor die in the stack. A step slope is formed in the step corner. The stepped slope defines a ramp extending between the top surface of the first semiconductor die and the top surface of the second semiconductor die. A metal line is formed over a bonding pad associated with the first semiconductor die, the stepped ramp, and a bonding pad associated with the second semiconductor die.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 510,912, filed on June 29, 2023, entitled “SEMICONDUCTOR DIE STACKING ARCHITECTURE AND CONNECTION METHOD THEREFORE,” the entire disclosure of which is hereby incorporated by reference in its entirety. Background Art

[0003] Die stacking is a process in which multiple semiconductor dies are stacked on top of each other and interconnected to form a single unit. In current die stacking architectures, bonding wires or through silicon vias (TSVs) are used to connect different semiconductor dies in a semiconductor stack.

[0004] However, bond wires can limit the performance capabilities of a semiconductor stack. For example, bond wires are often associated with one or more parasitic effects that prevent the semiconductor stack from performing at a very high level. Although TSVs can be used in place of bond wires and enable a semiconductor stack to perform at a very high level, forming TSVs in the various semiconductor dies of a semiconductor stack is expensive in terms of both time and cost.

[0005] Therefore, it would be beneficial to interconnect the semiconductor dies of a semiconductor stack without the use of bonding wires or TSVs while enabling the semiconductor stack to achieve high performance capabilities. Summary of the invention

[0006] The present application describes an architecture for stacking semiconductor dies and interconnecting the semiconductor dies by metal wires (also referred to herein as "transmission lines") instead of using bonding wires or through silicon vias (TSVs). Metal wires are less susceptible to parasitic effects when compared to bonding wires. Metal wires are also cheaper to manufacture when compared to TSVs. Metal wires can also enable the stacking of semiconductor dies to be performed at a level comparable to the stacking of semiconductor dies interconnected using TSVs.

[0007] As will be described in more detail herein, semiconductor dies are arranged in a stack and can be used in a semiconductor package. The stack of semiconductor dies can be arranged in a stepped configuration such that a step corner is formed or defined between a top surface of a first semiconductor die in the stack and a sidewall of a second semiconductor die in the stack. A step slope is formed in the step corner. The step slope defines an inclined surface extending between the top surface of the first semiconductor die and the top surface of the second semiconductor die. Metal lines are formed over a bonding pad associated with the first semiconductor die, the step slope, and a bonding pad associated with the second semiconductor die.

[0008] Because the metal wire extends on the slope of the step slope, the interconnection length between the bonding pad associated with the first semiconductor die and the bonding pad associated with the second semiconductor die is shorter when compared to the interconnection length using bonding wires. In addition, the use of metal wires instead of bonding wires enables the use of smaller bonding pads. Smaller bonding pads also enable smaller / tighter spacing between various bonding pads on a particular semiconductor die. Therefore, more interconnections can be made between various semiconductor dies. Therefore, semiconductor packaging can be performed at a higher level / frequency when compared to semiconductor packaging using bonding wires.

[0009] Thus, examples of the present disclosure describe a stack of semiconductor dies for semiconductor packaging. In one example, the stack of semiconductor dies is formed by a first semiconductor die and a second semiconductor die. The first semiconductor die and the second semiconductor die define a step corner between a surface of the first semiconductor die and a sidewall of the second semiconductor die. A step slope is formed in the step corner. A transmission line is formed over a first bonding pad associated with the first semiconductor die, the step slope, and a second bonding pad associated with the second semiconductor die.

[0010] The present application also describes a method for manufacturing a stack of semiconductor die for semiconductor packaging. In one example, the method includes stacking a second semiconductor die on a first semiconductor die to form a semiconductor die stack. The semiconductor die stack is defined at a stepped corner between a surface of the first semiconductor die and a sidewall of the second semiconductor die. A stepped slope is formed in the stepped corner. In addition, a transmission line is formed over a first bonding pad associated with the first semiconductor die, the stepped slope, and a second bonding pad associated with the second semiconductor die.

[0011] In another example, the present application describes a semiconductor package including a stack of semiconductor dies formed by a first semiconductor die and a second semiconductor die. In one example, the first semiconductor die and the second semiconductor die are defined at a stepped corner between a surface of the first semiconductor die and a sidewall of the second semiconductor die. The semiconductor package also includes a ramp device and a transmission device formed in the stepped corner. The transmission device is formed above a first connection device associated with the first semiconductor die, the ramp device, and a second connection device associated with the second semiconductor die.

[0012] This Summary is provided to introduce some concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Non-limiting and non-exhaustive examples are described with reference to the following figures.

[0014] Figure 1 A stack of semiconductor dies for use in a semiconductor package according to one example is shown.

[0015] Figure 2 A first operation in a manufacturing process is shown in which a plurality of semiconductor dies are stacked together to form a stack of semiconductor dies according to one example.

[0016] Figure 3 A second operation in a fabrication process is shown in which a step slope is formed in each step corner of a stack of semiconductor dies according to an example.

[0017] Figure 4 A third operation in a manufacturing process according to one example is shown in which a photoresist layer is disposed on a stack of semiconductor dies.

[0018] Figure 5 A fourth operation in a manufacturing process is shown according to one example, in which a patterning process is used to write or expose one or more patterns on bonding pads and / or step slopes of a stack of semiconductor dies.

[0019] Figure 6 A fifth operation in a manufacturing process is shown in which a metal layer is deposited on exposed bond pads and / or step slopes of a stack of semiconductor dies according to one example.

[0020] Figure 7 A sixth operation in a fabrication process according to one example is shown in which another photoresist layer is disposed over the stack of semiconductor dies.

[0021] Figure 8 A seventh operation in a manufacturing process is shown in which an electroplating process is performed on the metal layer according to one example.

[0022] Fig. 9 An eighth operation in a manufacturing process is shown in which a first photoresist layer and a second photoresist layer are removed from a stack of semiconductor dies according to an example. DETAILED DESCRIPTION

[0023] In the following detailed description, reference is made to the accompanying drawings which form a part of the detailed description, and in which specific embodiments or examples are shown by way of illustration. These aspects may be combined, other aspects may be utilized, and structural changes may be made without departing from the present disclosure. Therefore, the following detailed description should not be regarded as having a limiting meaning, and the scope of the present invention is defined by the appended claims and their equivalents.

[0024] Current semiconductor die stacking architectures require the use of bonding wires or through silicon vias (TSVs) to connect the various semiconductor dies in the stack of semiconductor dies. However, bonding wires are subject to parasitic effects (e.g., resistance, inductance) that can degrade the overall performance of the stack of semiconductor dies. Although TSVs address the parasitic effects of bonding wires, forming TSVs in a stack of semiconductor dies is time-intensive and expensive.

[0025] In order to solve the above problems, the present application describes a semiconductor die stacking architecture, in which metal lines (also referred to herein as "transmission lines") are used as interconnects instead of bonding wires or through-silicon vias (TSVs). For example, a semiconductor package includes a stack of semiconductor dies. The semiconductor dies are arranged in a stepped configuration so that a step corner is defined between the top surface of a first semiconductor die and the sidewall of a second semiconductor die. During manufacturing or processing, a step slope is formed in the step corner. The step slope is defined as an inclined surface extending between the top surface of the first semiconductor die and the top surface of the second semiconductor die. A metal line (or metal layer) is then formed over a bonding pad associated with the first semiconductor die, the step slope, and a bonding pad associated with the second semiconductor die.

[0026] Replacing the bonding wires with metal wires reduces the length of the interconnections between different semiconductor die in the stack of semiconductor die. For example, the metal wires extend upward (or downward) from the bonding pads on the first semiconductor die along the slope of the step slope and cover the bonding pads on the second semiconductor die. Therefore, when compared with the interconnections formed by the bonding wires, the length of the interconnections between the bonding pads is shorter.

[0027] In addition, metal wires enable bond pads to be smaller when compared to bond pads typically used with bond wires. Because the bond pads are smaller, the spacing between bond pads can also be smaller when compared to the spacing between bond pads used with bond wires. Due to the smaller spacing between bond pads, more bond pads and associated interconnects can be added to the semiconductor stack, which helps improve the performance of the semiconductor package. Metal wires can also enable more semiconductor dies to be included in the stack of semiconductor dies when compared to bond wire solutions.

[0028] Metal wires are also cheaper to manufacture when compared to TSVs.However, metal wires may also enable stacking of semiconductor dies to be performed at a level comparable to stacking of semiconductor dies that are interconnected using TSVs.

[0029] Accordingly, the present application describes many technical benefits, including but not limited to: enabling the manufacture of high-density semiconductor packages having an increased number of semiconductor dies compared to current semiconductor packages; increasing the number of interconnections between semiconductor dies in a stack of semiconductor dies; and improving the electrical performance of the semiconductor package when compared to semiconductor packages that use bonding wires when making electrical connections.

[0030] will be relative to Figures 1 to 9 These benefits and other examples are shown and described in more detail.

[0031] Figure 1 A stack 100 of semiconductor dies for semiconductor packaging according to one example is shown. The stack 100 of semiconductor dies includes a first semiconductor die 105, a second semiconductor die 110, a third semiconductor die 115, and a fourth semiconductor die 120. In one example, each semiconductor die is a memory die, such as a NAND flash memory die. Although NAND flash memory dies are specifically mentioned, the memory die can be any type of volatile or non-volatile memory die. In another example, the stack 100 of semiconductor dies can include any type of stackable semiconductor die and / or stackable integrated circuit.

[0032] In one example, the first semiconductor die 105 is disposed or mounted on a surface of a substrate 125 or printed circuit board (PCB). The substrate 125 may include or otherwise be associated with one or more conductive balls 130 that enable the semiconductor package to be electrically and / or communicatively coupled to a computing component or electronic device.

[0033] The second semiconductor die 110 is mounted on the top surface of the first semiconductor die 105. In one example, the second semiconductor die 105 is mounted on the first semiconductor die 105 using a die attach film (DAF). Although DAF is specifically mentioned, other mounting techniques may be used to mount the second semiconductor die 110 on the top surface of the first semiconductor die 105. Likewise, the third semiconductor die 115 is mounted on the top surface of the second semiconductor die 110, and the fourth semiconductor die 120 is mounted on the top surface of the third semiconductor die 115.

[0034] Each of the semiconductor dies is stacked on top of each other or otherwise arranged in a stepped configuration. Thus, a step corner 135 may be defined between a top surface of one semiconductor die and a sidewall of another semiconductor die. For example, the step corner 135 may be defined by a top surface of the first semiconductor die 105 and a sidewall of the second semiconductor die 110. The length and / or height of the step corner 135 may vary depending on the thickness or height of each semiconductor die, the length of each semiconductor die, and / or the position of each semiconductor die relative to the semiconductor die on which it is stacked.

[0035] In one example, a step slope 150 is disposed or otherwise formed in each step corner 135. The step slope 150 may be formed of a polymer or other material. The step slope 150 forms a planar surface (or substantially a planar surface) between the top surface of one semiconductor die and the top surface of another semiconductor die. For example, the step slope 150 may be formed between the top surface of the first semiconductor die 105 and the sidewall of the second semiconductor die 110.

[0036] In one example, the angle of the planar surface of the step slope 150 is between forty-five degrees and twenty degrees (or less). Although a specific range is given, the angle of the planar surface of the step slope 150 can be greater than forty-five degrees. In another example, the angle of the planar surface of the step slope 150 can be based on multiple factors, including but not limited to the thickness or height of each semiconductor die, the length of each semiconductor die, and / or the position of each semiconductor die relative to the semiconductor die on which it is stacked. Although a planar or substantially planar surface is described, the surface of the step slope 150 can be concave or convex.

[0037] Each semiconductor die in the stack 100 of semiconductor dies may also include a bonding pad 140. The bonding pad 140 may be disposed on a top surface of each semiconductor die. The bonding pad 140 may be used to electrically and / or communicatively couple the semiconductor dies to each other and / or to substrate fingers 145 disposed on the substrate 125. Although Figure 1A single bonding pad 140 on each semiconductor die is shown, but each semiconductor die may include multiple bonding pads 140. In one example, the spacing between bonding pads 140 on a particular semiconductor die may be between forty micrometers (μm) and thirty μm (or less). In contrast, the spacing between bonding pads of a stack of semiconductor dies in which bonding wires are used is typically between eighty μm and one hundred μm.

[0038] As previously indicated, the stack of semiconductor dies 100 does not use bonding wires, TSVs, or solder connections to interconnect each semiconductor die. Therefore, higher performance, lower cost, and higher density stacking can be achieved when compared to stacks of semiconductor dies using bonding wires, TSVs, and / or solder connections.

[0039] To achieve higher performance and higher density stacking at a lower cost, metal lines 155 are disposed over the bonding pads 140 and step slopes 150 associated with each semiconductor die. For example, the metal lines 155 may form transmission lines or interconnects between the bonding pads 140 on the first semiconductor die 105 and the bonding pads 140 on the second semiconductor die 110. The metal lines 155 may also extend upward (or downward) along the step slopes 150 disposed between the first semiconductor die 105 and the second semiconductor die 110. The metal lines 155 may also connect the bonding pads 140 of the various semiconductor dies to the substrate fingers 145.

[0040] Because the metal wire 155 extends upward (or downward) along each step slope 150, a shorter interconnection distance is achieved when compared to the interconnection distance using bonding wires. In addition, the metal wire 155 enables the bonding pads 140 to be spaced more closely together (e.g., a spacing between forty micrometers (μm) and thirty μm (or less)), such as previously described. The smaller spacing between the bonding pads 140 means that additional bonding pads 140 and associated transmission lines can be added to the stack 100 of semiconductor dies. When compared to a stack of semiconductor dies that are communicatively coupled using bonding wires, the additional transmission lines can achieve higher performance capabilities. Using metal wires 155 to replace bonding wires can also enable more semiconductor dies to be added to the stack when compared to current bonding wire solutions.

[0041] In one example, metal line 155 can be formed of copper. Although copper is specifically mentioned, other materials can also be used. In another example, metal line 155 is plated with copper (eg, using a copper electroplating process).

[0042] In one example, the stack of semiconductor dies 100 may further include an additional metal layer or ground plane. In one example, the additional metal layer may be used to construct a ground plane. For example, the ground plane may be positioned below the metal line 155 and / or below the step slope 150. In another example, the ground plane may be used to form a transmission line. In such an example, the ground plane may increase the signal integrity of the interconnect lines connecting the various semiconductor dies in the stack of semiconductor dies 100 to the substrate 125.

[0043] Figures 2 to 9 Various operations for fabricating a stack of semiconductor dies are shown and described, wherein the stacked semiconductor dies are interconnected without wirebonds, TSVs, or solder connections. In one example, a stack of semiconductor dies may be fabricated using a semiconductor die stack. Figures 2 to 9 The various operations described are used to produce Figure 1 A stack 100 of semiconductor dies is shown and described.

[0044] Figure 2 2 shows a first operation in a manufacturing process according to one example, in which a plurality of semiconductor dies are stacked together to form a stack 200 of semiconductor dies. Figure 2 As shown, the semiconductor dies are stacked on top of each other and arranged in a staircase configuration.

[0045] For example, the first semiconductor die 205 is stacked on or otherwise coupled to the substrate 225. The second semiconductor die 210 may be stacked on or otherwise coupled to the top surface of the first semiconductor die 205. Likewise, the third semiconductor die 215 may be stacked on the second semiconductor die 210 and the fourth semiconductor die 220 may be stacked on the third semiconductor die 215. Although four semiconductor dies are shown and described, any number of semiconductor dies may be stacked on top of each other to form the stack 200 of semiconductor dies. Additionally, although semiconductor dies are specifically mentioned, the stack 200 of semiconductor dies may include any type of stackable semiconductor dies and / or stackable integrated circuits.

[0046] In one example, a die attach film (DAF) can be used to attach each semiconductor die to another semiconductor die (or substrate 225). Although DAF is specifically mentioned, other materials and / or processes can be used to create the stack 200 of semiconductor dies and / or to secure the semiconductor dies to each other and / or to the substrate 225.

[0047] When the semiconductor dies are stacked in a stepped configuration, a step corner 250 is defined. For example, when the second semiconductor die 210 is stacked on the first semiconductor die 205, the step corner 250 is defined between the top surface of the first semiconductor die 205 and the sidewall of the second semiconductor die 210. Similar step corners 250 may be defined between the substrate 225 and the first semiconductor die 205, between the second semiconductor die 210 and the third semiconductor die 215, and between the third semiconductor die 215 and the fourth semiconductor die 220.

[0048] Each semiconductor die may also include a bonding pad 245. For example, the first semiconductor die 205 may include a bonding pad 245, the second semiconductor die 210 may include a bonding pad 245, and so on. The bonding pad 245 may be formed of a conductive material, such as copper, silver, gold, solder, or another material or combination of materials.

[0049] The substrate 225 may also include bonding pads or other connection mechanisms (e.g., substrate fingers 230). The substrate fingers 230 may be electrically and / or communicatively coupled to one or more traces 235 formed in or otherwise associated with the substrate 225. The traces 235 may also be communicatively and / or electrically coupled to one or more solder balls 240 disposed on a bottom surface of the substrate 225. Although solder balls 240 are specifically mentioned, other connection mechanisms may be used to electrically and / or communicatively couple the substrate 225 to an electronic device or component.

[0050] Figure 3 A second operation in a manufacturing process according to one example is shown, in which a step slope 300 is formed in each step corner 250 of the stack 200 of semiconductor dies. In one example, the step slope 300 is formed of a polymer or other material. The step slope 300 can be used to form a planar or substantially planar surface within each step corner 250 defined by the stack 200 of semiconductor dies. Although a planar or substantially planar surface is specifically mentioned, the surface of the step slope 250 can be concave or convex.

[0051] In one example, the surface of the step ramp 300 may have an angle of about forty-five degrees or less. However, the angle of the planar surface of the step ramp 300 may be based on a number of factors such as previously described.

[0052] The step slope 300 may provide the shortest path between the various bonding pads 245 of different semiconductor dies in the stack 200 of semiconductor dies. In addition, the step slope 300 may also be used to prevent short circuits from occurring between metal lines or transmission lines and the silicon forming the semiconductor dies.

[0053] In one example, the step slope 300 may extend from (or near) the bonding pad 245 on the top surface of the first semiconductor die 205 and extend upward or along the sidewall of the second semiconductor die 210. The step slope 300 may also extend around the top corners of the sidewalls of the second semiconductor die 210 and at least partially along the top surface of the second semiconductor die 210 (e.g., at least partially to the bonding pad 245 on the top surface of the second semiconductor die 210).

[0054] Figure 4 2 shows a third operation in a manufacturing process according to one example, in which a photoresist layer 400 is disposed over the stack 200 of semiconductor dies. Figure 4 As shown, the photoresist layer 400 may be disposed on the substrate 225, the step slope 300, the bonding pad 245, and / or the exposed portion of the substrate finger 230. In one example, the photoresist layer 400 is disposed over the stack 200 of semiconductor dies using a spraying process. The spraying process may be used to achieve a uniform or substantially uniform thickness. Although the spraying process is specifically mentioned, the photoresist layer 400 may be disposed over the stack 200 of semiconductor dies using any suitable technique.

[0055] Figure 5 A fourth operation in a manufacturing process according to one example is shown, in which a patterning process is used to write or expose one or more patterns on the bonding pads 245 and / or the step slopes 300 of the stack of semiconductor dies 200. The patterning process can also be used to write or expose one or more patterns on the substrate fingers 230.

[0056] In one example, the patterning process uses lasers (e.g., laser lithography) or ultraviolet light to create patterns or otherwise expose the bond pads 245, substrate fingers 230, and / or step slopes 300 for further processing. In one example, a laser writer or other mechanism performing the patterning process may be moved in the XY direction and in the Z direction to account for changes in the height of the stack 200 of semiconductor dies.

[0057] Figure 6 A fifth operation in the manufacturing process according to one example is shown in which a metal layer 600 is deposited on the exposed bonding pads 245 and / or the step slope 300 of the stack of semiconductor dies 200. The metal layer 600 may also be disposed on the substrate fingers 230 and / or any exposed photoresist layer 400.

[0058] In one example, the metal layer 600 is used to form a transmission line, metal line, or interconnect of the stack of semiconductor dies 200. The metal layer 600 may be deposited or otherwise formed on the bonding pad 245 and / or the step slope 300 using a vacuum deposition process. Although a vacuum deposition process is specifically mentioned, other thin metal deposition processes may also be used.

[0059] The metal layer 600 may be formed of copper. Although copper is specifically mentioned, other conductive materials such as gold, silver, or a combination of conductive materials may be used to form the metal layer 600.

[0060] Figure 7 1 shows a sixth operation in a manufacturing process according to one example, in which another photoresist layer 700 is disposed over the stack of semiconductor dies 200. In addition to adding the second photoresist layer 700, a second patterning process may also be used to write or expose one or more patterns on the metal layer 600 formed over the bonding pads 245, the step slopes 300, and / or the substrate fingers 230. In one example, the second photoresist layer 700 and the second patterning process may be similar to the above with respect to Figure 4 and Figure 5 The process described.

[0061] In addition, the sixth operation may also be used to form or expose electroplated contacts 710 associated with the stack of semiconductor dies 200. The electroplated contacts 710 may be used to facilitate current flow during the second metal deposition process, such as to Figure 8 as described.

[0062] Figure 8 A seventh operation in a manufacturing process according to one example is shown, in which an electroplating process is performed on the metal layer 600. In one example, the electroplating process is used to form a coating 800 (enlarged for illustration purposes) or plate over the exposed metal layer 600. The coating 800 can be formed on the entire metal layer 600 or on a portion of the metal layer 600. The coating 800 can be used to improve or otherwise enhance the conductivity of the metal layer 600 on the stack 200 of semiconductor dies. In one example, the coating 800 is formed of copper. Although copper is specifically mentioned, other conductive materials can also be used.

[0063] Fig. 9 An eighth operation in the manufacturing process according to one example is shown in which the first photoresist layer and the second photoresist layer are removed from the stack 200 of semiconductor dies. Fig. 9 The stack 200 of semiconductor dies shown can be used as part of a semiconductor package. In another example, the stack 200 of semiconductor dies can be similar to that of Figure 1 A stack 100 of semiconductor dies is shown and described.

[0064] Thus, examples of the present disclosure describe a stack of semiconductor die for semiconductor packaging, including: a first semiconductor die; a second semiconductor die, the second semiconductor die stacked on top of the first semiconductor die, the first semiconductor die and the second semiconductor die defining a step corner between a surface of the first semiconductor die and a sidewall of the second semiconductor die; a step slope, the step slope formed in the step corner; and a transmission line, the transmission line formed on a first bonding pad associated with the first semiconductor die, the step slope, and a second bonding pad associated with the second semiconductor die, wherein the transmission line electrically connects the first bonding pad and the second bonding pad. In one example, the step slope is formed of a polymer. In one example, the step slope forms an angle of approximately forty-five degrees between the surface of the first semiconductor die and the sidewall of the second semiconductor die. In one example, the step slope forms an angle of less than forty-five degrees between the surface of the first semiconductor die and the sidewall of the second semiconductor die. In one example, the stack of semiconductor dies further comprises a metal coating disposed over the transmission line, the first bonding pad, and the second bonding pad. In one example, the metal coating is copper. In one example, the first semiconductor die is associated with a plurality of bonding pads, and wherein each of the plurality of bonding pads has a pitch of approximately thirty micrometers (μm).

[0065] The present application also describes a method for assembling a stack of semiconductor die for semiconductor packaging, comprising: stacking a second semiconductor die on a first semiconductor die to form the stack of semiconductor die, the first semiconductor die and the second semiconductor die defining a stepped corner between a surface of the first semiconductor die and a sidewall of the second semiconductor die; forming a stepped slope in the stepped corner; and forming a transmission line over a first bonding pad associated with the first semiconductor die, the stepped slope, and a second bonding pad associated with the second semiconductor die, wherein the transmission line electrically connects the first bonding pad and the second bonding pad. In one example, the method further comprises, before forming the transmission line, disposing a photoresist layer over the stepped slope, the first bonding pad, and the second bonding pad. In one example, the method further comprises preparing the first bonding pad and the second bonding pad for the transmission line using a laser lithography process based at least in part on disposing the photoresist layer over the first bonding pad and the second bonding pad. In one example, the method further includes forming a metal coating over at least a portion of the transmission line, the first bonding pad, and the second bonding pad. In one example, the metal coating is copper. In one example, the step slope is formed of a polymer.

[0066] In another example, a stack of semiconductor dies for semiconductor packaging is disclosed. In one example, the stack of semiconductor dies includes: a first semiconductor die; a second semiconductor die, the second semiconductor die is stacked on top of the first semiconductor die, the first semiconductor die and the second semiconductor die are defined in a stepped corner between the surface of the first semiconductor die and the sidewall of the second semiconductor die; a ramp device, the ramp device is formed in the stepped corner; and a transmission device, the transmission device is formed on a first connection device associated with the first semiconductor die, the ramp device, and a second connection device associated with the second semiconductor die, wherein the transmission device electrically connects the first connection device and the second connection device of the first semiconductor die and the second semiconductor die. In one example, the ramp device is formed of a polymer. In one example, the ramp device forms an angle of approximately forty-five degrees between the surface of the first semiconductor die and the sidewall of the second semiconductor die. In one example, the ramp device forms an angle of less than forty-five degrees between the surface of the first semiconductor die and the sidewall of the second semiconductor die. In one example, the stack of semiconductor dies further comprises a coating device disposed over the transmission device, the first connection device, and the second connection device. In one example, the coating device is comprised of copper. In one example, the first semiconductor die is associated with a plurality of connection devices, and wherein each of the plurality of connection devices has a pitch of approximately thirty micrometers (μm).

[0067] The description and illustration of one or more aspects provided in this disclosure are not intended to limit or restrict the scope of the disclosure in any way. The aspects, examples, and details provided in this disclosure are considered sufficient to convey ownership and enable others to make and use the best mode of the disclosure claimed.

[0068] The disclosure claimed should not be construed as limited to any aspect, example or detail provided in the disclosure. Whether shown and described in combination or individually, various features are intended to be selectively rearranged, included or omitted to produce various embodiments with a set of specific features. Having provided the description and illustration of the present application, those skilled in the art may envision changes, modifications and alternative aspects that fall within the spirit of the broader aspects of the overall inventive concept embodied in the present application without departing from the broader scope of the disclosure claimed.

[0069] References to elements herein using names such as "first," "second," etc. generally do not limit the number or order of those elements. Rather, these names can be used as a method of distinguishing two or more elements or instances of elements. Thus, reference to a first and a second element does not mean that only two elements can be used, or that the first element precedes the second element. Additionally, unless otherwise specified, a group of elements may include one or more elements.

[0070] A term in the form of "at least one of A, B, or C" or "A, B, C, or any combination thereof" used in the specification or claims means "A or B or C, or any combination of these elements". For example, this term may include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, or 2A and B, etc. As an additional example, "at least one of A, B, or C" is intended to cover A, B, C, AB, -AC, BC, and ABC, and multiples of the same member. Similarly, "at least one of A, B, and C" is intended to cover A, B, C, AB, AC, BC, and ABC, and multiples of the same member.

[0071] Similarly, as used herein, a phrase referring to a list of items linked with "and / or" refers to any combination of items. As an example, "A and / or B" is intended to cover A alone, B alone, or A and B together. As another example, "A, B, and / or C" is intended to cover A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

Claims

1. A stack of semiconductor dies for semiconductor packaging, comprising: a first semiconductor die; a second semiconductor die stacked on top of the first semiconductor die, the first semiconductor die and the second semiconductor die defining a stepped corner between a surface of the first semiconductor die and a sidewall of the second semiconductor die; a step slope formed in the step corner; and A transmission line is formed on a first bonding pad associated with the first semiconductor die, the stepped ramp, and a second bonding pad associated with the second semiconductor die, wherein the transmission line electrically connects the first bonding pad and the second bonding pad. 2 . The stack of semiconductor dies of claim 1 , wherein the step slope is formed of a polymer.

3. The stack of semiconductor dies of claim 1, wherein the step slope forms an angle of approximately forty-five degrees between the surface of the first semiconductor die and the sidewall of the second semiconductor die.

4. The stack of semiconductor dies of claim 1, wherein the step slope forms an angle of less than forty-five degrees between the surface of the first semiconductor die and the sidewall of the second semiconductor die. 5 . The stack of semiconductor dies of claim 1 , further comprising a metal coating disposed over the transmission line, the first bonding pad, and the second bonding pad.

6. The stack of semiconductor dies of claim 5, wherein the metal coating is copper.

7. The stack of semiconductor dies of claim 1, wherein the first semiconductor die is associated with a plurality of bonding pads, and wherein each of the plurality of bonding pads has a pitch of approximately thirty micrometers (μm).

8. A method for assembling a stack of semiconductor die for use in a semiconductor package, comprising: stacking a second semiconductor die on a first semiconductor die to form a stack of the semiconductor die, the first semiconductor die and the second semiconductor die defining a stepped corner between a surface of the first semiconductor die and a sidewall of the second semiconductor die; forming a step slope in the step corner; as well as A transmission line is formed over a first bonding pad associated with the first semiconductor die, the stepped ramp, and a second bonding pad associated with the second semiconductor die, wherein the transmission line electrically connects the first bonding pad and the second bonding pad. 9 . The method of claim 8 , further comprising providing a photoresist layer over the stepped slope, the first bonding pad, and the second bonding pad before forming the transmission line.

10. The method of claim 9, further comprising preparing the first and second bond pads for the transmission line using a laser lithography process based at least in part on providing the photoresist layer over the first and second bond pads. 11 . The method of claim 8 , further comprising forming a metal coating over at least a portion of the transmission line, the first bonding pad, and the second bonding pad.

12. The method of claim 11, wherein the metal coating is copper.

13. The method of claim 8, wherein the step slope is formed of a polymer.

14. A stack of semiconductor dies for semiconductor packaging, comprising: a first semiconductor die; a second semiconductor die stacked on top of the first semiconductor die, the first semiconductor die and the second semiconductor die defining a stepped corner between a surface of the first semiconductor die and a sidewall of the second semiconductor die; a ramp device formed in the step corner; and A transmission device is formed on a first connection device associated with the first semiconductor die, the ramp device, and a second connection device associated with the second semiconductor die, wherein the transmission device electrically connects the first connection device and the second connection device of the first semiconductor die and the second semiconductor die.

15. The stack of semiconductor dies of claim 14, wherein the ramp means is formed of a polymer.

16. The stack of semiconductor dies of claim 14, wherein the ramp means forms an angle of approximately forty-five degrees between the surface of the first semiconductor die and the sidewall of the second semiconductor die.

17. The stack of semiconductor dies of claim 14, wherein the ramp means forms an angle of less than forty-five degrees between the surface of the first semiconductor die and the sidewall of the second semiconductor die.

18. The stack of semiconductor dies according to claim 14, further comprising a coating device disposed over the transfer device, the first connection device, and the second connection device.

19. The stack of semiconductor dies according to claim 18, wherein the coating device consists of copper.

20. The stack of semiconductor dies of claim 14, wherein the first semiconductor die is associated with a plurality of connection devices, and wherein each of the plurality of connection devices has a pitch of approximately thirty micrometers (μm).

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