Integrated circuit package and method of forming same

Abstract

An integrated circuit package and a method of forming the same are provided. An integrated circuit package may include a first die having a first substrate and a first via extending through the first substrate, a first gap-fill layer along sidewalls of the first substrate, an isolation layer on a surface of the first substrate and a surface of the first gap-fill layer, a first bonding layer on the isolation layer; and a first bonding pad in the first bonding layer. The isolation layer may overlap an interface between a sidewall of the first substrate and a sidewall of the first gap fill layer, and may extend on a sidewall of the first via.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit packages and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density is due to iterative reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, so too has the need for smaller and more innovative semiconductor die packaging technologies. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, an integrated circuit package is provided, comprising: a first die, wherein the first die comprises a first substrate and a first through hole extending through the first substrate; a first gap filling layer, along the side wall of the first substrate; an isolation layer, located on a surface of the first substrate and a surface of the first gap filling layer, wherein the isolation layer overlaps with an interface between the side wall of the first substrate and the side wall of the first gap filling layer, and wherein the isolation layer extends on the side wall of the first through hole; a first bonding layer, located on the isolation layer; and a first bonding pad, located in the first bonding layer.

[0004] According to another aspect of an embodiment of the present application, an integrated circuit package is provided, comprising: a first die, wherein the first die comprises a first substrate and a first through hole protruding from a top surface of the first substrate; a first gap filling layer surrounding the first die, wherein a thermal expansion coefficient of the first gap filling layer is different from a thermal expansion coefficient of the first substrate; an isolation layer in contact with a top surface of the first substrate and a top surface of the first gap filling layer, wherein the isolation layer overlaps an interface between the first substrate and the first gap filling layer, and wherein the first through hole extends through the isolation layer; a first bonding layer located on the isolation layer; a first bonding pad located in the first bonding layer; and a second die, wherein the second die comprises a second bonding layer and a second bonding pad located in the second bonding layer, wherein the second bonding layer is bonded to the first bonding layer, and wherein the second bonding pad is bonded to the first bonding pad.

[0005] According to another aspect of an embodiment of the present application, a method for forming an integrated circuit package is provided, the method comprising: attaching a first tube core to a carrier, wherein the first tube core includes a first substrate and a first through hole located in the first substrate; forming a first gap filling layer on the side wall of the first tube core, wherein the first gap filling layer includes a dielectric material; removing a portion of the first gap filling layer and a portion of the first substrate to expose the first through hole; forming an isolation layer on the first substrate and the first gap filling layer, wherein the isolation layer overlaps with an interface between the first substrate and the first gap filling layer, and wherein the first through hole extends into the isolation layer; forming a first bonding layer above the isolation layer; and forming a first bonding pad in the first bonding layer, wherein the first bonding pad is in contact with the first through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14A , Fig. 14B , Fig.15A and Fig. 15B Cross-sectional and top views are shown of intermediate stages in the formation of an integrated circuit package in accordance with some embodiments. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0009] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0010] An integrated circuit package having an isolation layer at an interface between a semiconductor device and a sealant and a method for forming the same are provided. According to some embodiments, one or more lower integrated circuit dies may be sealed in a lower gap filling layer, and an isolation layer may be formed on the surface of the lower gap filling layer and the lower integrated circuit die. The isolation layer may be located above the interface between the lower integrated circuit die and the lower gap filling layer. A bonding layer may be formed on the isolation layer, and a bonding pad may be formed in the bonding layer. One or more upper integrated circuit dies may be bonded to the bonding layer and the bonding pad, wherein the upper integrated circuit die may be directly located above the interface between the lower integrated circuit die and the lower gap filling layer. By forming an isolation layer directly above the interface between the lower integrated circuit die and the lower gap filling layer, the effect of a coefficient of thermal expansion (CTE) mismatch between the lower integrated circuit die and the lower gap filling layer on the bonding integrity between the upper integrated circuit die and the bonding layer and the bonding pad may be eliminated or reduced, thereby eliminating or reducing the risk of delamination of the upper integrated circuit die during the manufacture and operation of the integrated circuit package. As a result, better reliability of the integrated circuit package may be achieved.

[0011] Figure 1-Figure 13 The intermediate processing steps for forming an integrated circuit package are shown. Figure 1 , the lower integrated circuit die 100 is attached to the carrier 112 by an adhesive 114. The carrier 112 may be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The carrier 112 may be a wafer. In some embodiments, the adhesive 114 is a thermal release layer, such as an epoxy-based light-to-heat conversion (LTHC) release material, which loses its adhesive properties when heated. In some embodiments, the adhesive 114 is a UV glue, which loses its adhesive properties when exposed to UV light. Figure 1 The illustrated layout of the lower integrated circuit die 100 on the carrier 112 is one example, and other layouts are contemplated.

[0012] Each lower integrated circuit die 100 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM), a power management chip (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front end (AFE) die), etc. or a combination thereof.

[0013] Each lower integrated circuit die 100 may have a semiconductor substrate 102, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 102 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates may also be used, such as multilayer substrates or gradient substrates. The semiconductor substrate 102 may have an active surface (e.g., Figure 1 The surface facing downward in the middle), which can be called the front side, and the passive surface (e.g. Figure 1 The back side of the semiconductor substrate 102 may also be referred to as the back side of the lower integrated circuit die 100, and the front side of the semiconductor substrate 102 may face the front side of the lower integrated circuit die 100.

[0014] Devices (not shown separately) may be disposed at the active surface of the semiconductor substrate 102. These devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An interconnect structure 104 may be disposed on the active surface of the semiconductor substrate 102. The interconnect structure 104 may interconnect the devices to form an integrated circuit. The interconnect structure 104 may include a metallization pattern (not shown separately) in a dielectric layer (not shown separately). The dielectric layer may be a low-k dielectric layer. The metallization pattern may include metal lines and vias, which may be formed in the dielectric layer by a damascene process, such as a single damascene process, a dual damascene process, etc. The metallization pattern may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, combinations thereof, etc. The metallization pattern may be electrically coupled to the device. A seal ring 105 may extend through the interconnect structure 104 of each lower integrated circuit die 100. The seal ring 105 may surround the metallization pattern of the corresponding interconnect structure 104 in a top view, and the area between the seal ring 105 and the metallization pattern may be referred to as a keep-out zone (KOZ). The sealing ring 105 may be made of the same or similar material as the metallization pattern and manufactured using the same or similar process. The sealing ring 105 may be electrically isolated from the device.

[0015] The conductive via 106 may be disposed in the semiconductor substrate 102. The conductive via 106 may be electrically coupled to a metallization pattern of the interconnect structure 104. The semiconductor substrate 102 may be thinned in a subsequent process to expose the conductive via 106 at an inactive surface of the semiconductor substrate 102. After the thinning process, the conductive via 106 may be a through-substrate via (TSV), such as a through-silicon via. In some embodiments, the conductive via 106 is formed by a via-first process, so that the conductive via 108 may extend into the semiconductor substrate 102 but not into the interconnect structure 104. The conductive via 106 formed by the via-first process may be connected to a lower metallization pattern of the interconnect structure 104 (e.g., closer to the semiconductor substrate 102). In some embodiments, the conductive via 106 is formed by a via-middle process, so that the conductive via 104 may extend through a portion of the interconnect structure 104 and into the semiconductor substrate 102. The conductive via 106 formed by the via-middle process may be connected to a middle metallization pattern of the interconnect structure 104. In some embodiments, the conductive via 106 is formed by a via last process, so that the conductive via 104 can extend through the entire interconnect structure 104 and into the semiconductor substrate 102. The conductive via 106 formed by the via last process can be connected to an upper metallization pattern of the interconnect structure 104 (e.g., farther from the semiconductor substrate 102).

[0016] The bonding layer 108 may be disposed on the interconnect structure 104 on the front side of each lower integrated circuit die 100. The bonding layer 108 may be formed of an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS)-based oxide, etc.; a nitride such as silicon nitride, etc.; or the like. The bonding layer 108 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. One or more passivation layers (not shown separately) may be disposed between the bonding layer 108 and the interconnect structure 104.

[0017] The bonding pad 110 may extend through the bonding layer 108 and be electrically coupled to the metallization pattern of the interconnect structure 104. The bonding pad 110 may include a conductive column, a conductive pad, etc., to which external connections may be made. In some embodiments, the bonding pad 110 includes a conductive pad located on the front side of the lower integrated circuit die 100 and a conductive via connecting the conductive pad to the upper metallization pattern of the interconnect structure 104. In such an embodiment, the bonding pad 110 including the conductive pad and the conductive via may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The bonding pad 110 may be formed of a conductive material (such as copper, aluminum, etc.) by an appropriate coating process (such as plating, etc.).

[0018] exist Figure 2 , a lower gap filler layer 116 is formed around the lower integrated circuit die 100, and the semiconductor substrate 102 of the lower integrated circuit die 100 is thinned to expose the conductive via 106. In a top view, the lower gap filler layer 116 can surround the lower integrated circuit die 100. The lower gap filler layer 116 can extend along the sidewalls of the lower integrated circuit die 100 (including the semiconductor substrate 102, the interconnect structure 104, and the bonding layer 108). The lower gap filler layer 116 can have a different CTE than the components of the lower integrated circuit die 100 (e.g., the semiconductor substrate 102). The lower gap filler layer 116 can be an insulating layer and can be formed of a dielectric material, such as silicon oxide, PSG, BSG, BPSG, TEOS-based oxide, polymer, etc., which can be formed by a suitable deposition process, such as CVD, ALD, spin coating, etc. Initially, the lower gap filler layer 116 can cover the back side of the lower integrated circuit die 100.

[0019] One or more thinning processes may be performed to make the top surface of the lower gap-filling layer 116 flush with the top surface of the lower integrated circuit die 100 and expose the top surface of the conductive via 106. The one or more thinning processes may be a chemical mechanical polishing (CMP) process, a grinding process, an etch-back process, a combination thereof, etc., which are performed on the back side of the lower integrated circuit die 100. After the one or more thinning processes, the top surfaces of the lower gap-filling layer 116, the lower integrated circuit die 100 (including the semiconductor substrate 102 and the conductive via 106) may be substantially coplanar or flush (within process variation).

[0020] exist Figure 3 In the embodiment of the present invention, portions of the semiconductor substrate 102 and the lower gap filling layer 116 are further removed to expose the sidewalls of the conductive via 106. The removal process may be an etching process, such as a dry etching process, which selectively removes the semiconductor substrate 102 and the lower gap filling layer 116 while leaving the conductive via 106 substantially intact. In some embodiments, the removal rate of the semiconductor substrate 102 is similar to the removal rate of the lower gap filling layer 116, and after the removal process, the surface of the lower gap filling layer and the semiconductor substrate 102 are substantially coplanar or flush (within process variation).

[0021] exist Figure 4 , an isolation layer 117 is formed on the lower gap filling layer 116, the lower integrated circuit die 100, and the conductive via 106. The isolation layer 117 can isolate each conductive via 106 from the adjacent conductive via 206 to prevent current leakage. The isolation layer 117 can be formed as a conformal layer that contacts the sidewalls of the conductive via 106 and the lower gap filling layer 116, the semiconductor substrate 102, and the top surface of the conductive via 102. The isolation layer 117 can overlap the interface between the lower integrated circuit die 100 (including the semiconductor substrate 102) and the lower gap filling layer 116 (e.g., the sidewalls of the semiconductor substrate 102 and the sidewalls of the lower gap filling layer 116). As discussed in more detail below, forming the isolation layer 117 directly on the interface between the lower integrated circuit die 100 and the lower gap-fill layer 116 can eliminate or reduce the effects of CTE mismatch between underlying materials, such as between components of the lower integrated circuit die 100 (e.g., the semiconductor substrate 102) and the lower gap-fill layer 116, on the integrity of the bond between a bonding layer subsequently formed on the isolation layer 117 and an upper integrated circuit die subsequently bonded to the bonding layer.

[0022] The isolation layer 117 may be formed of one or more dielectric materials having a high Young's modulus and formed by one or more suitable deposition processes, such as CVD, ALD, etc. In some embodiments, the isolation layer 117 includes a first sublayer 117A formed on the lower gap filling layer 116, the lower integrated circuit die 100, and the conductive via 106, and a second sublayer 117B formed on the first sublayer 117A. In such an embodiment, the first sublayer 117A and the second sublayer 117B may include different materials. For example, the first sublayer 117A may include silicon nitride, silicon carbide, etc., and the second sublayer 117B may include silicon oxide, etc. In some embodiments, the isolation layer 117 includes a single material, such as silicon nitride, etc.

[0023] exist Figure 5 In the embodiment, the isolation layer 117 is partially removed to re-expose the top surface of the conductive via 106. Portions of the conductive via 106 may also be removed. The removal process may be a CMP process, a grinding process, an etch-back process, a combination thereof, or the like. After the removal process, the top surfaces of the isolation layer 117 and the conductive via 106 may be substantially coplanar or flush (within the process variation range). Portions of the isolation layer 117 may extend continuously from the sidewall of the conductive via 106 of one lower integrated circuit die 100 to the sidewall of the conductive via 106 of another lower integrated circuit die 100. In an embodiment where the isolation layer 117 includes a first sublayer 117A and a second sublayer 117B, as shown in FIG. Figure 5 As shown in the cross-sectional view of , the first sub-layer 1170 becomes U-shaped after the removal process and extends between the sidewalls of adjacent conductive vias 106 of the same lower integrated circuit die 100 or an adjacent lower integrated circuit die 100. The top surfaces of the first sub-layer 117A, the second sub-layer 117B, and the conductive via 106 are substantially coplanar or flush (within the process variation range).

[0024] exist Figure 6 In the embodiment, an etch stop layer 119 is formed on the isolation layer 117 and the conductive via 106, a bonding layer 118 is formed on the etch stop layer 118, and a bonding pad 120 is formed in the bonding layer 118 and the etch stop layer 119. The etch stop layer 119 can protect the conductive via 106 below during the formation of the bonding pad 120. The bonding pad 120 can be used to bond with the upper integrated circuit die in a subsequent process. The bonding pad 120 can extend through the bonding layer 118 and the etch stop layer 119. In some embodiments, the bonding layer 118 is directly formed on the isolation layer 117 and the conductive via 106, and the bonding pad 120 is formed in the bonding layer 118.

[0025] The bonding pad 120 may include an active bonding pad 120A and a dummy bonding pad 120B. The active bonding pad 120A may be a bonding pad 120 electrically coupled to a circuit system (e.g., a circuit system of the lower integrated circuit die 100). The active bonding pad 120A may be in contact with the conductive via 106 and the isolation layer 117. The isolation layer 117 may be located between the active bonding pad 120A and the semiconductor substrate 102. The dummy bonding pad 120B may be a bonding pad 120 electrically isolated from the circuit system (e.g., the circuit system of the lower integrated circuit die 100). The dummy bonding pad 120B may be in contact with the isolation layer 117, and the bottom surface of the dummy bonding pad 120B may be covered by the isolation layer 117. The dummy bonding pad 120B may be located directly above the lower gap filling layer 116 and the semiconductor substrate 102, and may be separated from the lower gap filling layer 116 and the semiconductor substrate 102 by the isolation layer 117.

[0026] The etch stop layer 119 may be formed of a dielectric material, such as silicon nitride, silicon carbide, etc., which may be formed by a suitable deposition process, such as CVD, ALD, etc. The bonding layer 118 may be formed of an oxide, such as silicon oxide, PSG, BSG, BPSG, TEOS-based oxide, titanium oxide, etc., or a nitride, such as silicon nitride, silicon oxynitride, silicon carbonitride, aluminum nitride, etc., which may be formed by a suitable deposition process, such as CVD, ALD, etc. The bonding pad 120 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The bonding pad 120 may be formed of a metal, such as copper, aluminum, etc., which may be formed by plating, etc. In some embodiments, a planarization process, such as a CMP process, a grinding process, an etch back process, a combination thereof, etc., is performed on the bonding layer 118 and the bonding pad 120. After the planarization process, the top surfaces of the bonding layer 118 and the bonding pad 120 may be substantially coplanar or flush (within the process variation range).

[0027] exist Figure 7 In the embodiment of the present invention, one or more upper integrated circuit dies 200 are bonded to the bonding layer 118 and the bonding pads 120. The upper integrated circuit die 200 may overlap with the lower integrated circuit die 100. For example, Figure 7An embodiment is shown in which an upper integrated circuit die 200A overlaps one lower integrated circuit die 100 and an upper integrated circuit die 200B overlaps two lower integrated circuit dies 100. The upper integrated circuit die 200B also overlaps the interface between the lower integrated circuit die 100 (including the semiconductor substrate 102) and the lower gap fill layer 116. Each of the two upper integrated circuit dies 200A can be electrically coupled to the corresponding lower integrated circuit die 100 below. The upper integrated circuit die 200B can be electrically coupled to the two lower integrated circuit dies 100. As a result, the lower integrated circuit dies 100 can be electrically coupled to each other through the upper integrated circuit die 200B. In some embodiments, the upper integrated circuit die 200B does not include any active devices and can therefore be referred to as a bridge die or a silicon bridge. In some embodiments, the upper integrated circuit die 200B includes active devices and can be referred to as an active integrated circuit die. Figure 7 The illustrated layout of the upper integrated circuit die 200 on the bonding layer 118 is one example, and other layouts are contemplated.

[0028] Each upper integrated circuit die 200 may be a logic die (e.g., CPU, GPU, SoC, AP, microcontroller, etc.), a memory die (e.g., DRAM die, SRAM die, etc.), a power management die (e.g., PMIC die), an RF die, a sensor die, a MEMS die, a signal processing die (e.g., DSP die), and a front-end die (e.g., AFE die), etc., or a combination thereof. The materials and manufacturing processes of the components in the upper integrated circuit die 200 may be found by referring to similar components in the lower integrated circuit die 100. Each upper integrated circuit die 200 may include a semiconductor substrate 202, which may have an active surface (e.g., Figure 7 The surface facing downward in the middle), which can be called the front side, and the passive surface (e.g. Figure 7 The back side of the semiconductor substrate 202 may also be referred to as the back side of the upper integrated circuit die 200 , and the front side of the semiconductor substrate 202 may face the front side of the upper integrated circuit die 200 .

[0029] Devices (not shown separately) may be disposed at the active surface of the semiconductor substrate 202. These devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An interconnect structure 204 may be disposed on the active surface of the semiconductor substrate 202. The interconnect structure 204 may interconnect the devices to form an integrated circuit. The interconnect structure 204 may include a metallization pattern (not shown separately) in a dielectric layer (not shown separately). The metallization pattern may be electrically coupled to the device. A bonding layer 206 may be disposed on the interconnect structure 204, located on the front side of the upper integrated circuit die 200. One or more passivation layers (not shown separately) may be disposed between the bonding layer 206 and the interconnect structure 204. The bonding layer 206 may include a material that is the same or similar to the bonding layer 118.

[0030] The bonding pads 208 may extend through the bonding layer 206 and may be electrically coupled to the metallization pattern of the interconnect structure 204. The bonding pads 208 may include active bonding pads 208A and dummy bonding pads 208B. The active bonding pads 208A may be bonding pads 208 (eg, bonding pads 208A and dummy bonding pads 208B) that are in contact with the active bonding pads 120A. Figure 6 ). The dummy bonding pad 208B may be a bonding pad 120 (as shown) that contacts the dummy bonding pad 120B. Figure 6 1 ). Active bonding pads 120A and active bonding pads 208A may be electrically coupled to the circuitry of lower integrated circuit die 100 and / or the circuitry of upper integrated circuit die 200. Dummy bonding pads 120B and dummy bonding pads 208B may be electrically isolated from the circuitry of lower integrated circuit die 100 and the circuitry of upper integrated circuit die 200. Bonding pads 208 may include the same or similar material as bonding pads 120.

[0031] The seal ring 205 may extend through the interconnect structure 204 of each upper integrated circuit die 200. In a top view, the seal ring 205 may surround the metallization pattern of the corresponding interconnect structure 204, and the area between the seal ring 205 and the metallization pattern may be referred to as a KOZ. The seal ring 205 may be made of the same or similar material as the metallization pattern and manufactured using the same or similar process. The seal ring 205 may be electrically isolated from the device.

[0032] The upper integrated circuit die 200 may be bonded to the bonding layer 118 and the bonding pads 120 by placing the upper integrated circuit die 200 using a pick and place process or the like, and then bonding the upper integrated circuit die 200 to the bonding layer 118 and the bonding pads 120. The bonding layer 206 of the upper integrated circuit die 200 may be directly bonded to the bonding layer 118 by dielectric-to-dielectric bonding, and the bonding pads 208 of the upper integrated circuit die 200 may be directly bonded to the corresponding bonding pads 120 by metal-to-metal bonding. Figure 7 In the illustrated embodiment, the bond pad 208 has the same or similar size and shape as the corresponding bond pad 120. In other embodiments, the bond pad 208 has a smaller size (eg, width) than the corresponding bond pad 120.

[0033] Bonding may include pre-bonding and annealing. During pre-bonding, a small pressure may be applied to press the upper integrated circuit die 200 against the bonding layer 118 and the bonding pad 120. Pre-bonding may be performed at low temperatures, such as room temperature. After pre-bonding, a direct bond, such as a dielectric-to-dielectric bond, may be formed between the bonding layer 206 and the bonding layer 118. Then, in a subsequent high temperature annealing step, the bonding strength between the bonding layer 206 and the bonding layer 118 may be increased. The bonding pad 208 may contact the bonding pad 120 after pre-bonding, or may expand during annealing to contact the bonding pad 120. In addition, during annealing, the material of the bonding pad 208 may be mixed or bonded with the material of the bonding pad 120, so that a metal-to-metal bond may be formed.

[0034] The isolation layer 117 located directly on the interface between the lower integrated circuit die 100 and the lower gap fill layer 116 can eliminate or reduce the impact of the CTE mismatch between the underlying materials, such as the components of the lower integrated circuit die 100 (e.g., semiconductor substrate 102) and the lower gap fill layer 116, on the bonding integrity between the upper integrated circuit die 200 and the bonding layer 118 and the bonding pad 120, thereby eliminating or reducing the risk of delamination of the upper integrated circuit die 200 during the manufacture and operation of the integrated circuit package. As a result, better reliability of the integrated circuit package can be achieved.

[0035] Figure 7 Take the front-to-back bonding configuration as an example, where after bonding, the back side of the lower integrated circuit die 100 faces the front side of the upper integrated circuit die 200. Other bonding configurations may be used, such as a front-to-front bonding configuration or other bonding configurations. In the front-to-front bonding configuration, the front side of the lower integrated circuit die 100 faces the front side of the upper integrated circuit die 200.

[0036] exist Figure 8, an upper gap filling layer 210 is formed around the upper integrated circuit die 200. In a top view, the upper gap filling layer 210 may surround the upper integrated circuit die 200. The upper gap filling layer 210 may extend along the sidewalls of the upper integrated circuit die 200 (including the semiconductor substrate 202, the interconnect structure 204, and the bonding layer 206). The upper gap filling layer 210 may be formed by the same or similar method as the lower gap filling layer 116, and is formed of the same or similar dielectric material as the lower gap filling layer 116. A thinning process may be performed to remove a portion of the back side of the semiconductor substrate 202 and a portion of the upper gap filling layer 210. The thinning process may be a CMP process, a grinding process, an etch back process, a combination thereof, or the like. After the thinning process, the top surfaces of the upper gap filling layer 210 and the upper integrated circuit die 200 (including the semiconductor substrate 202) may be substantially coplanar or flush (within a process variation range).

[0037] exist Fig. 9 In the embodiment, carrier 212 is bonded to the top surface of semiconductor substrate 202 and upper gap filling layer 210. Carrier 212 may be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. Carrier 212 may be a wafer having the same or similar size as carrier 112. In some embodiments, carrier 212 is bonded to semiconductor substrate 202 and upper gap filling layer 210 using bonding layers 213 and 214. Bonding layer 213 is formed on semiconductor substrate 202 and upper gap filling layer 210, and bonding layer 214 is formed on carrier 212. Bonding layer 213 and bonding layer 214 may each include a dielectric material, such as silicon dioxide, etc., and may be formed by a suitable deposition process, such as CVD, ALD, etc. The structure on carrier 112 may be bonded to carrier 212 via bonding layer 213 and bonding layer 214, and the bonding process is similar to that of carrier 112. Figure 7 The bonding process of the bonding layer 118 and the bonding layer 206 described in are the same or similar.

[0038] exist Fig.10 In the embodiment of the present invention, the carrier 112 and the adhesive 114 are removed, and a dielectric layer 216 is formed on the lower gap fill layer 116 and the front side of the lower integrated circuit die 100. The removal process may include projecting a light beam such as a laser beam or an ultraviolet beam onto the adhesive 114 (e.g., Figure 6), so that the adhesive 114 decomposes when exposed to the light beam, and the carrier 112 can be removed. In some embodiments, the dielectric layer 216 includes PBO, polyimide, BCB-based polymer, etc., and is formed by a suitable coating process, such as spin coating, lamination, etc. In some embodiments, the dielectric layer 216 includes silicon dioxide, silicon nitride, etc., and is formed by a suitable deposition process (such as CVD, ALD, etc.). In some embodiments, a redistribution structure (not separately shown) can be formed before forming the dielectric layer 216 to provide additional wiring.

[0039] exist Fig.11 In the embodiment of the present invention, an under bump metallization (UBM) 218 ​​and an electrical connector 220 are formed. The UBM 218 may have a portion extending along the surface of the dielectric layer 216 and a portion extending through the dielectric layer 216 to be physically and electrically coupled to the bonding pad 110. As a result, the UBM 218 is electrically coupled to the lower integrated circuit die 100.

[0040] As an example of forming UBM 218, dielectric layer 216 may be patterned to form openings that expose the bonding pad 110 and bonding layer 108 below. Patterning may be accomplished by acceptable photolithography and etching processes, such as forming a mask and then performing anisotropic etching. The mask may be removed after patterning. A seed layer (not shown separately) may be formed on dielectric layer 216, in an opening through dielectric layer 216, and on exposed portions of bonding pad 110 and bonding layer 108. The seed layer may be a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer on the titanium layer. The seed layer may be formed using a suitable deposition process, such as physical vapor deposition (PVD), etc. A photoresist may then be formed on the seed layer and patterned. The photoresist may be formed by spin coating, etc., and may be exposed to light for patterning. The pattern of the photoresist may correspond to UBM 218. The patterning may form openings through the photoresist to expose the seed layer.

[0041] Conductive material can be formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as chemical plating, electroplating, etc. The conductive material may include a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, etc. or a combination thereof. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed can be removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the portion of the seed layer on which the conductive material is not formed can be removed by an acceptable etching process (such as wet etching or dry etching). The remaining portion of the seed layer and the conductive material can form the UBM 218.

[0042] The electrical connector 220 may be formed on the UBM 218. The electrical connector 220 may be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse core die connection (C4) bump, a microbump, a bump formed by electroless nickel palladium immersion gold technology (ENEPIG), etc. In some embodiments, the electrical connector 220 includes a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. The electrical connector 220 may be formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow may be performed to shape the solder into a desired bump shape. In some embodiments, the electrical connector 220 includes a metal column, such as a copper column, formed by sputtering, printing, electroplating, chemical plating, CVD, etc., which is free of solder and has a substantially vertical sidewall. A metal cap layer may be formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and may be formed by a plating process. Figure 8 The structure shown may be referred to as wafer structure 250 .

[0043] exist Fig.12 In the embodiment, the wafer structure 250 is divided to form individual integrated circuit package components 250'. The above process can be performed using wafer level processing. The carrier 212 can be a wafer and can include a number of similar Figure 8 The structure shown (not shown separately). Wafer structure 250 can be placed on a belt 222 supported by a frame 224. Then, wafer structure 250 can be singulated along scribe lines 226, so that wafer structure 250 can be separated into individual integrated circuit package assemblies 250'. The die singulation process can include a sawing process, a laser cutting process, etc. A cleaning process or a rinsing process can be performed after the singulation process.

[0044] exist Fig.13 In the embodiment, the integrated circuit package component 250' is bonded to the package substrate 228, and an underfill 234 is formed between the integrated circuit package component 250' and the package substrate 228. The package substrate 228 may include a conductive pad 230. In some embodiments, the package substrate 228 includes a material such as glass fiber reinforced resin, bismaleimide triazine (BT) resin, other printed circuit board (PCB) materials, etc. In some embodiments, the package substrate 228 includes a material such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, etc.

[0045] The packaging substrate 228 may include active and passive devices (not shown separately), such as transistors, capacitors, resistors, combinations thereof, and the like. These devices may be formed using any suitable method. The packaging substrate 228 may include metallization layers and through holes (not shown separately) that are physically and electrically coupled to the conductive pads 230. The metallization layers may be formed over the active and passive devices, and various devices may be connected to form functional circuits. The metallization layers may be alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), wherein the through holes interconnect the conductive material layers. In some embodiments, the packaging substrate 228 has no active and passive devices.

[0046] During the bonding process, the electrical connector 220 can be reflowed to bond the integrated circuit package assembly 250' to the conductive pad 230. The electrical connector 220 can electrically and physically couple the package substrate 228 to the integrated circuit package assembly 250'. In some embodiments, a solder resist layer (not separately shown) is formed on the package substrate 228. The electrical connector 220 can be disposed in an opening in the solder resist layer to electrically and physically couple to the conductive pad 230. The solder resist layer can be used to protect areas of the package substrate 228 from external damage.

[0047] The bottom filler 234 can surround the electrical connector 220 and protect the joints caused by the reflow of the electrical connector 220. In the top view, the bottom filler 234 can surround the integrated circuit package component 250'. The bottom filler 234 can be formed by a capillary flow process after attaching the integrated circuit package component 250', or it can be formed by a suitable deposition method before attaching the integrated circuit package component 250'. The bottom filler 234 can then be cured. Fig.10 The illustrated structure may be referred to as an integrated circuit package 300 .

[0048] Fig.14A and Fig. 14B An embodiment is shown in which the semiconductor substrate 102 is recessed below the top surface of the lower gap-fill layer 116 . Fig.14A and Fig. 14B As shown in the above reference Figure 1 and Figure 2 The steps to follow after discussing the process. Fig.14A shows the Figure 3 Structures similar to those shown in the drawings, wherein similar parts refer to similar parts formed by similar processes. Fig.14AIn the process, portions of the semiconductor substrate 102 and the lower gap-filling layer 116 are further removed to expose the sidewalls of the conductive via 106. The removal rate of the semiconductor substrate 102 may be higher than the removal rate of the lower gap-filling layer 116, and after the removal process, the top surface of the semiconductor substrate 102 may be lower than the top surface of the lower gap-filling layer 116, and the sidewalls of the lower gap-filling layer 116 may be exposed.

[0049] Fig. 14B shows a diagram similar to some embodiments Fig.13 The integrated circuit package 300 of the illustrated integrated circuit package 302, wherein similar components refer to similar components formed by similar processes. Figure 4-Figure 13 After the described process, the integrated circuit package 302 may correspond to the Fig.14A The structure obtained by the embodiment shown. Fig. 14B , the isolation layer 117 may overlap with the interface between the lower integrated circuit die 100 (including the semiconductor substrate 102) and the lower gap-filling layer 116 (e.g., the sidewalls of the semiconductor substrate 102 and the sidewalls of the lower gap-filling layer 116). The isolation layer 117 may extend on the sidewalls of the lower gap-filling layer 116. The bottom surface of the isolation layer 117 may be located below the top surface of the lower gap-filling layer 116.

[0050] Fig.15A and Fig. 15B An embodiment is shown in which the lower gap-fill layer 116 is recessed below the top surface of the semiconductor substrate 102 . Fig.15A and Fig. 15B As shown in the above reference Figure 1 and Figure 2 The steps to follow after discussing the process. Fig.15A shows the Figure 3 Structures similar to those shown in the drawings, wherein similar parts refer to similar parts formed by similar processes. Fig.15A In the process, portions of the semiconductor substrate 102 and the lower gap-filling layer 116 are further removed to expose the sidewalls of the conductive vias 106. The removal rate of the semiconductor substrate 102 may be lower than the removal rate of the lower gap-filling layer 116, and after the removal process, the top surface of the lower gap-filling region 116 may be lower than the top surface of the semiconductor substrate 102, and the sidewalls of the semiconductor substrate 102 may be exposed.

[0051] Fig. 15B shows a diagram similar to some embodiments Fig.13 The integrated circuit package 300 is an integrated circuit package 304 of the illustrated integrated circuit package 300, wherein similar components refer to similar components formed by similar processes. Figure 4-Figure 13After the described process, the integrated circuit package 304 may correspond to the Fig.15A The structure obtained by the embodiment shown. Fig. 15B , the isolation layer 117 may overlap the interface between the lower integrated circuit die 100 (including the semiconductor substrate 102) and the lower gap-filling layer 116 (e.g., the sidewalls of the semiconductor substrate 102 and the sidewalls of the lower gap-filling layer 116). The isolation layer 117 may extend on the sidewalls of the semiconductor substrate 102. The bottom surface of the isolation layer 117 may be located below the top surface of the semiconductor substrate 102.

[0052] Various embodiments are described above in the context of a system on integrated circuit die (SoIC) packaging configuration. It should be understood that various embodiments may also be applicable to other packaging configurations, such as substrate integrated fan-out (InFO), core die on wafer on substrate (CoWoS), etc.

[0053] Embodiments may have some advantageous features. By forming the isolation layer 117 directly on the interface between the lower integrated circuit die 100 and the lower gap filler layer 116, the effect of the CTE mismatch between the components of the lower integrated circuit die 100 (e.g., semiconductor substrate 102) and the lower gap filler layer 116 on the bonding integrity between the upper integrated circuit die 200 and the bonding layer 118 and the bonding pad 120 may be eliminated or reduced, thereby eliminating or reducing the risk of delamination of the upper integrated circuit die 200 during the manufacture and operation of the integrated circuit packages 300, 302, and 304. As a result, the reliability of the integrated circuit packages 300, 302, and 304 is better.

[0054] In one embodiment, an integrated circuit package includes: a first die, wherein the first die includes a first substrate and a first through hole extending through the first substrate; a first gap fill layer along the sidewall of the first substrate; an isolation layer located on a surface of the first substrate and a surface of the first gap fill layer, wherein the isolation layer overlaps an interface between the sidewall of the first substrate and the sidewall of the first gap fill layer, and wherein the isolation layer extends on the sidewall of the first through hole; a first bonding layer located on the isolation layer; and a first bonding pad located in the first bonding layer. In one embodiment, the first bonding pad is directly above the first gap fill layer, and wherein the first bonding pad is separated from the first gap fill layer by the isolation layer. In one embodiment, the first bonding pad contacts the isolation layer, and wherein the first bonding pad is electrically isolated from the circuit system. In one embodiment, the integrated circuit package further includes a second bonding pad located in the first bonding layer, wherein the second bonding pad contacts the first through hole, and wherein the second bonding pad is electrically coupled to the circuit system. In one embodiment, the isolation layer is located between the second bonding pad and the first substrate. In one embodiment, the isolation layer includes two sublayers of different materials. In one embodiment, the integrated circuit package further comprises an etch stop layer between the first bonding layer and the isolation layer, wherein the first bonding pad extends through the etch stop layer. In one embodiment, the integrated circuit package further comprises a second die bonded to the first bonding layer and the first bonding pad, wherein the second die overlaps an interface between a sidewall of the first substrate and a sidewall of the first gap fill layer.

[0055] In one embodiment, an integrated circuit package includes: a first die, wherein the first die includes a first substrate and a first through hole protruding from a top surface of the first substrate; a first gap fill layer surrounding the first die, wherein a thermal expansion coefficient of the first gap fill layer is different from a thermal expansion coefficient of the first substrate; an isolation layer in contact with a top surface of the first substrate and a top surface of the first gap fill layer, wherein the isolation layer overlaps an interface between the first substrate and the first gap fill layer, and wherein the first through hole extends through the isolation layer; a first bonding layer located on the isolation layer; a first bonding pad located in the first bonding layer; and a second die, wherein the second die includes a second bonding layer and a second bonding pad located in the second bonding layer, wherein the second bonding layer is bonded to the first bonding layer, and wherein the second bonding pad is bonded to the first bonding pad. In one embodiment, the top surface of the first substrate and the top surface of the first gap fill layer are flush. In one embodiment, the top surface of the first substrate is located below the top surface of the first gap fill layer. In one embodiment, the top surface of the first substrate is located above the top surface of the first gap fill layer. In one embodiment, the first bonding pad is separated from the first gap-filling layer by an isolation layer, and wherein the first bonding pad is a dummy bonding pad.

[0056] In one embodiment, a method of forming an integrated circuit package includes: attaching a first die to a carrier, wherein the first die includes a first substrate and a first through hole in the first substrate; forming a first gap fill layer on a sidewall of the first die, wherein the first gap fill layer includes a dielectric material; removing a portion of the first gap fill layer and a portion of the first substrate to expose the first through hole; forming an isolation layer on the first substrate and the first gap fill layer, wherein the isolation layer overlaps an interface between the first substrate and the first gap fill layer, and wherein the first through hole extends into the isolation layer; forming a first bonding layer over the isolation layer; and forming a first bonding pad in the first bonding layer, wherein the first bonding pad contacts the first through hole. In one embodiment, forming the isolation layer includes forming a first isolation sublayer on the first substrate and the first gap fill layer, and forming a second isolation sublayer on the first isolation sublayer, and wherein the first isolation sublayer and the second isolation sublayer include different materials. In one embodiment, a top surface of the isolation layer and a top surface of the first through hole are flush. In one embodiment, the isolation layer includes a silicon nitride layer. In one embodiment, the method further comprises forming an etch stop layer on the isolation layer before forming the first bonding layer, wherein the first pad extends through the etch stop layer. In one embodiment, the method further comprises forming a second bonding pad in the first bonding layer, wherein the second bonding pad is directly above the first gap fill layer, and wherein the isolation layer covers a bottom surface of the second bonding pad. In one embodiment, the method further comprises bonding the second die to the first bonding layer, the first bonding pad, and the second bonding pad using dielectric-to-dielectric bonding and metal-to-metal bonding.

[0057] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit package, comprising: a first die, wherein the first die comprises a first substrate and a first via extending through the first substrate; a first gap-filling layer along the sidewalls of the first substrate; an isolation layer located on a surface of the first substrate and a surface of the first gap-filling layer, wherein the isolation layer overlaps an interface between a sidewall of the first substrate and a sidewall of the first gap-filling layer, and wherein the isolation layer extends on a sidewall of the first through hole; A first bonding layer, located on the isolation layer; and The first bonding pad is located in the first bonding layer.

2. The integrated circuit package according to claim 1, wherein: The first bonding pad is directly over the first gap-filling layer, and wherein the first bonding pad is separated from the first gap-filling layer by the isolation layer.

3. The integrated circuit package according to claim 1, wherein: The first bonding pad contacts the isolation layer, and wherein the first bonding pad is electrically isolated from the circuitry.

4. The integrated circuit package of claim 1 , further comprising a second bonding pad located in the first bonding layer, wherein: The second bond pad contacts the first via, and wherein the second bond pad is electrically coupled to circuitry.

5. The integrated circuit package according to claim 1, further comprising an etch stop layer between the first bonding layer and the isolation layer, wherein The first bond pad extends through the etch stop layer.

6. The integrated circuit package of claim 1, further comprising a second die bonded to the first bonding layer and the first bonding pad, wherein: The second die overlaps an interface between a sidewall of the first substrate and a sidewall of the first gap-filling layer.

7. An integrated circuit package, comprising: a first die, wherein the first die comprises a first substrate and a first via protruding from a top surface of the first substrate; a first gap-filling layer surrounding the first die, wherein a thermal expansion coefficient of the first gap-filling layer is different from a thermal expansion coefficient of the first substrate; an isolation layer in contact with a top surface of the first substrate and a top surface of the first gap-filling layer, wherein the isolation layer overlaps an interface between the first substrate and the first gap-filling layer, and wherein the first via extends through the isolation layer; A first bonding layer, located on the isolation layer; a first bonding pad located in the first bonding layer; and A second die, wherein the second die comprises a second bonding layer and a second bonding pad in the second bonding layer, wherein the second bonding layer is bonded to the first bonding layer, and wherein the second bonding pad is bonded to the first bonding pad.

8. The integrated circuit package according to claim 7, wherein: The first bonding pad is separated from the first gap-filling layer by the isolation layer, and wherein the first bonding pad is a dummy bonding pad.

9. A method of forming an integrated circuit package, the method comprising: attaching a first die to a carrier, wherein the first die includes a first substrate and a first through-via in the first substrate; forming a first gap-filling layer on the sidewalls of the first die, wherein the first gap-filling layer comprises a dielectric material; removing a portion of the first gap-filling layer and a portion of the first substrate to expose the first through hole; forming an isolation layer on the first substrate and the first gap-filling layer, wherein the isolation layer overlaps an interface between the first substrate and the first gap-filling layer, and wherein the first through hole extends into the isolation layer; forming a first bonding layer over the isolation layer; and A first bonding pad is formed in the first bonding layer, wherein the first bonding pad contacts the first through hole.

10. The method according to claim 9, wherein: Forming the isolation layer includes forming a first isolation sublayer on the first substrate and the first gap-filling layer, and forming a second isolation sublayer on the first isolation sublayer, wherein the first isolation sublayer and the second isolation sublayer include different materials.

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